KR20130084901A - Flash memory device and reading method of flash memory device - Google Patents

Abstract

PURPOSE: A flash memory system and a lead method of the flash memory system are provided to quickly and accurately correct a lead error, thereby reducing the overhead of the system. CONSTITUTION: In a wear-out table which consider each of the block of flash memory as an index, the selection index of the selection block is updated (S120). When the current request of the lead retry of the selection block is received, with reference to the lead retry table which corresponds to the wear-out included in the selection index, the lead level starting the lead retry of the selection block is determined (S140). [Reference numerals] (S120) Update the indexes for selected blocks in a wear-out degree table in which each block of a flash memory serves as an index; (S140) Set a reading level at which a reading re-try is initiated for a selected block based on a reading re-try table corresponding to a wear-out degree included in a selected index when a request for a reading re-try for the selected block is received

Description

Flash memory device and reading method of flash memory device

The present invention relates to a flash memory system and a read method in a flash memory system. In particular, the present invention relates to a flash memory system and a read method in a flash memory system that can reduce the overhead of the system while improving read reliability by quickly correcting a read error. It is about a method.

Flash memory systems are scaled down according to the demand for high integration, and the number of bits stored in each memory cell is increasing. Thus, the lead margin between each program state is decreasing. Therefore, read errors frequently occur. Therefore, methods for accurately and quickly performing read errors have been discussed.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a flash memory system and a read method in a flash memory system capable of quickly and accurately correcting a read error, thereby reducing overhead of the system and improving read reliability.

A read method in a flash memory system including a flash memory and a memory controller according to an exemplary embodiment of the present invention includes a wear degree in which each of the blocks of the flash memory is an index. Updating a selection index for the selection block of the indexes in a wear-out table; And a read retry table corresponding to the degree of wear included in the selection index when a current request of a read retry for the selection block is received, the read for the selection block. Setting a read level at which to start the retry.

The read retry table corresponding to the wear degree included in the selection index may be one of read retry tables provided separately for each endurance state of the flash memory.

The read retry table corresponding to the wear degree included in the selection index may have a read environment of the flash memory as an index.

The read environment may be at least one of a retention characteristic and a read disturb characteristic of the flash memory.

The selection index is,

The wear degree of the selection block and indexes corresponding to the start read level of the previous request of the read retry for the selection block among the indexes constituting the read retry table may be included.

Read at a voltage level from the starting lead level to the last lead level of the last index of the read retry table corresponding to the wear included in the selection index until the error underlying the current request of the read retry is corrected. The method may further include repeating the operation.

Starting the read correction operation different from the read retry when the error is not corrected even by the read operation by the last read level of the last index of the read index corresponding to the wear level included in the selection index. It can be provided.

A read correction operation different from the read retry may be a read correction operation using a low density parity check code (LDPC) method.

The first command may be an erase command.

The flash memory may transmit an incremental step pulse erase loop count (ISPE) value required to erase the selection block in response to the erase command to the memory controller as a wear rate of the selection block.

According to an aspect of the present invention, there is provided a memory system including: a flash memory including a plurality of blocks and detecting state information on a selection block in response to a first command; And a read retry table provided separately for each endurance state when the first command is transmitted to the flash memory and a current request for read retry for the selection block is received. The memory controller may set a read level for starting a read retry of the selection block with reference to a read retry table corresponding to the state information.

The memory controller updates a selection index for the selection block among the indexes in a wear-out table in which each block of the flash memory is an index based on the state information. And an error controller configured to set a read level for starting a read retry for the selection block based on index information of a read retry table corresponding to a previous request of the read retry included in the selection index. have.

The memory system may be included in a solid state drive.

According to the read method in the flash memory system and the flash memory system according to an embodiment of the present invention, in performing a read retry on a memory block in which an error occurs, an advantage of minimizing the number of attempts to read retry There is this.

Therefore, according to the flash memory system and the read method in the flash memory system according to the embodiment of the present invention, it is possible to prevent the reliability of the read due to high integration.

BRIEF DESCRIPTION OF THE DRAWINGS A brief description of each drawing is provided to more fully understand the drawings recited in the description of the invention.
1 is a flowchart illustrating a read method in a flash memory system according to an exemplary embodiment of the present invention.
2 is a block diagram illustrating a flash memory system according to an exemplary embodiment of the present invention.
3A and 3B are diagrams illustrating a memory cell array of the flash memory of FIG. 2.
4 is a diagram illustrating a distribution of memory cells of the flash memory of FIG. 2.
FIG. 5 is a diagram illustrating an example of the first command and status information of FIG. 2.
6 is a diagram illustrating an example of a wear table of FIG. 2.
FIG. 7 is a diagram illustrating an example of the read retry table of FIG. 2.
8 is a diagram illustrating an example of an index of the wear table of FIG. 6.
FIG. 9 is a diagram illustrating an example in which a plurality of read retry tables of FIG. 7 are provided.
10 is a flowchart illustrating a read method in a flash memory system according to another embodiment of the present invention.
11 is a block diagram illustrating a computing system device according to an exemplary embodiment of the present invention.
12 is a block diagram illustrating a memory card according to an exemplary embodiment of the present invention.
FIG. 13 illustrates a solid state drive (SSD) according to an exemplary embodiment of the present invention.
14 is a diagram illustrating a server system and a network system including an SSD.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art, and the following embodiments may be modified in various other forms, The present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an," and "the" include plural forms unless the context clearly dictates otherwise. Also, " comprise " and / or " comprising " when used herein should be interpreted as specifying the presence of stated shapes, numbers, steps, operations, elements, elements, and / And does not preclude the presence or addition of one or more other features, integers, operations, elements, elements, and / or groups. As used herein, the term " and / or " includes any and all combinations of one or more of the listed items.

Although the terms first, second, etc. are used herein to describe various elements, regions and / or regions, it should be understood that these elements, components, regions, layers and / Do. These terms are not intended to be in any particular order, up or down, or top-down, and are used only to distinguish one member, region or region from another member, region or region. Thus, the first member, region or region described below may refer to a second member, region or region without departing from the teachings of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings schematically showing embodiments of the present invention. In the figures, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions illustrated herein, including, for example, variations in shape resulting from manufacturing.

1 is a flowchart illustrating a read method in a flash memory system according to an exemplary embodiment of the present invention, and FIG. 2 is a block diagram illustrating a flash memory system according to an exemplary embodiment of the present invention.

1 and 2, a flash memory system MSYS according to an embodiment of the present invention includes a flash memory MEM and a controller Ctrl. The read method thereof includes updating a selection index for a selection block (S120) and a selection block in a wear-out table in which each block of the flash memory MEM is an index. When a current request for a read retry for a received is received, a read that starts a read retry for the selection block by referring to a read retry table corresponding to the degree of wear included in the selection index. A step S140 of setting a read level RLEV is provided. This will be described in detail.

The flash memory MEM outputs the data DTA stored in the memory cell array (not shown) in response to the read command CMD_RD. In detail, the flash memory MEM applies an initial read voltage RV0 to memory cells (not shown) corresponding to the address Addr of the read command CMD_RD, and stores the data stored in the memory cells. DTA) is output to the memory controller Ctrl.

The flash memory MEM of the flash memory system MSYS according to the embodiment of the present invention may include a memory cell array MA having the structure shown in FIG. 3A. The memory cell array MA includes a (a is an integer of 2 or more) blocks BLK0 to BLKa-1, and each of the blocks BLK0 to BLKa-1 is b And the pages PAG0 to PAGb-1 may include c (c is an integer of 2 or more) sectors (SEC0 to SECc-1). In FIG. 3A, the pages PAG0 to PAGb-1 and the sectors SEC0 to SECC-1 are shown for the block BLK0 only for convenience of illustration, but the other blocks BLK1 to BLKa-1 also block BLK0. It may have the same structure as.

When the memory cell array MA according to the embodiment of the present invention is the memory cell array of the NAND flash memory as described above, the blocks BLK0 to BLKa-1 of FIG. It may be provided as an example such as 3b. Referring to FIG. 3B, each of the blocks BLK0 to BLKa-1 has a number of d (d is an integer of 2 or more) in which eight memory cells MCEL are connected in series in the bit lines BLO to BLD-1. It may be provided as a string (STR). Each string STR may also include a drain select transistor Str1 and a source select transistor Str2 which are connected to both ends of memory cells MCEL connected in series.

The NAND flash memory device having the structure as shown in FIG. 3B is erased in units of blocks, and performs a program in units of pages PAG corresponding to each word line WL0 to WL7. 3B shows an example in which eight pages PAG for eight word lines WL0 to WL7 are provided in one block. However, the blocks BLK0 to BLKa-1 of the memory cell array MA according to the embodiment of the present invention may have a different number of memory cells than the number of memory cells MCEL and pages PAG shown in FIG. It may be provided with a page. In addition, the flash memory MEM of FIG. 1 may include a plurality of memory cell arrays that perform the same operation in the same structure as the memory cell array MA described above.

Each of the memory cells MCEL of the semiconductor memory device having the structure as shown in FIG. 3B may have a threshold voltage Vth included in one of the distributions as shown in FIG. 4 according to the number of bits of programmed program data. have. FIG. 4A illustrates a cell distribution in a single-level cell (SLC) flash memory in which memory cells MCELs are programmed with one bit, and FIG. 4B illustrates two memory cells MCELs each. 4 shows a cell spread in a 2-bit MLC (multi-level cell) flash memory programmed into bits, and FIG. 4C shows a cell spread in a 3-bit MLC flash memory in which memory cells MCEL are programmed to 3 bits, respectively. .

In the case of the SLC flash memory, each of the memory cells MCEL of the memory cell array MA of FIG. 3B has an erased state E and a program state as shown in FIG. 4A according to a value of programmed data. Has a threshold voltage included in one of (P) states. Alternatively, in the case of a 2-bit MLC flash memory, each of the memory cells MCEL of the memory cell array MA of FIG. 3B has an erased state E and a first program state P1 to a third program state P3. Has a threshold voltage included in one of the states. Alternatively, in the case of a 3-bit MLC flash memory, each of the memory cells MCEL of the memory cell array MA of FIG. 3B has an erased state E and a first program state P1 to a seventh program state P7. Has a threshold voltage included in one of the states.

However, the present invention is not limited thereto, and each of the memory cells MCEL of the memory cell array MA of FIG. 3B may be programmed with 4 bits or more although not shown in FIG. 4. In addition, the flash memory MEM of FIG. 1 may include memory cells MCEL programmed with different numbers of bits.

Referring back to FIG. 2, the flash memory MEM receives the first command CMD1 from the memory controller Ctrl. The first command CMD1 may be an erase command, as shown in FIG. 5. In this case, the first command CMD1 includes an identifier (eg, an address of a block) of a block to be erased. For example, the first command CMD1 may be an erase command for the block BLK0 of FIG. 3A. However, the present invention is not limited thereto, and the first command CMD1 may be a program command or the like.

The flash memory MEM performs a corresponding operation in response to the first command CMD1. In the above example, the flash memory MEM may perform an erase operation on the block BLK0 of FIG. 3A. An erase operation according to an embodiment of the present invention may be performed until all cells of the block to be erased are erased, for example, until all cells of the block are erased (E) of FIG. 4. , By applying erase voltage pulses in which the voltage level is sequentially increased, respectively. As such, the scheme is called an incremental step pulse erase (ISPE) scheme by using the erase voltage pulses in which the voltage level increases sequentially.

The flash memory MEM detects the state information Inf_ST from the result of the execution of the first command CMD1. For the above example, as shown in FIG. 5, the flash memory MEM may detect the ISPE loop count value as the state information Inf_ST. The ISPE loop count value is the number of erase voltage pulses required for the select block to be erased in response to the erase command. For example, in performing the erase on the block BLK0 of FIG. 3A, if five sequentially erased voltage pulses are used, the ISPE loop count value "5" for the block BLK0 is the state information for the block BLK0. It may be detected as (Inf_ST). The flash memory MEM may store state information Inf_ST in the register REG.

The ISPE loop count value may correspond to the degree of wear on the selection block. For example, as the ISPE loop count value increases, it may be determined that wear on the selection block is increased. However, the present invention is not limited thereto, and when the first command CMD1 is a program command, the status information Inf_ST may be the number of program pulses required for programming the corresponding page in an incremental step pulse program (ISPP) method. .

2, the flash memory MEM transmits the state information Inf_ST to the memory controller Ctrl. The memory controller Ctrl may include an error controller ETU. The error control unit ETU may update the wear level table TAB1 based on the state information Inf_ST. The wear table TAB1 may be loaded into system memory (eg, SRAM (not shown)) included in the memory controller Ctrl.

An example for the wear table TAB1 is shown in FIG. 6. Referring to FIG. 6, the wear level table TAB1 according to an embodiment of the present invention may use a block identifier (block address) as an index of the table. For example, the index of the wear table TAB1 may be addresses 0 to a-1 for blocks BLK0 to BLKa-1 of FIG. 3A.

The wear table TAB1 may also include a wear degree corresponding to the state information Inf_ST. In the above example, the wear level may be an ISPE loop count value for the select block. FIG. 6 shows an example in which the wear degree of index 0 of the wear table TAB1 is 4, the wear degree of the index 1 is 2, and the wear degree of the index a-1 is 7. FIG. When the degree of wear represents the ISPE loop count value for the selection block, FIG. 6 shows an example where the degree of wear for blocks BLK0, BLK1, and BLKa-1 is 4, 2, and 7, respectively. That is, FIG. 6 illustrates a case in which four, two, and seven erase pulses are required to erase blocks BLK0, BLK1, and BLKa-1.

When the state information Inf_ST is received, the error controller ETU of FIG. 2 updates the contents of the index corresponding to the state information Inf_ST in the wear level table TAB1 of FIG. 6. For example, if the state information Inf_ST is due to the first command CMD1 for the block BLKa-1, the error control unit ETU updates the contents of the index for the block BLKa-1 of the wear table TAB1. . For example, the error control unit ETU may update the wear level 7 of the index a-1 of the wear level table TAB1 to the wear level 8.

The wear table TAB1 according to an embodiment of the present invention may also include index information for the read retry table TAB2. The read retry table TAB2 may index the read environment of the flash memory MEM or the memory system MSYS. The read environment of the flash memory MEM or the memory system MSYS affects the read of data programmed into the flash memory MEM, such as a retention characteristic or a read disturb characteristic of the memory. Say For example, retention or read disturb may lead to incorrect data, other than the programmed data. As shown in FIG. 1, the read retry table TAB2 may be loaded into a system memory (eg, SRAM (not shown)) included in the memory controller Ctrl.

An example of the read retry table TAB2 is shown in FIG. 7. Indexes 0 through n of the read retry table TAB2 may represent the above-described read environment. For example, index 0 may be a first state for read disturb and index 1 may be a second state for read disturb. In addition, the index n may be a first state for retention.

The read retry table TAB2 includes a value for the read level for each index. The read level refers to the level of the read voltage applied to the page during the read retry operation for the selection block, that is, the page included in the selection block. The read retry operation is performed in the flash memory MEM by a read retry request generated when an error is detected when reading data programmed into the flash memory MEM. That is, since an error has occurred in the read operation due to the read voltage of the set level, the read retry is performed by changing the read level again. For reference, detection of a read error may be performed by an error checking and correction (ECC) engine (not shown). The ECC engine may be included inside or outside the memory controller Ctrl. The ECC may transmit a read retry request RRR to the error control unit ETU of FIG. 2.

The error control unit ETU according to an exemplary embodiment of the present invention may determine the successive indexes from the read level of any index until the read operation of the read retry table TAB2 is normally completed, that is, until the read error is corrected. The read retry operation is performed by changing the voltage level of the read voltage to the read level.

Each index of the read retry table TAB2 may include a plurality of read levels, because the MLC flash memory requires a plurality of read levels to read the MLC. For example, three different read voltages are required to distinguish four states as shown in FIG. 7 illustrates an example of including three read levels in each index.

2, 6, and 7, the error control unit ETU according to the embodiment of the present invention may perform a read retry, that is, when a read error occurs, the selection index of the wear table TAB1 ( With reference to the read retry table index included in the index of the selection block, the read level at which the read retry is started is set.

If the read command CMD_RD is for the block BLK1, since the selection index on the wear table TAB1 is index 1, the error control unit ECTU refers to the read retry table index 1 included in the index 1 on the wear table TAB1. Thus, the read level of the read retry table TAB2 is set to the read level at which the read retry starts. In the example of FIG. 7, index 1 of the read retry table TAB2 includes read levels of RV21, RV22, and RV23.

In this case, the error controller ETU changes the read voltage set for the read command CMD_RD to the read levels of RV21, RV22, and RV23 at index 1 of the read retry table TAB2 to start the read retry operation. . As described above, if the read error is not corrected even at the read level of index 1 of the read retry table TAB2, the error control unit ETU reads the next index (index 2) on the read retry table TAB2. The read retry is again performed at the levels RV31, RV32, and RV33. The error control unit ETU repeats the above operation until the last index n on the read retry table TAB2 until the read error is corrected.

Although FIG. 2 illustrates that the read retry CMD_RR is performed directly from the error control unit ETU, the error control unit ETU may include a read retry in a separate unit that performs read control included in the memory controller Ctrl. It may just provide information about lead levels. In addition, although the read retry CMD_RR is illustrated separately from the read command CMD_RD, this is merely to conceptually distinguish between the read command and the read retry. That is, the read retry CMD_RR may be a read command CMD_RD in which the initial read voltage RV0 is changed to the read level RLEV.

8 is a diagram illustrating an example of information included in an index on a wear table according to an embodiment of the present invention.

6 and 8, each index on the wear level table TAB1 may include 1 byte of information, 4 bits of which indicate information on wear level, and the remaining 4 bits indicate read retry table indexes. Information may be indicated. FIG. 8 shows an example in which the wear level 7 and the read retry table index 3 of the index a-1 of the wear table TAB1 of FIG. 6 are shown in bits 0 to 3 and bits 4 to 7, respectively.

Referring back to FIG. 2, the error control unit ETU according to the embodiment of the present invention updates the read retry table index information LInd included in each index of the wear table TAB1 according to the read retry operation result. do. For example, if the read retry for the selection block BLK1 is completed with the read level of the index 2 of the read retry table TAB2 of FIG. 7, that is, the read error for the block BLK1 is read retry table TAB2 of FIG. 7. If corrected by the read level of index 2 of FIG. 2, the error control unit ETU may update the read retry table index of index 1 of the wear table TAB1 of FIG. 6 from 1 to 2.

As described above, when the read retry is requested again, that is, when a current request for the read retry is received, the error control unit ETU is included in the retry table included in the index of the wear table TAB1 for the corresponding block. The read retry starts from the read level of the index. For example, after updating the retry table index of the index 1 of the wear table TAB1 of FIG. 6 for the block BLK1 from 1 to 2, the read retry for the block BLK1 is required again. The controller ETU may start the read retry from the read level of the index 2 of the read retry table TAB2.

As described above, according to the memory system and the read method thereof according to the exemplary embodiment of the present invention, the number of read retries can be minimized by setting the read level by reflecting the latest read retry result at the next read retry time. Therefore, according to the memory system and the read method thereof according to the embodiment of the present invention, the read performance of the memory system can be improved.

Referring back to FIG. 2, in setting the read level of the read retry, the error controller ETU according to an embodiment of the present invention may first select one of a plurality of read retry tables. As shown in FIG. 9, if three read retry tables TAB2A to TAB2C exist in the memory system MSYS according to an exemplary embodiment of the present invention, the error controller ETU may read read retry tables TAB2A to TAB2C. Of these, the lead retry table corresponding to the wear degree WO included in the selection index of the wear degree table TAB1 is first selected. In FIG. 9, read levels of the read retry tables TAB2A to TAB2C are denoted by the same reference numerals, but their values are different from each other.

Wear is associated with the endurance of the flash memory MEM or each block. That is, the degree of wear may vary according to the endurance of each block.

Therefore, the read retry tables TAB2A to TAB2C are separately provided for each endurance state of the flash memory MEM. The endurance of the flash memory can be represented by a P / E cycle (Program / Erase Cycle). For example, the first read retry table TAB2A of FIG. 9 is a read retry table for a case in which a P / E cycle is less than 1K, and the second read retry table TAB2B is P. The read retry table for the case where the / E cycle is 1K or more and less than 2K, and the third read retry table TAB2C may be the read retry table for the case where the P / E cycle is 2K or more and less than 3K. Alternatively, the first read retry table TAB2A of FIG. 9 is a read retry table for a case where the P / E cycle is less than 1K, and the second read retry table TAB2B has a P / E cycle of 1K or more and less than 3K. The read retry table for the case, and the third read retry table (TAB2C) may be a read retry table for the case that the P / E cycle is more than 3K and less than 5K. Without being limited thereto, the read retry tables according to the embodiment of the present invention may be set for different P / E cycles.

The wear degree WO included in the selection index of the wear degree table TAB1 according to the embodiment of the present invention is changed, so that the lead retry table TAB2 and the changed wear degree WO corresponding to the wear degree WO before the change are changed. The corresponding read retry table TAB2 may be different. For example, the wear degree WO before the change to index 0 of the wear table TAB1 had a P / E cycle of less than 1K, and the program / erase for the block corresponding to index 0 of the wear table TAB1. Increasing the operation, the wear index (WO) of the index 0 can represent the case where the P / E cycle is 1K or more. In the above example, the error control unit ETU corresponds to the wear level WO of the index 0, and the second read retry table TAB2B is searched in the first read retry table TAB2A of FIG. 9. Can be changed to When the read retry table is changed in this way, the read retry table index information LInd on the index of the wear degree table may be initialized to zero.

The error control unit ETU selects one of the plurality of read retry tables based on the wear degree on the selection index of the wear table TAB1 when a read retry for the selection block is required. For example, if the wear degree of the index 1 of FIG. 6 with respect to the block BLK1 is 2, the error control unit ETU may determine P / P in the first read retry table TAB2A to third read retry table TAB2C of FIG. 9. The read retry operation on the block BLK1 may be performed by referring to the first read retry table TAB2A having an E cycle of 1K.

As described above, according to the memory system and the read method thereof according to the embodiment of the present invention, a read retry table provided separately for each endurance is provided in a situation in which a read error increases due to high integration of a flash memory and a read retry entry time is increased. By performing a read retry with reference, the number of read retries can be minimized. Therefore, system overhead due to the setting of the read level can be reduced. Accordingly, according to the memory system and the read method thereof according to the embodiment of the present invention, it is possible to save system resources and reduce the time required for read retry.

10 is a flowchart illustrating a read method according to another exemplary embodiment of the present invention.

2 and 10, the read method according to another embodiment of the present invention performs the read retry based on the read retry table TAB2 using the read method of FIG. 1 described above (S1020). That is, the read retry for the selection block is updated by referring to the read retry table corresponding to the wear degree included in the selection index when the selection index for the selection block is updated and the current request of the read retry for the selection block is received. Set the starting read level. At this time, as described above, the read retry is repeated at the read level of another index of the corresponding read retry table until the read error is corrected.

As a result, if the read error is corrected (YES in S1040), read error correction is completed (S1060). On the other hand, if the read error is not corrected even at the read level of the last index of the read retry table (NO in S1040), the read method of FIG. 10 corrects the read error using another read error correction scheme. For example, in the read method of FIG. 10, if the read error is not corrected even at the read level of the last index of the read retry table, a soft decision (low density parity check code, LDPC) method may be used. It is possible to move to the read correction step by decision. The low density parity check code (LDPC) is a method of correcting an error based on hard decision information obtained through a hard decision read and reliability information obtained through a soft decision read.

As described above, according to the read method according to another exemplary embodiment of the present invention, the number of read retries can be minimized, and if the read error is not corrected by the read retries, the entry into another read error correction scheme can be advanced. Therefore, the overall read performance and the reliability of the memory system can be improved.

11 is a block diagram illustrating a computing system device according to an exemplary embodiment of the present invention.

The computing system CSYS according to an embodiment of the present invention includes a processor (CPU), a user interface (UI), and a flash memory system (MSYS) electrically connected to a bus (BUS). The flash memory system MSYS includes a memory controller Ctrl and a flash memory MEM. In the flash memory MEM, N-bit data (N is an integer of 1 or larger) to be processed or to be processed by the processor CPU will be stored through the memory controller Ctrl. The flash memory system MSYS of FIG. 11 may be the same as the flash memory system MSYS of FIG. 2. Therefore, according to the computing system CSYS, the reliability of the read of the flash memory system MSYS can be improved by simple control without the addition of additional modules or the like.

The computing system CSYS according to an embodiment of the present invention may further include a power supply device PS. In addition, when the flash memory MEM is a flash memory device that executes a program by the program method of FIG. It can be provided.

When the computing system CSYS according to the embodiment of the present invention is a mobile device, a modem such as a battery and a baseband chipset for supplying an operating voltage of the computing system may be additionally provided. In addition, it is common knowledge in the art that an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may be further provided in the computing system CSYS according to the embodiment of the present invention. This is obvious to those who have learned, so a detailed description is omitted.

12 is a block diagram illustrating a memory card according to an embodiment of the present invention.

Referring to FIG. 12, a memory card MCRD according to an embodiment of the present invention includes a memory controller Ctrl and a flash memory MEM. The memory controller Ctrl controls data writing to or reading data from the flash memory MEM in response to a request from an external host (not shown) received through the input / output means I / O. . Also, the memory controller Ctrl controls the erase operation on the flash memory MEM. The memory controller Ctrl of the memory card MCRD according to an exemplary embodiment of the present invention may include interface units (not shown) and RAM (not shown) for performing an interface with a host and a memory device, respectively, in order to perform the above control operations. RAM) and the like. The memory card MCRD according to the exemplary embodiment of the present invention may be implemented with the flash memory system MSYS of FIG. 2.

The memory card MCRD of FIG. 12 may be a compact flash card (CFC), a microdrive, a smart media card (SMC) multimedia card (MMC), a secure digital card (SDC) : Security Digital Card), a Memory Stick, and a USB flash memory driver. Therefore, according to the memory card MCRD of FIG. 12, the overhead of the system can be reduced while improving the reliability of the read.

FIG. 13 illustrates a solid state drive (SSD) according to an exemplary embodiment of the present invention.

Referring to FIG. 13, an SSD according to an embodiment of the present invention includes an SSD controller SCTL and a flash memory MEM. The SSD controller SCTL may include a processor PROS, a RAM, a cache buffer CBUF, and a memory controller Ctrl connected to a bus BUS. The processor PROS controls the memory controller Ctrl to exchange data with the flash memory MEM in response to a request (command, address, data) of the host (not shown). The processor PROS and the memory controller Ctrl of the SSD according to the embodiment of the present invention may be implemented as one ARM processor. Data necessary for the operation of the processor PROS may be loaded into the RAM. For example, the table TAB of FIG. 2 may be loaded into RAM.

The host interface HOST I / F receives a request from the host and transmits the request to the processor PROS or transmits data transmitted from the flash memory MEM to the host. Host interfaces (HOST I / F) include Universal Serial Bus (USB), Man Machine Communication (MMC), Peripheral Component Interconnect-Express (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Various interface protocols, such as Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), and Intelligent Drive Electronics (IDE), can interface with the host. Data to be transferred to the flash memory MEM or data transferred from the flash memory MEM may be temporarily stored in the cache buffer CBUF. The cache buffer CBUF may be an SRAM or the like.

The SSD according to the embodiment of the present invention may be implemented by the flash memory system MSYS of FIG. 2. Therefore, according to the SSD of FIG. 13, the overhead of the system can be reduced while improving the reliability of the read by reducing the number of read retries.

14 is a diagram illustrating a server system and a network system including an SSD.

Referring to FIG. 14, a network system NSYS according to an embodiment of the present invention may include a server system SSYS and a plurality of terminals TEM1 to TEMn connected through a network. The server system SSYS according to an embodiment of the present invention responds to a request received from a server SERVER and terminals TEM1 to TEMn processing a request received from a plurality of terminals TEM1 to TEMn connected to a network. And an SSD for storing corresponding data. In this case, the SSD of FIG. 14 may be the SSD of FIG. 13. That is, the SSD of FIG. 14 may include an SSD controller SCTL and a flash memory MEM, and the flash memory MEM may be a flash memory device that performs a read by the read method of FIG. 1.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms are employed herein, they are used for purposes of describing the present invention only and are not used to limit the scope of the present invention.

For example, an example in which the read retry CMD_RR is performed by the read level RLEV set by the error controller ETU is described, but the present invention is not limited thereto. According to an exemplary embodiment of the present invention, the error controller ETU may detect an offset indicating a difference between the read level RLEV and the reference level Rref, as shown in FIG. 15. As described above, the memory controller Ctrl of FIG. 2 may be provided with a separate unit that performs read control in response to the output of the error controller ETU. The unit performing the read control may control the read retry to be performed at a voltage level of which the reference level Rref is changed by the offset of FIG. 15.

Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (10)

In a read method in a flash memory system including a flash memory and a memory controller,
Updating a selection index for the selection block of the index in a wear-out table having each of the blocks of the flash memory as an index; And
When a current request for read retry for the selection block is received, the read retry table for the selection block is referred to by referring to a read retry table corresponding to the degree of wear included in the selection index. And setting a read level at which to start the trie. The lead retry table of claim 1, wherein the read retry table corresponding to the degree of wear included in the selection index includes:
And one of read retry tables provided separately for each endurance state of the flash memory. The lead retry table of claim 1, wherein the read retry table corresponding to the degree of wear included in the selection index includes:
And a read environment of the flash memory as an index. The method of claim 3, wherein the lead environment,
And at least one of a retention characteristic and a read disturb characteristic of the flash memory. The method of claim 1, wherein the selection index,
And information about an index corresponding to a wear level of the selection block and a start lead level for a previous request of a read retry for the selection block among the indexes constituting the read retry table. The method according to claim 1,
Read at a voltage level from the starting lead level to the last lead level of the last index of the read retry table corresponding to the wear included in the selection index until the error underlying the current request of the read retry is corrected. And repeating the operation. The method of claim 6,
Starting the read correction operation different from the read retry when the error is not corrected even by the read operation by the last read level of the last index of the read index corresponding to the wear level included in the selection index. The lead method characterized by the above-mentioned. The method of claim 7, wherein the read correction operation different from the read retry,
And a read correction operation using a Low Density Parity Check Code (LDPC) method. The method of claim 1, wherein the first command comprises:
A read method comprising an erase instruction. The method of claim 9, wherein the flash memory,
And a ISPE loop count (Incremental Step Pulse Erase Loop Count) required to erase the selection block in response to the erase command, to the memory controller as a wear rate for the selection block.

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