CN110275668B

CN110275668B - Block management method, memory control circuit unit and memory storage device

Info

Publication number: CN110275668B
Application number: CN201810207659.2A
Authority: CN
Inventors: 林小东; 李明彦; 李国荣
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2018-03-14
Filing date: 2018-03-14
Publication date: 2022-09-13
Anticipated expiration: 2038-03-14
Also published as: CN110275668A

Abstract

The invention provides a block management method, a memory control circuit unit and a memory storage device, which are used for managing a plurality of entity blocks in a rewritable nonvolatile memory module. The method comprises the following steps: reading user data from a first physical block of the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block; inputting a plurality of parameters corresponding to the first entity block into the block recognition machine learning model so as to group the first entity block into the first block group or the second block group according to the output result of the block recognition machine learning model; establishing a first block mapping table and a second block mapping table; the logical address of the first block mapping table is mapped to the physical block belonging to the first block group and the logical address of the second block mapping table is mapped to the physical block belonging to the second block group.

Description

Block management method, memory control circuit unit and memory storage device

Technical Field

The present invention relates to a block management method, a memory control circuit unit and a memory storage device, and more particularly, to a block management method, a memory control circuit unit and a memory storage device based on machine learning.

Background

Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory module (e.g., flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices as described above.

Flash memory is typically partitioned into a plurality of physical blocks. Generally, a physical block is the smallest unit of erase in a flash memory. That is, each physical block contains the minimum number of memory cells that are erased together. Each physical block is typically divided into a plurality of physical pages (physical pages). A physical page is usually the smallest unit of programming (program), that is, the smallest unit of writing data or reading data.

When the flash memory storage device is used as a storage medium for installing an operating system of a computer, the operating system frequently accesses specific data, such as a File Allocation Table (FAT). Under the above operation scheme, the physical blocks of the flash memory storage device are frequently erased to complete the data update. However, the erase count of the physical blocks is limited (e.g., the physical blocks are damaged after ten thousand erase cycles), so the life of the flash memory device is greatly shortened when the physical blocks are frequently erased.

Generally, an operating system has a specific usage pattern for storing data on a storage device. For example, some physical blocks may be worn too much, and some physical blocks may be worn too little. Therefore, if different writing mechanisms can be designed according to the wear level of each entity block, the performance of the flash memory storage device can be effectively improved, and the service life of the flash memory storage device can be prolonged. Therefore, those skilled in the art need to continuously develop a block management method capable of evenly using all the physical blocks in the flash memory storage system to effectively prolong the life of the flash memory storage system.

Disclosure of Invention

The invention provides a block management method, a memory control circuit unit and a memory storage device.

An exemplary embodiment of the present invention provides a block management method for managing a plurality of physical blocks in a rewritable nonvolatile memory module. The block management method comprises the following steps: reading user data from a first physical block of the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block; inputting a plurality of parameters corresponding to the first entity block into the block recognition machine learning model so as to group the first entity block into a first block group or a second block group according to an output result of the block recognition machine learning model; establishing a first block mapping table and a second block mapping table; mapping the logical address of the first block mapping table to a first physical block belonging to a first block group; and mapping the logical address of the second block mapping table to the first physical block belonging to the second block group.

In an exemplary embodiment of the invention, the logical address of the first block mapping table is arranged before the logical address of the second block mapping table.

In an exemplary embodiment of the invention, the frequency of overwriting the data stored in the logical address of the first block mapping table is greater than the frequency of overwriting the data stored in the logical address of the second block mapping table.

In an exemplary embodiment of the present invention, the plurality of parameters includes at least one of a read-busy-time parameter, an error bit position parameter and a storage retention parameter.

In an exemplary embodiment of the invention, the error bit position parameter is obtained according to a distribution of a plurality of error bits in an upper physical programming unit, a distribution of a plurality of error bits in a middle physical programming unit, and a distribution of a plurality of error bits in a lower physical programming unit in reading the user data from each physical block.

In an exemplary embodiment of the invention, the block management method further includes: the memory management circuit is used for grouping the first physical block into a second block group when the user data read from the first physical block cannot be corrected in the error checking and correcting operation and is corrected after the re-reading operation.

In an exemplary embodiment of the invention, the block management method further includes: writing test data into each of the plurality of physical blocks; reading out test data from each of the plurality of physical blocks to obtain a plurality of parameters corresponding to each of the plurality of physical blocks; and inputting parameters corresponding to each of the plurality of physical blocks into the block recognition machine learning model by taking each of the plurality of physical blocks as a unit, and grouping the plurality of physical blocks into at least a first block group and a second block group according to an output result of the block recognition machine learning model.

In an exemplary embodiment of the invention, the block management method further includes: writing test data into the first test entity blocks and reading the test data to obtain parameters corresponding to the first test entity blocks; writing the test data into the plurality of second test entity blocks and reading the test data to obtain parameters corresponding to the plurality of second test entity blocks; and performing machine learning operation by using the plurality of first test entity blocks, the parameters corresponding to the plurality of first test entity blocks, the plurality of second test entity blocks and the parameters corresponding to the plurality of second test entity blocks as training data to train the block recognition machine learning model.

In an exemplary embodiment of the invention, the block management method further includes: before mapping the logical address of the first block mapping table to the entity block belonging to the first block group, the entity blocks belonging to the first block group are sorted according to the output result of the block recognition machine learning model.

An exemplary embodiment of the present invention provides a memory storage device, which includes a connector, a rewritable nonvolatile memory module and a memory control circuit unit. The connector is used for electrically connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity blocks. The memory control circuit unit is electrically connected to the connector and the rewritable nonvolatile memory module. The memory control circuit unit is used for writing test data into each entity block. The memory control circuit unit is used for issuing a reading instruction sequence to read out user data from a first entity block in the entity blocks so as to obtain a plurality of parameters corresponding to the first entity block. In addition, the memory control circuit unit is used for establishing a first block mapping table and a second block mapping table; mapping the logical address of the first block mapping table to a first physical block belonging to a first block group; and mapping the logical address of the second block mapping table to the first physical block belonging to the second block group.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to arrange the logical address of the first block mapping table before the logical address of the second block mapping table.

In an exemplary embodiment of the invention, the frequency of overwriting the data of the logical addresses stored in the first block mapping table by the memory control circuit unit is greater than the frequency of overwriting the data of the logical addresses stored in the second block mapping table by the memory control circuit unit.

In an exemplary embodiment of the invention, the memory control circuit unit is configured to group the first physical blocks into the second block group when the user data read from the first physical blocks cannot be corrected in the error checking and correcting operation and is corrected after the re-reading operation.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to issue a write command sequence to write test data into each of the plurality of physical blocks; the memory control circuit unit is also used for issuing a reading instruction sequence to read out test data from each of the plurality of physical blocks so as to obtain a plurality of parameters corresponding to each of the plurality of physical blocks; and the memory control circuit unit is further used for inputting parameters corresponding to each of the plurality of physical blocks into the block identification machine learning model so as to group the plurality of physical blocks into at least a first block group and a second block group according to an output result of the block identification machine learning model.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to write test data into a plurality of first testable physical blocks and read the test data to obtain a plurality of parameters corresponding to the first testable physical blocks, and write the test data into a plurality of second testable physical blocks and read the test data to obtain a plurality of parameters corresponding to the second testable physical blocks. The memory control circuit unit is further configured to perform a machine learning operation using the first test entity block, the parameter corresponding to the first test entity block, the second test entity block, and the parameter corresponding to the second test entity block as training data to train a block recognition machine learning model.

In an exemplary embodiment of the invention, before the operation of mapping the logical address of the first block mapping table to the physical block belonging to the first block group, the memory control circuit unit is further configured to sort the physical blocks belonging to the first block group according to the output result of the block identity machine learning model.

An exemplary embodiment of the present invention provides a memory control circuit unit, which includes a host interface, a memory interface and a memory management circuit. The host interface is used for electrically connecting to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module, and the rewritable nonvolatile memory module comprises a plurality of entity blocks. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used for issuing a reading command sequence to read out user data from a first entity block in the entity blocks so as to obtain a plurality of parameters corresponding to the first entity block. In addition, the memory management circuit is used for issuing a writing command sequence and inputting a plurality of parameters corresponding to the first entity block into the block identification machine learning model so as to group the first entity block into the first block group or the second block group according to an output result of the block identification machine learning model. The memory management circuit is used for establishing a first block mapping table and a second block mapping table. The memory management circuit is used for mapping the logical address of the first block mapping table to a first entity block belonging to a first block group; and the memory management circuit is used for mapping the logical address of the second block mapping table to the first physical block belonging to the second block group.

In an exemplary embodiment of the invention, the memory management circuit is further configured to arrange the logical address of the first block mapping table before the logical address of the second block mapping table.

In an exemplary embodiment of the invention, the frequency of overwriting the data stored in the logical address of the first block mapping table by the memory management circuit is greater than the frequency of overwriting the data stored in the logical address of the second block mapping table by the memory management circuit.

In an exemplary embodiment of the invention, the memory management circuit is configured to group the first physical block into the second block group when the user data read from the first physical block cannot be corrected in the error checking and correcting operation and is corrected after the re-reading operation.

In an exemplary embodiment of the invention, the memory management circuit is further configured to issue a write command sequence to write test data into each of the plurality of physical blocks; the memory management circuit is further used for issuing a reading instruction sequence to read out test data from each of the plurality of physical blocks so as to obtain a plurality of parameters corresponding to each of the plurality of physical blocks; and the memory management circuit is used for inputting the parameters corresponding to each of the plurality of physical blocks into the block identification machine learning model so as to group the plurality of physical blocks into at least a first block group and a second block group according to the output result of the block identification machine learning model.

In an exemplary embodiment of the invention, the memory management circuit is further configured to issue a write command sequence to write the test data into the first physical blocks and read the test data to obtain a plurality of parameters corresponding to the first physical blocks. In addition, the memory management circuit is used for sending a write-in command sequence to write the test data into the second test entity blocks and read the test data so as to acquire a plurality of parameters corresponding to the second test entity blocks. And the memory management circuit is further configured to perform a machine learning operation using the first test physical block, the parameter corresponding to the first test physical block, the second test physical block, and the parameter corresponding to the second test physical block as training data to train the block recognition machine learning model.

In an exemplary embodiment of the invention, before the operation of mapping the logical address of the first block mapping table to the physical block belonging to the first block group, the memory management circuit is further configured to sort the physical blocks belonging to the first block group according to the output result of the block identity machine learning model.

Based on the above, the block management method, the memory control circuit unit and the memory storage device provided by the present invention utilize the block recognition machine learning model to determine the use status of the physical blocks according to the parameters of the physical blocks and group the physical blocks, so as to prioritize the physical blocks with good use status, thereby achieving the purpose of evenly using all the physical blocks in the flash memory storage system.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment.

FIG. 2 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment.

FIG. 3 is a diagram illustrating a host system and a memory storage device according to another example embodiment.

FIG. 4 is a schematic block diagram illustrating a host system and a memory storage device according to an example embodiment.

FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an example embodiment.

FIG. 6 is a diagram illustrating a mapping of logical addresses and physical blocks during initialization, according to an example embodiment.

Fig. 7 is a block diagram illustrating block management by a block recognition machine learning model according to an example embodiment.

Fig. 8 is a diagram illustrating mapping of physical blocks and a block mapping table according to an example embodiment.

Fig. 9 is a flowchart illustrating a block management method according to an example embodiment.

Fig. 10 is a flowchart illustrating a method of building a block recognition machine learning model according to an example embodiment.

Fig. 11 is a flowchart illustrating a method for physical block regrouping according to an example embodiment.

Description of the reference numerals

10: a memory storage device;

11: a host system;

12: input/output (I/O) devices;

110: a system bus;

111: a processor;

112: random Access Memory (RAM);

113: read Only Memory (ROM);

114: a data transmission interface;

20: a main board;

201: a U disk;

202: a memory card;

203: a solid state disk;

204: a wireless memory storage device;

205: a global positioning system module;

206: a network interface card;

207: a wireless transmission device;

208: a keyboard;

209: a screen;

210: a horn;

30: a memory storage device;

31: a host system;

32: an SD card;

33: a CF card;

34: an embedded storage device;

341: an embedded multimedia card;

342: an embedded multi-chip package storage device;

402: a connection interface unit;

404: a memory control circuit unit;

406: a rewritable non-volatile memory module;

502: a memory management circuit;

504: a host interface;

506: a memory interface;

508: a buffer memory;

510: a power management circuit;

512: an error checking and correcting circuit;

LBA (0) -LBA (N), LBA (M +1), LBA (M + 2): a logical address;

410(0) - (410 (N), 410(S), 410(M +1), 410(P), 410(N +1), 410(N +2), 410(N + 3): a physical block;

701: identifying a machine learning model by a block;

702: training data;

1. 2, 703: a parameter;

420: a first block group;

430: a second block group;

4101: a first test entity block;

4102: a second test entity block;

70:31: reading a busy time parameter;

7032: an error bit position parameter;

7033: storing the retention force parameter;

TA: a first block mapping table;

TB: a second block mapping table;

s901: writing test data into each entity block;

s903: reading out test data from each physical block to obtain a plurality of parameters corresponding to each physical block;

s905: inputting parameters corresponding to each physical block into the block recognition machine learning model by taking each physical block as a unit so as to group the physical blocks into at least a first block group or a second block group according to an output result of the block recognition machine learning model;

s907: establishing a first block mapping table and a second block mapping table;

s909: mapping the logical address of the first block mapping table to the physical block belonging to the first block group and mapping the logical address of the second block mapping table to the physical block belonging to the second block group;

s1001: writing test data into a plurality of first test entity blocks and reading the test data to obtain parameters corresponding to the first test entity blocks;

s1003: writing the test data into a plurality of second test entity blocks and reading the test data to obtain parameters corresponding to the second test entity blocks;

s1005: a step of performing machine learning operation by using the first test physical block, the parameter corresponding to the first test physical block, the second test physical block and the parameter corresponding to the second test physical block as training data to train the block to identify a machine learning model;

s1101: reading user data from a first physical block of the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block;

s1103: inputting the parameters corresponding to the first physical block into the block recognition machine learning model to regroup the first physical block into the first block group or the second block group according to another output result of the block recognition machine learning model.

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module and a controller (also referred to as a control circuit unit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

Fig. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment, and fig. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to another example embodiment.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 can be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through the data transmission interface 114 in a wired or wireless manner. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory Storage device 204 can be, for example, a Near Field Communication (NFC) memory Storage device, a wireless facsimile (WiFi) memory Storage device, a Bluetooth (Bluetooth) memory Storage device, or a Bluetooth low energy (iBeacon) memory Storage device based on various wireless Communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, the disclosure is not limited thereto. FIG. 3 is a diagram illustrating a host system and a memory storage device according to another example embodiment. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded Multi-media cards (eMMC) 341 and/or embedded Multi-Chip Package memory devices (eMCP) 342, and various types of embedded memory devices electrically connecting the memory module to the substrate of the host system.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

In the exemplary embodiment, the connection interface unit 402 is compatible with Secure Digital (SD) interface standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to Serial Advanced Technology Attachment (SATA) standard, Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, High-Speed Peripheral Component connection interface (PCI Express) standard, Universal Serial Bus (USB) standard, Ultra High Speed-I interface standard, Ultra High Speed-II interface standard, Ultra High Speed-m (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, Multi-Chip-Package (Package-p), Multi-Chip Memory (Multi-Chip) standard, MMC) interface standard, an Embedded Multimedia memory Card (eMMC) interface standard, a Universal Flash Storage (UFS) interface standard, an Embedded Multi-Chip Package (eMCP) interface standard, a Compact Flash (CF) interface standard, an Integrated Device Electronics (IDE) standard, or other suitable standards. In the present exemplary embodiment, the connection interface unit 402 and the memory control circuit unit 404 can be packaged in one chip, or the connection interface unit 402 is disposed outside a chip containing the memory control circuit unit.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a solid state type, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 has physical blocks (also called physical erase units) 410(0) -410 (P). For example, the physical blocks 410(0) - (410P) may belong to the same memory die (die) or to different memory dies. Each physical block has a plurality of physical pages (also called physical programming units), wherein the physical pages belonging to the same physical block can be written and erased independently and simultaneously. However, it should be understood that the present invention is not limited thereto, and each physical block may be composed of 64 physical pages, 256 physical pages, or any other physical pages.

In more detail, the physical block is the minimum unit of erase. That is, each physical block contains the minimum number of memory cells that are erased together. The physical page is the smallest unit of programming. That is, the physical page is the smallest unit of write data. Each physical page typically includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical access addresses for storing user data, and the redundancy bit region stores system data (e.g., control information and error correction codes). In the exemplary embodiment, each physical page has 8 physical access addresses in the data bit area, and one physical access address has a size of 512 bytes (byte). However, in other exemplary embodiments, the data bit region may include a greater or lesser number of physical access addresses, and the size and number of the physical access addresses are not limited in the present invention. For example, in an exemplary embodiment, the physical block is a physical erase unit, and the physical page is a physical program unit or a physical sector, but the invention is not limited thereto.

In the exemplary embodiment, the rewritable nonvolatile memory module 406 is a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 data bit in one memory Cell). However, the invention is not limited thereto, and the rewritable nonvolatile memory module 406 may also be a Multi-Level Cell (MLC) NAND type flash memory module (i.e., a flash memory module capable of storing 2 data bits in one memory Cell), a plural Level Cell (TLC) NAND type flash memory module (i.e., a flash memory module capable of storing 3 data bits in one memory Cell), or other memory modules with the same characteristics.

FIG. 5 is a schematic block diagram of a memory control circuit unit shown in accordance with an example embodiment.

Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504 and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10.

In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in a solid state. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a driver, and when the memory control circuit 404 is enabled, the microprocessor first executes the driver to load the control command stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform operations such as data writing, reading and erasing.

In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 can also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory unit management circuit is used for managing the entity block of the rewritable nonvolatile memory module 406; the memory writing circuit is used for issuing a writing instruction to the rewritable nonvolatile memory module 406 so as to write data into the rewritable nonvolatile memory module 406; the memory reading circuit is used for sending a reading instruction to the rewritable nonvolatile memory module 406 so as to read data from the rewritable nonvolatile memory module 406; the memory erasing circuit is used for issuing an erasing instruction to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406; the data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406.

The host interface 504 is electrically connected to the memory management circuit 502 and is electrically connected to the connection interface unit 402 for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the UHS-I interface standard, the UHS-II interface standard, the SD standard, the MS standard, the MMC standard, the CF standard, the IDE standard, or other suitable data transfer standards.

The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506.

The buffer memory 508 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 508, a power management circuit 510, and an error checking and correcting circuit 512.

The power management circuit 510 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.

The error checking and correcting circuit 512 is electrically connected to the memory management circuit 502 and is used for performing an error checking and correcting process to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the Error Checking and Correcting circuit 512 generates an Error Checking and Correcting Code (ECC Code) corresponding to the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC Code into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the corresponding error checking and correcting codes are simultaneously read, and the error checking and correcting circuit 512 performs an error checking and correcting process on the read data according to the error checking and correcting codes.

In the exemplary embodiment, the error checking and correcting circuit 512 is implemented by a low density parity check code (LDPC). However, in another exemplary embodiment, the error checking and correcting circuit 512 may also be implemented with BCH code, convolutional code (convolutional code), turbo code (turbo code), bit flipping (bit flipping), and other encoding/decoding algorithms.

Specifically, the memory management circuit 202 generates an error correction Frame (ECC Frame) according to the received data and corresponding error checking and correcting codes (hereinafter also referred to as error correction codes) and writes the ECC Frame into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error checking and correcting circuit 512 verifies the correctness of the read data according to the error correction codes in the error correction code frame.

Operations performed by the memory management circuit 502, the host interface 504 and the memory interface 506, the buffer memory 508, the power management circuit 510, and the error checking and correcting circuit 512 are described below, and may also be referred to as being performed by the memory control circuit unit 404.

It should be understood that when the operation of the physical blocks of the rewritable non-volatile memory module 406 is described herein, it is a logical concept to operate the physical blocks in "grouping" or the like. That is, the physical block of the rewritable nonvolatile memory module is not physically located, but is logically operated.

Generally, before the memory storage device 10 is shipped, a manufacturer uses a Mass Production tool (MP tool) to perform a card-opening operation on the memory storage device 10 to perform an initialization operation.

Referring to FIG. 6, for example, the memory management circuit 502 allocates logical addresses LBA (0) LBA (N) to map the physical blocks 410(0) 410 (N). In an exemplary embodiment, the memory management circuit 502 extracts the physical blocks to store a logical address-physical address mapping table (logical address-physical address mapping table) to record mapping relationships between the logical addresses LBA (0) to LBA (N) and the physical blocks 410(0) to 410 (N).

Please refer to fig. 7. In an exemplary embodiment, the memory management circuit 502 is configured to issue a write command sequence to write test data into the first test entity blocks 4101 and the second test entity blocks 4102 in the rewritable nonvolatile memory module 406 respectively and issue a read command sequence to read test data respectively, so as to obtain the parameters 1 corresponding to the first test entity blocks 4101 and the parameters 2 corresponding to the second test entity blocks, and the memory management circuit 502 performs a machine learning operation by using the first test entity blocks 4101, the parameters 1 corresponding to the first test entity blocks, the second test entity blocks 4102 and the parameters 2 corresponding to the second test entity blocks as the training data 702 to identify the machine learning model 701 according to the training blocks.

In an exemplary embodiment, the memory management circuit 502 writes the test data into the plurality of physical blocks 410(0) -410 (N) in the rewritable non-volatile memory module 406 to obtain a plurality of parameters 703 corresponding to the physical blocks 410(0) -410 (N), and inputs the parameters 703 corresponding to each physical block into the trained block recognition machine learning model 701 in units of each physical block, so as to group the physical blocks 410(0) -410 (N) in the rewritable non-volatile memory module 406 into at least a first block group 420 and a second block group 430 according to the output result of the block recognition machine learning model 701.

The parameters 703 corresponding to the physical blocks 410(0) - (410 (N) are related to the degree of wear of the physical blocks or other factors affecting the use status of the physical blocks. In the exemplary embodiment, the parameters 703 corresponding to the physical blocks 410(0) - (410 (N) include, for example, a read busy time parameter 7031, an error bit position parameter 7032, and a storage retention parameter 7033. Herein, the error bit position parameter 7032 is obtained according to the distribution of the error bits in the upper physical program unit, the distribution of the error bits in the middle physical program unit, and the distribution of the error bits in the lower physical program unit in the test data read from the physical blocks 410(0) - (410 (N)).

Similarly, parameter 1 corresponding to the first test entity block 4101 and parameter 2 corresponding to the second test entity block 4102 also include a read busy time parameter, an error bit location parameter and a storage retention parameter.

Specifically, assume that 1000 physical blocks in the rewritable nonvolatile memory module 406 are used as samples, test data is written into the 1000 physical blocks used as samples and read out, a plurality of parameters corresponding to each of the 1000 physical blocks are obtained, and the parameters and the 1000 physical blocks are used as training data 702 of the block recognition machine learning model 701 for machine learning to train the block recognition machine learning model 701. In particular, after the training data 702 is input into the block recognition machine learning model 701, the block recognition machine learning model 701 performs learning analysis on the training data 702, extracts features of the training data 702, finds out rules between the parameters and the 1000 entity blocks, constructs at least two sets of sets, determines the usage status of the entity blocks by learning the extracted features and the found rules, and divides the 1000 entity blocks into at least two groups of block groups according to the at least two sets of sets. In general, the greater the number of samples as training data, the more the block recognition machine learning model 701 learns, and the more the accuracy of the block recognition machine learning model 701 can be improved.

For example, when one of the physical blocks as a sample receives an instruction to read/write test data, the time for writing the test data to or reading the test data from the physical block is used as a read-busy time parameter. If the time for writing the test data into the physical block or reading the test data from the physical block is longer than the predetermined time, that is, the read busy time parameter of the physical block is greater than the predetermined read busy time parameter, the physical block as the sample is classified as a physical block with a normal (or poor) use status and grouped into the second block group 430. At this time, the block recognition machine learning model 701 performs machine learning, extracts features from the read busy time parameter of the entity block as a sample, and analyzes rules between the read busy time parameter and the grouping of the entity block. For example, for a block with the same or similar read-busy time parameter or a larger value than the predetermined read-busy time parameter, the block-recognition machine learning model 701 classifies the block as the second block group 430 with a general (or poor) usage status.

The block recognition machine learning model 701 may also determine and group the physical blocks according to the locations of the memory cells in the physical blocks where error bits occur. For example, assuming that the rewritable nonvolatile memory module 406 is a multi-Level Cell (TLC) NAND flash memory module, when the test data is written into the sample physical block of the TLC NAND flash memory module and the test data is read out from the physical block, the error bit position parameter corresponding to the physical block can be obtained. The positions of the memory cells of the physical block where the error bits occur include a distribution of a plurality of error bits in an upper physical programming unit, a distribution of a plurality of error bits in a middle physical page, and a distribution of error bits in a lower physical programming unit. The block recognition machine learning model 701 classifies the physical blocks into good-use or general (or poor) use groups according to the error bit position parameters. For example, when the test data is read from the physical blocks, if the test data cannot be corrected in the error checking and correcting operation and the test data must be re-read using the re-read voltage to complete the correction, the physical blocks are classified into a group with a normal (or poor) use status and grouped into the second block group 430.

That is, when the memory management circuit 502 reads the test data from the physical block using the read voltage, if the test data cannot be read using the read voltage, the memory management circuit 502 adjusts the read voltage to perform the read operation on the physical block again. If the adjusted reading voltage is used to perform the re-reading operation on the physical block to read the test data, and the error checking and correcting operation can be used to detect the error position of the physical block and correct the error, such physical block can still be used and its use status is normal (or poor). In other words, when the memory management circuit 502 reads the test data from the physical blocks using the read voltage, if the test data can be corrected in the error checking and correcting operation, the physical blocks are classified into the groups with good use status and grouped into the first block group 420. Similarly, the block recognition machine learning model 701 extracts the characteristics of the error bit position parameters of the entity blocks as the samples, analyzes the rules between the error bit position parameters and the grouping of the entity blocks, and performs machine learning.

In order to improve the accuracy of the block recognition machine learning model 701, the block recognition machine learning model 701 extracts features from all parameters of 1000 physical blocks as samples, and machine-learns the parameters and rules between grouping the physical blocks, thereby establishing the block recognition machine learning model 701 with sufficient accuracy, which can group the physical blocks 410(0) to 410(N) in the rewritable non-volatile memory module 406 after machine learning.

Referring to fig. 8, the memory management circuit 502 establishes a first block mapping table TA and a second block mapping table TB. The first block mapping table TA has logical addresses LBA (0) LBA (M) and the second block mapping table TB has logical addresses LBA (M +1) LBA (N). In the exemplary embodiment, the logical addresses LBA (0) to LBA (M) of the first block mapping table TA are arranged before the logical addresses LBA (M +1) to LBA (n) of the second block mapping table TB. The physical blocks 410(0) - (410N) in the rewritable nonvolatile memory module 406 can be divided into two groups, i.e., a first block group 420 and a second block group 430, with good use status and general (or poor) use status by the block recognition machine learning model 701. In an exemplary embodiment, the block recognition machine learning model 701 divides the entity blocks with good usage status into a first block group 420, and divides the entity blocks with normal (or poor) usage status into a second block group 430. The logical addresses LBA (0) to LBA (M) of the first block mapping table TA are mapped to the physical blocks belonging to the first block group 420, and the logical addresses LBA (M +1) to LBA (n) of the second block mapping table TB are mapped to the physical blocks belonging to the second block group 430.

For example, in an exemplary embodiment, the memory management circuit 502 stores data with high overwriting frequency in the logical addresses LBA (0) to LBA (M) of the first block mapping table TA, and stores data with lower overwriting frequency in the logical addresses LBA (M +1) to LBA (n) of the second block mapping table TB. Generally, the memory management circuit 502 selects the physical block with the logical address arranged in the front, that is, the memory management circuit 502 selects the physical block mapped to the first block group 420 for preferential use.

Referring to fig. 8 again, the memory management circuit 502 searches the physical blocks 410(0) from the physical blocks 410(0) - (410 (N) of the rewritable nonvolatile memory module 406, the memory management circuit 502 issues a write command sequence to write test data into the physical blocks 410(0) and issues a read command sequence to read the test data from the physical blocks 410(0) to obtain read busy time parameters, error bit position parameters and storage retention parameters corresponding to the physical blocks 410(0), and then inputs the parameters into the block recognition machine learning model 701, and the block recognition machine learning model 701 learns the physical blocks 410(0) according to the parameters. For example, if the block id machine learning model 701 classifies the physical block 410(0) into the second block group 430 with a normal (or poor) use status according to the parameters of the physical block 410(0) and the rules between the grouping, the physical block 410(0) is mapped to the logical address LBA (M +1) in the second block mapping table TB.

Similarly, the memory management circuit 502 continues to search the physical block 410 (1) from the physical blocks 410(0) - (410 (N) of the rewritable nonvolatile memory module 406, and the memory management circuit 502 issues a write command sequence to write test data into the physical block 410 (1) and issues a read command sequence to read test data from the physical block 410 (1), so as to obtain parameters corresponding to the physical block 410 (1), and then inputs the parameters into the block recognition machine learning model 701. If the block id machine learning model 701 learns to classify the physical block 410 (1) into the first block group 420 with better utilization according to the rules between the above parameters and groups, the physical block 410 (1) is mapped to the logical address LBA (0) in the first block mapping table TA.

The memory management circuit 502 continues to search the entity block 410(S) from the entity blocks 410(0) - (410 (N) of the rewritable nonvolatile memory module 406, and the memory management circuit 502 issues a write command sequence to write test data into the entity block 410(S) and issues a read command sequence to read the test data, and after obtaining parameters corresponding to the entity block 410(S), inputs the parameters into the block recognition machine learning model 701. If the block id machine learning model 701 classifies the physical block 410(S) into the first block group 420 with better use status according to the rule learning between the above parameters and grouping, the physical block 410(S) is mapped to the logical address LBA (1) in the first block mapping table TA.

The memory management circuit 502 continues to search the entity block 410(M) from the entity blocks 410(0) - (410 (N) of the rewritable nonvolatile memory module 406, and the memory management circuit 502 issues a write command sequence to write test data into the entity block 410(M) and issues a read command sequence to read the test data, and after obtaining parameters corresponding to the entity block 410(M), the parameters are input into the block recognition machine learning model 701. If the bmt 701 classifies the physical block 410(M) into the first block group 420 with better use status according to the rule learning between the above parameters and grouping, the physical block 410(M) is mapped to the logical address LBA (2) in the first bmt TA.

Further, before mapping the logical address LBA (2) of the first block mapping table TA to the physical blocks belonging to the first block group 420, the physical blocks belonging to the first block group 420 are sorted according to the output result of the block identification machine learning model 701. That is, the physical blocks 410 (1) and 410(S) belonging to the first block group 420 are sorted before mapping the logical address LBA (2) of the first block mapping table TA to 410 (M).

Similarly, before mapping the logical addresses LBA (M +1) -LBA (n) of the second block mapping table TB to the physical blocks belonging to the second block group 430, the physical blocks belonging to the second block group 430 are sorted according to the output result of the block identification machine learning model 701.

In an exemplary embodiment, if the physical blocks 410(S) of the physical blocks 410(0) - (410N) of the rewritable non-volatile memory module 406 need to be regrouped, the user data is read from the physical blocks 410(S) to obtain a plurality of parameters corresponding to the physical blocks 410(S), and the parameters are input into the block recognition machine learning model 701, so as to regroup the physical blocks 410(S) into the first block group 420 or the second block group 430 according to another output result of the block recognition machine learning model 701.

Please refer to fig. 9. In step S901, the memory management circuit 502 writes test data to each physical block.

In step S903, the memory management circuit 502 reads out test data from each physical block to obtain a plurality of parameters corresponding to each physical block.

In step S905, the memory management circuit 502 inputs the parameters corresponding to each physical block into the block recognition machine learning model for each physical block as a unit, so as to group the physical blocks into at least a first block group or a second block group according to the output result of the block recognition machine learning model.

In step S907, the memory management circuit 502 establishes a first block mapping table and a second block mapping table.

In step S909, the memory management circuit 502 maps the logical address of the first block mapping table to the physical block belonging to the first block group, and maps the logical address of the second block mapping table to the physical block belonging to the second block group.

Referring to fig. 10, before the step of writing the test data into each physical block by the memory management circuit 502, a step S1001 is further included. In step S1001, the memory management circuit 502 issues a write command sequence to write the test data into the first test entity blocks and issues a read command sequence to read the test data, so as to obtain the parameters corresponding to the first test entity blocks.

In step S1003, the memory management circuit 502 issues a write command sequence to write the test data into the plurality of second test entity blocks and issues a read command sequence to read the test data, so as to obtain parameters corresponding to the second test entity blocks.

In step S1005, the memory management circuit 502 performs a machine learning operation using the first test physical block, the parameter corresponding to the first test physical block, the second test physical block and the parameter corresponding to the second test physical block as training data to train the block recognition machine learning model.

Referring to fig. 11, in step S1101, the memory management circuit 502 issues a read command sequence to read out user data from a first physical block of the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block.

In step S1103, the parameters corresponding to the first physical block are input into the block-recognition machine learning model, so as to regroup the first physical block into the first block group or the second block group according to another output result of the block-recognition machine learning model.

In summary, the block recognition machine learning model of the present invention determines the usage status of the physical blocks according to a plurality of parameters of the physical blocks and groups the physical blocks, and maps the logical addresses arranged in the block mapping table to the physical blocks with good usage status, so as to preferentially write data with high overwriting frequency, such as operating system data, and maps the logical addresses arranged in the block mapping table to the physical blocks with normal (or poor) usage status, so as to write data with low overwriting frequency.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A block management method for managing a plurality of physical blocks in a rewritable nonvolatile memory module is characterized by comprising the following steps:

writing test data into a first entity block in the entity blocks;

reading the test data from the first physical block of the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block;

grouping the first physical blocks into a first block group or a second block group according to the plurality of parameters corresponding to the first physical blocks and rules between the plurality of parameters and the grouping of the plurality of physical blocks;

establishing a first block mapping table and a second block mapping table;

sorting the entity blocks belonging to the first block group;

mapping the logical address of the first block mapping table to the physical block belonging to the first block group;

sorting the physical blocks belonging to the second block group; and

mapping the logical address of the second block mapping table to the physical block belonging to the second block group,

wherein the plurality of parameters include an error bit position parameter obtained from a distribution of a plurality of error bits in an upper physical program cell, a distribution of a plurality of error bits in a middle physical program cell, and a distribution of a plurality of error bits in a lower physical program cell in reading the test data from each of the plurality of physical blocks, an

The rules between the plurality of parameters and the grouping of the plurality of physical blocks include:

grouping the physical blocks into the first block group when the test data read from one of the plurality of physical blocks is corrected in an error checking and correcting operation; and grouping another physical block among the plurality of physical blocks into the second block group when another test data read from the another physical block cannot be corrected in the error checking and correcting operation and is corrected after a re-reading operation.

2. The method of claim 1, wherein logical addresses of said first block mapping table are arranged before logical addresses of said second block mapping table.

3. The block management method of claim 2, wherein a frequency of overwriting of data stored at logical addresses of the first block mapping table is greater than a frequency of overwriting of data stored at logical addresses of the second block mapping table.

4. The block management method of claim 1, wherein said plurality of parameters further comprises at least one of a read busy time parameter and a memory hold force parameter.

5. The tile management method of claim 1, further comprising:

when the test data read from the first physical block cannot be corrected in an error checking and correcting operation and is corrected after a re-reading operation, grouping the first physical block into the second block group.

6. The block management method of claim 1, wherein sorting the physical blocks belonging to the first block group comprises:

and before mapping the logical address of the first block mapping table to the entity block belonging to the first block group, sorting the entity blocks belonging to the first block group.

7. A memory storage device, comprising:

a connector for electrically connecting to a host system;

the rewritable nonvolatile memory module comprises a plurality of entity blocks; and

a memory control circuit unit electrically connected to the connector and the rewritable nonvolatile memory module,

the memory control circuit unit is used for issuing a write-in command sequence to write test data into a first entity block in the entity blocks;

wherein the memory control circuit unit is configured to issue a read command sequence to read the test data from the first physical block of the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block;

wherein the memory control circuit unit is configured to group the first physical blocks into a first block group or a second block group according to the plurality of parameters corresponding to the first physical blocks and a rule between the plurality of parameters and the grouping of the plurality of physical blocks;

the memory control circuit unit is used for establishing a first block mapping table and a second block mapping table;

the memory control circuit unit is used for sorting the entity blocks belonging to the first block group;

wherein the memory control circuit unit is used for mapping the logical address of the first block mapping table to the physical block belonging to the first block group,

the memory control circuit unit is used for sorting the entity blocks belonging to the second block group; and

wherein the memory control circuit unit is used for mapping the logical address of the second block mapping table to the physical block belonging to the second block group,

wherein the plurality of parameters include an error bit location parameter obtained based on a distribution of a plurality of error bits in an upper physical program cell, a distribution of a plurality of error bits in a middle physical program cell, and a distribution of a plurality of error bits in a lower physical program cell in reading the test data from each of the plurality of physical blocks, an

Rules between the plurality of parameters and the grouping of the plurality of physical blocks include:

grouping the physical blocks into the first block group when the test data read from one of the physical blocks is corrected in an error checking and correcting operation; and grouping another physical block among the plurality of physical blocks into the second block group when another test data read from the another physical block cannot be corrected in the error checking and correcting operation and is corrected after a re-reading operation.

8. The memory storage device of claim 7, wherein the memory control circuitry is to arrange logical addresses of the first block mapping table before logical addresses of the second block mapping table.

9. The memory storage device of claim 8, wherein a frequency of overwriting of data by the memory control circuitry to store logical addresses in the first block map is greater than a frequency of overwriting of data by the memory control circuitry to store logical addresses in the second block map.

10. The memory storage device of claim 7, wherein the plurality of parameters further comprises at least one of a read busy time parameter and a storage hold force parameter.

11. The memory storage device of claim 7, wherein the memory control circuit unit is configured to group the first physical block into the second group of blocks when the test data read from the first physical block cannot be corrected in an error checking and correcting operation and is corrected after a re-read operation.

12. The memory storage device of claim 7, wherein the memory control circuitry unit is further configured to sort the physical blocks belonging to the first group of blocks prior to the operation of mapping the logical addresses of the first block mapping table to the physical blocks belonging to the first group of blocks.

13. A memory control circuit unit, characterized in that the memory control circuit unit comprises:

a host interface for electrically connecting to a host system;

the memory interface is electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of entity blocks; and

a memory management circuit electrically connected to the host interface and the memory interface,

wherein the memory management circuit is configured to issue a write command sequence to write test data into a first physical block of the plurality of physical blocks;

wherein the memory management circuit is configured to issue a read command sequence to read the test data from the first physical block of the plurality of physical blocks to obtain a plurality of parameters corresponding to the first physical block;

wherein the memory management circuitry is to group the first physical block into a first group of blocks or a second group of blocks according to the plurality of parameters corresponding to the first physical block and a rule between the plurality of parameters and the grouping of the plurality of physical blocks;

wherein the memory management circuit is used for establishing a first block mapping table and a second block mapping table;

wherein the memory management circuit is configured to sort the physical blocks belonging to the first group of blocks;

wherein the memory management circuit is configured to map logical addresses of the first block mapping table to physical blocks belonging to the first block group;

wherein the memory management circuit is configured to sort the physical blocks belonging to the second group of blocks; and

wherein the memory management circuit is used for mapping the logical address of the second block mapping table to the physical block belonging to the second block group,

grouping the physical blocks into the first block group when the test data read from one of the plurality of physical blocks is corrected in an error checking and correcting operation; and grouping another physical block into the second block group when another test data read from another physical block of the plurality of physical blocks cannot be corrected in the error checking and correcting operation and is corrected after a re-reading operation.

14. The memory control circuitry unit of claim 13, wherein the memory management circuitry is further to arrange logical addresses of the first block mapping table before logical addresses of the second block mapping table.

15. The memory control circuitry unit of claim 14, wherein a frequency of overwriting of data by the memory management circuitry to store logical addresses of the first block map is greater than a frequency of overwriting of data by the memory management circuitry to store logical addresses of the second block map.

16. The memory control circuit unit of claim 13, wherein the plurality of parameters further comprises at least one of a read busy time parameter and a memory hold force parameter.

17. The memory control circuit unit of claim 13, wherein the memory management circuit is configured to group the first physical block into the second group of blocks when the test data read from the first physical block cannot be corrected in an error checking and correcting operation and is corrected after a re-read operation.

18. The memory control circuit unit of claim 13, wherein the memory management circuit is further configured to sort the physical blocks belonging to the first block group before the operation of mapping the logical addresses of the first block mapping table to the physical blocks belonging to the first block group.