CN109308930B

CN109308930B - Data writing method, memory control circuit unit and memory storage device

Info

Publication number: CN109308930B
Application number: CN201710628850.XA
Authority: CN
Inventors: 叶志刚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2017-07-28
Filing date: 2017-07-28
Publication date: 2021-08-24
Anticipated expiration: 2037-07-28
Also published as: CN109308930A

Abstract

The invention provides a data writing method, a memory control circuit unit and a memory storage device. The method comprises the following steps: transmitting a first data request command to the host system to obtain a plurality of data, wherein the plurality of data are arranged in the host system according to an order; according to a first data request command, acquiring first data in the plurality of data from the host system, and after acquiring the first data, continuously acquiring second data in the plurality of data from the host system; writing the first data to a corresponding physical page on a first word line of the plurality of word lines; and writing the second data to another corresponding physical page on a second word line of the word lines, wherein the first word line belongs to a first memory sub-module of the memory sub-modules, the second word line belongs to a second memory sub-module of the memory sub-modules, and the first data and the second data are not arranged consecutively in the sequence.

Description

Data writing method, memory control circuit unit and memory storage device

Technical Field

The invention relates to a data writing method, a memory control circuit unit and a memory storage device.

Background

Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory module (e.g., flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices as described above.

Generally, the rewritable nonvolatile memory module includes a plurality of word lines, and the memory cells on each word line form a plurality of physical pages for storing data. A memory controller of a memory storage device typically issues commands to a host system to obtain continuous data to be stored between a start location and an end location of the rewritable nonvolatile memory module according to the data to be stored in the start location and the end location.

In particular, if multiple word lines are written in parallel, the memory storage device usually requires a large amount of buffer memory space to temporarily store continuous data from the host system. And when the programming is executed, the memory controller selects the data of the corresponding entity page to be stored on each word line from the buffer memory space and writes the selected data into the entity page on each word line respectively so as to achieve the effect of parallel writing.

However, the above process usually consumes a large amount of buffer memory space, and thus, if the memory storage device is not configured with a large buffer memory, parallel writing cannot be performed, which affects the writing performance. Therefore, the technical aim of the technical field is to achieve the parallel writing speed of data and reduce the use amount of a buffer memory.

Disclosure of Invention

The invention provides a data writing method, a memory control circuit unit and a memory storage device, which can issue an instruction to obtain a plurality of discontinuous data which are respectively stored on different word lines from a host system, thereby avoiding the memory storage device from temporarily storing a large amount of continuous data to consume excessive resources and achieving the technical effect of simultaneously writing entity pages on a plurality of word lines.

The invention provides a data writing method, which is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of memory sub-modules which are respectively and electrically connected to a memory control circuit unit, the plurality of memory sub-modules comprise a plurality of word lines, a plurality of memory units on the same word line in the plurality of word lines form a plurality of entity pages, and the data writing method comprises the following steps: transmitting a first data request command to the host system to obtain a plurality of data, wherein the plurality of data are arranged in the host system according to an order; obtaining first data in the plurality of data from the host system according to the first data request instruction; after the first data is obtained, continuously obtaining second data in the plurality of data from the host system; writing first data to a corresponding physical page on a first word line of the plurality of word lines via a first data bus; and writing the second data to another corresponding physical page on a second word line of the word lines via a second data bus, wherein the first word line belongs to a first memory sub-module of the memory sub-modules, the second word line belongs to a second memory sub-module of the memory sub-modules, and the first data and the second data are arranged discontinuously in the sequence.

In an embodiment of the present invention, the first data includes first sub data and second sub data, the second data includes third sub data and fourth sub data, and the step of writing the first data into the corresponding physical page on the first word line of the word lines includes: the first sub data and the second sub data are written into the first physical page and the second physical page on the first word line respectively in sequence. Wherein writing the second data to another corresponding physical page on a second wordline of the plurality of wordlines comprises: and sequentially writing the third sub data and the fourth sub data into a third physical page and a fourth physical page on the second word line respectively.

In an embodiment of the invention, after the step of sequentially writing the third sub data and the fourth sub data into the third physical page and the fourth physical page on the second word line, respectively, the data writing method further includes: transmitting a second data request command to the host system; obtaining third data and fourth data in the plurality of data from the host system according to a second data request instruction; and sequentially writing fifth sub-data and sixth sub-data in the third data into a fifth physical page and a sixth physical page on the first word line, and sequentially writing seventh sub-data and eighth sub-data in the fourth data into a seventh physical page and an eighth physical page on the second word line, wherein the third data and the fourth data are discontinuous in the sequence of the plurality of data.

In an embodiment of the present invention, the first data and the third data are consecutive in the order of the plurality of data, and the second data and the fourth data are consecutive in the order of the plurality of data.

In an embodiment of the invention, the second data and the third data are consecutive in the sequence of the plurality of data.

In an embodiment of the invention, the first data request command instructs the host system to transmit first data of a corresponding physical page to be stored on the first word line and second data of another corresponding physical page to be stored on the second word line.

The invention provides a memory control circuit unit, which is used for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of memory sub-modules, the memory sub-modules comprise a plurality of word lines, a plurality of memory units on the same word line in the word lines form a plurality of entity pages, and the memory control circuit unit comprises: a host interface, a memory interface, and memory management circuitry. The host interface is electrically connected to the host system. The memory interface is electrically connected to the rewritable nonvolatile memory module, and the plurality of memory sub-modules are respectively electrically connected to the memory interface. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used for executing the following operations: transmitting a first data request command to the host system to obtain a plurality of data, wherein the plurality of data are arranged in the host system according to an order; obtaining first data in the plurality of data from the host system according to the first data request instruction; after the first data is obtained, continuously obtaining second data in the plurality of data from the host system; writing first data to a corresponding physical page on a first word line of the plurality of word lines via a first data bus; and writing the second data to another corresponding physical page on a second word line of the word lines via a second data bus, wherein the first word line belongs to a first memory sub-module of the memory sub-modules, the second word line belongs to a second memory sub-module of the memory sub-modules, and the first data and the second data are arranged discontinuously in the sequence.

In an embodiment of the invention, the first data includes first sub data and second sub data, and the second data includes third sub data and fourth sub data, wherein in the operation of writing the first data into the corresponding physical page on the first word line of the plurality of word lines, the memory management circuit sequentially writes the first sub data and the second sub data into the first physical page and the second physical page on the first word line, respectively. In the operation of writing the second data into another corresponding physical page on a second word line of the plurality of word lines, the memory management circuit sequentially writes the third sub-data and the fourth sub-data into the third physical page and the fourth physical page on the second word line, respectively.

In an embodiment of the invention, after the third sub data and the fourth sub data are sequentially written into the third physical page and the fourth physical page on the second word line, respectively, the memory management circuit transmits a second data request command to the host system. The memory management circuit obtains third data and fourth data from the host system according to the second data request command. The memory management circuit sequentially writes fifth sub-data and sixth sub-data of third data into a fifth physical page and a sixth physical page on the first word line, and sequentially writes seventh sub-data and eighth sub-data of fourth data into a seventh physical page and an eighth physical page on the second word line, wherein the third data and the fourth data are discontinuous in the sequence of the plurality of data.

The invention provides a memory storage device, comprising: the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit are connected. The connection interface unit is electrically connected to the host system. The rewritable nonvolatile memory module comprises a plurality of memory sub-modules, wherein the plurality of memory sub-modules comprise a plurality of word lines, and a plurality of memory units on the same word line in the plurality of word lines form a plurality of entity pages. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module, and the plurality of memory sub-modules are respectively electrically connected to the memory control circuit unit. The memory control circuit unit is used for executing the following operations: transmitting a first data request command to the host system to obtain a plurality of data, wherein the plurality of data are arranged in the host system according to an order; obtaining first data in the plurality of data from the host system according to the first data request instruction; after the first data is obtained, continuously obtaining second data in the plurality of data from the host system; writing first data to a corresponding physical page on a first word line of the plurality of word lines via a first data bus; and writing the second data to another corresponding physical page on a second word line of the word lines via a second data bus, wherein the first word line belongs to a first memory sub-module of the memory sub-modules, the second word line belongs to a second memory sub-module of the memory sub-modules, and the first data and the second data are arranged discontinuously in the sequence.

In an embodiment of the invention, the first data includes first sub data and second sub data, and the second data includes third sub data and fourth sub data, wherein in an operation of writing the first data into a corresponding physical page on a first word line of the plurality of word lines, the memory control circuit unit sequentially writes the first sub data and the second sub data into the first physical page and the second physical page on the first word line, respectively. In the operation of writing the second data into another corresponding physical page on a second word line of the word lines, the memory control circuit unit sequentially writes the third sub-data and the fourth sub-data into the third physical page and the fourth physical page on the second word line, respectively.

In an embodiment of the invention, after the third sub data and the fourth sub data are sequentially written into the third physical page and the fourth physical page on the second word line, respectively, the memory control circuit unit transmits a second data request command to the host system. The memory control circuit unit obtains third data and fourth data of the plurality of data from the host system according to the second data request command. The memory control circuit unit sequentially writes the fifth sub-data and the sixth sub-data of the third data into the fifth physical page and the sixth physical page on the first word line, and sequentially writes the seventh sub-data and the eighth sub-data of the fourth data into the seventh physical page and the eighth physical page on the second word line

And a plane in which the third data and the fourth data are discontinuous in the order of the plurality of data.

Based on the above, the data writing method, the memory control circuit unit and the memory storage device of the invention obtain a plurality of data which are not continuous and are respectively stored on different word lines from the host system by issuing the command, thereby avoiding the memory storage device from temporarily storing a large amount of continuous data to consume excessive resources, and achieving the technical effect of simultaneously writing the entity pages on the plurality of word lines.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device and an I/O device according to another example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention;

FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;

FIG. 7 is a flowchart illustrating a data writing method according to an exemplary embodiment of the present invention;

FIGS. 8A-8C are schematic diagrams illustrating a physical page for writing data onto word lines, respectively, according to an exemplary embodiment of the present invention;

FIG. 9 is a schematic diagram illustrating a physical page for writing data onto word lines, respectively, according to another exemplary embodiment of the present invention;

fig. 10 is a flowchart illustrating a data writing method according to another exemplary embodiment of the present invention.

The reference numbers illustrate:

30. 10: memory storage device

31. 11: host system

110: system bus

111: processor with a memory having a plurality of memory cells

112: random access memory

113: read-only memory

114: data transmission interface

12: input/output (I/O) device

20: main machine board

201: portable disk

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network interface card

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

32: SD card

33: CF card

34: embedded memory device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

502: memory management circuit

504: host interface

506: memory interface

508: error checking and correcting circuit

510: buffer memory

512: power management circuit

310: first memory sub-module

320: second memory sub-module

312: first block surface of first memory submodule

314: second block surface of first memory submodule

316. 326: data bus

322: first block surface of second memory submodule

324: second block surface of second memory submodule

410(0) - (410 (N), 420(0) - (420 (N), 430(0) - (430 (N), 440(0) - (440 (N)): physical erase unit

Step S701: transmitting a first data request command to a host system to obtain a plurality of data, the plurality of data being arranged in the host system according to an order

Step S703: obtaining a first data of the plurality of data from the host system according to the first data request command, and after obtaining the first data, continuing to obtain a second data of the plurality of data from the host system

Step S705: writing the first data into the corresponding physical page on the first word line

Step S707: writing the second data into another corresponding physical page on the second word line

WL1, WL2, WL3, WL 4: word line

P1(0), P1(1), P1(2), P1(3), P1(4), P1(5), P2(0), P2(1), P2(2), P2(3), P2(4), P2(5), P3(0), P3(1), P3(2), P3(3), P3(4), P3(5), P4(0), P4(1), P4(2), P4(3), P4(4), P4 (5): entity page

DATA0, DATA1, DATA2, DATA3, DATA4, DATA5, DATA6, DATA7, DATA8, DATA9, DATA10, DATA11, DATA12, DATA13, DATA14, DATA15, DATA16, DATA17, DATA18, DATA19, DATA20, DATA21, DATA22, DATA 23: sub data

Step S1001: transmitting a first data request command to a host system to obtain a plurality of data, the plurality of data being arranged in the host system according to an order

Step S1003: obtaining a first data of the plurality of data from the host system according to the first data request command, and after obtaining the first data, continuing to obtain a second data of the plurality of data from the host system

Step S1005: sequentially writing the first sub-data and the second sub-data of the first data into the first physical page and the second physical page on the first word line respectively

Step S1007: sequentially writing the third sub-data and the fourth sub-data in the second data into the third physical page and the fourth physical page on the second word line, respectively

Step S1009: transmitting a second data request command to the host system

Step S1011: a step of obtaining a third data and a fourth data from the host system according to a second data request command

Step S1013: sequentially writing the fifth sub-data and the sixth sub-data of the third data into the fifth physical page and the sixth physical page on the first word line, and sequentially writing the seventh sub-data and the eighth sub-data of the fourth data into the seventh physical page and the eighth physical page on the second word line

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another exemplary embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through the data transmission interface 114 in a wired or wireless manner. The memory storage device 10 may be, for example, a personal disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, Bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded Multi-Media Card (eMMC) 341 and/or embedded Multi-Chip Package (eMCP) memory device 342, which electrically connects the memory module directly to the embedded memory device on the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used to electrically connect the memory storage device 10 to the host system 11. In the exemplary embodiment, the connection interface unit 402 conforms to the Peripheral Component Interconnect Express (PCI Express) standard and is compatible with the NVM Express interface standard. In particular, the flash non-volatile memory interface standard is a protocol for communication between a host system and a memory device, which defines a temporary memory interface, an instruction set, and a function set between a controller of the memory storage device and an operating system of the host system, and facilitates data access speed and data transfer rate of the memory storage device based on a PCIe interface by optimizing the interface standard of the memory storage device. However, in other exemplary embodiments, the connection interface unit 402 may conform to other suitable standards. In addition, the connection interface unit 402 can be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 is disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In the exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical programming cells, and the physical programming cells form a plurality of physical erasing cells. Specifically, the memory cells on the same word line constitute one or more physical programming cells. If each memory cell can store more than 2 bits, the physical programming cells on the same word line can be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.

In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundancy bit region stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit region includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other exemplary embodiments, the data bit region may include 8, 16 or more or less physical fans, and the size of each physical fan may be larger or smaller. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, the physical erase unit is a physical block (block).

FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention.

Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.

In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are programmed into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another example embodiment, the control instructions of the memory management circuit 502 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is electrically connected to the memory management circuit 502 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the command sequences may include a write command sequence for indicating data to be written, a read command sequence for indicating data to be read, an erase command sequence for indicating data to be erased, and corresponding command sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes the read identification code, the memory address, and other information.

In an exemplary embodiment, the memory control circuitry 404 further includes error checking and correction circuitry 508, buffer memory 510, and power management circuitry 512.

The error checking and correcting circuit 508 is electrically connected to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.

The buffer memory 510 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.

FIG. 6 is a schematic block diagram of a rewritable nonvolatile memory module according to a first exemplary embodiment of the present invention.

Referring to FIG. 6, the rewritable nonvolatile memory module 406 includes a first memory sub-module 310 and a second memory sub-module 320. For example, the first memory sub-module 310 and the second memory sub-module 320 are memory dies (die), respectively. The first memory sub-module 310 has a first block face 312 and a second block face 314 and the second memory sub-module 320 has a first block face 322 and a second block face 324. The first block surface 312 of the first memory sub-module 310 has erase units 410(0) -410 (N), the second block surface 314 of the first memory sub-module 310 has erase units 420(0) -420 (N), the first block surface 322 of the second memory sub-module 320 has erase units 430(0) -430 (N), and the second block surface 324 of the second memory sub-module 320 has erase units 440(0) -440 (N).

For example, the first memory sub-module 310 and the second memory sub-module 320 are electrically connected to the memory control circuit unit 404 through the independent data bus 316 and the independent data bus 326, respectively. Accordingly, the memory management circuit 502 may write data to the first memory submodule 310 and the second memory submodule 320 through the data bus 316 and the data bus 326 in a parallel (parallel) manner.

However, it should be understood that, in another exemplary embodiment of the invention, the first memory sub-module 310 and the second memory sub-module 320 may also be electrically connected to the memory control circuit unit 404 only through 1 data bus. Here, the memory management circuit 502 may write data to the first memory sub-module 310 and the second memory sub-module 320 through a single data bus in an interleaved (interleave) manner.

In particular, the first memory sub-module 310 and the second memory sub-module 320 may include a plurality of word lines, and the plurality of memory cells on the same word line form a plurality of physical pages. Each of the physically erased cells of the first and

second memory sub-modules

310 and 320 has a plurality of physical pages, wherein the physical pages belonging to the same physically erased cell can be written independently and erased simultaneously. For example, each physical erase unit consists of 128 physical pages. However, it should be understood that the present invention is not limited thereto, and each physical erase unit can be composed of 64 physical pages, 256 physical pages, or any other physical pages.

In more detail, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. The physical page is the smallest unit of programming. That is, the physical page is the smallest unit of write data. However, it should be understood that in another exemplary embodiment of the present invention, the minimum unit of the written data may be a Sector (Sector) or other size. Each physical page typically includes a data bit region and a redundancy bit region. The data bit region is used for storing user data, and the redundancy bit region is used for storing system data (such as error checking and correcting codes). It should be noted that, in another exemplary embodiment, a physically erased cell may also refer to a physical address, a physically programmed cell, or consist of multiple continuous or discontinuous physical addresses.

It should be noted that although the exemplary embodiment of the invention is described by taking the rewritable nonvolatile memory module 406 including 2 memory sub-modules as an example, the invention is not limited thereto.

In the present exemplary embodiment, the memory management circuit 502 may issue a data request command to the host system 11. The data request command instructs the host system 11 to transmit a first data of a corresponding physical page to be stored on a word line of the rewritable non-volatile memory module 406 and a second data of another corresponding physical page to be stored on another word line of the rewritable non-volatile memory module 406. The word line for writing the first data belongs to a first memory sub-module, the word line for writing the second data belongs to a second memory sub-module, and the first memory sub-module is different from the second memory sub-module. The first data and the second data may be two data that are not consecutive to each other among a plurality of consecutive data. That is, in the present exemplary embodiment, the memory management circuit 502 may issue a data request command to the host system 11 according to the position where the data is actually stored in the physical page, so as to directly obtain the corresponding data for writing, instead of obtaining all the data according to the original arrangement order of the data. Thus, the memory management circuit 502 can directly acquire the data required for the current write to the host system 11 without acquiring all the data and temporarily storing all the data in the buffer memory 510 before selecting the data, so that the usage amount of the buffer memory 510 can be reduced.

Fig. 7 is a flowchart illustrating a data writing method according to an exemplary embodiment of the invention.

Referring to fig. 7, in step S701, the memory management circuit 502 transmits at least one first data request command to the host system 11 to obtain first data and second data of a plurality of data, wherein the plurality of data are arranged according to an order in the host system, and the order of the first data and the second data in the plurality of data is not sequential. The first data request command instructs the host system 11 to transmit first data of a corresponding physical page to be stored on a first word line and second data of another corresponding physical page to be stored on a second word line. In step S703, the memory management circuit 502 obtains a first data of the plurality of data from the host system 11 according to the first data request command, and subsequently obtains a second data of the plurality of data from the host system 11 after obtaining the first data. Thereafter, in step S705, the memory management circuit 502 writes the first data into the corresponding physical page on the first word line. Finally, in step S707, the memory management circuit 502 writes the second data into another corresponding physical page on the second word line. In particular, the first word line belongs to a first memory sub-module, the second word line belongs to a second memory sub-module, and the first memory sub-module is different from the second memory sub-module.

The data writing process of the data writing method of the present application is described in more detail with reference to the following embodiments.

Fig. 8A to 8C are schematic diagrams illustrating a physical page for writing a plurality of data onto a plurality of word lines, respectively, according to an exemplary embodiment of the present invention.

Referring to fig. 8A to 8C, in the present exemplary embodiment, it is assumed that the rewritable nonvolatile memory module 406 is a Three-dimensional (3D) NAND flash memory module, and the memory cells on each word line in the rewritable nonvolatile memory module 406 can form four physical pages. As shown in fig. 8A, the rewritable nonvolatile memory module 406 may include, for example, a word line WL1 (also referred to as a first word line) belonging to a first memory sub-module and a word line WL2 (also referred to as a second word line) belonging to a second memory sub-module. The memory cells on the word line WL1 form the physical pages P1(0) to P1(3), and the memory cells on the word line WL2 form the physical pages P2(0) to P2 (3).

It is assumed that the memory management circuit 502 writes a plurality of consecutive data into the physical pages on the word line WL1 and the word line WL 2. The plurality of continuous data comprise first data, second data, third data and fourth data, and the arrangement sequence of the plurality of data is the first data, the third data, the second data and the fourth data in sequence. The first DATA includes sub DATA0 and sub DATA1, the third DATA includes sub DATA2 and sub DATA3, the second DATA includes sub DATA4 and sub DATA5, and the fourth DATA includes sub DATA6 and sub DATA 7. That is, from the viewpoint of the sub-DATA, the arrangement order of the sub-DATA is the sub-DATA 0, the sub-DATA 1, the sub-DATA 2, the sub-DATA 3, the sub-DATA 4, the sub-DATA 5, the sub-DATA 6, and the sub-DATA 7 in this order.

When the memory management circuit 502 is to write physical pages on the word line WL1 and the word line WL2 in parallel, the memory management circuit 502 sends at least one data request command (also referred to as a first data request command) to the host system 11 to request the host system 11 to send data of the physical pages P1(0) and P1(1) to be stored on the word line WL1 and data of the physical pages P2(0) and P2(1) to be stored on the word line WL 2.

Next, referring to fig. 8B, the memory management circuit 502 obtains the first data and the second data of the plurality of continuous data from the host system 11 according to the first data request command. The first DATA includes sub DATA0 (also referred to as first sub DATA) to be written into the physical page P1(0) on the word line WL1 and sub DATA1 (also referred to as second sub DATA) to be written into the physical page P1(1) on the word line WL 1. The second DATA includes sub DATA4 (also referred to as third sub DATA) to be written in the physical page P2(0) on the word line WL2 and sub DATA5 (also referred to as fourth sub DATA) to be written in the physical page P2(1) on the word line WL 2. That is, the first data request command is used to obtain the first data and the second data which are not consecutive in the plurality of consecutive data. Thereafter, the memory management circuit 502 can sequentially write the sub-DATA 0 and the sub-DATA 1 into the physical page P1(0) (also referred to as a first physical page) and the physical page P1(1) (also referred to as a second physical page), respectively. Similarly, the memory management circuit 502 can sequentially write the sub DATA4 and the sub DATA5 to the physical page P2(0) (also referred to as a third physical page) and the physical page P2(1) (also referred to as a fourth physical page), respectively.

Thereafter, the memory management circuit 502 may send at least one data request command (also referred to as a second data request command) to the host system 11 to request the host system 11 to send the data to be stored in the physical pages P1(2) and P1(3) on the word line WL1 and the data to be stored in the physical pages P2(2) and P2(3) on the word line WL 2.

Referring to fig. 8C, the memory management circuit 502 may obtain the third data and the fourth data of the plurality of consecutive data from the host system 11 according to the second data request command. The third DATA includes sub DATA2 (also referred to as fifth sub DATA) for writing into the physical page P1(2) on the word line WL1 and sub DATA3 (also referred to as sixth sub DATA) for writing into the physical page P1(3) on the word line WL 1. The fourth DATA includes sub DATA6 (also referred to as seventh sub DATA) for writing into the physical page P2(2) on the word line WL2 and sub DATA7 (also referred to as eighth sub DATA) for writing into the physical page P2(3) on the word line WL 2. That is, the second data request command is used to obtain the third data and the fourth data which are not consecutive in the plurality of consecutive data. Thereafter, the memory management circuit 502 may sequentially write the sub DATA2 and the sub DATA3 to the physical page P1(2) (also referred to as a fifth physical page) and the physical page P1(3) (also referred to as a sixth physical page), respectively. Similarly, the memory management circuit 502 can sequentially write the sub DATA6 and the sub DATA7 into the physical page P2(2) (also referred to as a seventh physical page) and the physical page P2(3) (also referred to as an eighth physical page), respectively.

In particular, after the writing, the third data stored in the end physical pages P1(2) to P1(3) of the word line WL (1) is continued to the second data stored in the beginning physical pages P2(0) to P2(1) of the word line WL (2). That is, after the write operation, data is sequentially stored in the word line WL1 and the word line WL 2.

It should be noted, however, that the present invention is not limited to the number of physical pages on a word line. In other embodiments, a word line may include more or fewer physical pages.

FIG. 9 is a diagram illustrating a physical page on which data are written onto word lines, respectively, according to another exemplary embodiment of the invention.

Referring to fig. 9, in the present exemplary embodiment, it is assumed that the rewritable nonvolatile memory module 406 is a Three-dimensional (3D) NAND flash memory module, and memory cells on each word line in the rewritable nonvolatile memory module 406 form six physical pages. As shown in fig. 9, the rewritable nonvolatile memory module 406 may include, for example, a word line WL1, a word line WL2, a word line WL3, and a word line WL 4. The memory cells on the word line WL1 form the physical pages P1(0) to P1(5), the memory cells on the word line WL2 form the physical pages P2(0) to P2(5), the memory cells on the word line WL3 form the physical pages P3(0) to P3(5), and the memory cells on the word line WL4 form the physical pages P4(0) to P4 (5). The word line WL1, the word line WL2, the word line WL3, and the word line WL4 belong to different memory sub-modules. For example, word line WL1 belongs to a first memory sub-module, word line WL2 belongs to a second memory sub-module, word line WL3 belongs to a third memory sub-module, and word line WL4 belongs to a fourth memory sub-module.

When the memory management circuit 502 is to write the physical pages on the word line WL1, the word line WL2, the word line WL3, and the word line WL4 in parallel, the memory management circuit 502 sends at least one data request command to the host system 11 to request the host system 11 to send data to be stored in the physical pages P1(0) -P1 (1) on the word line WL1, data to be stored in the physical pages P2(0) -P2 (1) on the word line WL2, data to be stored in the physical pages P3(0) -P3 (1) on the word line WL3, and data to be stored in the physical pages P4(0) -P4 (1) on the word line WL 4.

The memory management circuit 502 can obtain, from the host system 11, the sub DATA0 and the sub DATA1 to be written into the physical pages P1(0) to P1(1) on the word line WL1, the sub DATA6 and the sub DATA7 to be written into the physical pages P2(0) to P2(1) on the word line WL2, the sub DATA12 and the sub DATA13 to be written into the physical pages P3(0) to P3(1) on the word line WL3, and the sub DATA18 and the sub DATA19 to be written into the physical pages P4(0) to P4(1) on the word line WL4, in accordance with a DATA request command sent to the host system 11.

Thereafter, the memory management circuit 502 may sequentially write the sub DATA0, the sub DATA1, the sub DATA6, the sub DATA7, the sub DATA12, the sub DATA13, the sub DATA18, and the sub DATA19 into the entity page P1(0), the entity page P1(1), the entity page P2(0), the entity page P2(1), the entity page P3(0), the entity page P3(1), the entity page P4(0), and the entity page P4(1), respectively.

Then, the memory management circuit 502 sends at least one data request command to the host system 11 to request the host system 11 to send the data to be stored in the physical pages P1(2) -P1 (3) on the word line WL1, the data to be stored in the physical pages P2(2) -P2 (3) on the word line WL2, the data to be stored in the physical pages P3(2) -P3 (3) on the word line WL3, and the data to be stored in the physical pages P4(2) -P4 (3) on the word line WL 4.

The memory management circuit 502 may obtain, from the host system 11, the sub DATA2 and the sub DATA3 to be written to the physical page P1(2) to P1(3) on the word line WL1, the sub DATA8 and the sub DATA9 to be written to the physical page P2(2) to P2(3) on the word line WL2, the sub DATA14 and the sub DATA15 to be written to the physical page P3(2) to P3(3) on the word line WL3, and the sub DATA20 and the sub DATA21 to be written to the physical page P4(2) to P4(3) on the word line WL4, in accordance with a DATA request command sent to the host system 11.

Thereafter, the memory management circuit 502 may sequentially write the sub DATA2, the sub DATA3, the sub DATA8, the sub DATA9, the sub DATA14, the sub DATA15, the sub DATA20, and the sub DATA21 into the entity page P1(2), the entity page P1(3), the entity page P2(2), the entity page P2(3), the entity page P3(2), the entity page P3(3), the entity page P4(2), and the entity page P4(3), respectively.

Thereafter, the memory management circuit 502 may transmit at least one data request command to the host system 11 to request the host system 11 to transmit data to be stored in the physical pages P1(4) -P1 (5) on the word line WL1, data to be stored in the physical pages P2(4) -P2 (5) on the word line WL2, data to be stored in the physical pages P3(4) -P3 (5) on the word line WL3, and data to be stored in the physical pages P4(4) -P4 (5) on the word line WL 4.

The memory management circuit 502 may obtain, from the host system 11, the sub DATA4 and the sub DATA5 to be written to the physical page P1(4) to P1(5) on the word line WL1, the sub DATA10 and the sub DATA11 to be written to the physical page P2(4) to P2(5) on the word line WL2, the sub DATA16 and the sub DATA17 to be written to the physical page P3(4) to P3(5) on the word line WL3, and the sub DATA22 and the sub DATA23 to be written to the physical page P4(4) to P4(5) on the word line WL4, in accordance with a DATA request command sent to the host system 11.

Thereafter, the memory management circuit 502 may sequentially write the sub DATA4, the sub DATA5, the sub DATA10, the sub DATA11, the sub DATA16, the sub DATA17, the sub DATA22, and the sub DATA23 into the entity page P1(4), the entity page P1(5), the entity page P2(4), the entity page P2(5), the entity page P3(4), the entity page P3(5), the entity page P4(4), and the entity page P4(5), respectively.

In particular, the above-described order relationship among the sub-DATA is, in order, sub-DATA 0, sub-DATA 1, sub-DATA 2, sub-DATA 3, sub-DATA 4, sub-DATA 5, sub-DATA 6, sub-DATA 7, sub-DATA 8, sub-DATA 9, sub-DATA 10, sub-DATA 11, sub-DATA 12, sub-DATA 13, sub-DATA 14, sub-DATA 15, sub-DATA 16, sub-DATA 17, sub-DATA 18, sub-DATA 19, sub-DATA 20, sub-DATA 21, sub-DATA 22, and sub-DATA 23. As can be seen from the above, the memory management circuit 502 can obtain discontinuous data from the host system 11 and write data to each word line at a time. As can be seen from the contents of fig. 9, after the write operation is performed, the sub-DATA 6 and DATA7 of the physical pages P2(0) to P2(1) stored on the word line WL2 are the sub-DATA 4 and DATA5 which are connected to the physical pages P1(4) to P1(5) stored on the word line WL 1. The sub-DATA DATA12 and DATA13 stored in the physical pages P3(0) to P3(1) on the word line WL3 are the sub-DATA DATA10 and DATA11 continuing to the physical pages P2(4) to P2(5) on the word line WL 2. The sub-DATA DATA18 and DATA19 stored in the physical pages P4(0) to P4(1) on the word line WL4 are the sub-DATA DATA16 and DATA17 continuing to the physical pages P3(4) to P3(5) on the word line WL 3.

Referring to fig. 10, in step S1001, the memory management circuit 502 transmits a first data request command to the host system 11 to obtain a first data and a second data of a plurality of data, wherein the plurality of data are arranged according to an order in the host system, and the order of the first data and the second data in the plurality of data is not consecutive. The first data request command instructs the host system to transmit first data for storing a corresponding physical page on a first word line and second data for storing another corresponding physical page on a second word line. In step S1003, the memory management circuit 502 obtains the first data of the plurality of data from the host system 11 according to the first data request command, and subsequently obtains the second data of the plurality of data from the host system 11 after obtaining the first data. In step S1005, the memory management circuit 502 sequentially writes the first sub data and the second sub data of the first data into the first physical page and the second physical page on the first word line, respectively. In step S1007, the memory management circuit 502 sequentially writes the third sub data and the fourth sub data of the second data into the third physical page and the fourth physical page on the second word line, respectively. In step S1009, the memory management circuit 502 transmits a second data request instruction to the host system 11. In step S1011, the memory management circuit 502 obtains, from the host system 11, third data and fourth data of a plurality of data in which the order of the third data and the fourth data is not consecutive, the order of the first data and the third data is consecutive, and the order of the second data and the fourth data is consecutive, in accordance with the second data request command. In step S1013, the memory management circuit 502 sequentially writes the fifth sub-data and the sixth sub-data of the third data into the fifth physical page and the sixth physical page on the first word line, and sequentially writes the seventh sub-data and the eighth sub-data of the fourth data into the seventh physical page and the eighth physical page on the second word line. In particular, the first word line belongs to a first memory sub-module, the second word line belongs to a second memory sub-module, and the first memory sub-module is different from the second memory sub-module.

It is noted that, assuming that the fifth physical page and the sixth physical page on the first word line are the last two physical pages on the first word line, the second data stored in the fifth physical page and the sixth physical page in the sequence of the plurality of data is the third data stored in the first two physical pages (i.e., the third physical page and the fourth physical page) on the second word line.

In summary, the data writing method, the memory control circuit unit and the memory storage device of the invention can issue the command to obtain the plurality of data which are not continuous and are respectively stored on different word lines from the host system, thereby avoiding the memory storage device from temporarily storing a large amount of continuous data to consume excessive resources, and achieving the technical effect of simultaneously writing the entity pages on the plurality of word lines.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A data writing method is used for a rewritable nonvolatile memory module of a memory storage device, the rewritable nonvolatile memory module comprises a plurality of memory sub-modules which are respectively and electrically connected to a memory control circuit unit, the plurality of memory sub-modules comprise a plurality of word lines, and a plurality of memory units on the same word line in the plurality of word lines form a plurality of entity pages, and the data writing method is characterized by comprising the following steps:

transmitting at least one first data request command to a host system to obtain a plurality of data, wherein the plurality of data are arranged in the host system according to an order;

according to the first data request command, directly obtaining first data in the plurality of data from the host system through a connection interface unit of the memory storage device, and

transmitting at least one second data request command to the host system;

obtaining third data and fourth data in the plurality of data from the host system according to the second data request instruction;

after the first data is obtained, directly obtaining second data in the plurality of data from the host system through the connection interface unit to reduce the usage amount of a buffer memory of the memory storage device;

writing the first data to a first physical page and a second physical page on a first wordline of the plurality of wordlines via a first data bus, the first wordline belonging to a first memory sub-module of the plurality of memory sub-modules; and

writing the second data to a third physical page and a fourth physical page on a second wordline of the plurality of wordlines via a second data bus, the second wordline belonging to a second memory sub-module of the plurality of memory sub-modules,

writing the third data to a fifth physical page and a sixth physical page on a first wordline of the plurality of wordlines via the first data bus;

writing the fourth data to a seventh physical page and an eighth physical page on a second wordline of the plurality of wordlines via the second data bus,

wherein the third data and the second data are arranged consecutively in the order.

2. The data writing method according to claim 1, wherein the first data includes first sub data and second sub data, the second data includes third sub data and fourth sub data,

wherein writing the first data to a corresponding physical page on the first one of the plurality of word lines comprises:

sequentially writing the first sub data and the second sub data into a first physical page and a second physical page on the first word line respectively,

wherein writing the second data to another corresponding physical page on the second one of the word lines comprises:

and sequentially writing the third sub data and the fourth sub data into a third physical page and a fourth physical page on the second word line respectively.

3. The data writing method according to claim 2, wherein the third data includes fifth sub data and sixth sub data, and the fourth data includes seventh sub data and eighth sub data, and after the step of sequentially writing the third sub data and the fourth sub data into the third physical page and the fourth physical page on the second word line, respectively, the data writing method further comprises:

sequentially writing the fifth sub-data and the sixth sub-data of the third data into the fifth physical page and the sixth physical page on the first word line, and sequentially writing the seventh sub-data and the eighth sub-data of the fourth data into the seventh physical page and the eighth physical page on the second word line,

wherein the third data and the fourth data are discontinuous in the order of the plurality of data.

4. The data writing method according to claim 3, wherein the first data and the third data are consecutive in the order of the plurality of data, and the second data and the fourth data are consecutive in the order of the plurality of data.

5. The data writing method of claim 1, wherein the first data request command instructs the host system to transmit the first data of a corresponding physical page to be stored on the first word line and the second data of another corresponding physical page to be stored on the second word line.

6. A memory control circuit unit for controlling a rewritable nonvolatile memory module of a memory storage device, wherein the rewritable nonvolatile memory module comprises a plurality of memory sub-modules, the plurality of memory sub-modules comprises a plurality of word lines, and a plurality of memory cells on the same word line among the plurality of word lines form a plurality of physical pages, the memory control circuit unit comprising:

a host interface for electrically connecting to a host system;

the memory interface is used for being electrically connected to the rewritable nonvolatile memory module, and the plurality of memory sub-modules are respectively and electrically connected to the memory interface;

a memory management circuit electrically connected to the host interface and the memory interface,

wherein the memory management circuit is configured to send at least one first data request command to the host system to obtain a plurality of data, and the plurality of data are arranged in an order in the host system,

wherein the memory management circuit is further configured to obtain a first data of the plurality of data directly from the host system through a connection interface unit of the memory storage device according to the first data request command, and

wherein the memory management circuit is further configured to transmit at least one second data request command to the host system;

wherein the memory management circuit is further configured to obtain third data and fourth data of the plurality of data from the host system according to the second data request command;

wherein the memory management circuit is further configured to obtain second data of the plurality of data directly from the host system through the connection interface unit after obtaining the first data, so as to reduce the usage amount of a buffer memory of the memory storage device,

wherein the memory management circuit is further configured to write the first data to a first physical page and a second physical page on a first wordline of the plurality of wordlines via a first data bus, the first wordline belonging to a first memory sub-module of the plurality of memory sub-modules,

wherein the memory management circuit is further configured to write the second data to a third physical page and a fourth physical page on a second wordline of the plurality of wordlines via a second data bus, the second wordline belonging to a second memory sub-module of the plurality of memory sub-modules,

wherein the memory management circuit is further configured to write the third data to a fifth physical page and a sixth physical page on a first word line of the plurality of word lines via the first data bus;

wherein the memory management circuit is further configured to write the fourth data to a seventh physical page and an eighth physical page on a second word line of the plurality of word lines via the second data bus,

7. The memory control circuit unit of claim 6, wherein the first data includes first sub data and second sub data, the second data includes third sub data and fourth sub data,

wherein writing the first data to a corresponding physical page on the first one of the word lines,

the memory management circuit is further configured to sequentially write the first sub data and the second sub data into a first physical page and a second physical page on the first word line,

wherein the writing of the second data to another corresponding physical page on the second one of the plurality of word lines,

the memory management circuit is further configured to sequentially write the third sub data and the fourth sub data into a third physical page and a fourth physical page on the second word line, respectively.

8. The memory control circuit unit of claim 7, wherein the third data comprises a fifth sub-data and a sixth sub-data, the fourth data comprises a seventh sub-data and an eighth sub-data, and after the operations of sequentially writing the third sub-data and the fourth sub-data into the third physical page and the fourth physical page on the second word line respectively,

the memory management circuit is further configured to sequentially write a fifth sub-data and a sixth sub-data of the third data to a fifth physical page and a sixth physical page on the first word line, and sequentially write a seventh sub-data and an eighth sub-data of the fourth data to a seventh physical page and an eighth physical page on the second word line,

9. The memory control circuit unit according to claim 8, wherein the first data and the third data are consecutive in the order of the plurality of data, and the second data and the fourth data are consecutive in the order of the plurality of data.

10. The memory control circuit unit of claim 6, wherein the first data request command instructs the host system to transfer the first data of a corresponding physical page to be stored on the first word line and the second data of another corresponding physical page to be stored on the second word line.

11. A memory storage device, comprising:

the connection interface unit is used for electrically connecting to a host system;

the rewritable nonvolatile memory module comprises a plurality of memory sub-modules, wherein the memory sub-modules comprise a plurality of word lines, and a plurality of memory units on the same word line in the word lines form a plurality of entity pages; and

a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module, and the plurality of memory sub-modules are respectively electrically connected to the memory control circuit unit,

wherein the memory control circuit unit is configured to send at least a first data request command to the host system to obtain a plurality of data, and the plurality of data are arranged in an order in the host system,

wherein the memory control circuit unit is further configured to obtain a first data of the plurality of data directly from the host system through the connection interface unit according to the first data request command, and

wherein the memory control circuit unit is further configured to transmit at least one second data request command to the host system;

wherein the memory control circuit unit is further configured to obtain third data and fourth data of the plurality of data from the host system according to the second data request command;

wherein the memory control circuit unit is further configured to directly obtain second data of the plurality of data from the host system through the connection interface unit after obtaining the first data, so as to reduce the usage amount of a buffer memory of the memory storage device,

wherein the memory control circuit unit is further configured to write the first data to a first physical page and a second physical page on a first word line of the plurality of word lines via a first data bus, the first word line belonging to a first memory sub-module of the plurality of memory sub-modules,

wherein the memory control circuit unit is further configured to write the second data to a third physical page and a fourth physical page on a second word line of the plurality of word lines via a second data bus, the second word line belonging to a second memory sub-module of the plurality of memory sub-modules,

wherein the memory control circuit unit is further configured to write the third data to a fifth physical page and a sixth physical page on a first word line of the plurality of word lines via the first data bus;

wherein the memory control circuit unit is further configured to write the fourth data to a seventh physical page and an eighth physical page on a second word line of the plurality of word lines via the second data bus,

12. The memory storage device of claim 11, wherein the first data comprises first sub data and second sub data, the second data comprises third sub data and fourth sub data,

the memory control circuit unit is further configured to sequentially write the first sub data and the second sub data into a first physical page and a second physical page on the first word line,

the memory control circuit unit is further configured to sequentially write the third sub data and the fourth sub data into a third physical page and a fourth physical page on the second word line, respectively.

13. The memory storage device of claim 12, wherein the third data comprises a fifth sub-data and a sixth sub-data, the fourth data comprises a seventh sub-data and an eighth sub-data, and after sequentially writing the third sub-data and the fourth sub-data to the third physical page and the fourth physical page on the second word line, respectively,

the memory control circuit unit is further configured to sequentially write a fifth sub-data and a sixth sub-data of the third data into a fifth physical page and a sixth physical page on the first word line, and sequentially write a seventh sub-data and an eighth sub-data of the fourth data into a seventh physical page and an eighth physical page on the second word line,

14. The memory storage device according to claim 13, wherein the first data and the third data are consecutive in the order of the plurality of data, and the second data and the fourth data are consecutive in the order of the plurality of data.

15. The memory storage device of claim 11, wherein the first data request command instructs the host system to transfer the first data of a corresponding physical page to be stored on the first wordline and the second data of another corresponding physical page to be stored on the second wordline.