CN102890617B - Memory control method, memory controller and memory storage device - Google Patents
Memory control method, memory controller and memory storage device Download PDFInfo
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- CN102890617B CN102890617B CN201110200388.6A CN201110200388A CN102890617B CN 102890617 B CN102890617 B CN 102890617B CN 201110200388 A CN201110200388 A CN 201110200388A CN 102890617 B CN102890617 B CN 102890617B
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Abstract
The invention provides a memory control method, a memory controller and a memory storage device. The method comprises the steps of identifying whether a transmission mode between the memory storage device and a host computer system belongs to a first transmission mode or a second transmission mode, and grouping memory chips of the memory storage device into a plurality of memory chip groups. The method also comprises the steps of erasing data stored in the memory chips by a first erase mode when the transmission mode belongs to the first transmission mode, and erasing the data stored in the memory chips by a second erase mode when the transmission mode belongs to the second transmission mode, wherein at least one part of memory chip groups in the first erase mode can be simultaneously enabled, and any two memory chip groups in the second erase mode are not simultaneously enabled.
Description
Technical field
The present invention relates to Memory Controller and the memorizer memory devices of a kind of memory control methods for type nonvolatile module and implementation the method.
Background technology
Digital camera, mobile phone and MP3 are very rapid in growth over the years, and the demand of consumer to Storage Media is also increased rapidly.Because type nonvolatile (rewritablenon-volatile memory) has the little characteristic with mechanical structure etc. of data non-volatile, power saving, volume, be applicable to portable applications, be the most applicablely used on the battery-powered product of this kind of Portable.Portable disk is exactly a kind of storage device using type nonvolatile as Storage Media.Because type nonvolatile volume low capacity is large, so be widely used in the storage of individual significant data.Therefore, type nonvolatile industry becomes a ring quite popular in electronic industry in recent years.
Memory chip in memorizer memory devices has multiple physical blocks (physicalblock), and each physical blocks has multiple physical page (physical page), when wherein writing data in physical blocks, data must be write in order according to the order of physical page.In general, write data to the program of physical page and can divide into instruction and data transmit (transfer) and data programing (program) two parts.Specifically, in for the physical page at memory chip during storage data, first instruction and data can transfer in the buffer zone in memory chip by the control circuit of memorizer memory devices.Afterwards, storage core sector-meeting by the data programing (that is, write) in buffer zone in the page.During the control circuit of memorizer memory devices transfers data to memory chip, memory chip is in a transmission state.Further, during data are programmed to physical page, memory chip is in one busy (busy) state.
In order to promote the writing speed of memorizer memory devices, memorizer memory devices can configure multiple memory chip and in an interleaved manner or parallel mode to write data.Such as, to be configured with the memorizer memory devices of first and second memory chip coupled via a data input/output bus and control circuit, when (namely host computer system for storing many page datas in memorizer memory devices, data length is the data being greater than 1 page) time, one of them page data can be transferred to first memory chip by control circuit.Afterwards, during first memory chip is in busy condition, another page data can be transferred to second memory chip by control circuit.Then, when second memory chip is in busy condition, another page data can be transferred to first memory chip by control circuit, alternately the page data for write is transferred to first memory chip and second memory chip thus, to shorten the time of write data.
Particularly, when memory chip is in transmission state or busy condition, storage core sector-meeting needs power supply to perform transmission or programming.But, the electric power provided for usage data transmission interface is as the memory card of main power source or Portable disk, when many memory chips together enable (namely, be in busy condition or transmission state) time, the electric power that data transmission interface provides may be not enough and cause and write unsuccessfully.
Similarly, the program of the data in physical page of erasing block also can be divided into command and data and to erase two parts.But memory chip performs data and erases required electric power much larger than the electric power performed needed for data write.Therefore, developing a kind of memory control methods, so that under use interlace mode or parallel mode write data, can avoid the instability caused because electric power is not enough when performing and erasing instruction, is have it necessary.
Summary of the invention
The invention provides a kind of memory control methods, Memory Controller and memorizer memory devices, it take into account under write usefulness, can avoid performing the instability caused because electric power is not enough when erasing instruction.
Exemplary embodiment of the present invention proposes a kind of memory control methods, for memorizer memory devices, wherein this memorizer memory devices has type nonvolatile module and this type nonvolatile module has multiple memory chip.This memory control methods comprises transmission mode between recognition memory storage device and host computer system for belonging to the first transmission mode or the second transmission mode, and memory chip is grouped into multiple memory chip group.This memory control methods also comprises, when transmission mode is for belonging to the first transmission mode, first pattern of erasing of use is erased the multiple data be stored in this little memory chip, wherein can be enabled in first at least part of memory chip group of erasing in pattern among this little memory chip group simultaneously.This memory control methods also comprises, when transmission mode is for belonging to the second transmission mode, second pattern of erasing of use is erased the data be stored in this little memory chip, wherein can not be enabled in second any two memory chip groups of erasing in pattern among this little memory chip group simultaneously.
In one example of the present invention embodiment, above-mentioned memory chip comprises the 0th memory chip, first memory chip, second memory chip, 3rd memory chip, 4th memory chip, 5th memory chip, 6th memory chip and the 7th memory chip, wherein the 0th memory chip and first memory chip are coupled to the Memory Controller of memorizer memory devices via zero data input/output bus, second memory chip and the 3rd memory chip are coupled to Memory Controller via the first data input/output bus, 4th memory chip and the 5th memory chip are coupled to Memory Controller via the second data input/output bus, 6th memory chip and the 7th memory chip are coupled to Memory Controller via the 3rd data input/output bus.In addition, above-mentioned step memory chip being grouped into memory chip group comprises: the 0th memory chip, second memory chip, the 4th memory chip and the 6th memory chip are grouped into the 0th memory chip group; And first memory chip, the 3rd memory chip, the 5th memory chip and the 7th memory chip are grouped into first memory chipset.
In one example of the present invention embodiment, the erase step of the data be stored in memory chip of above-mentioned use first pattern of erasing comprises: synchronously assign one to the 0th memory chip of the 0th memory chip group, second memory chip, the 4th memory chip and the 6th memory chip and to erase instruction; And perform this at the 0th memory chip, second memory chip, the 4th memory chip and the 6th memory chip and erase between order period, synchronously instruction of erasing is assigned to the 4th memory chip of first memory chipset, the 5th memory chip, the 6th memory chip and the 7th memory chip.
In one example of the present invention embodiment, the erase step of the data be stored in memory chip of above-mentioned use second pattern of erasing comprises: synchronously assign instruction of erasing to the 0th memory chip of the 0th memory chip group, second memory chip, the 4th memory chip and the 6th memory chip; And after the 0th memory chip, second memory chip, the 4th memory chip and the 6th memory chip complete this instruction of erasing, synchronously instruction of erasing is assigned to the 4th memory chip of first memory chipset, the 5th memory chip, the 6th memory chip and the 7th memory chip.
In one example of the present invention embodiment, above-mentioned memory control methods also comprises: at least part of memory chip group simultaneously among enable above-mentioned memory chip group writes the write data coming from host computer system.
In one example of the present invention embodiment, above-mentioned memory control methods also comprises, transmission mode between memorizer memory devices and host computer system is ultra direct memory (UltraDirect Memory Access, UDMA) pattern 0, ultra direct memory pattern 1, ultra direct memory pattern 2, ultra direct memory mode 3, ultra direct memory pattern 4 or process input output (programmed input/output, PIO) during pattern, transmission mode between recognition memory storage device and host computer system is for belonging to the second transmission mode.
In one example of the present invention embodiment, above-mentioned memory control methods also comprises, transmission mode between memorizer memory devices and host computer system be ultra direct memory pattern 5 or ultra direct memory pattern 6 time, recognition memory storage device and this transmission mode of host computer system are for belonging to the first transmission mode.
Exemplary embodiment of the present invention proposes a kind of Memory Controller, and for controlling type nonvolatile module, wherein this type nonvolatile module has multiple memory chip.This Memory Controller comprises host interface, memory interface, microcontroller, Memory Management Unit, data-transmission mode recognition unit and storer erased cell.Host interface is in order to be coupled to host computer system.Memory interface is in order to be coupled to type nonvolatile module.Microcontroller is coupled to host interface and memory interface.Memory Management Unit is coupled to microcontroller, and in order to this little memory chip is grouped into multiple memory chip group.Data-transmission mode recognition unit is coupled to microcontroller, and in order to identify that transmission mode between host interface and host computer system is for belonging to the first transmission mode or the second transmission mode.Storer erased cell is coupled to microcontroller.At this, wherein when transmission mode is for belonging to the first transmission mode, storer erased cell uses the first pattern of erasing to erase the multiple data be stored in this little memory chip, wherein can be enabled in first at least part of memory chip group of erasing in pattern among this little memory chip group simultaneously.In addition, when transmission mode is for belonging to the second transmission mode, storer erased cell uses the second pattern of erasing to erase the data be stored in a little memory chip, wherein can not be enabled in second any two memory chip groups of erasing in pattern among this little memory chip group simultaneously.
In one example of the present invention embodiment, above-mentioned memory chip comprises the 0th memory chip, first memory chip, second memory chip, 3rd memory chip, 4th memory chip, 5th memory chip, 6th memory chip and the 7th memory chip, wherein the 0th memory chip and first memory chip are coupled to host interface via zero data input/output bus, second memory chip and the 3rd memory chip are coupled to host interface via the first data input/output bus, 4th memory chip and the 5th memory chip are coupled to host interface via the second data input/output bus, 6th memory chip and the 7th memory chip are coupled to host interface via the 3rd data input/output bus.At this, the 0th memory chip, second memory chip, the 4th memory chip and the 6th memory chip are grouped into the 0th memory chip group and first memory chip, the 3rd memory chip, the 5th memory chip and the 7th memory chip are grouped into first memory chipset by above-mentioned Memory Management Unit.
In one example of the present invention embodiment, when transmission mode is for belonging to the first transmission mode, above-mentioned storer erased cell is to the 0th memory chip of the 0th memory chip group, second memory chip, 4th memory chip and the 6th memory chip synchronously assign instruction of erasing, and at the 0th memory chip, second memory chip, 4th memory chip and the 6th memory chip perform erases between order period, storer erased cell is to the 4th memory chip of first memory chipset, 5th memory chip, 6th memory chip and the 7th memory chip synchronously assign instruction of erasing.
In one example of the present invention embodiment, when transmission mode is for belonging to the second transmission mode, above-mentioned storer erased cell is to the 0th memory chip of the 0th memory chip group, second memory chip, 4th memory chip and the 6th memory chip are synchronously assigned one and to be erased instruction, and at the 0th memory chip, second memory chip, after 4th memory chip and the 6th memory chip complete this instruction of erasing, storer erased cell is to the 4th memory chip of first memory chipset, 5th memory chip, 6th memory chip and the 7th memory chip synchronously assign instruction of erasing.
In one example of the present invention embodiment, above-mentioned Memory Controller also comprises a storer writing unit, and at least part of memory chip group wherein while of this storer writing unit among enable above-mentioned memory chip group writes the multiple write data coming from host computer system.
In one example of the present invention embodiment, when transmission mode between host interface and host computer system is ultra direct memory pattern 0, ultra direct memory pattern 1, ultra direct memory pattern 2, ultra direct memory mode 3, ultra direct memory pattern 4 or process input output pattern, the transmission mode between data-transmission mode recognition unit identification host interface and host computer system is for belonging to the second transmission mode.In addition.Transmission mode between host interface and host computer system be ultra direct memory pattern 5 or ultra direct memory pattern 6 time, data-transmission mode recognition unit identification host interface and this transmission mode of host computer system are for belonging to the first transmission mode.
Exemplary embodiment of the present invention proposes a kind of memorizer memory devices, and it comprises connector, type nonvolatile module and Memory Controller.Connector is in order to be coupled to host computer system.Type nonvolatile module has multiple memory chip.Memory Controller is coupled to type nonvolatile module.At this, Memory Controller in order to this little memory chip is grouped into multiple memory chip group and transmission mode between identification connector and host computer system for belonging to the first transmission mode or the second transmission mode.And, when transmission mode is for belonging to the first transmission mode, Memory Controller uses the first pattern of erasing to erase the data be stored in this little memory chip, wherein can be enabled in first at least part of memory chip group of erasing in pattern among this little memory chip group simultaneously.In addition, when transmission mode is for belonging to the second transmission mode, Memory Controller uses the second pattern of erasing to erase the data be stored in this little memory chip, wherein can not be enabled in second any two memory chip groups of erasing in pattern among this little memory chip group simultaneously.
In one example of the present invention embodiment, above-mentioned memory chip comprises the 0th memory chip, first memory chip, second memory chip, 3rd memory chip, 4th memory chip, 5th memory chip, 6th memory chip and the 7th memory chip, wherein the 0th memory chip and first memory chip are coupled to host interface via zero data input/output bus, second memory chip and the 3rd memory chip are coupled to host interface via the first data input/output bus, 4th memory chip and the 5th memory chip are coupled to host interface via the second data input/output bus, 6th memory chip and the 7th memory chip are coupled to host interface via the 3rd data input/output bus.At this, the 0th memory chip, second memory chip, the 4th memory chip and the 6th memory chip are grouped into the 0th memory chip group and first memory chip, the 3rd memory chip, the 5th memory chip and the 7th memory chip are grouped into first memory chipset by above-mentioned Memory Controller.
In one example of the present invention embodiment, when transmission mode is for belonging to the first transmission mode, above-mentioned Memory Controller is to the 0th memory chip of the 0th memory chip group, second memory chip, 4th memory chip and the 6th memory chip synchronously assign instruction of erasing, and at the 0th memory chip, second memory chip, 4th memory chip and the 6th memory chip perform erases between order period, Memory Controller is to the 4th memory chip of first memory chipset, 5th memory chip, 6th memory chip and the 7th memory chip synchronously assign instruction of erasing.
In one example of the present invention embodiment, when transmission mode is for belonging to the second transmission mode, above-mentioned Memory Controller is to the 0th memory chip of the 0th memory chip group, second memory chip, 4th memory chip and the 6th memory chip are synchronously assigned one and to be erased instruction, and at the 0th memory chip, second memory chip, after 4th memory chip and the 6th memory chip complete this instruction of erasing, Memory Controller is to the 4th memory chip of first memory chipset, 5th memory chip, 6th memory chip and the 7th memory chip synchronously assign instruction of erasing.
In one example of the present invention embodiment, the above-mentioned Memory Controller at least part of memory chip group simultaneously among enable above-mentioned memory chip group writes the multiple write data coming from host computer system.
In one example of the present invention embodiment, when transmission mode between connector and host computer system is ultra direct memory pattern 0, ultra direct memory pattern 1, ultra direct memory pattern 2, ultra direct memory mode 3, ultra direct memory pattern 4 or process input output pattern, the transmission mode between Memory Controller identification host interface and host computer system is for belonging to the second transmission mode.In addition.Transmission mode between connector and host computer system be ultra direct memory pattern 5 or ultra direct memory pattern 6 time, Memory Controller identification host interface and this transmission mode of host computer system are for belonging to the first transmission mode.
Exemplary embodiment of the present invention proposes a kind of memory control methods, for memorizer memory devices, wherein memorizer memory devices has type nonvolatile module and type nonvolatile module has multiple memory chip and the multiple data input/output bus coupling so far a little memory chip.This memory control methods comprises transmission mode between recognition memory storage device and host computer system for belonging to the first transmission mode or the second transmission mode.This memory control methods also comprises, and when transmission mode is for belonging to the first transmission mode, first pattern of erasing of use is erased the multiple data be stored in this little memory chip; And when transmission mode is for belonging to the second transmission mode, second pattern of erasing of use is erased the data be stored in this little memory chip, wherein first erase mode operating time operating current be greater than second erase mode operating time operating current.
In one example of the present invention embodiment, first erase mode operating time simultaneously by the number of the memory chip of action be greater than second erase mode operating time simultaneously by the number of the memory chip of action.
In one example of the present invention embodiment, first erase mode operating time simultaneously by the number of the data input/output bus of action be greater than second erase mode operating time simultaneously by the number of the data input/output bus of action.
Based on above-mentioned, the memory control methods of exemplary embodiment of the present invention, Memory Controller and memorizer memory devices can use the different patterns of erasing to perform data according to different transmission modes and erase and operate, avoid the instability because electric power supply deficiency causes thus.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the outline flowchart according to the memory control methods shown in this exemplary embodiment.
Fig. 2 A is host computer system according to the present invention first exemplary embodiment and the summary block scheme of memorizer memory devices being coupled to host computer system.
Fig. 2 B is the schematic diagram of computing machine, input/output device and memorizer memory devices according to exemplary embodiment of the present invention.
Fig. 2 C is the schematic diagram of host computer system according to another exemplary embodiment of the present invention and memorizer memory devices.
Fig. 3 is the summary block scheme of the memorizer memory devices shown in Fig. 2 A.
Fig. 4 is according to example physical blocks being grouped into solid element shown in this exemplary embodiment.
Fig. 5 is the summary block scheme according to the Memory Controller shown in this exemplary embodiment.
Fig. 6 performs data according to enable multiple memory chip group while shown in this exemplary embodiment to erase the schematic diagram of running.
Fig. 7 be according to the same time shown in this exemplary embodiment only an enable memory chip group perform data erase running schematic diagram.
Fig. 8 is the summary block scheme of the Memory Controller according to another exemplary embodiment.
Fig. 9 is the process flow diagram according to the memory control methods shown in this exemplary embodiment.
Reference numeral:
S101, S103, S105, S107: the summary step of memory control methods
1000: host computer system
1100: computing machine
1102: microprocessor
1104: random access memory
1106: input/output device
1108: system bus
1110: data transmission interface
1202: mouse
1204: keyboard
1206: display
1208: printer
1212: Portable disk
1214: memory card
1216: solid state hard disc
1310: digital camera
1312:SD card
1314:MMC card
1316: memory stick
1318:CF card
1320: embedded storage device
100: memorizer memory devices
102: connector
104: Memory Controller
106: type nonvolatile module
200-0: the zero memory cell
200-1: first memory unit
200-2: second memory unit
200-3: the three memory cell
210-0: the zero memory chip
210-1: first memory chip
210-2: second memory chip
210-3: the three memory chip
210-4: the four memory chip
210-5: the five memory chip
210-6: the six memory chip
210-7: the seven memory chip
220-0,220-1,220-2,220-3: data input/output bus
300 (0) ~ 300 (N), 301 (0) ~ 301 (N), 302 (0) ~ 302 (N), 303 (0) ~ 303 (N), 304 (0) ~ 304 (N), 305 (0) ~ 305 (N), 306 (0) ~ 306 (N), 307 (0) ~ 307 (N): physical blocks
410 (0) ~ 410 (N): solid element
502: microcontroller
504: host interface
506: memory interface
552: Memory Management Unit
554: data-transmission mode recognition unit
556: storer erased cell
508: memory buffer
510: electric power management circuit
512: bug check and correcting circuit
558: storer writing unit
560: storer reading unit
S901, S903, S905, S907, S909, S911, S913: the step of memory control methods
Embodiment
The instability of the system caused to avoid the electricity shortage of above-mentioned factor data transmission interface, the present invention proposes can to use according to different data-transmission modes different data to erase the memory control methods of pattern.As shown in the exemplary embodiment of Fig. 1, in this memory control methods, the memory chip of memorizer memory devices can be grouped into multiple memory chip group (S101), and the transmission mode between recognition memory storage device and host computer system is for belonging to the first transmission mode or the second transmission mode (S103).When this transmission mode is for belonging to the first transmission mode, first pattern of erasing of use is erased and is stored in multiple data (S105) in this little memory chip and when transmission mode is for belonging to the second transmission mode, second pattern of erasing of use is erased the data (S107) be stored in this little memory chip, wherein, first erase mode operating time operating current be greater than the second operating current of erasing mode operating.Specifically, such as, first erase mode operating time simultaneously by the number of the memory chip of action be greater than second erase mode operating time among memory chip simultaneously by the number of the memory chip of action, thus first erase mode operating time operating current be greater than the second operating current of erasing mode operating.Again such as, first erase mode operating time simultaneously by the number of the data input/output bus of action be greater than second erase mode operating time simultaneously by the number of the data input/output bus of action, make thus first erase mode operating time operating current be greater than the second operating current of erasing mode operating.That is, when using more not enough second transmission mode of power supply, lower the second pattern of erasing of power consumption can be used, to avoid the instability of system.In order to can the present invention be more clearly understood, be described with several exemplary embodiment below.
Generally speaking, memorizer memory devices (also known as, type nonvolatile stocking system) comprises memory module and controller (also known as, control circuit).Usual memorizer memory devices can use together with host computer system, data can be write to memorizer memory devices or read data from memorizer memory devices to make host computer system.In addition, memorizer memory devices is also had to be comprise embedded type nonvolatile and can be executed in host computer system using substantially as the software of the controller of this embedded type nonvolatile.
Fig. 2 A is host computer system according to the present invention first exemplary embodiment and the summary block scheme of memorizer memory devices being coupled to host computer system.
Please refer to Fig. 2 A, host computer system 1000 generally comprises computing machine 1100 and I/O (input/output, I/O) device 1106.Computing machine 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the mouse 1202 of Fig. 2 B, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Fig. 2 B, input/output device 1106 can also comprise other devices.
In embodiments of the present invention, memorizer memory devices 100 is coupled by data transmission interface 1110 other elements with host computer system 1000.Data can be write to memorizer memory devices 100 by microprocessor 1102, random access memory 1104 with the process of input/output device 1106 or read data from memorizer memory devices 100.Such as, memorizer memory devices 100 can be Portable disk 1212, memory card 1214 or solid state hard disc (Solid StateDrive, SSD) 1216 as shown in Figure 2 B.
Generally speaking, host computer system 1000 can be can any system of storage data substantially.Although in this exemplary embodiment, host computer system 1000 explains with computer system, but host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.Such as, when host computer system is digital camera (video camera) 1310, memorizer memory devices is then its SD card 1312 used, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded storage device 1320 (as shown in Figure 2 C).Embedded storage device 1320 comprises embedded multi-media card (Embedded MMC, eMMC).
Fig. 3 is the summary block scheme of the memorizer memory devices shown in Fig. 2 A.
Please refer to Fig. 3, memorizer memory devices 100 comprises connector 102, Memory Controller 104 and type nonvolatile module 106.
Connector 102 is coupled to Memory Controller 104 and in order to be coupled to host computer system 1000.In this exemplary embodiment, connector 102 is compatible to compact flash (Compact Flash, CF) interface standard.But, it must be appreciated, the present invention is not limited thereto, connector 102 can also be meet Institute of Electrical and Electric Engineers (Institute of Electrical and ElectronicEngineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (PeripheralComponent Interconnect Express, PCI Express) standard, Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) standard, USB (universal serial bus) (Universal Serial Bus, USB) standard, memory stick (Memory Stick, MS) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, safe digital (SecureDigital, SD) interface standard, integrated form drives electrical interface (Integrated Device Electronics, IDE) standard or other standards be applicable to.
Memory Controller 104 can perform with multiple logic gate of hardware pattern or firmware pattern implementation or steering order, and according to the instruction of host computer system 1000 carry out in type nonvolatile module 106 data write, read and the running such as to erase.
Type nonvolatile module 106 is coupled to Memory Controller 104, and in order to store the data that host computer system 1000 writes.In this exemplary embodiment, the non-volatile type nonvolatile module 106 of duplicative is multi-level cell memory (MultiLevel Cell, MLC) NAND flash memory module.But, the present invention is not limited thereto, the non-volatile type nonvolatile module 106 of duplicative also single-order storage unit (Single Level Cell, SLC) NAND flash memory module, other flash memory modules or other there is the memory module of identical characteristics.
In this exemplary embodiment, type nonvolatile module 106 has the 0th memory cell 200-0, first memory unit 200-1, second memory unit 200-2, the 3rd memory cell 200-3.In this exemplary embodiment, 0th memory cell 200-0 has the 0th memory chip 210-0 and first memory chip 210-1, first memory unit 200-1 has second memory chip 210-2 and the 3rd memory chip 210-3, and second memory unit 200-2 has the 4th memory chip 210-4 and the 5th memory chip 210-5 and the 3rd memory cell 200-3 has the 6th memory chip 210-6 and the 7th memory chip 210-7.
Each memory chip (that is, the 0th memory chip 210-0, first memory chip 210-1, second memory chip 210-2, the 3rd memory chip 210-3, the 4th memory chip 210-4, the 5th memory chip 210-5, the 6th memory chip 210-6 and the 7th memory chip 210-7) has multiple storage unit and carrys out storage data.Particularly, the storage unit of storage data first must be performed data and erases after running and could be used to store new data again.In the design of type nonvolatile module 106, this little storage unit can be laid (layout) according to its circuit and be divided into multiple physical blocks.Physical blocks is the least unit of erasing.That is, each physical blocks contain minimal amount in the lump by the storage unit of erasing.Each physical blocks has several physical page, and physical page is the minimum unit of programming.But it must be appreciated, in another exemplary embodiment of the present invention, the least unit of write data can also be sector (Sector) or other sizes.In other words, physical page is write data or the minimum unit reading data.Each physical page comprises user's data bit element district and redundancy bit district.User's data bit element district is in order to store the data of user, and redundancy bit district is in order to the data (such as, bug check and correcting code) of stocking system.
In this exemplary embodiment, Memory Controller 104 transmits data by multiple data input/output bus (Data input/output (I/O) bus) and receives data to memory cell 200-0 ~ 200-3 or from memory cell 200-0 ~ 200-3.Specifically, instruction and data are transferred to the 0th memory chip 210-0 and first memory chip 210-1 via zero data input/output bus 220-0 by Memory Controller 104; Via the first data input/output bus 220-1, instruction and data are transferred to second memory chip 210-2 and the 3rd memory chip 210-3; Via the second data input/output bus 220-2, instruction and data are transferred to the 4th memory chip 210-4 and the 5th memory chip 210-5; And via the 3rd data input/output bus 220-3, instruction and data are transferred to the 6th memory chip 210-6 and the 7th memory chip 210-7.
In this exemplary embodiment, the physical blocks in each memory chip can be stored device controller 104 group and is multiple solid element and manages in units of solid element.
Fig. 4 is according to example physical blocks being grouped into solid element shown in this exemplary embodiment.
Please refer to Fig. 4, Memory Controller 104 can by the physical blocks 300 (0) ~ 300 (N) of the 0th memory chip, the physical blocks 301 (0) ~ 301 (N) of first memory chip, the physical blocks 302 (0) ~ 302 (N) of second memory chip, the physical blocks 303 (0) ~ 303 (N) of the 3rd memory chip, the physical blocks 304 (0) ~ 304 (N) of the 4th memory chip, the physical blocks 305 (0) ~ 305 (N) of the 5th memory chip, the physical blocks 306 (0) ~ 306 (N) of the 6th memory chip and the physical blocks 307 (0) ~ 307 (N) of the 7th memory chip are grouped into solid element 410 (0) ~ 410 (N) respectively.
Particularly each solid element is made up of the physical blocks of in each memory chip, and therefore Memory Controller 104 can use parallel model (parallel mode) and interleaving mode (interleave mode) to promote the speed of access data.Specifically, because in type nonvolatile module 106, each memory cell is by independently data input/output bus and Memory Controller 104 couple, therefore in parallel write mode (parallel write mode), Memory Controller 104 can transmit write data to corresponding memory module, to promote writing speed via many data input/output bus simultaneously.That is, when for writing a solid element, because solid element is made up of the physical blocks belonging to different memory unit, therefore in parallel model, the data of the physical page of corresponding different entities block can transmit simultaneously separately by many data input/output bus and write by Memory Controller 104.
Moreover because each memory module comprises two memory chips, therefore data interlace can be sent to two memory chips in same memory module, more to promote writing speed by Memory Controller 104.Specifically, as mentioned above, the process writing data in memory chip comprises instruction and data transmit (transfer) and data programing (program) two parts.Staggered write mode (interleave write mode) is exactly that during utilizing one of them memory chip just to perform data programing, move instruction and data give another memory chip in two memory chips using same data input/output bus transmission data.
In exemplary embodiment of the present invention, Memory Controller 104 meeting configuration logic unit is with mapping entity unit.Specifically, the solid element of part can be grouped into data field and idle district by Memory Controller 104.The solid element (being also called data entity unit) of data field is the solid element being regarded as storage data, and the solid element (being also called idle solid element) in idle district is the solid element writing new data.Such as, when receiving write instruction from host computer system 1000 with during for being stored to the data of a certain logical block, Memory Controller 104 can extract solid element as daily record (log) solid element from idle district, and data is write so far in log entities unit.Afterwards, when performing data consolidation procedure to a certain logical block, Memory Controller 104 can extract solid element and write as the new data solid element of this logical blocks corresponding the valid data belonging to this logical block from idle district, and replaces original data entity unit mapping this logical block.
In this exemplary embodiment, Memory Controller 102 meeting service logic unit-solid element mapping table (logical unit-physical unit mapping table) is to record the mapping relations between logical block and the solid element of data field.In addition, because host computer system 1000 is with logic access address (such as, sector (Sector)) carry out access data for unit, when host computer system 1000 access data, the logic access address of correspond to memories storage device 100 can be converted to corresponding logical page (LPAGE) by Memory Controller 104.Such as, when host computer system 1000 is for accessing a certain logic access address, the logic access address that host computer system 1000 can access by Memory Controller 104 is converted to the multi-dimensional address formed with the logical block of correspondence and logical page (LPAGE), and by logical block-solid element mapping table access data in the physical page of correspondence.
Fig. 5 is the summary block scheme according to the Memory Controller shown in this exemplary embodiment.
Please refer to Fig. 5, Memory Controller 104 comprises microcontroller 502, host interface 504, memory interface 506, Memory Management Unit 552, data-transmission mode recognition unit 554 and storer erased cell 556.
Microcontroller 502 is in order to the overall operation of control store controller 104.
Host interface 504 is coupled to microcontroller 502 and in order to receive and to identify the instruction that transmits of host computer system 1000 and data.In this exemplary embodiment, host interface 504 is compatible to CF standard.But, it must be appreciated and the present invention is not limited thereto, host interface 504 can also be compatible to PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, SATA standard, MS standard, MMC standard, SD standard, IDE standard or other data transmission standards be applicable to.
Memory interface 506 is coupled to microcontroller 502 and in order to access type nonvolatile module 106.That is, the data for writing to type nonvolatile module 106 can be converted to the receptible form of type nonvolatile module 106 via memory interface 506.
Memory Management Unit 552 is coupled to this microcontroller 502 and in order to manage type nonvolatile module 106.
Such as, physical blocks can be grouped into multiple solid element to access by Memory Management Unit 552.In addition, Memory Management Unit 552 can record in logic access address and physical blocks that host computer system 1000 accesses between physical address mapping relations.In more detail, solid element by belong to different memory chip multiple physical blocks to form and the physical blocks of type nonvolatile module 106 is that the mode of rotating carrys out storage data.In this exemplary embodiment, Memory Management Unit 552 can configure corresponding logical block, carrys out mapping entity unit, carries out data access in order to host computer system 1000.Base this, Memory Management Unit 552 must to record between logical block and solid element the mapping relations (that is, service logic unit-solid element mapping table) of constantly changing.
It is worth mentioning that, due in this exemplary embodiment, Memory Controller 104 carries out data write running to type nonvolatile module 106 in units of solid element, therefore, when carrying out data write running to a solid element, write instruction must be assigned to the multiple physical blocks in multiple memory chip.That is, the data belonging to same logical block can be write in multiple memory chip dispersedly.Similarly, when a solid element is carried out data erase running time, must assign to the multiple physical blocks in multiple memory chip instruction of erasing.
Data-transmission mode recognition unit 554 is coupled to microcontroller 502, and in order to identify that transmission mode between host interface and host computer system is for belonging to the first transmission mode or the second transmission mode.Specifically, when memorizer memory devices 100 is coupled to host computer system 1000, host computer system 1000 can first send instruction to memorizer memory devices 100, to inquire the essential information of memorizer memory devices 100.Afterwards, Memory Controller 104 can send essential information to host computer system 1000, and wherein this essential information can comprise the supported transmission mode of connector 102.Then, host computer system 1000 can give an order to memorizer memory devices 100, uses which kind of transmission mode to operate to indicate.Then, the host interface 504 of Memory Controller 104 can send the information about adopted transmission mode to microcontroller 502.Particularly, the currently used transmission mode of information identification that data-transmission mode recognition unit 554 can transmit according to host interface 504 belongs to the first transmission mode or the second transmission mode.
Such as, for CF memory card, transmission mode possible between memorizer memory devices and host computer system is ultra direct memory (Ultra Direct Memory Access, UDMA) pattern 0 ~ 6 or process input output (programmed input/output, PIO) pattern.The transmission mode adopted between memorizer memory devices 100 and host computer system 1000 be UDMA pattern 0 ~ 4 or PIO pattern time, data-transmission mode recognition unit 554 can the transmission mode between recognition memory storage device 100 and host computer system 1000 be belong to the second transmission mode.In addition, transmission mode between memorizer memory devices 100 and host computer system 1000 be UDMA pattern 5 or UDMA pattern 6 time, data-transmission mode recognition unit 554 can the transmission mode between recognition memory storage device 100 and host computer system 1000 be belong to the first transmission mode.That is, the higher and supply of transfer rate can be identified as belonging to the first transmission mode compared with the transmission mode of large power supply and the lower and transmission mode that is supply small electric source of transfer rate can be identified as belonging to the second transmission mode.
Storer erased cell 556 is coupled to microcontroller 502 and erases running in order to perform data to type nonvolatile module 106.Particularly, storer erased cell 556 can be belong to the first transmission mode or the second transmission mode and perform data in different ways and erase according to the transmission mode between memorizer memory devices 100 and host computer system 1000.
Specifically, memory chip can be grouped into multiple memory chip group according to the configuration of data input/output bus by Memory Management Unit 552.Such as, the 0th memory chip 210-0, second memory chip 210-2, the 4th memory chip 210-4 and the 6th memory chip 210-6 can be grouped into the 0th memory chip group and first memory chip 210-1, the 3rd memory chip 210-3, the 5th memory chip 210-5 and the 7th memory chip 210-7 are grouped into first memory chipset by Memory Management Unit 552.Because the 0th memory chip 210-0, second memory chip 210-2, the 4th memory chip 210-4 are connected with Memory Controller respectively by different data input/output bus from the 6th memory chip 210-6, the memory chip therefore in the 0th memory chip group can the simultaneously instruction assigned of execute store controller 104 in parallel.Similarly, first memory chip 210-1, the 3rd memory chip 210-3, the 5th memory chip 210-5 are connected with Memory Controller respectively by different data input/output bus from the 7th memory chip 210-7, and the memory chip therefore in first memory chipset can the simultaneously instruction assigned of execute store controller 104 in parallel.
To erase running and transmission mode between memorizer memory devices 100 and host computer system 1000 is when belonging to the first transmission mode when data need be carried out to solid element, storer erased cell 556 synchronously can be assigned to erase instruction and perform this at the memory chip of the 0th memory chip group to all memory chips of the 0th memory chip group and erase between order period, storer erased cell 556 can synchronously assign instruction of erasing (as shown in Figure 6) to the memory chip of first memory chipset, crisscross at this and to assign instruction of erasing between memory chip group and be also called staggered pattern of erasing.Specifically, due under the first transmission mode, memorizer memory devices 100 can receive larger current from host computer system 1000, and therefore, storer erased cell 556 enable multiple memory chip group can perform running of erasing simultaneously, promotes the speed of erasing thus.At this, the pattern of erasing that corresponding first transmission mode adopts also is called that first erases pattern.
In addition, to erase running and transmission mode between memorizer memory devices 100 and host computer system 1000 is when belonging to the second transmission mode when data need be carried out to solid element, storer erased cell 556 can synchronously assign to all memory chips of the 0th memory chip group the instruction and after the memory chip of the 0th memory chip group completes this instruction of erasing, storer erased cell 556 just can synchronously assign instruction of erasing (as shown in Figure 7) to the memory chip of first memory chipset of erasing.Specifically, due under the second transmission mode, the electric current that memorizer memory devices 100 receives from host computer system 1000 is less, and therefore, for avoiding instability, storer erased cell 556 only an enable memory chip group can perform running of erasing simultaneously.At this, the pattern of erasing that corresponding second transmission mode adopts also is called that second erases pattern.
Fig. 8 is the summary block scheme of the Memory Controller according to another exemplary embodiment.
Please refer to Fig. 8, except above-mentioned microcontroller 502, main frame connect 504, memory interface 506, Memory Management Unit 552, data-transmission mode recognition unit 554 and storer erased cell 556, Memory Controller 804 also comprises storer writing unit 558.
Storer writing unit 558 is coupled to microcontroller 502 and in order to data to be write in type nonvolatile module 106.Particularly, in this exemplary embodiment, storer writing unit 558 enable multiple memory chip group can write the write data coming from host computer system simultaneously.That is, storer writing unit 558 can use parallel write mode or staggered write mode to write data.
In addition, Memory Controller 804 also can also comprise storer reading unit 560.Storer reading unit 560 in order to read data from type nonvolatile module 106.Similarly, in this exemplary embodiment, data-reading unit 560 enable multiple memory chip group can read data simultaneously.That is, storer writing unit 558 can use the pattern of reading in parallel or staggered read mode to read data.
In addition, Memory Controller 804 also also can comprise memory buffer 508, electric power management circuit 510 and bug check and correcting circuit 512.
Memory buffer 508 is coupled to microcontroller 502 and comes from the data and instruction of host computer system 1000 in order to temporary or come from the data of type nonvolatile module 106.
Electric power management circuit 510 is coupled to microcontroller 502 and in order to the power supply of control store storage device 100.
Bug check and correcting circuit 512 are coupled to microcontroller 502 and in order to perform an error-correcting routine to guarantee the correctness of data.Specifically, when host interface 504 receives main frame write instruction from host computer system 1000, bug check and correcting circuit 512 can be that the write data that this main frame corresponding writes instruction produce corresponding bug check and correcting code (ErrorChecking and Correcting Code, ECC Code), and these write data can write in type nonvolatile module 106 with corresponding error-correcting code by storer writing unit 558.Afterwards, can read error-correcting code corresponding to these data when storer reading unit 560 reads data from type nonvolatile module 106, and bug check and correcting circuit 512 can according to this error-correcting code to read data execution error correction programs simultaneously.
It must be appreciated, in this exemplary embodiment, Memory Management Unit 552, data-transmission mode recognition unit 554, storer erased cell 556, storer writing unit 558 are carry out implementation with hardware structure with storer reading unit 560, but the present invention is not limited thereto.In another exemplary embodiment of the present invention, Memory Management Unit 552, data-transmission mode recognition unit 554, storer erased cell 556, storer writing unit 558 firmware pattern can also carry out implementation with storer reading unit 560.Such as, implementation Memory Management Unit 552, data-transmission mode recognition unit 554, storer erased cell 556, storer writing unit 558 can be burned onto with the steering order of storer reading unit 560 and be configured in the ROM (read-only memory) of Memory Controller.When memorizer memory devices 100 operates, this little steering order can have been performed to erase according to the data of the embodiment of the present invention, write and erase to operate and memory management operates by microcontroller.
In addition, in another exemplary embodiment of the present invention, implementation Memory Management Unit 552, data-transmission mode recognition unit 554, storer erased cell 556, storer writing unit 558 can also procedure code pattern be stored in the specific region (such as, being exclusively used in the system region of storage system data in type nonvolatile module) of type nonvolatile module with the steering order of storer reading unit 560.Such as, ROM (read-only memory) (not shown) and random access memory (not shown) can be configured in Memory Controller, and this ROM (read-only memory) has a driving code section.When Memory Controller is enabled, microcontroller first can perform this and drive code section the steering order be stored in type nonvolatile module to be loaded into so far in random access memory, reruns this little steering order afterwards and erases with the data performing exemplary embodiment of the present invention, write and erase and to operate and memory management operates.
It is worth mentioning that, in this exemplary embodiment, erase in pattern first, every 2 data input/output bus (being also called passage (channel)) can be divided into one group and 2 groups of binary channels can alternately be used for assigning instruction of erasing, to carry out staggered erasing (as shown in Figure 6), make at least part of memory chip group to perform to erase running thus simultaneously and promote the speed of erasing; Further, erase in pattern second, every 2 passages can be divided into one group, but between 2 groups of binary channels, do not use staggered erase mode to make the memory chip simultaneously operated to be restricted, to reduce power consumption.
But in another exemplary embodiment of the present invention, the first pattern of erasing also can be implemented as: 4 passages are used to assign instruction of erasing, and to make all memory chip groups perform running of erasing simultaneously, promotes the speed of erasing thus simultaneously; And, second pattern of erasing also can be implemented as: every 2 passages can be divided into one group, between 2 groups of binary channels, do not use staggered erase mode, and 2 passages in 1 group of binary channels can alternately be used for assigning instruction of erasing, the number of the memory chip of restriction start simultaneously thus.
In addition, in another exemplary embodiment of the present invention, the first pattern of erasing also can be implemented as: 4 passages are alternately used for assigning instruction of erasing, and to make all memory chip groups perform running of erasing simultaneously, promotes the speed of erasing thus; And, second pattern of erasing also can be implemented as: every 2 passages can be divided into one group, between 2 groups of binary channels, use staggered erase mode, and 2 passages in 1 group of binary channels can not alternately be used for assigning instruction of erasing, the number of the memory chip of restriction start simultaneously thus.
Moreover in another exemplary embodiment of the present invention, the first pattern of erasing also can be implemented as: 4 passages are used to assign instruction of erasing, and to make all memory chip groups perform running of erasing simultaneously, promotes the speed of erasing thus simultaneously; And, second pattern of erasing also can be implemented as: every 2 passages can be divided into one group, between 2 groups of binary channels, do not use staggered erase mode, and 2 passages in 1 group of binary channels can be used for assigning instruction of erasing simultaneously, the number of the memory chip of restriction start simultaneously thus.
Fig. 9 is the process flow diagram according to the memory control methods shown in this exemplary embodiment, its illustrate perform data erase running storer rate-determining steps.
Please refer to Fig. 9, in step S901,0th memory chip 210-0, second memory chip 210-2, the 4th memory chip 210-4 and the 6th memory chip 210-6 can be grouped into the 0th memory chip group, and first memory chip 210-1, the 3rd memory chip 210-3, the 5th memory chip 210-5 and the 7th memory chip 210-7 can be grouped into first memory chipset.
Afterwards, in step S903, the transmission mode between memorizer memory devices and host computer system can be identified whether belong to the first transmission mode.
If the transmission mode between memorizer memory devices and host computer system is when belonging to the first transmission mode, in step S905, instruction of erasing can by the memory chip synchronously assigned to the 0th memory chip group and in step s 907, instruction of erasing can by the memory chip synchronously assigned to first memory chipset.That is, erase in pattern in first of corresponding first transmission mode, at least part of memory chip group can be enabled simultaneously.
If the transmission mode between memorizer memory devices and host computer system is non-belong to the first transmission mode (namely, belong to the second transmission mode) time, in step S909, instruction of erasing can by the memory chip synchronously assigned to the 0th memory chip group, and in step S911, the storage core sector-meeting of the 0th memory chip group is judged whether complete this instruction of erasing.
If the memory chip of the 0th memory chip group complete this erase instruction time, then in step S913, instruction of erasing can by the memory chip synchronously assigned to first memory chipset.Otherwise, if the memory chip of the 0th memory chip group do not complete this erase instruction time, then step S911 can be performed again.That is, erase in pattern in second of corresponding second transmission mode, any two memory chip groups among this little memory chip group can not be enabled simultaneously.To erase pattern compared to first, erase in pattern second, less storage core sector-meeting by action simultaneously and less data input/output bus, therefore, the second transmission mode of the less electric current of corresponding supply, the running of memorizer memory devices 100 still Absorbable organic halogens.
In sum, multiple memory chip can be grouped into multiple memory chip group according to the configuration of data input/output bus by the memory control methods of exemplary embodiment of the present invention, Memory Controller and memorizer memory devices.In addition, when execution data erase running, the transmission mode adopted between memorizer memory devices and host computer system can be identified, wherein when transmission mode is for belonging to first transmission mode that can provide larger current, multiple storage core sector-meeting is simultaneously enabled to perform data and erases and when transmission mode is for belonging to second transmission mode that cannot provide larger current, and only a storage core sector-meeting is enabled to perform data and erases.Base this, the memory control methods of exemplary embodiment of the present invention, Memory Controller and memorizer memory devices can be avoided performing when erasing instruction because of instability that electric power deficiency causes effectively.
Although the present invention with embodiment disclose as above, so itself and be not used to limit the present invention, any person of an ordinary skill in the technical field, when doing a little change and retouching, and does not depart from the spirit and scope of the present invention.
Claims (21)
1. a memory control methods, for a memorizer memory devices, wherein this memorizer memory devices has a type nonvolatile module and this type nonvolatile module has multiple memory chip, and this memory control methods comprises:
Identify that a transmission mode between this memorizer memory devices and a host computer system is for belonging to one first transmission mode or one second transmission mode;
Those memory chips are grouped into multiple memory chip group;
When this transmission mode is for belonging to this first transmission mode, use one first pattern of erasing to erase the multiple data be stored in those memory chips, wherein can be enabled in this first at least part of memory chip group of erasing in pattern among those memory chip groups simultaneously; And
When this transmission mode is for belonging to this second transmission mode, use one second pattern of erasing to erase those data be stored in those memory chips, wherein can not be enabled in these second any two memory chip groups of erasing in pattern among those memory chip groups simultaneously.
2. memory control methods according to claim 1, wherein those memory chips comprise one the 0th memory chip, a first memory chip, a second memory chip, one the 3rd memory chip, one the 4th memory chip, one the 5th memory chip, one the 6th memory chip and one the 7th memory chip
Wherein the 0th memory chip and this first memory chip are coupled to a Memory Controller of this memorizer memory devices via a zero data input/output bus, this second memory chip and the 3rd memory chip are coupled to this Memory Controller via one first data input/output bus, 4th memory chip and the 5th memory chip are coupled to this Memory Controller via one second data input/output bus, 6th memory chip and the 7th memory chip are coupled to this Memory Controller via one the 3rd data input/output bus,
The step wherein those memory chips being grouped into those memory chip groups comprises:
0th memory chip, this second memory chip, the 4th memory chip and the 6th memory chip are grouped into one the 0th memory chip group; And
This first memory chip, the 3rd memory chip, the 5th memory chip and the 7th memory chip are grouped into a first memory chipset.
3. memory control methods according to claim 2, wherein uses the erase step of those data be stored in those memory chips of this first pattern of erasing to comprise:
Synchronously assign one to the 0th memory chip of the 0th memory chip group, this second memory chip, the 4th memory chip and the 6th memory chip to erase instruction; And
Performing this at the 0th memory chip, this second memory chip, the 4th memory chip and the 6th memory chip erases between order period, synchronously assigns this instruction of erasing to the 4th memory chip of this first memory chipset, the 5th memory chip, the 6th memory chip and the 7th memory chip.
4. memory control methods according to claim 2, wherein uses the erase step of those data be stored in those memory chips of this second pattern of erasing to comprise:
Synchronously assign one to the 0th memory chip of the 0th memory chip group, this second memory chip, the 4th memory chip and the 6th memory chip to erase instruction; And
After the 0th memory chip, this second memory chip, the 4th memory chip and the 6th memory chip complete this instruction of erasing, synchronously this instruction of erasing is assigned to the 4th memory chip of this first memory chipset, the 5th memory chip, the 6th memory chip and the 7th memory chip.
5. memory control methods according to claim 1, wherein also comprises:
At least part of memory chip group simultaneously among those memory chip groups enable writes the multiple write data coming from this host computer system.
6. memory control methods according to claim 1, wherein also comprises:
This transmission mode between this memorizer memory devices and this host computer system is a ultra direct memory (Ultra Direct Memory Access, UDMA) pattern 0, ultra direct memory pattern 1, ultra direct memory pattern 2, ultra direct memory mode 3, a ultra direct memory pattern 4 or process input output (programmed input/output, PIO), during pattern, identify that this transmission mode between this memorizer memory devices and this host computer system is for belonging to this second transmission mode; And
This transmission mode between this memorizer memory devices and this host computer system be a ultra direct memory pattern 5 or a ultra direct memory pattern 6 time, identify that this memorizer memory devices and this transmission mode of this host computer system are for belonging to this first transmission mode.
7. a Memory Controller, for controlling a type nonvolatile module, wherein this type nonvolatile module has multiple memory chip, and this Memory Controller comprises:
One host interface, in order to be coupled to a host computer system;
One memory interface, in order to be coupled to this type nonvolatile module;
One microcontroller, is coupled to this host interface and this memory interface;
One Memory Management Unit, is coupled to this microcontroller, and in order to those memory chips are grouped into multiple memory chip group;
One data-transmission mode recognition unit, is coupled to this microcontroller, and in order to identify that a transmission mode between this host interface and this host computer system is for belonging to one first transmission mode or one second transmission mode; And
One storer erased cell, is coupled to this microcontroller,
Wherein when this transmission mode is for belonging to this first transmission mode, this storer erased cell uses one first pattern of erasing to erase the multiple data be stored in those memory chips, wherein can be enabled in this first at least part of memory chip group of erasing in pattern among those memory chip groups simultaneously
Wherein when this transmission mode is for belonging to this second transmission mode, this storer erased cell uses one second pattern of erasing to erase those data be stored in those memory chips, wherein can not be enabled in these second any two memory chip groups of erasing in pattern among those memory chip groups simultaneously.
8. Memory Controller according to claim 7,
Wherein those memory chips comprise one the 0th memory chip, a first memory chip, a second memory chip, one the 3rd memory chip, one the 4th memory chip, one the 5th memory chip, one the 6th memory chip and one the 7th memory chip
Wherein the 0th memory chip and this first memory chip are coupled to this host interface via a zero data input/output bus, this second memory chip and the 3rd memory chip are coupled to this host interface via one first data input/output bus, 4th memory chip and the 5th memory chip are coupled to this host interface via one second data input/output bus, 6th memory chip and the 7th memory chip are coupled to this host interface via one the 3rd data input/output bus
Wherein the 0th memory chip, this second memory chip, the 4th memory chip and the 6th memory chip are grouped into one the 0th memory chip group and this first memory chip, the 3rd memory chip, the 5th memory chip and the 7th memory chip are grouped into a first memory chipset by this Memory Management Unit.
9. Memory Controller according to claim 8, wherein when this transmission mode is for belonging to this first transmission mode, this storer erased cell is to the 0th memory chip of the 0th memory chip group, this second memory chip, 4th memory chip and the 6th memory chip are synchronously assigned one and to be erased instruction, and at the 0th memory chip, this second memory chip, 4th memory chip and the 6th memory chip perform this and erase between order period, this storer erased cell is to the 4th memory chip of this first memory chipset, 5th memory chip, 6th memory chip and the 7th memory chip synchronously assign this instruction of erasing.
10. Memory Controller according to claim 8, wherein when this transmission mode is for belonging to this second transmission mode, this storer erased cell is to the 0th memory chip of the 0th memory chip group, this second memory chip, 4th memory chip and the 6th memory chip are synchronously assigned one and to be erased instruction, and at the 0th memory chip, this second memory chip, after 4th memory chip and the 6th memory chip complete this instruction of erasing, this storer erased cell is to the 4th memory chip of this first memory chipset, 5th memory chip, 6th memory chip and the 7th memory chip synchronously assign this instruction of erasing.
11. Memory Controllers according to claim 7, wherein also comprise a storer writing unit,
At least part of memory chip group wherein while of this storer writing unit among those memory chip groups enable writes the multiple write data coming from this host computer system.
12. Memory Controllers according to claim 7,
This transmission mode wherein between this host interface and this host computer system is a ultra direct memory (Ultra Direct Memory Access, UDMA) pattern 0, ultra direct memory pattern 1, ultra direct memory pattern 2, ultra direct memory mode 3, a ultra direct memory pattern 4 or process input output (programmed input/output, PIO) during pattern, this transmission mode between this this host interface of data-transmission mode recognition unit identification and this host computer system is for belonging to this second transmission mode
This transmission mode wherein between this host interface and this host computer system be a ultra direct memory pattern 5 or a ultra direct memory pattern 6 time, this this host interface of data-transmission mode recognition unit identification and this transmission mode of this host computer system are for belonging to this first transmission mode.
13. 1 kinds of memorizer memory devices, comprising:
A connector, in order to be coupled to a host computer system;
One type nonvolatile module, has multiple memory chip; And
One Memory Controller, is coupled to this type nonvolatile module,
Wherein this Memory Controller is in order to be grouped into multiple memory chip group by those memory chips and to identify that a transmission mode between this connector and this host computer system is for belonging to one first transmission mode or one second transmission mode,
Wherein when this transmission mode is for belonging to this first transmission mode, this Memory Controller uses one first pattern of erasing to erase the multiple data be stored in those memory chips, wherein can be enabled in this first at least part of memory chip group of erasing in pattern among those memory chip groups simultaneously
Wherein when this transmission mode is for belonging to this second transmission mode, this Memory Controller uses one second pattern of erasing to erase those data be stored in those memory chips, wherein can not be enabled in these second any two memory chip groups of erasing in pattern among those memory chip groups simultaneously.
14. memorizer memory devices according to claim 13,
Wherein those memory chips comprise one the 0th memory chip, a first memory chip, a second memory chip, one the 3rd memory chip, one the 4th memory chip, one the 5th memory chip, one the 6th memory chip, one the 7th memory chip
Wherein the 0th memory chip and this first memory chip are coupled to this host interface via a zero data input/output bus, this second memory chip and the 3rd memory chip are coupled to this host interface via one first data input/output bus, 4th memory chip and the 5th memory chip are coupled to this host interface via one second data input/output bus, and the 6th memory chip and the 7th memory chip are coupled to this host interface via one the 3rd data input/output bus
Wherein the 0th memory chip, this second memory chip, the 4th memory chip and the 6th memory chip are grouped into one the 0th memory chip group and this first memory chip, the 3rd memory chip, the 5th memory chip and the 7th memory chip are grouped into a first memory chipset by this Memory Controller.
15. memorizer memory devices according to claim 14,
Wherein when this transmission mode is for belonging to this first transmission mode, this Memory Controller is to the 0th memory chip of the 0th memory chip group, this second memory chip, 4th memory chip and the 6th memory chip are synchronously assigned one and to be erased instruction, and at the 0th memory chip, this second memory chip, 4th memory chip and the 6th memory chip perform this and erase between order period, this Memory Controller is to the 4th memory chip of this first memory chipset, 5th memory chip, 6th memory chip and the 7th memory chip synchronously assign this instruction of erasing.
16. memorizer memory devices according to claim 14,
Wherein when this transmission mode is for belonging to this second transmission mode, this Memory Controller is to the 0th memory chip of the 0th memory chip group, this second memory chip, 4th memory chip and the 6th memory chip are synchronously assigned one and to be erased instruction, and at the 0th memory chip, this second memory chip, after 4th memory chip and the 6th memory chip complete this instruction of erasing, this Memory Controller is to the 4th memory chip of this first memory chipset, 5th memory chip, 6th memory chip and the 7th memory chip synchronously assign this instruction of erasing.
17. memorizer memory devices according to claim 13, at least part of memory chip group wherein while of this Memory Controller among those memory chip groups enable writes the multiple write data coming from this host computer system.
18. memorizer memory devices according to claim 13,
This transmission mode wherein between this connector and this host computer system is a ultra direct memory (Ultra Direct Memory Access, UDMA) pattern 0, ultra direct memory pattern 1, ultra direct memory pattern 2, ultra direct memory mode 3, a ultra direct memory pattern 4 or process input output (programmed input/output, PIO) during pattern, this transmission mode between this this connector of Memory Controller identification and this host computer system is for belonging to this second transmission mode
This transmission mode wherein between this connector and this host computer system be a ultra direct memory pattern 5 or a ultra direct memory pattern 6 time, this this connector of Memory Controller recognition unit identification and this transmission mode of this host computer system are for belonging to this first transmission mode.
19. 1 kinds of memory control methods, for a memorizer memory devices, wherein this memorizer memory devices has a type nonvolatile module and this type nonvolatile module has multiple memory chip and is coupled to multiple data input/output bus of those memory chips, and this memory control methods comprises:
Identify that a transmission mode between this memorizer memory devices and a host computer system is for belonging to one first transmission mode or one second transmission mode;
When this transmission mode is for belonging to this first transmission mode, one first pattern of erasing of use is erased the multiple data be stored in those memory chips; And
When this transmission mode is for belonging to this second transmission mode, one second pattern of erasing of use is erased those data be stored in those memory chips,
Wherein this first erase mode operating time operating current be greater than this second erase mode operating time operating current.
20. memory control methods according to claim 19, wherein this first erase mode operating time among those memory chips simultaneously by a number of the memory chip of action be greater than this second erase mode operating time among those memory chips simultaneously by a number of the memory chip of action.
21. memory control methods according to claim 19, wherein this first erase mode operating time among those data input/output bus simultaneously by a number of the data input/output bus of action be greater than this second erase mode operating time among those data input/output bus simultaneously by a number of the data input/output bus of action.
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| TWI599888B (en) * | 2016-10-24 | 2017-09-21 | 緯創資通股份有限公司 | Server system and method for detecting transmission mode of server system |
| TWI658402B (en) | 2017-07-20 | 2019-05-01 | 群聯電子股份有限公司 | Data writing method, memory control circuit unit and memory storage device |
| CN109308930B (en) * | 2017-07-28 | 2021-08-24 | 群联电子股份有限公司 | Data writing method, memory control circuit unit and memory storage device |
| EP3663901B1 (en) | 2017-08-31 | 2022-12-28 | Huawei Technologies Co., Ltd. | Information writing method and device |
| CN112216329B (en) * | 2019-07-12 | 2023-11-07 | 群联电子股份有限公司 | Data erasing method, memory control circuit unit and memory storage device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1362708A (en) * | 2001-01-02 | 2002-08-07 | 吴秀林 | Read-write method for flash memory chip |
| CN1892896A (en) * | 2005-07-08 | 2007-01-10 | 英飞凌科技股份公司 | Semiconductor memory module with bus architecture |
| CN1941205A (en) * | 2005-08-17 | 2007-04-04 | 赛芬半导体有限公司 | A method of erasing non-volatile memory cells |
| CN101082891A (en) * | 2007-05-10 | 2007-12-05 | 忆正存储技术(深圳)有限公司 | Paralleling flash memory controller |
| CN101496109A (en) * | 2006-02-28 | 2009-07-29 | 飞思卡尔半导体公司 | Non-volatile memory having a multiple block erase mode and method therefor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6331951B1 (en) * | 2000-11-21 | 2001-12-18 | Advanced Micro Devices, Inc. | Method and system for embedded chip erase verification |
| KR100960041B1 (en) * | 2002-06-18 | 2010-05-31 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | Method and device for recording marks representing data in an information layer of an optical record carrier |
| KR100811274B1 (en) * | 2006-12-28 | 2008-03-07 | 주식회사 하이닉스반도체 | Method for erasing data of nand type flash memory device |
| JP2009252255A (en) * | 2008-04-01 | 2009-10-29 | Renesas Technology Corp | Nonvolatile semiconductor memory device |
-
2011
- 2011-07-18 CN CN201110200388.6A patent/CN102890617B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1362708A (en) * | 2001-01-02 | 2002-08-07 | 吴秀林 | Read-write method for flash memory chip |
| CN1892896A (en) * | 2005-07-08 | 2007-01-10 | 英飞凌科技股份公司 | Semiconductor memory module with bus architecture |
| CN1941205A (en) * | 2005-08-17 | 2007-04-04 | 赛芬半导体有限公司 | A method of erasing non-volatile memory cells |
| CN101496109A (en) * | 2006-02-28 | 2009-07-29 | 飞思卡尔半导体公司 | Non-volatile memory having a multiple block erase mode and method therefor |
| CN101082891A (en) * | 2007-05-10 | 2007-12-05 | 忆正存储技术(深圳)有限公司 | Paralleling flash memory controller |
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