CN103914391A - Data reading method, memory controller and memory storage device - Google Patents
Data reading method, memory controller and memory storage device Download PDFInfo
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- CN103914391A CN103914391A CN201310005604.0A CN201310005604A CN103914391A CN 103914391 A CN103914391 A CN 103914391A CN 201310005604 A CN201310005604 A CN 201310005604A CN 103914391 A CN103914391 A CN 103914391A
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Abstract
The invention provides a data reading method, a memory controller and a memory storage device. The reading method is used for an erasable nonvolatile memory comprising a plurality of entity erasing units. The method comprises configuring a plurality of logic addresses to be mapped to part of the entity erasing units; receiving a plurality of reading instructions from a host system, wherein the reading instructions indicate and read a plurality of first logic addresses in the logic addresses; executing the reading instructions, and determining whether the first logic addresses are continuous; pre-reading data belonging to a logic range from the entity erasing units if the first logic addresses are continuous. By means of the data reading method, the memory controller and the memory storage device, the data reading speed can be improved.
Description
Technical field
The invention relates to a kind of method for reading data, and relate to especially a kind of method for reading data for erasable formula non-volatile memory module, Memory Controller and memory storage apparatus.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, and consumer is also increased rapidly to the demand of medium.Due to erasable formula non-volatile memory module (for example, flash memory) have that data are non-volatile, power saving, volume be little, and the characteristic such as machinery-free structure, so be applicable to being very much built in above-mentioned given an example various portable multimedia devices.
In general, erasable formula non-volatile memory module can be controlled by a Memory Controller, and Memory Controller can receive the reading command that comes from host computer system.Memory Controller can be according to received reading command reading out data from erasable formula non-volatile memory module.Memory Controller can be set up an instruction array, has wherein stored the reading command that comes from host computer system.Memory Controller can discretional orders array in the execution sequence of reading command.And Memory Controller can pre-read (pre-read) some data to one memory buffer from erasable formula non-volatile memory module, can increase the speed of reading out data with convenient host computer system will read multiple continuous address time.But host computer system is assigned reading command not necessarily can be sequentially to Memory Controller, this can cause the data that pre-read to be eliminated from memory buffer.Therefore, how to increase the speed of reading out data, the subject under discussion that those skilled in the art are concerned about for this reason.
Summary of the invention
In exemplary embodiment of the present invention, propose a kind of method for reading data, Memory Controller and memory storage apparatus, can increase the speed of reading out data.
The present invention's one exemplary embodiment proposes a kind of method for reading data, for controlling an erasable formula non-volatile memory module.This erasable formula non-volatile memory module comprises multiple entity erase units.Above-mentioned method for reading data comprises: configure multiple logical addresses to map to the entity erase unit of part; Receive multiple the first reading command from host computer system, wherein multiple the first logical addresses in above-mentioned logical address are read in the first reading command indication; Carry out the first reading command, and judge whether the first logical address is continuous; And if the first logical address is continuously, read in advance the data that belong to the first logic scope to memory buffer from entity erase unit.
In an exemplary embodiment, above-mentioned method for reading data, also comprises: receive second reading command that comes from host computer system, wherein second logical address is read in the second reading command indication; Judge that the second logical address is whether in the preset range in above-mentioned logical address, wherein preset range comprises the first logic scope; If whether the second logical address in preset range, judges the second logical address is the initial logical address of the first logic scope; And if the second logical address is initial logical address, transmit the data that belong to the second logical address to host computer system.
In an exemplary embodiment, above-mentioned method for reading data, also comprise: if the second logical address is initial logical address, read in advance the data that belong to second logic scope from entity erase unit to memory buffer, wherein the second logic scope is to continue after the first logic scope.
In an exemplary embodiment, above-mentioned method for reading data also comprises: if the second logical address not for initial logical address, maintains the data that belong to the first logic scope in memory buffer and starts a timer; And if the numerical value that timer records is greater than a critical value, remove the data that belong to the first logic scope in memory buffer.
In an exemplary embodiment, above-mentioned critical value is proportional to reading the time of erasable formula non-volatile memory module.
In an exemplary embodiment, above-mentioned method for reading data also comprises: receive a third reading instruction fetch that comes from host computer system, wherein the 3rd logical address in logical address is read in third reading instruction fetch indication; And if the 3rd logical address is initial logical address, replacement timer and transmission belong to the data of the 3rd logical address to host computer system.
In an exemplary embodiment, above-mentioned method for reading data also comprises: if the second logical address, not in preset range, is removed the data that belong to the first logic scope in memory buffer.
In an exemplary embodiment, above-mentioned method for reading data also comprises: receive second reading command that comes from host computer system, wherein second logical address in logical address is read in the second reading command indication; Judge that the second logical address is whether in preset range, wherein preset range comprises the first logic scope; If the second logical address in preset range, judges that the second logical address is whether in the first logic scope; If the second logical address in the first logic scope, transmits the data that belong to the second logical address to host computer system.
In an exemplary embodiment, above-mentioned method for reading data also comprises: if the second logical address not in the first logic scope, maintains the data that belong to the first logic scope in memory buffer and starts a timer; And if the numerical value that timer records is greater than critical value, remove the data that belong to the first logic scope in memory buffer.
In an exemplary embodiment, the size of above-mentioned the first logic scope equals the size of the storage space of memory buffer.
With another one angle, the present invention's one exemplary embodiment proposes a kind of memory storage apparatus, comprises connector, erasable formula non-volatile memory module and Memory Controller.Connector is to be electrically connected to a host computer system.Erasable formula non-volatile memory module comprises multiple entity erase units.Memory Controller is to be electrically connected to connector and erasable formula non-volatile memory module, in order to configure multiple logical addresses to map to the entity erase unit of part, and receives multiple the first reading command from host computer system.Multiple the first logical addresses in above-mentioned logical address are read in these the first reading command indications.Memory Controller is also in order to carry out these the first reading command, and judges whether the first logical address is continuous.If the first logical address is that Memory Controller in order to read in advance data to memory buffer that belongs to the first logic scope in above-mentioned logical address from entity erase unit continuously.
In an exemplary embodiment, above-mentioned Memory Controller is also in order to receive the second reading command that comes from host computer system, and wherein the second logical address in logical address is read in the second reading command indication.Memory Controller is also in order to judge that the second logical address is whether in the preset range in logical address, and wherein preset range comprises the first logic scope.If the second logical address is in preset range, Memory Controller is also in order to judge whether the second logical address is the initial logical address of the first logic scope.If the second logical address is initial logical address, Memory Controller is also in order to transmit the data that belong to the second logical address to host computer system.
In an exemplary embodiment, if the second logical address is not initial logical address, Memory Controller is also in order to maintain the data that belong to the first logic scope in memory buffer and to start timer.If the numerical value that timer records is greater than critical value, Memory Controller is also in order to remove the data that belong to the first logic scope in memory buffer.
In an exemplary embodiment, above-mentioned Memory Controller is also in order to receive the third reading instruction fetch that comes from host computer system, and wherein the 3rd logical address in logical address is read in third reading instruction fetch indication.If the 3rd logical address is initial logical address, the data that Memory Controller also belongs to the 3rd logical address in order to reset timer and transmission are to host computer system.
In an exemplary embodiment, above-mentioned Memory Controller is also in order to receive the second reading command that comes from host computer system, and wherein the second logical address in logical address is read in the second reading command indication.Memory Controller is also in order to judge that the second logical address is whether in the preset range in logical address.If the second logical address is in preset range, Memory Controller is also in order to judge that the second logical address is whether in the first logic scope.If the second logical address is in the first logic scope, Memory Controller is also in order to transmit the data that belong to the second logical address to host computer system.
In an exemplary embodiment, if the second logical address not in the first logic scope, Memory Controller is also in order to maintain the data that belong to the first logic scope in memory buffer and to start timer.If the numerical value that timer records is greater than critical value, Memory Controller is also in order to remove the data that belong to the first logic scope in memory buffer.
With another one angle, the present invention's one exemplary embodiment proposes a kind of Memory Controller, for controlling an erasable formula non-volatile memory module.This Memory Controller comprises host interface, memory interface and memory management circuitry.Host interface is to be electrically connected to a host computer system.Memory interface is to be electrically connected to erasable formula non-volatile memory module, and this erasable formula non-volatile memory module comprises multiple entity erase units.Memory management circuitry is to be electrically connected to host interface and memory interface, in order to configure multiple logical addresses to map to the entity erase unit of part, and receives multiple the first reading command from host computer system.Wherein multiple the first logical addresses in above-mentioned logical address are read in these the first reading command indications.Memory management circuitry is also in order to carry out the first reading command, and judges whether the first logical address is continuous.If the first logical address is that memory management circuitry in order to read in advance data to memory buffer that belongs to the first logic scope in above-mentioned logical address from entity erase unit continuously.
In an exemplary embodiment, above-mentioned memory management circuitry is also in order to receive the second reading command that comes from host computer system, and wherein the second logical address in logical address is read in the second reading command indication.Memory management circuitry is also in order to judge that the second logical address is whether in the preset range in logical address, and wherein preset range comprises the first logic scope.If the second logical address is in preset range, memory management circuitry is also in order to judge whether the second logical address is the initial logical address of the first logic scope.If the second logical address is initial logical address, memory management circuitry is also in order to transmit the data that belong to the second logical address to host computer system.
In an exemplary embodiment, if the second logical address is initial logical address, memory management circuitry also in order to read in advance the data that belong to the second logic scope to memory buffer from entity erase unit, and wherein the second logic scope is to continue after the first logic scope.
In an exemplary embodiment, if the second logical address is not initial logical address, memory management circuitry is also in order to maintain the data that belong to the first logic scope in memory buffer and to start timer.If the numerical value that timer records is greater than critical value, memory management circuitry is also in order to remove the data that belong to the first logic scope in memory buffer.
In an exemplary embodiment, above-mentioned memory management circuitry is also in order to receive the third reading instruction fetch that comes from host computer system, and wherein the 3rd logical address in logical address is read in third reading instruction fetch indication.If the 3rd logical address is initial logical address, the data that memory management circuitry also belongs to the 3rd logical address in order to reset timer and transmission are to host computer system.
In an exemplary embodiment, if the second logical address not in preset range, memory management circuitry is also in order to remove the data that belong to the first logic scope in memory buffer.
In an exemplary embodiment, above-mentioned memory management circuitry is also in order to receive the second reading command that comes from host computer system, and wherein the second logical address in logical address is read in the second reading command indication.Memory management circuitry is also in order to judge that the second logical address is whether in the preset range in logical address.If the second logical address is in preset range, memory management circuitry is also in order to judge that the second logical address is whether in the first logic scope.If the second logical address is in the first logic scope, memory management circuitry is also in order to transmit the data that belong to the second logical address to host computer system.
In an exemplary embodiment, if the second logical address not in the first logic scope, memory management circuitry is also in order to maintain the data that belong to the first logic scope in memory buffer and to start timer.If the numerical value that timer records is greater than critical value, memory management circuitry is also in order to remove the data that belong to the first logic scope in memory buffer.
Based on above-mentioned, whether method for reading data, Memory Controller and memory storage apparatus proposed by the invention can read continuous logical address according to the reading command being finished and judge whether to want pre-read data.Thus, can increase the speed of reading out data.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A is according to the schematic diagram of the shown host computer system of an exemplary embodiment and memory storage apparatus;
Figure 1B is according to the schematic diagram of the shown computer of an exemplary embodiment, input/output device and memory storage apparatus;
Fig. 1 C is according to the schematic diagram of the shown host computer system of an exemplary embodiment and memory storage apparatus;
Fig. 2 is the summary calcspar that the memory storage apparatus shown in Figure 1A is shown;
Fig. 3 is according to the summary calcspar of the shown Memory Controller of an exemplary embodiment;
Fig. 4 is according to the example schematic of the erasable formula non-volatile memory module of the shown management of an exemplary embodiment;
Fig. 5 is the example schematic that record shelves are shown according to an exemplary embodiment;
Fig. 6 A illustrates according to an exemplary embodiment schematic diagram that reads in advance the data that belong to a logic scope;
Fig. 6 B illustrates according to an exemplary embodiment system flowchart that judges that pre-reading data is later;
Fig. 7 is the process flow diagram that method for reading data is shown according to an exemplary embodiment.
Description of reference numerals:
1000: host computer system;
1100: computer;
1102: microprocessor;
1104: random access memory;
1106: input/output device;
1108: system bus;
1110: data transmission interface;
1202: mouse;
1204: keyboard;
1206: display;
1208: printer;
1212:U dish;
1214: storage card;
1216: solid state hard disc;
1310: digital camera;
1312:SD card;
1314:MMC card;
1316: storage card;
1318:CF card;
1320: embedded memory storage;
100: memory storage apparatus;
102: connector;
104: Memory Controller;
106: erasable formula non-volatile memory module;
304 (0)～304 (R): entity erase unit;
202: memory management circuitry;
204: host interface;
206: memory interface;
252: memory buffer;
254: electric power management circuit;
256: bug check and correcting circuit;
410: data field;
420: idle district;
430: system region;
440: replace district;
450 (0)～450 (E): logical address
510: record shelves;
511～515: reading command;
610,640: logic scope;
620: logical address;
630: preset range;
S602, S604, S606, S608, S610, S612, S614: the step of system flowchart;
S702, S704, S706, S708: the step of method for reading data.
Embodiment
[the first exemplary embodiment]
Generally speaking, memory storage apparatus (also claiming storage system) comprises erasable formula non-volatile memory module and controller (also claiming control circuit).Conventionally memory storage apparatus is to use together with host computer system, so that host computer system can write to data memory storage apparatus or reading out data from memory storage apparatus.
Figure 1A is according to the schematic diagram of the shown host computer system of an exemplary embodiment and memory storage apparatus.
Please refer to Figure 1A, host computer system 1000 generally comprises computer 1100 and I/O (input/output, I/O) device 1106.Computer 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Figure 1B is according to the schematic diagram of the shown computer of an exemplary embodiment, input/output device and memory storage apparatus, and with reference to Figure 1B, input/output device 1106 comprises as the mouse 1202 of Figure 1B, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.
In embodiments of the present invention, memory storage apparatus 100 is to be electrically connected by data transmission interface 1110 and other elements of host computer system 1000.Data can be write to memory storage apparatus 100 or reading out data from memory storage apparatus 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106.For example, memory storage apparatus 100 can be the erasable formula nonvolatile memory memory storage of USB flash disk 1212, storage card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 as shown in Figure 1B etc.
Generally speaking, host computer system 1000 is for coordinating to store substantially any system of data with memory storage apparatus 100.Although in this exemplary embodiment, host computer system 1000 is to explain with computer system, but host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.For example, be digital camera (video camera) 1310 o'clock in host computer system, erasable formula nonvolatile memory memory storage is its SD card 1312 using, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded memory storage 1320 (as shown in Figure 1 C).Embedded memory storage 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is to be directly electrically connected on the substrate of host computer system.
Fig. 2 is the summary calcspar that the memory storage apparatus shown in Figure 1A is shown.
Please refer to Fig. 2, memory storage apparatus 100 comprises connector 102, Memory Controller 104 and erasable formula non-volatile memory module 106.
In this exemplary embodiment, connector 102 is to be compatible with advanced annex (Serial AdvancedTechnology Attachment, the SATA) standard of sequence.But, it must be appreciated, the invention is not restricted to this, connector 102 can be also to meet advanced annex arranged side by side (Parallel Advanced TechnologyAttachment, PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical andElectronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (PeripheralComponent Interconnect Express, PCI Express) standard, USB (universal serial bus) (UniversalSerial Bus, USB) standard, safety digit (Secure Digital, SD) interface standard, a hypervelocity generation (UltraHigh Speed-I, UHS-I) interface standard, two generations of hypervelocity (Ultra High Speed-II, UHS-II) interface standard, storage card (Memory Stick, MS) interface standard, multimedia storage card (Multi MediaCard, MMC) interface standard, down enters formula multimedia storage card (Embedded Multimedia Card, eMMC) interface standard, general flash memory (Universal Flash Storage, UFS) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated DeviceElectronics, DE) standard or other applicable standards.
Memory Controller 104 is multiple logic gates or the steering order with example, in hardware or solid form implementation in order to execution, and in erasable formula non-volatile memory module 106, carries out the runnings such as writing, read and wipe of data according to the instruction of host computer system 1000.
Erasable formula non-volatile memory module 106 is to be electrically connected to Memory Controller 104, and the data that write in order to host system 1000.Erasable formula non-volatile memory module 106 has entity erase unit 304 (0)～304 (R).For example, entity erase unit 304 (0)～304 (R) can belong to same memory crystal grain (die) or belong to different memory crystal grain.Each entity erase unit has respectively a plurality of entity sequencing unit, and the entity sequencing unit that belongs to same entity erase unit can be write independently and side by side be wiped.For example, each entity erase unit is made up of 128 entity sequencing unit.But, it must be appreciated, the invention is not restricted to this, each entity erase unit can be made up of 64 entity sequencing unit, 256 entity sequencing unit or other arbitrarily individual entity sequencing unit.
In more detail, entity erase unit is the least unit of wiping.Also the unit being wiped free of in the lump that, each entity erase unit contains minimal amount.The minimum unit that entity sequencing unit is sequencing.The minimum unit that, entity sequencing unit is data writing.Each entity sequencing unit generally includes data bit district and redundant digit district.Data bit district comprises multiple entities access address in order to store user's data, and redundant digit district for example, in order to the data (, control information and error correcting code) of storage system.In this exemplary embodiment, in the data bit district of each entity sequencing unit, can comprise 4 entity access addresses, and the size of an entity access address is 512 bytes (byte, B).But, in other exemplary embodiment, in data bit district, also can comprise 8,16 or the more or less entity access address of number, the present invention does not limit size and the number of entity access address.For example, entity erase unit is physical blocks, and entity sequencing unit is physical page or entity fan.
In this exemplary embodiment, erasable formula non-volatile memory module 106 is multilevel-cell (MultiLevel Cell, MLC) NAND type flash memory module, in a storage bag, can store at least 2 Bit datas.But, the invention is not restricted to this, also single layer cell (Single Level Cell of erasable formula non-volatile memory module 106, SLC) NAND type flash memory module, plural layer unit (Trinary Level Cell, TLC) NAND type flash memory module, other flash memory module or other have the memory module of identical characteristics.
Fig. 3 is according to the summary calcspar of the shown Memory Controller of an exemplary embodiment.
Please refer to Fig. 3, Memory Controller 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.
Memory management circuitry 202 is in order to the overall operation of control store controller 104.Specifically, memory management circuitry 202 has multiple steering orders, and in the time that memory storage apparatus 100 operates, these a little steering orders can be performed to carry out the runnings such as writing, read and wipe of data.
In this exemplary embodiment, the steering order of memory management circuitry 202 is to carry out implementation with solid form.For example, memory management circuitry 202 has microprocessor unit (not shown) and ROM (read-only memory) (not shown), and these a little steering orders are to be burned onto in this ROM (read-only memory).In the time that memory storage apparatus 100 operates, these a little steering orders can be carried out to carry out by microprocessor unit the runnings such as writing, read and wipe of data.
In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also can procedure code form for example be stored in, in the specific region (, being exclusively used in the system region of storage system data in memory module) of erasable formula non-volatile memory module 106.In addition, memory management circuitry 202 has microprocessor unit (not shown), ROM (read-only memory) (not shown) and random access memory (not shown).Particularly, this ROM (read-only memory) has the code of driving, and in the time that Memory Controller 104 is enabled, microprocessor unit can first be carried out this and drive code section that the steering order being stored in erasable formula non-volatile memory module 106 is loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can move these a little steering orders to carry out the runnings such as writing, read and wipe of data.
In addition,, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also can an example, in hardware be carried out implementation.For example, memory management circuitry 202 comprises microcontroller, Memory Management Unit, storer writing unit, storer reading unit, memory erase unit and data processing unit.Memory Management Unit, storer writing unit, storer reading unit, memory erase unit and data processing unit are to be electrically connected to microcontroller.Wherein, Memory Management Unit is in order to manage the physical blocks of erasable formula non-volatile memory module 106; Storer writing unit writes instruction data are write in erasable formula non-volatile memory module 106 in order to erasable formula non-volatile memory module 106 is assigned; Storer reading unit is in order to assign reading command with reading out data from erasable formula non-volatile memory module 106 to erasable formula non-volatile memory module 106; Memory erase unit is in order to assign erasing instruction so that data are wiped from erasable formula non-volatile memory module 106 to erasable formula non-volatile memory module 106; And data processing unit is wanted the data that write to the data of erasable formula non-volatile memory module 106 and read from erasable formula non-volatile memory module 106 in order to processing.
Host interface 204 is instruction and the data that are electrically connected to memory management circuitry 202 and transmit in order to reception and identification host computer system 1000.That is to say, the instruction that host computer system 1000 transmits and data can be sent to memory management circuitry 202 by host interface 204.In this exemplary embodiment, host interface 204 is to be compatible with SATA standard.But, it must be appreciated and the invention is not restricted to this, host interface 204 can be to be also compatible with PATA standard, IEEE 1394 standards, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other applicable data transmission standards.
Memory interface 206 is to be electrically connected to memory management circuitry 202 and in order to the erasable formula non-volatile memory module 106 of access.That is to say, the data of wanting to write to erasable formula non-volatile memory module 106 can be converted to 106 receptible forms of erasable formula non-volatile memory module via memory interface 206.
In the present invention's one exemplary embodiment, Memory Controller 104 also comprises memory buffer 252, electric power management circuit 254 and bug check and correcting circuit 256.
Memory buffer 252 is to be electrically connected to memory management circuitry 202 and in order to the temporary data that come from the data and instruction of host computer system 1000 or come from erasable formula non-volatile memory module 106.
Electric power management circuit 254 is to be electrically connected to memory management circuitry 202 and the power supply in order to control store memory storage 100.
Bug check and correcting circuit 256 be electrically connected to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives while writing instruction from host computer system 1000, bug check can produce corresponding bug check and correcting code (Error Checking andCorrecting Code for the corresponding data that this writes instruction with correcting circuit 256, ECC Code), and memory management circuitry 202 can write to corresponding these data that write instruction in erasable formula non-volatile memory module 106 with corresponding bug check and correcting code.Afterwards, when memory management circuitry 202 can read bug check corresponding to these data and correcting code when reading out data from erasable formula non-volatile memory module 106 simultaneously, and bug check and correcting circuit 256 can be according to this bug check and correcting code to read data execution error inspection and correction programs.
Fig. 4 is according to the example schematic of the erasable formula non-volatile memory module of the shown management of an exemplary embodiment.
It must be appreciated, in the time that this describes the running of physical blocks of erasable formula non-volatile memory module 106, carrying out application entity block with words such as " extraction ", " exchange ", " grouping ", " rotating " is concept in logic.That is to say, the physical location of the physical blocks of erasable formula non-volatile memory module is not changed, but in logic the physical blocks of erasable formula non-volatile memory module is operated.
Please refer to Fig. 4, Memory Controller 104 can logically be grouped into multiple regions by the physical blocks of erasable formula non-volatile memory module 304 (0)～304 (R), for example, be data field 410, idle district 420, system region 430 and replacement district 440.In another exemplary embodiment, replace district 440 and also can share the physical blocks that comprises invalid data with idle district 420.
Data field 410 is the data that come from host computer system 1000 in order to storage with the physical blocks in idle district 420.Specifically, data field 410 is physical blocks of storage data, and the physical blocks in idle district 420 is the physical blocks in order to replacement data district 410.Therefore, the physical blocks in idle district 420 is empty or spendable physical blocks, does not wherein store data or stored to be labeled as invalid data useless.That is to say, the physical blocks in idle district 420 has been performed wipes running, or can first be performed and wipe running when the physical blocks in idle district 420 is extracted for storing the physical blocks of extracting before data.Therefore, the physical blocks in idle district 420 is the physical blocks that can be used.
The physical blocks that belongs in logic system region 430 is in order to register system data, and wherein this system data comprises physical blocks number, the physical page number of each physical blocks etc. about the manufacturer of memory chips and model, memory chips.
Belonging in logic the physical blocks replacing in district 440 is to substitute physical blocks.For example, erasable formula non-volatile memory module can be reserved 4% physical blocks and uses as changing in the time dispatching from the factory.That is to say, in the time that damage with the physical blocks in system region 430 in data field 410, idle district 420, being reserved in the physical blocks replacing in district 440 is in order to replacing damaged physical blocks (, bad physical blocks (badblock)).Therefore,, if replace when still having normal physical blocks in district 440 and physical blocks damage occurring, Memory Controller 104 can extract normal physical blocks from replace district 440 changes the physical blocks of damage.If when replacing in district 440 without normal physical blocks and physical blocks damage occurring, Memory Controller 104 can be declared as write protection (writeprotect) state by whole memory storage apparatus 100, and data writing again.
Particularly, the quantity of the physical blocks in data field 410, idle district 420, system region 430 and replacement district 440 can be different according to different storer specifications.In addition, it must be appreciated, in the running of memory storage apparatus 100, the grouping relation that physical blocks is associated to data field 410, idle district 420, system region 430 and replacement district 440 can dynamically change.For example, while being substituted the physical blocks replacement in district when the physical blocks damage in idle district, the physical blocks that originally replaces district can be associated to idle district.
In this exemplary embodiment, Memory Controller 104 can be beneficial to carry out data access in the physical blocks of storage data in configuration logic address 450 (0)～450 (E).For example, for example, when memory storage apparatus 100 (is passed through archives economy by operating system 1110, FAT 32) when format, logical address 450 (0)～450 (E) maps to the physical blocks 304 (0)～304 (A) of data field 410 respectively.At this, memory management circuitry 202 (or Memory Controller 104) can be set up logical address-entity erase unit mapping table (logical address-physical erasing unit mapping table), to record the mapping relations between logical block addresses and entity erase unit.In this exemplary embodiment, the size of each logical address 450 (0)～450 (E) is same as the size of an entity erase unit,, logical address also can be called as logical block addresses (logical block address, LBA).But, in other exemplary embodiment, the size of each logical address 450 (0)～450 (E) can be also the size of an entity sequencing unit, and the present invention is the size of circumscription logic address 450 (0)～450 (E) not.
Host computer system 1000 can be assigned multiple reading command to memory management circuitry 202 (or Memory Controller 104), and these reading command are that one or more logical address in logical address 450 (0)～450 (E) is read in indication.Memory management circuitry 202 (or Memory Controller 104) can be put into these reading command in the middle of an instruction array (command queue), and memory management circuitry 202 (or Memory Controller 104) can determine to carry out the order of these reading command.If memory management circuitry 202 (or Memory Controller 104) will be carried out a reading command, memory management circuitry 202 (or Memory Controller 104) can obtain the logical address that this reading command will read, and obtain the entity erase unit that this logical address is shone upon, from then on reading out data in entity erase unit, and send these data to host computer system 1000.But, carrying out before a reading command, memory management circuitry 202 (or Memory Controller 104) can pre-read some data to the memory buffer 252 in Memory Controller 104 from entity erase unit 304 (0)～304 (B); Next, if the data that this reading command will read are in memory buffer 252, memory management circuitry 202 (or Memory Controller 104) just can send the data in memory buffer 252 to host computer system 1000, increases thus the speed of reading out data.In another exemplary embodiment, the data that memory management circuitry 202 (or Memory Controller 104) pre-reads also can be placed in a memory buffer beyond Memory Controller 104, and the present invention is also not subject to the limits.
Fig. 5 is the example schematic that record shelves are shown according to an exemplary embodiment.
Please refer to Fig. 5, after memory management circuitry 202 (or Memory Controller 104) receives multiple reading command (also claiming the first reading command) and executes these reading command from host computer system 1000, the reading command being finished can be existed in record shelves 510.For example, in record shelves 510, recorded and be performed complete reading command 511～515, it is indicated respectively and reads logical address 450 (2), 450 (4), 450 (1), 450 (0) and 450 (3) (also claiming the first logical address).Memory management circuitry 202 (or Memory Controller 104) is first to receive reading command 511, receive in order reading command 512～515 again from host computer system 1000; In other words,, according to the order that receives reading command 511～515, memory management circuitry 202 (or Memory Controller 104) can't find that host computer system 1000 will read continuous logical address.But in this exemplary embodiment, memory management circuitry 202 (or Memory Controller 104) is executing after reading command 511～515 and can judge whether the logical address that reading command 511～515 will read is continuous.For example, after the logical address that memory management circuitry 202 (or Memory Controller 104) will read in the reading command 511～515 that sorted, can discovery logic address 450 (0)～450 (4) be continuous.Although this expression host computer system 1000 be transmission reading command sequentially 511～515 to memory management circuitry 202 (or Memory Controller 104), host computer system 1000 is reading continuous logical address 450 (0)～450 (4).Because logical address 450 (0)～450 (4) is that the logical address that next host computer system 1000 will read may be also continuous continuously.Therefore, memory management circuitry 202 (or Memory Controller 104) can read the data that belong to a logic scope in advance.
In this exemplary embodiment, in record shelves 510,5 reading command 511～515 are recorded.But, in other exemplary embodiment, also can the more or less reading command of record count in record shelves 5 10.And memory management circuitry 202 (or Memory Controller 104) is judging in record shelves 510 have n reading command for starting pre-reading data continuously later, wherein n is positive integer.But the present invention does not limit the numerical value of n.
Fig. 6 A illustrates according to an exemplary embodiment schematic diagram that reads in advance the data that belong to a logic scope.
Please refer to Fig. 6 A, the logical address 450 (0)～450 (4) reading due to the reading command in record shelves 510 is that therefore memory management circuitry 202 (or Memory Controller 104) can read the data that belong to logic scope 610 in advance to memory buffer 252 continuously.Memory management circuitry 202 (or Memory Controller 104) also can be set a preset range 630, and preset range 630 can comprise logic scope 610.But the present invention is the size of circumscription logic scope 610 and preset range 630 not.Next, memory management circuitry 202 (or Memory Controller 104) can receive the reading command (also claiming the second reading command) from host computer system 1000.Logical address 620 (also claiming the second logical address) is read in this second reading command indication.Memory management circuitry 202 (or Memory Controller 104) can first decision logic address 620 whether in preset range 630.If logical address 620 is in preset range 630, whether memory management circuitry 202 (or Memory Controller 104) can decision logic address 620 be also the initial logical address (, logical address 450 (5)) of logic scope 610.If logical address 620 is logical address 450 (5), memory management circuitry 202 (or Memory Controller 104) can read the data that belong to logical address 620 from memory buffer 252, and sends these data to host computer system 1000.
On the other hand, if logical address 620 is in preset range 630 but be not logical address 450 (5), memory management circuitry 202 (or Memory Controller 104) can maintain the data that belong to logic scope 610 in memory buffer 252 and start a timer.The present invention does not limit and realizes this timer by software or the mode of hardware.At this, although host computer system 1000 will not read logical address 450 (5) at present, but because logical address 620 is also in preset range 630, therefore host computer system 1000 likely can read logical address 450 (5) within ensuing a period of time again.So memory management circuitry 202 (or Memory Controller 104) can't just be removed the data that belong to logic scope 610 in memory buffer 252 after obtaining the second reading command.But if the numerical value that this timer records is greater than a critical value, memory management circuitry 202 (or Memory Controller 104) can be removed the data that belong to logic scope 610 in memory buffer 252.In addition, if logical address 620 not in preset range 630, memory management circuitry 202 (or Memory Controller 104) also can be removed the data that belong to logic scope 610 in memory buffer 252.
After timer is activated, if memory management circuitry 202 (or Memory Controller 104) receives the next reading command (also claiming third reading instruction fetch) from host computer system 1000, and when the logical address (also claiming the 3rd logical address) that reads is indicated in this third reading instruction fetch for logical address 450 (5), this timer of memory management circuitry 202 (or Memory Controller 104) meeting replacement, and send the data that belong to logical address 450 (5) to host computer system 1000.
In other words, memory management circuitry 202 (or Memory Controller 104) can maintain the data that belong to logic scope 610 in memory buffer 252, until host computer system 1000 will read the logical address beyond preset range 630 or host computer system 1000 does not all read logical address 450 (5) (numerical value that, timer records is greater than a critical value) in a Preset Time.In an exemplary embodiment, this critical value is to be proportional to of erasable formula non-volatile memory module 106 to read the time.This reads the erasable formula non-volatile memory module 106 of time representation and carries out a needed time of reading command.If it is larger that this reads the time, memory management circuitry 202 (or Memory Controller 104) can increase this critical value, increases the data that belong to logic scope 610 thus and be stored in the time of memory buffer 252.For example, it is reading the time of twice that memory management circuitry 202 (or Memory Controller 104) can be set this critical value, but the present invention not subject to the limits.
In an exemplary embodiment, memory management circuitry 202 (or Memory Controller 104) also can once transmit the data that belong to multiple logical addresses to host computer system 1000.For example, memory management circuitry 202 (or Memory Controller 104) is first to receive the reading command that reads logical address 450 (6) to receive the reading command that reads logical address 450 (5) again, and the reading command that reads logical address 450 (6) can first be stored in the middle of instruction array.In the time judging that host computer system 1000 will read logical address 450 (5), memory management circuitry 202 (or Memory Controller 104) can send the data that belong to logical address 450 (5), 450 (6) to host computer system 1000.In an exemplary embodiment, the step that the data that belong to logical address 450 (5), 450 (6) is sent to host computer system 1000 also can be carried out by another circuit (not shown), and the present invention is also not subject to the limits.
In this exemplary embodiment, the size of logic scope 610 equals the size of the storage space of memory buffer 252.But in another exemplary embodiment, the size of logic scope 610 also can be less than the size of the storage space of memory buffer 252, the present invention is also not subject to the limits.And, when logical address 620 is logical address 450 (5), and after the data that belong to logical address 450 (5) have been transmitted to host computer system 1000, memory management circuitry 202 (or Memory Controller 104) also can read in advance the data that belong to logic scope 640 (also claiming the second logic scope) to memory buffer 252 from entity erase unit 304 (0)～304 (R).Logic scope 640 is to continue after logic scope 610, but the not size of circumscription logic scope 640 of the present invention.For example, if memory management circuitry 202 (or Memory Controller 104) once sends the data that belong to logical address 450 (5), 450 (6) to host computer system 1000, logic scope 640 can comprise two logical addresses.But, in another exemplary embodiment, memory management circuitry 202 (or Memory Controller 104) also can be in the time that host computer system 1000 reads to logical address 450 (F) or other logical address, read in advance the data that belong to logic scope 640, the present invention is also not subject to the limits.
In this exemplary embodiment, logic scope 610 is to continue in logical address 450 (0)～450 (4) afterwards.But in other exemplary embodiment, logic scope 610 also can be in logical address 450 (0)～450 (4) before.For instance, host computer system 1000 is to read from big to small continuous logical address, therefore after to execute multiple logical addresses be continuous reading command, the logic scope 610 that memory management circuitry 202 (or Memory Controller 104) reads in advance can be before these continuous logic addresses.And logic scope 640 can be before logic scope 610.
Fig. 6 B illustrates according to an exemplary embodiment system flowchart that judges that pre-reading data is later.
Please refer to Fig. 6 B, in step S602, memory management circuitry 202 (or Memory Controller 104) can read the data that belong to logic scope 610 in advance to memory buffer 252.
In step S604, memory management circuitry 202 (or Memory Controller 104) can receive a reading command, and logical address 620 is read in this reading command indication.
In step S606, memory management circuitry 202 (or Memory Controller 104) can judge this logical address 620 whether in preset range 630.
If the result of step S606 is no, in step S608, memory management circuitry 202 (or Memory Controller 104) is removed the data that belong to logic scope 610 in memory buffer 252.
If the result of step S606 is yes, in step S610, whether memory management circuitry 202 (or Memory Controller 104) decision logic address 620 is the initial logical address 450 (5) of logic scope 610.
If the result of step S610 is no, in step S612, memory management circuitry 202 (or Memory Controller 104) can wait for a period of time, and removes if exceed this time the data that belong to logic scope 610 in memory buffer 252.
If the result of step S610 is yes, in step S614, memory management circuitry 202 (or Memory Controller 104) can send the data that belong to logical address 620 to host computer system 1000.
[the second exemplary embodiment]
The second exemplary embodiment and the first exemplary embodiment are similar, only describe difference at this.Please refer to Fig. 6 A, in the first exemplary embodiment, memory management circuitry 202 (or Memory Controller 104) is to transmit data to host computer system in logical address 620 during for logical address 450 (5).But in the second exemplary embodiment, memory management circuitry 202 (or Memory Controller 104) can just transmit data to host computer system 1000 in the time that logical address 620 is any one logical address in logic scope 610.
Specifically, after reading in advance and belonging to the data of logic scope 610 and receive the reading command that reads logical address 620, memory management circuitry 202 (or Memory Controller 104) can decision logic address 620 whether within preset range 630.If logical address 620 is not within preset range 630, memory management circuitry 202 (or Memory Controller 104) can be removed the data that belong to logic scope 610 in memory buffer 252.If logical address 620 is within logic scope 630, memory management circuitry 202 (or Memory Controller 104) can be again decision logic address 620 whether in logic scope 610.If logical address 620 is in logic scope 610, memory management circuitry 202 (or Memory Controller 104) can send the data that belong to logical address 620 to host computer system 1000.If logical address 620 is within preset range 630 but not within logic scope 610, memory management circuitry 202 (or Memory Controller 104) can maintain the data that belong to logic scope 610 in memory buffer 252 and start timer.If the numerical value that this timer records is greater than critical value, memory management circuitry 202 (or Memory Controller 104) can be removed the data that belong to logic scope 610 in memory buffer 252.
Fig. 7 is the process flow diagram that method for reading data is shown according to an exemplary embodiment.It should be noted that can arrange in pairs or groups the first exemplary embodiment or the second exemplary embodiment of the process flow diagram shown in Fig. 7 implement together, or implement separately, the present invention is also not subject to the limits.
Please refer to Fig. 7, in step S702, memory management circuitry 202 (or Memory Controller 104) can configure multiple logical addresses to map to the entity erase unit of part.
In step S704, memory management circuitry 202 (or Memory Controller 104) can receive from multiple reading command of host computer system and carry out these reading command.Wherein multiple the first logical addresses are read in these reading command indications.
In step S706, memory management circuitry 202 (or Memory Controller 104) can judge whether the first logical address is continuous.If the result of step S706 is no, memory management circuitry 202 (or Memory Controller 104) can be got back to step S704, receives next reading command and judges whether the logical address that n reading command being finished will read is continuous.If the result of step S706 is yes, memory management circuitry 202 (or Memory Controller 104) can be carried out step S708.
In step S708, memory management circuitry 202 (or Memory Controller 104) can read in advance in data to memory buffer that belongs to a logic scope from entity erase unit.Within this memory buffer can be configured in Memory Controller 104 or outside.
In Fig. 7, each step has described in detail as above, just repeats no more at this.On the other hand, in Fig. 7, each step can be multiple procedure codes or circuit by implementation, and the present invention does not limit and carrys out the method for reading data shown in implementation Fig. 7 by the mode of software or hardware.
In sum, the embodiment of the present invention proposes method for reading data, Memory Controller and memory storage apparatus can judge that whether host computer system reads continuous logical address, judges whether to want pre-reading data thus.And, whether logical address that can will read according to the host computer system next one (or in instruction array a logical address that reading command will read) in a preset range, judges whether the data dimension being pre-read to be held in memory buffer thus.Thus, can increase the speed of reading out data.
Finally it should be noted that: above each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (26)
1. a method for reading data, for an erasable formula non-volatile memory module, is characterized in that, this erasable formula non-volatile memory module comprises multiple entity erase units, and this method for reading data comprises:
Configure multiple logical addresses to map to those entity erase units of part;
Receive multiple the first reading command from a host computer system, wherein multiple the first logical addresses in those logical addresses are read in those the first reading command indications;
Carry out those the first reading command, and judge whether those first logical addresses are continuous; And
If those first logical addresses are continuously, from those entity erase units, read in advance data to memory buffer that belongs to one first logic scope in those logical addresses.
2. method for reading data according to claim 1, is characterized in that, also comprises:
Reception comes from one second reading command of this host computer system, and wherein one second logical address in those logical addresses is read in this second reading command indication;
Judge that this second logical address is whether in the preset range in those logical addresses, wherein this preset range comprises this first logic scope;
If whether this second logical address in this preset range, judges this second logical address is an initial logical address of this first logic scope; And
If this second logical address is this initial logical address, transmit the data that belong to this second logical address to this host computer system.
3. method for reading data according to claim 2, is characterized in that, also comprises:
If this second logical address is this initial logical address, from those entity erase units, read in advance the data that belong to one second logic scope in those logical addresses to this memory buffer, wherein this second logic scope is to continue after this first logic scope.
4. method for reading data according to claim 2, is characterized in that, also comprises:
If this second logical address is not this initial logical address, maintains the data that belong to this first logic scope in this memory buffer and start a timer; And
If the numerical value that this timer records is greater than a critical value, remove the data that belong to this first logic scope in this memory buffer.
5. method for reading data according to claim 4, is characterized in that, this critical value is proportional to one of this erasable formula non-volatile memory module and reads the time.
6. method for reading data according to claim 4, is characterized in that, also comprises:
Reception comes from a third reading instruction fetch of this host computer system, and wherein the 3rd logical address of 1 in those logical addresses is read in this third reading instruction fetch indication; And
If the 3rd logical address is this initial logical address, reset this timer and transmission belong to the data of the 3rd logical address to this host computer system.
7. method for reading data according to claim 2, is characterized in that, also comprises:
If this second logical address, not in this preset range, is removed the data that belong to this first logic scope in this memory buffer.
8. method for reading data according to claim 1, is characterized in that, also comprises:
Reception comes from one second reading command of this host computer system, and wherein one second logical address in those logical addresses is read in this second reading command indication;
Judge that this second logical address is whether in the preset range in those logical addresses, wherein this preset range comprises this first logic scope;
If this second logical address in this preset range, judges that this second logical address is whether in this first logic scope; And
If this second logical address in this first logic scope, transmits the data that belong to this second logical address to this host computer system.
9. method for reading data according to claim 8, is characterized in that, also comprises:
If this second logical address not in this first logic scope, maintains the data that belong to this first logic scope in this memory buffer and starts a timer; And
If the numerical value that this timer records is greater than a critical value, remove the data that belong to this first logic scope in this memory buffer.
10. method for reading data according to claim 1, is characterized in that, the size of this first logic scope equals the size of a storage space of this memory buffer.
11. 1 kinds of memory storage apparatus, is characterized in that, comprising:
A connector, in order to be electrically connected to a host computer system;
One erasable formula non-volatile memory module, comprises multiple entity erase units; And
One Memory Controller, be electrically connected to this connector and this erasable formula non-volatile memory module, in order to configure multiple logical addresses to map to those entity erase units of part, and receive multiple the first reading command from this host computer system, wherein multiple the first logical addresses in those logical addresses are read in those the first reading command indications
Wherein, this Memory Controller is in order to carry out those the first reading command, and judges whether those first logical addresses are continuously,
If those first logical addresses are that this Memory Controller in order to read in advance data to memory buffer that belongs to one first logic scope in those logical addresses from those entity erase units continuously.
12. memory storage apparatus according to claim 11, it is characterized in that, this Memory Controller is also in order to receive one second reading command that comes from this host computer system, and wherein one second logical address in those logical addresses is read in this second reading command indication
This Memory Controller is also in order to judge that this second logical address is whether in the preset range in those logical addresses, and wherein this preset range comprises this first logic scope,
If this second logical address is in this preset range, this Memory Controller is also in order to judge whether this second logical address is an initial logical address of this first logic scope,
If this second logical address is this initial logical address, this Memory Controller is also in order to transmit the data that belong to this second logical address to this host computer system.
13. memory storage apparatus according to claim 12, it is characterized in that, if this second logical address is not this initial logical address, this Memory Controller is also in order to maintain the data that belong to this first logic scope in this memory buffer and to start a timer
If the numerical value that this timer records is greater than a critical value, this Memory Controller is also in order to remove the data that belong to this first logic scope in this memory buffer.
14. memory storage apparatus according to claim 13, it is characterized in that, this Memory Controller is also in order to receive a third reading instruction fetch that comes from this host computer system, and wherein the 3rd logical address of 1 in those logical addresses is read in this third reading instruction fetch indication
If the 3rd logical address is this initial logical address, the data that this Memory Controller also belongs to the 3rd logical address in order to reset this timer and transmission are to this host computer system.
15. memory storage apparatus according to claim 11, it is characterized in that, this Memory Controller is also in order to receive one second reading command that comes from this host computer system, and wherein one second logical address in those logical addresses is read in this second reading command indication
This Memory Controller is also in order to judge that this second logical address is whether in the preset range in those logical addresses, and wherein this preset range comprises this first logic scope,
If this second logical address is in this preset range, this Memory Controller is also in order to judge that this second logical address is whether in this first logic scope,
If this second logical address is in this first logic scope, this Memory Controller is also in order to transmit the data that belong to this second logical address to this host computer system.
16. memory storage apparatus according to claim 15, it is characterized in that, if this second logical address is not in this first logic scope, this Memory Controller is also in order to maintain the data that belong to this first logic scope in this memory buffer and to start a timer
If the numerical value that this timer records is greater than a critical value, this Memory Controller is also in order to remove the data that belong to this first logic scope in this memory buffer.
17. 1 kinds of Memory Controllers, is characterized in that, for controlling an erasable formula non-volatile memory module, this Memory Controller comprises:
One host interface, in order to be electrically connected to a host computer system;
One memory interface, in order to be electrically connected to this erasable formula non-volatile memory module, wherein this erasable formula non-volatile memory module comprises multiple entity erase units; And
One memory management circuitry, be electrically connected to this host interface and this memory interface, in order to configure multiple logical addresses to map to those entity erase units of part, and receive multiple the first reading command from this host computer system, wherein multiple the first logical addresses in those logical addresses are read in those the first reading command indications
Wherein, this memory management circuitry is in order to carry out those the first reading command, and judges whether those first logical addresses are continuously,
If those first logical addresses are that this memory management circuitry in order to read in advance data to memory buffer that belongs to one first logic scope in those logical addresses from those entity erase units continuously.
18. Memory Controllers according to claim 17, it is characterized in that, this memory management circuitry is also in order to receive one second reading command that comes from this host computer system, and wherein one second logical address in those logical addresses is read in this second reading command indication
This memory management circuitry is also in order to judge that this second logical address is whether in the preset range in those logical addresses, and wherein this preset range comprises this first logic scope,
If this second logical address is in this preset range, this memory management circuitry is also in order to judge whether this second logical address is an initial logical address of this first logic scope,
If this second logical address is this initial logical address, this memory management circuitry is also in order to transmit the data that belong to this second logical address to this host computer system.
19. Memory Controllers according to claim 18, it is characterized in that, if this second logical address is this initial logical address, this memory management circuitry also in order to read in advance the data that belong to one second logic scope in those logical addresses to this memory buffer from those entity erase units, and wherein this second logic scope is to continue after this first logic scope.
20. Memory Controllers according to claim 18, it is characterized in that, if this second logical address is not this initial logical address, this memory management circuitry is also in order to maintain the data that belong to this first logic scope in this memory buffer and to start a timer
If the numerical value that this timer records is greater than a critical value, this memory management circuitry is also in order to remove the data that belong to this first logic scope in this memory buffer.
21. Memory Controllers according to claim 20, is characterized in that, wherein this critical value is proportional to one of this erasable formula non-volatile memory module and reads the time.
22. Memory Controllers according to claim 20, it is characterized in that, this memory management circuitry is also in order to receive a third reading instruction fetch that comes from this host computer system, and wherein the 3rd logical address of 1 in those logical addresses is read in this third reading instruction fetch indication
If the 3rd logical address is this initial logical address, the data that this memory management circuitry also belongs to the 3rd logical address in order to reset this timer and transmission are to this host computer system.
23. Memory Controllers according to claim 18, is characterized in that, if this second logical address not in this preset range, this memory management circuitry is also in order to remove the data that belong to this first logic scope in this memory buffer.
24. Memory Controllers according to claim 17, it is characterized in that, this memory management circuitry is also in order to receive one second reading command that comes from this host computer system, and wherein one second logical address in those logical addresses is read in this second reading command indication
This memory management circuitry is also in order to judge that this second logical address is whether in the preset range in those logical addresses, and wherein this preset range comprises this first logic scope,
If this second logical address is in this preset range, this memory management circuitry is also in order to judge that this second logical address is whether in this first logic scope,
If this second logical address is in this first logic scope, this memory management circuitry is also in order to transmit the data that belong to this second logical address to this host computer system.
25. Memory Controllers according to claim 24, it is characterized in that, if this second logical address is not in this first logic scope, this memory management circuitry is also in order to maintain the data that belong to this first logic scope in this memory buffer and to start a timer
If the numerical value that this timer records is greater than a critical value, this memory management circuitry is also in order to remove the data that belong to this first logic scope in this memory buffer.
26. Memory Controllers according to claim 25, is characterized in that, the size of this first logic scope equals the size of a storage space of this memory buffer.
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| CN110286846B (en) * | 2018-03-19 | 2023-03-14 | 深圳大心电子科技有限公司 | Data moving method and storage controller |
| CN116504293A (en) * | 2023-06-27 | 2023-07-28 | 芯天下技术股份有限公司 | Method and device for reading non flash, memory chip and equipment |
| CN116504293B (en) * | 2023-06-27 | 2023-10-13 | 芯天下技术股份有限公司 | Method and device for reading non flash, memory chip and equipment |
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