CN111831210B - Memory management method, memory control circuit unit and memory storage device - Google Patents

Memory management method, memory control circuit unit and memory storage device Download PDF

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Publication number
CN111831210B
CN111831210B CN201910313385.XA CN201910313385A CN111831210B CN 111831210 B CN111831210 B CN 111831210B CN 201910313385 A CN201910313385 A CN 201910313385A CN 111831210 B CN111831210 B CN 111831210B
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physical
units
unit
error bits
distribution
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CN111831210A (en
Inventor
林炳全
陈玺宇
黄祥睿
谢秉谕
王子家
林昀佑
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket

Abstract

The invention provides a memory management method, a memory storage device and a memory control circuit unit. The method comprises the following steps: recording the number of error bits of each upper physical programming unit and the number of error bits of each lower physical programming unit in each physical erasing unit; judging whether the first entity erasing unit is a bad entity erasing unit according to the distribution of the error bit numbers of the upper entity programming unit and the lower entity programming unit of the first entity erasing unit in the entity erasing units; and if the first physical erasing unit is judged to be a bad physical erasing unit, executing data moving operation on the data on the first physical erasing unit.

Description

Memory management method, memory control circuit unit and memory storage device
Technical Field
The present invention relates to a memory management method, and more particularly, to a memory management method for determining the quality of a rewritable nonvolatile memory module according to the distribution of error bits, and a memory control circuit unit and a memory storage device using the same.
Background
Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, such that consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable multimedia devices.
In general, the degradation of the rewritable nonvolatile memory module can be determined by whether the maximum number of erroneous bits in the physically erased cell exceeds a threshold value or the distribution of threshold voltages. However, if only one of the physical erasing units has the maximum number of error bits and the other physical erasing units have good status, it is impossible to directly determine whether the physical erasing unit has been degraded according to the maximum number of error bits exceeding the threshold value, and it is impossible to perform the operation of avoiding the data loss in advance.
Accordingly, how to determine the state of the rewritable nonvolatile memory module and adjust the data read/write mechanism of the rewritable nonvolatile memory module correspondingly is one of the subjects of the study of the person skilled in the art.
Disclosure of Invention
The invention provides a memory management method, a memory control circuit unit and a memory storage device, which can judge the state of a physical erasing unit and avoid data loss.
An exemplary embodiment of the present invention provides a memory management method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical erasing units, and each physical erasing unit includes a plurality of physical programming units. The method comprises the following steps: recording the number of error bits of each upper physical programming unit and the number of error bits of each lower physical programming unit in each physical erasing unit; judging whether the first entity erasing unit is a bad entity erasing unit according to the distribution of the number of error bits of the upper entity programming unit and the distribution of the number of error bits of the lower entity programming unit of the first entity erasing unit in the entity erasing units; and if the first physical erasing unit is judged to be a bad physical erasing unit, executing data moving operation on the data on the first physical erasing unit.
In an exemplary embodiment of the present invention, the memory management method further includes: respectively calculating the average value of the number of error bits of the upper physical programming unit and the average value of the number of error bits of the lower physical programming unit in each physical erasing unit; and if the average value of the number of error bits of the upper physical programming unit is larger than the average value of the number of error bits of the lower physical programming unit, judging the first physical erasing unit as a bad physical erasing unit.
In an exemplary embodiment of the present invention, the memory management method further includes: recording the number of error bits of the physical programming units in each physical erasing unit; judging whether the first physical erasing unit is a bad physical erasing unit according to the distribution of the number of error bits of the upper physical programming unit, the distribution of the number of error bits of the middle physical programming unit and the distribution of the number of error bits of the lower physical programming unit of the first physical erasing units.
In an exemplary embodiment of the present invention, the memory management method further includes: respectively calculating the average value of the number of error bits of the upper physical programming unit, the average value of the number of error bits of the middle physical programming unit and the average value of the number of error bits of the lower physical programming unit in each physical erasing unit; if the average value of the number of error bits of the upper physical programming unit is larger than the average value of the number of error bits of the middle physical programming unit, and the average value of the number of error bits of the middle physical programming unit is larger than the average value of the number of error bits of the lower physical programming unit, the first physical erasing unit is judged to be a bad physical erasing unit.
In an exemplary embodiment of the present invention, the memory management method further includes: according to the equationRespectively obtaining the distribution of the number of error bits of the upper physical programming unit, the distribution of the number of error bits of the middle physical programming unit and the distribution of the number of error bits of the lower physical programming unit in each physical erasing unit, wherein mu is the number of error bits of the upper physical programming unit, the middle physical programming unit and the lower physical programming units in each physical erasing unitAverage value, σ, is the standard deviation of the error bit numbers of the upper physical program unit, the middle physical program unit and the lower physical program unit in each physical erase unit 2 The variance of the number of error bits of the upper, middle and lower physical program units in each physical erase unit is given by x, and f (x; mu, sigma) is the distribution of the number of error bits of each physical erase unit.
In an exemplary embodiment of the present invention, the step of obtaining the distribution of the number of error bits of the upper physical program unit, the distribution of the number of error bits of the middle physical program unit, and the distribution of the number of error bits of the lower physical program unit in each physical erase unit according to the above equation includes: if the occurrence probability of x in one standard deviation is 68.2%, the occurrence probability of x in two standard deviations is 95.4%, and the occurrence probability of x in three standard deviations is 99.7%, the distribution of the number of error bits corresponding to the first physical erasing unit is normal distribution, and it is determined that the first physical erasing unit is not a bad physical erasing unit.
In an exemplary embodiment of the present invention, the step of determining whether the first physical erase unit is a bad physical erase unit according to the distribution of the number of error bits of the upper physical program unit, the distribution of the number of error bits of the middle physical program unit, and the distribution of the number of error bits of the lower physical program unit of the first physical erase unit includes: and judging whether the first entity erasing unit is a bad entity erasing unit according to the average value of the error bit numbers of the first entity erasing unit, the error bit number corresponding to the most entity programming unit in the first entity erasing unit and the median of the plurality of groups of error bit numbers corresponding to the entity programming unit in the first entity erasing unit.
In an exemplary embodiment of the present invention, the memory management method further includes: if the number of the error bits corresponding to the most physical programming units in the first physical erasing unit is larger than the median of the multiple groups of error bits corresponding to the physical programming units in the first physical erasing unit, and the median of the multiple groups of error bits corresponding to the physical programming units in the first physical erasing unit is larger than the average value of the error bits of the first physical erasing unit, judging the first physical erasing unit as a bad physical erasing unit.
In an exemplary embodiment of the invention, the step of performing the data moving operation on the data of the first physical erase unit includes: the data on the first physically erased cell is moved to a second physically erased cell of the physically erased cells.
An exemplary embodiment of the present invention provides a memory storage device, including: the memory control circuit unit is connected with the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit. The connection interface unit is used for being electrically connected to the host system. The rewritable nonvolatile memory module comprises a plurality of physical erasing units, and each physical erasing unit comprises a plurality of physical programming units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for recording the number of error bits of the upper physical programming unit and the number of error bits of the lower physical programming unit in each physical erasing unit. The memory control circuit unit is used for judging whether the first entity erasing unit is a bad entity erasing unit according to the distribution of the number of error bits of the upper entity programming unit and the distribution of the number of error bits of the lower entity programming unit of the first entity erasing unit. In addition, if the first physical erasing unit is judged to be a bad physical erasing unit, the memory control circuit unit is also used for executing data moving operation on the data of the first physical erasing unit.
In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to calculate an average value of the number of error bits of the upper physical program unit and an average value of the number of error bits of the lower physical program unit in each physical erase unit, respectively. And if the average value of the number of error bits of the upper physical programming unit is larger than the average value of the number of error bits of the lower physical programming unit, the memory control circuit unit is further used for judging the first physical erasing unit as a bad physical erasing unit.
In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to record a number of error bits of each of the physical program units in each of the physical erase units, and the memory control circuit unit is further configured to determine whether the first physical erase unit is a bad physical erase unit according to a distribution of the number of error bits of an upper physical program unit, a distribution of the number of error bits of the middle physical program unit, and a distribution of the number of error bits of a lower physical program unit of the first physical erase units.
In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to calculate an average value of the number of error bits of the upper physical program unit, an average value of the number of error bits of the middle physical program unit, and an average value of the number of error bits of the lower physical program unit in each physical erase unit, respectively. And if the average value of the number of error bits of the upper physical program unit is larger than the average value of the number of error bits of the middle physical program unit, and the average value of the number of error bits of the middle physical program unit is larger than the average value of the number of error bits of the lower physical program unit, the memory control circuit unit is further configured to determine that the first physical erase unit is a bad physical erase unit.
In an exemplary embodiment of the present invention, the memory control circuit unit is further configured toRespectively obtaining the distribution of the number of error bits of the upper physical programming unit, the distribution of the number of error bits of the middle physical programming unit and the distribution of the number of error bits of the lower physical programming unit in each physical erasing unit, wherein mu is the upper physical erasing unitAverage value of error bit numbers of the upper, middle and lower physical program units, sigma is standard deviation of error bit numbers of the upper, middle and lower physical program units in each physical erase unit, sigma is the average value of error bit numbers of the upper, middle and lower physical program units in each physical erase unit 2 The variance of the number of error bits of the upper, middle and lower physical program units in each physical erase unit is given by x, and f (x; mu, sigma) is the distribution of the number of error bits of the upper, middle and lower physical program units in each physical erase unit.
In an exemplary embodiment of the present invention, if the occurrence probability of x within one standard deviation is 68.2%, the occurrence probability of x within two standard deviations is 95.4%, and the occurrence probability of x within three standard deviations is 99.7%, the distribution of the number of error bits corresponding to the first physical erase unit is a normal distribution, and the memory control circuit unit is further configured to determine that the first physical erase unit is not the bad physical erase unit.
In an exemplary embodiment of the invention, the memory control circuit unit is configured to determine whether the first physical erase unit is a bad physical erase unit according to an average value of the number of error bits of the first physical erase unit, the number of error bits corresponding to the most physical program units in the first physical erase unit, and a median among a plurality of sets of error bits corresponding to the physical program units in the first physical erase unit.
In an exemplary embodiment of the present invention, if the number of error bits corresponding to the most physical program units in the first physical erase unit is greater than the median of the plurality of sets of error bits corresponding to the physical program units in the first physical erase unit, and the median of the plurality of sets of error bits corresponding to the physical program units in the first physical erase unit is greater than the average value of the number of error bits of the first physical erase unit, the memory control circuit unit determines that the first physical erase unit is a bad physical erase unit.
In an exemplary embodiment of the present invention, in the operation of performing the data moving operation on the data of the first physically erased cells, the memory control circuit unit is configured to move the data of the first physically erased cells to the second physically erased cells among the physically erased cells.
An exemplary embodiment of the invention provides a memory control circuit unit for controlling a rewritable nonvolatile memory module including a plurality of physical erasing units. Each of the physical erasing units includes a plurality of physical programming units. The memory control circuit unit includes: host interface, memory interface and memory management circuitry. The host interface is used for being electrically connected to the host system. The memory interface is used for being electrically connected to the rewritable nonvolatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used for recording the number of error bits of each upper physical programming unit and the number of error bits of each lower physical programming unit in each physical erasing unit, and judging whether the first physical erasing unit is a bad physical erasing unit according to the distribution of the number of error bits of the upper physical programming unit and the distribution of the number of error bits of the lower physical programming unit of the first physical erasing unit. If the first physical erasing unit is judged to be a bad physical erasing unit, the memory management circuit is used for executing data moving operation on the data of the first physical erasing unit.
In an exemplary embodiment of the present invention, the average value of the number of error bits of the upper physical program unit and the average value of the number of error bits of the lower physical program unit in each physical erase unit are calculated respectively. And if the average value of the number of error bits of the upper physical programming unit is larger than the average value of the number of error bits of the lower physical programming unit, the memory management circuit is further configured to determine that the first physical erasing unit is a bad physical erasing unit.
In an exemplary embodiment of the present invention, the memory management circuit is further configured to record a number of error bits of each of the physical program units in each of the physical erase units, and the memory management circuit is further configured to determine whether the first physical erase unit is a bad physical erase unit according to a distribution of the number of error bits of an upper physical program unit, a distribution of the number of error bits of the middle physical program unit, and a distribution of the number of error bits of a lower physical program unit of the first physical erase units.
In an exemplary embodiment of the present invention, the memory management circuit further calculates an average value of the number of error bits of the upper physical program unit, an average value of the number of error bits of the middle physical program unit, and an average value of the number of error bits of the lower physical program unit in each physical erase unit, respectively. And if the average value of the number of error bits of the upper physical program unit is larger than the average value of the number of error bits of the middle physical program unit, and the average value of the number of error bits of the middle physical program unit is larger than the average value of the number of error bits of the lower physical program unit, the memory management circuit is further configured to determine that the first physical erase unit is a bad physical erase unit.
In an exemplary embodiment of the present invention, the memory management circuit is further configured toRespectively obtaining the distribution of the number of error bits of the upper physical programming unit, the distribution of the number of error bits of the middle physical programming unit and the distribution of the number of error bits of the lower physical programming unit in each physical erasing unit, wherein mu is the average value of the number of error bits of the upper physical programming unit, the middle physical programming unit and the lower physical programming unit in each physical erasing unit, sigma is the standard deviation of the number of error bits of the upper physical programming unit, the middle physical programming unit and the lower physical programming unit in each physical erasing unit 2 For each physical erasing unit, the variance of the error bit numbers of the upper physical programming unit, the middle physical programming unit and the lower physical programming unit is x, x is the upper physical programming unit, the middle physical programming unit in each physical erasing unitThe number of error bits of the body program unit and the lower body program unit, f (x; mu, sigma), is the distribution of the number of error bits of each body erase unit.
In an exemplary embodiment of the invention, if the occurrence probability of x within one standard deviation is 68.2%, the occurrence probability of x within two standard deviations is 95.4%, and the occurrence probability of x within three standard deviations is 99.7%, the distribution of the number of error bits corresponding to the first physical erase unit is a normal distribution, and the memory management circuit determines that the first physical erase unit is not a bad physical erase unit.
In an exemplary embodiment of the invention, the memory management circuit determines whether the first physical erase unit is a bad physical erase unit according to an average value of the number of error bits of the first physical erase unit, the number of error bits corresponding to the most physical program units in the first physical erase unit, and a median among a plurality of sets of error bits corresponding to the physical program units in the first physical erase unit.
In an exemplary embodiment of the present invention, if the number of error bits corresponding to the most physical program units in the first physical erase unit is greater than the median of the plurality of sets of error bits corresponding to the physical program units in the first physical erase unit, and the median of the plurality of sets of error bits corresponding to the physical program units in the first physical erase unit is greater than the average value of the number of error bits of the first physical erase unit, the memory management circuit determines that the first physical erase unit is a bad physical erase unit.
In an exemplary embodiment of the present invention, in performing a data moving operation on the data of the first physically erased cells, the memory management circuit is further configured to move the data of the first physically erased cells to the second physically erased cells among the physically erased cells.
Based on the above, the present invention provides a memory management method, a memory storage device and a memory control circuit unit, which acquire parameters of the same physical erasing unit, such as average value, standard deviation, median, etc., of the number of error bits corresponding to all the upper physical programming unit and the lower physical programming unit, respectively, according to the distribution of the number of error bits in the physical erasing unit, so as to determine whether the physical erasing unit is a bad physical erasing unit, thereby avoiding data loss.
Drawings
FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention.
FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention.
FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention.
FIG. 7 is a diagram illustrating a distribution of the number of error bits of the first physical erase unit 610 (0) according to another exemplary embodiment of the present invention.
Fig. 8A, 8B and 8C are diagrams illustrating distribution of the number of error bits as right offset, non-offset and left offset, respectively, according to another exemplary embodiment of the present invention.
FIG. 8A is a diagram illustrating a distribution of the number of error bits of a first physically erased cell as a worse right offset according to another exemplary embodiment of the present invention.
FIG. 8B is a diagram illustrating a distribution of the number of error bits of a first physically erased cell according to another exemplary embodiment of the present invention.
FIG. 8C is a diagram illustrating a distribution of the number of error bits of the first physically erased cell according to another exemplary embodiment of the present invention with a left offset better than a right offset.
FIG. 8D is a diagram illustrating a distribution of the number of error bits in an aged state of a first physical erase cell according to another exemplary embodiment of the present invention.
FIG. 9 is a flowchart of a memory management method according to an example embodiment of the invention.
FIG. 10 is a flowchart of a memory management method according to another exemplary embodiment of the present invention.
FIG. 11 is a flowchart of a memory management method according to another exemplary embodiment of the present invention.
[ symbolic description ]
10: memory storage device
11: host system
110: system bus
111: processor and method for controlling the same
112: random access memory
113: read-only memory
114: data transmission interface
12: input/output (I/O) device
20: motherboard
201: USB flash disk
202: memory card
203: solid state disk
204: wireless memory storage device
205: global positioning system module
206: network interface card
207: wireless transmission device
208: keyboard with keyboard body
209: screen panel
210: horn with horn body
32: SD card
33: CF card
34: embedded memory device
341: embedded multimedia card
342: embedded multi-chip packaging storage device
402: connection interface unit
404: memory control circuit unit
406: rewritable nonvolatile memory module
502: memory management circuit
504: host interface
506: memory interface
508: error checking and correcting circuit
510: buffer memory
512: power management circuit
601: storage area
602: idle zone
610 (0) to 610 (B): physical erasing unit
612 (0) to 612 (C): logic unit
S901, S903, S905: steps of a memory management method
S1001, S1003, S1005, S1007: steps of a memory management method
S1101, S1103, S1105, S1107: steps of a memory management method
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Memory storage devices are typically used with host systems so that the host system can write data to or read data from the memory storage device.
FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 are electrically connected to a system bus 110.
In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 through the system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.
In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through a wired or wireless manner via the data transmission interface 114. The memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (iBeacon) or the like based on a variety of wireless communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.
In an example embodiment, the host system referred to is any system that can cooperate with substantially a memory storage device to store data. Although the host system is described in the above exemplary embodiment as a computer system, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded memory devices of various types, such as embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or embedded multi-chip package (embedded Multi Chip Package, eMCP) memory device 342, that electrically connect the memory module directly to the substrate of the host system.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable nonvolatile memory module 406.
The connection interface unit 402 is used for electrically connecting the memory storage device 10 to the host system 11. In the present exemplary embodiment, the connection interface unit 402 is compatible with the serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a standard compliant with a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a High-Speed peripheral component interconnect (Peripheral Component Interconnect Express, PCI Express) standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, s) interface standard, an ehcp interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in a single chip, or the connection interface unit 402 may be disposed off-chip with the memory control circuit unit 404.
The memory control circuit unit 404 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to the instructions of the host system 11.
The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a complex-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. By applying the read voltage, it can be determined which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.
In the exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical program cells, and the physical program cells form a plurality of physical erase cells. Specifically, memory cells on the same word line constitute one or more physical programming units. For example, if each memory cell can store more than 3 bits, the physical program units on the same word line can be classified into at least a lower physical program unit, a middle physical program unit, and an upper physical program unit. Taking TLC NAND flash memory as an example, the least significant bits (Least Significant Bit, LSB) of the memory cells on the same word line form a lower physical programming unit; CSB (Central Significant Bit) of the memory cells on the same word line constitute a middle-body programming unit; and the most significant bit (Most Significant Bit, MSB) of the memory cells on the same word line constitute an upper physical programming unit. Generally, in TLCNAND flash memory, the writing speed of the lower physical programming unit is higher than the writing speeds of the middle physical programming unit and the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the middle physical programming unit and the upper physical programming unit.
In the present exemplary embodiment, the physical programming unit is the minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit is a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units typically include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504 and a memory interface 506.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform writing, reading and erasing operations of data while the memory storage device 10 is operating. The operation of the memory management circuit 502 is described as follows, which is equivalent to the description of the operation of the memory control circuit unit 404.
In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.
In another example embodiment, the control instructions of the memory management circuit 502 may also be stored in program code form in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area of the memory module dedicated to storing system data). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit 404 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.
Furthermore, in another example embodiment, the control instructions of the memory management circuit 502 may also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read instruction sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erase circuit is configured to issue an erase command sequence to the rewritable nonvolatile memory module 406 to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, read command sequence, and erase command sequence may include one or more program codes or command codes, respectively, and are used to instruct the rewritable nonvolatile memory module 406 to perform the corresponding write, read, erase, etc. In an example embodiment, the memory management circuitry 502 may also issue other types of sequences of instructions to the rewritable non-volatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 504 is electrically connected to the memory management circuit 502 and is used for receiving and determining the commands and data transmitted by the host system 11. That is, the instructions and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the present exemplary embodiment, host interface 504 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with PATA standards, IEEE 1394 standards, PCI Express standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.
The memory interface 506 is electrically connected to the memory management circuit 502 and is used to access the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format acceptable to the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 is to access the rewritable nonvolatile memory module 406, the memory interface 506 will transmit the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These sequences of instructions are, for example, generated by memory management circuitry 502 and transferred to rewritable non-volatile memory module 406 through memory interface 506. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.
In an example embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508, a buffer memory 510, and a power management circuit 512.
The error checking and correcting circuit 508 is electrically connected to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 406. Then, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 508 performs an error check and correction operation on the read data according to the error correction code and/or the error check code.
The buffer memory 510 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.
FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention.
It should be noted that in the following exemplary embodiments, the operation of the physical erase unit in terms of "select" and "group" is a logical concept in describing the management of the physical erase unit of the rewritable nonvolatile memory module 406. That is, the physical locations of the physical erased cells of the rewritable nonvolatile memory module 406 are not changed, but the physical erased cells of the rewritable nonvolatile memory module 406 are logically operated.
Referring to FIG. 6, the memory management circuit 502 groups the physical erase units 610 (0) -610 (B) of the rewritable nonvolatile memory module 406 into a memory area 601 and a spare (spare) area 602. For example, physical erase units 610 (0) through 610 (A) belong to the memory area 601, and physical erase units 610 (A+1) through 610 (B) belong to the spare area 602. In the present exemplary embodiment, a physically erased cell refers to a physically erased cell. However, in another exemplary embodiment, one physical erase unit may also include a plurality of physical erase units. In addition, the memory management circuit 502 may associate a physical erase unit to one of the memory area 601 and the spare area 602 by using a tag.
During operation of the memory device 10, the association of a particular physical erased cell with either the memory region 601 or the spare region 602 may dynamically change. For example, when write data is received from the host system 11, the memory management circuit 502 selects a physical erase unit from the spare area 602 to store at least a portion of the write data and associates the physical erase unit to the memory area 601. In addition, after erasing a physical erased cell belonging to the memory area 601 to erase data therein, the memory management circuit 502 associates the erased physical erased cell to the spare area 602.
In the present exemplary embodiment, the physical erased cells belonging to the spare area 602 are also referred to as spare physical erased cells, and the physical erased cells belonging to the storage area 601 are also referred to as non-spare (non-spare) physical erased cells. Each physical erased cell belonging to the spare area 602 is an erased physical erased cell and does not store any data, and each physical erased cell belonging to the storage area 601 stores data. Furthermore, each physical erase unit belonging to the spare area 602 may not store any valid data, and each physical erase unit belonging to the storage area 601 may store valid data and/or invalid data.
In an example embodiment, memory management circuit 502 configures logic units 612 (0) -612 (C) to map physically erased cells in memory region 601. In the exemplary embodiment, the host system 11 accesses the physical erase unit belonging to the memory area 601 by a Logical Address (LA). Thus, each of the logic units 612 (0) -612 (C) refers to a logical address. However, in another exemplary embodiment, each of the logic units 612 (0) -612 (C) may also refer to a logic program unit, a logic erase unit, or be composed of a plurality of consecutive or non-consecutive logic addresses. In addition, each of logic cells 612 (0) -612 (C) may be mapped to one or more physical erase cells.
In the exemplary embodiment, the memory management circuit 502 records a mapping relationship (also referred to as a logical-to-physical mapping relationship) between logical units and physical erase units in at least one logical-to-physical mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access to the memory storage device 10 according to the logical-to-physical mapping table.
In an exemplary embodiment, a TLC NAND type flash memory module is illustrated. After the physical program units of the physical erase units 610 (0) -610 (a) belonging to the memory area 601 are written with data, the upper physical program unit, the middle physical program unit and the lower physical program unit written with data generate error bits correspondingly because the physical program units on the same word line are classified into the upper physical program unit, the middle physical program unit and the lower physical program unit.
The memory management circuit 502 records the number of error bits of each upper physical program unit, the number of error bits of each lower physical program unit, and the number of error bits of each upper physical program unit of each physical erase unit 610 (0) -610 (a). The memory management circuit 502 determines whether one of the physical erase units 610 (0) -610 (a) (e.g., the first physical erase unit 610 (0)) is a bad physical erase unit according to the distribution of the number of error bits of the upper physical program unit, the distribution of the number of error bits of the middle physical program unit, and the distribution of the number of error bits of the lower physical program unit of each of the physical erase units 610 (0) -610 (a). After the memory management circuit 502 determines whether the first physically erased cell 610 (0) is a bad physically erased cell, the memory management circuit 502 continues to determine the status of the rewritable nonvolatile memory module 406 one by one for other physically erased cells.
In the following exemplary embodiments, the memory management circuit 502 is described in detail to obtain parameters such as average, standard deviation, median of the number of error bits of the upper physical program unit, the middle physical program unit and the lower physical program unit in each physical erase unit according to the distribution of the number of error bits of the upper physical program unit, the distribution of the number of error bits of the middle physical program unit and the distribution of the number of error bits of the lower physical program unit of each physical erase unit, so as to determine whether the physical erase unit is a bad physical erase unit.
In an exemplary embodiment, taking an example of determining whether the first physical erasing unit 610 (0) among the physical erasing units 610 (0) -610 (a) is a bad physical erasing unit, the memory management circuit 502 calculates an average value XP of the number of error bits of all the upper physical programming units, an average value UP of the number of error bits of all the middle physical programming units, and an average value LP of the number of error bits of all the lower physical programming units in the first physical erasing unit 610 (0) according to the distribution of the number of error bits of the upper physical programming units, the distribution of the number of error bits of the middle physical programming units, and the distribution of the number of error bits of the lower physical programming units in the first physical erasing unit 610 (0).
If the average value XP of the number of error bits of all the upper physical program units in the first physical erase unit 610 (0) is greater than the average value UP of the number of error bits of all the middle physical program units, and the average value UP of the number of error bits of all the middle physical program units is greater than the average value LP of the number of error bits of all the lower physical program units, the memory management circuit 502 determines the first physical erase unit 610 (0) as a bad physical erase unit. In other words, when XP > UP > LP is met, the memory management circuit 502 determines the first physical erase unit 610 (0) as a bad physical erase unit, and after the first physical erase unit 610 (0) is determined as a bad physical erase unit, the memory management circuit 502 performs a data moving operation on the data of the first physical erase unit 610 (0).
In an exemplary embodiment, the memory management circuit 502 can move the data stored in the first physical erase unit 610 (0) to the second physical erase unit 610 (1), and classify the first physical erase unit 610 (0) as a bad physical erase unit, and the first physical erase unit 610 (0) is not used in the subsequent data access. In another example embodiment, the memory management circuit 502 may also move the data stored in the first physical erase unit 610 (0) to the third physical erase unit 610 (a+1) in the spare area 602, that is, the memory management circuit 502 may select the third physical erase unit 610 (a+1) from the spare area 602 to store the data and associate the third physical erase unit 610 (a+1) to the memory area 601. Thereafter, the memory management circuit 502 performs an erase operation on the first physical erase unit 610 (0), and when another data is programmed into the first physical erase unit 610 (0), the memory management circuit 502 classifies the first physical erase unit 610 (0) as a bad physical erase unit if a programming error occurs during the programming of the another data into the first physical erase unit 610 (0).
In another example embodiment, the memory management circuit 502 can determine the first physically erased cell 610 (0) as a non-bad physically erased cell according to whether the distribution of the number of error bits of the first physically erased cell 610 (0) is a normal distribution.
In the exemplary embodiment, the memory management circuit 502 obtains the distribution of the number of error bits of the upper physical program unit, the distribution of the number of error bits of the middle physical program unit, and the distribution of the number of error bits of the lower physical program unit of each of the physical erase units 610 (0) -610 (a), respectively, according to equation (1).
Wherein μ is the average of the number of error bits of the upper, middle and lower physical program units of each of the physical erase units 610 (0) -610 (A), and σ is the average of the number of error bits of each of the physical erase units 610 (0) -610 (A)Standard deviation, sigma, of the number of erroneous bits of an upper, middle and lower physical program unit of a physical erase unit 2 The variance of the number of error bits for the upper, middle and lower physical program units of each of the physical erase units 610 (0) -610 (a), x being the number of error bits for the upper, middle and lower physical program units of each of the physical erase units 610 (0) -610 (a), f (x; μ, σ) being the distribution of the number of error bits for each of the physical erase units 610 (0) -610 (a).
FIG. 7 is a diagram illustrating a distribution of the number of error bits of the first physical erase unit 610 (0) according to another exemplary embodiment of the present invention.
Referring to FIG. 7, the occurrence probability of x within one standard deviation is about 68.2%, i.e. satisfies the relationship (2), where x is the number of error bits of the upper physical program unit, the middle physical program unit and the lower physical program unit of the first physical erase unit 610 (0),
Pr(μ-σ≤X≤μ+σ)≈0.6827...(2)
the occurrence probability of x within twice the standard deviation is about 95.4%, that is, the relation (3) is satisfied,
Pr(μ-2σ≤X≤μ+2σ)≈0.9545...(3)
the occurrence probability of x within three times standard deviation is about 99.7%, that is, the relation (4) is satisfied,
Pr(μ-3σ≤X≤μ+3σ)≈0.9973...(4)
that is, if the occurrence probabilities of x in the one, two and three standard deviations are about 68.2%, 95.4% and 99.7%, respectively, the distribution of the number of error bits of the first physical erase unit 610 (0) is a normal distribution, and the memory management circuit 502 determines the first physical erase unit 610 (0) as a non-bad physical erase unit.
In another example embodiment, the memory management circuit 502 can determine whether the first physical erase unit 610 (0) is a bad physical erase unit according to whether the distribution of the number of error bits of the first physical erase unit 610 (0) is offset. In detail, the memory management circuit 502 determines whether the first physical erasing unit 610 (0) is a bad physical erasing unit according to the average value Mean of the number of error bits of the first physical erasing unit 610 (0), the number Mode of error bits corresponding to the most physical erasing unit in the first physical erasing unit 610 (0), and the Median of the number of error bits corresponding to the physical erasing unit in the first physical erasing unit 610 (0) (i.e. the Median of the number of error bits corresponding to the physical erasing unit).
Referring to FIG. 8A, FIG. 8A is a diagram illustrating a distribution of the number of error bits of the first physical erase unit 610 (0) as a right offset according to another exemplary embodiment of the present invention. If the number of error bits Mode corresponding to the most physically programmed cells in the first physically erased cell 610 (0) is greater than the Median among the plurality of sets of error bits corresponding to physically programmed cells in the first physically erased cell 610 (0), and the Median among the plurality of sets of error bits corresponding to physically programmed cells in the first physically erased cell 610 (0) is greater than the average Mean of the number of error bits Mean of the first physically erased cell 610 (0), i.e. meets Mode > Median > Mean, the memory management circuit 502 determines that the first physically erased cell 610 (0) is a bad physically erased cell, and performs a data moving operation on the data stored in the first physically erased cell 610 (0). The foregoing details of the data moving operation are not described herein.
As another example, FIG. 8B is a diagram illustrating a distribution of the number of error bits of a first physically erased cell as being unbiased according to another exemplary embodiment of the present invention. FIG. 8C is a diagram illustrating a distribution of the number of error bits of the first physical erase unit 610 (0) according to another exemplary embodiment of the present invention with a left offset better than a right offset. If the average Mean value Mean of the number of error bits of the first physical erase unit 610 (0) is greater than the Median of the number of error bits corresponding to the physical program units in the first physical erase unit 610 (0), and the Median of the number of error bits corresponding to the physical program units in the first physical erase unit 610 (0) is greater than the number Mode of error bits corresponding to the most physical program units in the first physical erase unit 610 (0), that is, the Mean > Median > Mode is met, the memory management circuit 502 determines that the first physical erase unit 610 (0) is a good physical erase unit and does not perform a data moving operation on the data stored in the first physical erase unit 610 (0). As another example, FIG. 8D is a diagram illustrating a distribution of the number of error bits in the first physical erase unit 610 (0) in an aged state according to another exemplary embodiment of the present invention. As shown in FIG. 8D, the number of erroneous bits of the first physical erase unit 610 (0) is flattened, and the first physical erase unit 610 (0) in the aged state has a higher probability of being determined to be a bad physical erase unit. It should be noted that although the above description exemplifies a TLC NAND type flash memory module, in another exemplary embodiment, an MLC NAND type flash memory module may also be suitable. The memory management circuit 502 obtains parameters such as an average value, a standard deviation, a median, etc. of the number of error bits in the upper physical program unit and the lower physical program unit in the first physical erase unit 610 (0) according to the distribution of the number of error bits in the first physical erase unit 610 (0) to determine whether the first physical erase unit 610 (0) is a bad physical erase unit. For example, if the average XP of the number of error bits of the upper physical program unit in the first physical erase unit 610 (0) is greater than the average LP of the number of error bits of the lower physical program unit, the memory management circuit 502 determines the first physical erase unit 610 (0) as a bad physical erase unit. In other words, when XP > LP is met, the memory management circuit 502 determines the first physical erase unit 610 (0) as a bad physical erase unit, and after determining the first physical erase unit 610 (0) as a bad physical erase unit, the memory management circuit 502 performs a data moving operation on the data of the first physical erase unit 610 (0).
FIG. 9 is a flowchart of a memory management method according to an example embodiment of the invention.
Referring to FIG. 9, in step S901, the memory management circuit 502 records the number of error bits of each upper physical program unit, the number of error bits of each middle physical program unit, and the number of error bits of each lower physical program unit of each physical erase unit 610 (0) -610 (A).
In step S903, the memory management circuit 502 determines whether the first physical erasing unit 610 (0) is a bad physical erasing unit according to the distribution of the number of error bits of the upper physical programming unit, the distribution of the number of error bits of the middle physical programming unit, and the distribution of the number of error bits of the lower physical programming unit of the first physical erasing unit 610 (0).
If the first physical erasing unit 610 (0) is determined to be a bad physical erasing unit, in step S905, the memory management circuit 502 performs a data moving operation on the data of the first physical erasing unit 610 (0).
FIG. 10 is a flowchart of a memory management method according to another exemplary embodiment of the present invention.
Referring to FIG. 10, in step S1001, the memory management circuit 502 records the number of error bits of each upper physical program unit, the number of error bits of each middle physical program unit, and the number of error bits of each lower physical program unit of each physical erase unit 610 (0) -610 (A).
In step S1003, the memory management circuit 502 calculates an average value XP of the number of error bits of the upper physical program unit, an average value UP of the number of error bits of the middle physical program unit, and an average value LP of the number of error bits of the lower physical program unit of each of the physical erase units 610 (0) -610 (a), respectively.
In step S1005, the memory management circuit 502 determines whether XP > UP > LP is met to determine whether the first physically erased cell 610 (0) is a bad physically erased cell.
If the average value XP of the number of error bits of the upper physical program unit of the first physical erase unit 610 (0) among the physical erase units 610 (0) -610 (a) is greater than the average value UP of the number of error bits of the middle physical program unit, and the average value UP of the number of error bits of the middle physical program unit is greater than the average value LP of the number of error bits of the lower physical program unit, i.e. accords with XP > UP > LP, in step S1007, the memory management circuit 502 determines that the first physical erase unit 610 (0) is a bad physical erase unit, and performs a data moving operation on the data on the first physical erase unit 610 (0).
FIG. 11 is a flowchart of a memory management method according to another exemplary embodiment of the present invention.
Referring to FIG. 11, in step S1101, the memory management circuit 502 records the number of error bits of each upper physical program unit, the number of error bits of each middle physical program unit, and the number of error bits of each lower physical program unit of each of the physical erase units 610 (0) -610 (A).
In step S1103, the memory management circuit 502 obtains an average Mean value Mean of the number of error bits of the first physical erasing unit 610 (0) among the physical erasing units 610 (0) -610 (a), the number Mode of error bits corresponding to the most physical programming units among the first physical erasing unit 610 (0), and Median medians among the plurality of sets of error bits corresponding to the physical programming units among the first physical erasing unit 610 (0).
In step S1105, the memory management circuit 502 determines whether the Mode > Median > Mean is met to determine whether the first physical erase unit 610 (0) is a bad physical erase unit.
If the Mode > media > Mean is met, in step S1107, the memory management circuit 502 determines that the first physical erase unit 610 (0) is a bad physical erase unit, and performs a data moving operation on the data on the first physical erase unit 610 (0).
In summary, the present invention provides a memory management method, a memory storage device and a memory control circuit unit, which at least obtain parameters of the same physical erasing unit, such as average value, standard deviation, median, etc. of the number of error bits corresponding to all the upper physical programming unit and the lower physical programming unit, respectively, according to the distribution of the number of error bits, so as to determine whether the physical erasing unit is a bad physical erasing unit, gradually determine all the physical erasing units in the rewritable nonvolatile memory module, thereby determining the quality of the rewritable nonvolatile memory module, and correspondingly adjusting the data read/write mechanism of the rewritable nonvolatile memory module.

Claims (27)

1. A memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erase units, each of the plurality of physical erase units comprising a plurality of physical program units, the memory management method comprising:
recording the number of error bits of each upper physical programming unit and the number of error bits of each lower physical programming unit in each of the plurality of physical erasing units;
Judging whether a first entity erasing unit is a bad entity erasing unit according to the distribution of the number of error bits of a plurality of upper entity programming units and the distribution of the number of error bits of a plurality of lower entity programming units of the first entity erasing unit; and
and if the first entity erasing unit is judged to be the bad entity erasing unit, executing data moving operation on the data on the first entity erasing unit.
2. The memory management method of claim 1, wherein determining whether a first physical erased cell of the plurality of physical erased cells is the bad physical erased cell based on a distribution of a number of error bits of the plurality of upper physical programmed cells and a distribution of a number of error bits of the plurality of lower physical programmed cells comprises:
respectively calculating the average value of the error bit numbers of the upper entity programming units and the average value of the error bit numbers of the lower entity programming units in each entity erasing unit; and
and if the average value of the error bit numbers of the upper physical programming units in the first physical erasing unit is larger than the average value of the error bit numbers of the lower physical programming units, judging the first physical erasing unit as the bad physical erasing unit.
3. The memory management method of claim 1, further comprising:
recording the number of error bits of the physical programming units in each of the plurality of physical erasing units;
wherein the step of determining whether a first physical erased cell of the plurality of physical erased cells is the bad physical erased cell according to the distribution of the number of error bits of the plurality of upper physical programmed cells and the distribution of the number of error bits of the plurality of lower physical programmed cells of the first physical erased cell comprises:
judging whether the first physical erasing unit is the bad physical erasing unit according to the distribution of the number of error bits of the upper physical programming units, the distribution of the number of error bits of the middle physical programming units and the distribution of the number of error bits of the lower physical programming units of the first physical erasing unit.
4. The memory management method of claim 3, wherein the step of determining whether the first physical erase unit is a bad physical erase unit according to a distribution of the number of error bits of the plurality of upper physical program units, a distribution of the number of error bits of the plurality of middle physical program units, and a distribution of the number of error bits of the plurality of lower physical program units of the first physical erase unit comprises:
Respectively calculating the average value of the error bit numbers of the upper entity programming units, the average value of the error bit numbers of the middle entity programming units and the average value of the error bit numbers of the lower entity programming units in each entity erasing unit; and
and if the average value of the error bit numbers of the plurality of upper entity programming units in the first entity erasing unit is larger than the average value of the error bit numbers of the plurality of middle entity programming units, and the average value of the error bit numbers of the plurality of middle entity programming units is larger than the average value of the error bit numbers of the plurality of lower entity programming units, judging the first entity erasing unit as the bad entity erasing unit.
5. The memory management method of claim 3, wherein the memory management method further comprises:
according to equation (1), the distribution of the number of error bits of the upper physical program units, the distribution of the number of error bits of the middle physical program units and the distribution of the number of error bits of the lower physical program units in each of the plurality of physical erase units are obtained,
Wherein μ is an average value of the numbers of error bits of the plurality of upper physical program units, the plurality of middle physical program units, and the plurality of lower physical program units in each of the plurality of physical erase units, σ is a standard deviation of the numbers of error bits of the plurality of upper physical program units, the plurality of middle physical program units, and the plurality of lower physical program units in each of the plurality of physical erase units, σ 2 For each of the plurality of physical erase units, the plurality of upper physical program units, the plurality of middle physical program units, and the plurality of lower physical program units, x is a variance of the number of error bits of each of the plurality of physical erase units, the plurality of upper physical program units, the plurality of middle physical program unitsAnd the number of error bits of the plurality of lower physical programming units.
6. The memory management method according to claim 5, wherein the step of obtaining the distribution of the number of error bits of the upper physical program units, the distribution of the number of error bits of the middle physical program units, and the distribution of the number of error bits of the lower physical program units in each of the plurality of physical erase units according to equation (1) comprises:
If the occurrence probability of x in one standard deviation is 68.2%, the occurrence probability of x in two standard deviations is 95.4%, and the occurrence probability of x in three standard deviations is 99.7%, the distribution of the number of error bits corresponding to the first physical erasing unit is normal distribution, and the first physical erasing unit is judged to be not the bad physical erasing unit.
7. The memory management method of claim 3, wherein determining whether the first physical erase unit of the plurality of physical erase units is the bad physical erase unit according to a distribution of a number of error bits of the plurality of upper physical program units, a distribution of a number of error bits of the plurality of middle physical program units, and a distribution of a number of error bits of the plurality of lower physical program units in each of the plurality of physical erase units comprises:
and judging whether the first entity erasing unit is the bad entity erasing unit according to the average value of the error bit numbers of the first entity erasing unit, the error bit number corresponding to the most entity programming unit in the first entity erasing unit and the median of the plurality of groups of error bit numbers corresponding to the entity programming unit in the first entity erasing unit.
8. The memory management method of claim 7, further comprising:
and if the number of the error bits corresponding to the most physical programming units in the first physical erasing units is larger than the median of the plurality of groups of error bits corresponding to the physical programming units in the first physical erasing units, and the median of the plurality of groups of error bits corresponding to the physical programming units in the first physical erasing units is larger than the average value of the number of the error bits of the first physical erasing units, judging the first physical erasing units as bad physical erasing units.
9. The memory management method of claim 1, wherein performing the data movement operation on the data on the first physical erase unit comprises:
and moving the data on the first physical erasing unit to a second physical erasing unit in the plurality of physical erasing units.
10. A memory storage device, comprising:
the connection interface unit is used for being electrically connected to the host system;
a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of physical erasing units, and each physical erasing unit comprises a plurality of physical programming units; and
A memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is used for recording the number of error bits of each upper physical programming unit and the number of error bits of each lower physical programming unit in each of the plurality of physical erasing units,
wherein the memory control circuit unit is used for judging whether the first physical erasing unit is a bad physical erasing unit according to the distribution of the number of error bits of a plurality of upper physical programming units and the distribution of the number of error bits of a plurality of lower physical programming units of the first physical erasing unit,
the memory control circuit unit is further configured to perform a data moving operation on the data of the first physical erase unit if the first physical erase unit is determined to be the bad physical erase unit.
11. The memory storage device of claim 10, wherein,
the memory control circuit unit is further configured to calculate an average value of the number of error bits of the upper physical program units and an average value of the number of error bits of the lower physical program units in each of the plurality of physical erase units,
If the average value of the number of error bits of the plurality of upper physical program units in the first physical erase unit is greater than the average value of the number of error bits of the plurality of lower physical program units, the memory control circuit unit determines that the first physical erase unit is the bad physical erase unit.
12. The memory storage device of claim 10, wherein,
the memory control circuit unit is also used for recording the error bit number of the physical programming unit in each of the plurality of physical erasing units, and
the memory control circuit unit is further configured to determine whether the first physical erase unit is the bad physical erase unit according to a distribution of the number of error bits of the plurality of upper physical program units, a distribution of the number of error bits of the plurality of middle physical program units, and a distribution of the number of error bits of the plurality of lower physical program units of the first physical erase unit.
13. The memory storage device of claim 12, wherein,
the memory control circuit unit is further configured to calculate an average value of the number of error bits of the upper physical program units, an average value of the number of error bits of the middle physical program units, and an average value of the number of error bits of the lower physical program units in each of the plurality of physical erase units,
If the average value of the number of error bits of the plurality of upper physical program units in the first physical erase unit is greater than the average value of the number of error bits of the plurality of middle physical program units, and the average value of the number of error bits of the plurality of middle physical program units is greater than the average value of the number of error bits of the plurality of lower physical program units, the memory control circuit unit is further configured to determine that the first physical erase unit is the bad physical erase unit.
14. The memory storage device of claim 12, wherein,
the memory control circuit unit is further configured to obtain a distribution of the number of error bits of the plurality of upper physical program units, a distribution of the number of error bits of the plurality of middle physical program units, and a distribution of the number of error bits of the plurality of lower physical program units in each of the plurality of physical erase units according to equation (1),
wherein μ is an average value of the numbers of error bits of the plurality of upper physical program units, the plurality of middle physical program units, and the plurality of lower physical program units in each of the plurality of physical erase units, σ is a standard deviation of the numbers of error bits of the plurality of upper physical program units, the plurality of middle physical program units, and the plurality of lower physical program units in each of the plurality of physical erase units, σ 2 For each of the plurality of physical erase units, the plurality of upper physical program units, the plurality of middle physical program units, and the plurality of lower physical program units, x is a variance of the number of error bits of each of the plurality of physical erase units, the plurality of upper physical program units, the plurality of middle physical program unitsThe number of error bits of the body programming unit and the plurality of lower body programming units, f (x; mu, sigma), is the distribution of the number of error bits of each of the plurality of body erasing units.
15. The memory storage device of claim 14, wherein the memory control circuit unit is further configured to, according to equation (1), obtain a distribution of the number of error bits of the upper physical program units, a distribution of the number of error bits of the middle physical program units, and a distribution of the number of error bits of the lower physical program units in each of the plurality of physical erase units,
if the occurrence probability of x within one standard deviation is 68.2%, the occurrence probability of x within two standard deviations is 95.4%, and the occurrence probability of x within three standard deviations is 99.7%, the distribution of the number of error bits corresponding to the first physical erase unit is a normal distribution, and the memory control circuit unit is further configured to determine that the first physical erase unit is not the bad physical erase unit.
16. The memory storage device of claim 12, wherein the memory control circuit unit is further configured to determine whether the first physical erase cell of the plurality of physical erase cells is the bad physical erase cell during operation according to a distribution of the number of error bits of the upper physical program cells, a distribution of the number of error bits of the middle physical program cells, and a distribution of the number of error bits of the lower physical program cells in each of the plurality of physical erase cells,
the memory control circuit unit is further configured to determine whether the first physical erase unit is the bad physical erase unit according to an average value of the number of error bits of the first physical erase unit, the number of error bits corresponding to the most physical program units in the first physical erase unit, and a median among a plurality of sets of error bits corresponding to the physical program units in the first physical erase unit.
17. The memory storage device of claim 16, wherein,
if the number of the error bits corresponding to the most physical programming units in the first physical erasing units is greater than the median of the plurality of groups of error bits corresponding to the physical programming units in the first physical erasing units, and the median of the plurality of groups of error bits corresponding to the physical programming units in the first physical erasing units is greater than the average value of the number of error bits of the first physical erasing units, the memory control circuit unit is further configured to determine that the first physical erasing units are bad physical erasing units.
18. The memory storage device of claim 10, wherein the memory control circuit unit is further configured to, in operation to perform the data movement operation on the data on the first physical erase unit,
the memory control circuit unit is also used for moving the data on the first physical erasing unit to a second physical erasing unit in the plurality of physical erasing units.
19. A memory control circuit unit for controlling a rewritable non-volatile memory module including a plurality of physical erase units, wherein each of the plurality of physical erase units includes a plurality of physical program units, the memory control circuit unit comprising:
the host interface is used for being electrically connected to a host system;
a memory interface electrically connected to the rewritable non-volatile memory module; and
a memory management circuit electrically connected to the host interface and the memory interface,
wherein the memory management circuit is used for recording the number of error bits of each upper physical programming unit and the number of error bits of each lower physical programming unit in each of the plurality of physical erasing units,
Wherein the memory management circuit is used for judging whether the first physical erasing unit is a bad physical erasing unit according to the distribution of the number of error bits of a plurality of upper physical programming units and the distribution of the number of error bits of a plurality of lower physical programming units of the first physical erasing unit,
if the first physical erasing unit is judged to be the bad physical erasing unit, the memory management circuit is used for executing data moving operation on the data of the first physical erasing unit.
20. The memory control circuit unit of claim 19, wherein,
the memory management circuit is further configured to calculate an average value of the number of error bits of the upper physical program units and an average value of the number of error bits of the lower physical program units in each of the plurality of physical erase units,
if the average value of the number of error bits of the plurality of upper physical program units in the first physical erase unit is greater than the average value of the number of error bits of the plurality of lower physical program units, the memory management circuit is further configured to determine that the first physical erase unit is the bad physical erase unit.
21. The memory control circuit unit of claim 19, wherein,
the memory management circuit is further configured to record a number of error bits of the physical program unit in each of the plurality of physical erase units,
the memory management circuit is further configured to determine whether the first physical erase unit is the bad physical erase unit according to a distribution of the number of error bits of the plurality of upper physical program units, a distribution of the number of error bits of the plurality of middle physical program units, and a distribution of the number of error bits of the plurality of lower physical program units of the first physical erase unit.
22. The memory control circuit unit of claim 21, wherein,
the memory management circuit is further configured to calculate an average value of the number of error bits of the upper physical program units, an average value of the number of error bits of the middle physical program units, and an average value of the number of error bits of the lower physical program units in each of the plurality of physical erase units,
if the average value of the number of error bits of the plurality of upper physical program units in the first physical erase unit is greater than the average value of the number of error bits of the plurality of middle physical program units, and the average value of the number of error bits of the plurality of middle physical program units is greater than the average value of the number of error bits of the plurality of lower physical program units, the memory management circuit is further configured to determine that the first physical erase unit is the bad physical erase unit.
23. The memory control circuit unit of claim 21, wherein,
the memory management circuit is further configured to obtain a distribution of the number of error bits of the upper physical program units, a distribution of the number of error bits of the middle physical program units, and a distribution of the number of error bits of the lower physical program units in each of the plurality of physical erase units according to equation (1),
wherein μ is an average value of the number of error bits of the upper physical program units, the middle physical program units and the lower physical program units in each of the plurality of physical erase units, σ is the upper physical erase units in each of the plurality of physical erase unitsVolume programming unit, standard deviation of error bit number of the plurality of middle entity programming units and the plurality of lower entity programming units, sigma 2 And (3) for each of the plurality of physical erase units, the plurality of middle physical program units and the plurality of lower physical program units, x is a variance of the number of error bits of the plurality of upper physical program units, the plurality of middle physical program units and the plurality of lower physical program units in each of the plurality of physical erase units, and f (x; mu, sigma) is a distribution of the number of error bits of each of the plurality of physical erase units.
24. The memory control circuit unit of claim 23, wherein,
the memory management circuit is further configured to, according to equation (1), obtain a distribution of the number of error bits of the upper physical program units, a distribution of the number of error bits of the middle physical program units, and a distribution of the number of error bits of the lower physical program units in each of the plurality of physical erase units,
if the occurrence probability of x within one standard deviation is 68.2%, the occurrence probability of x within two standard deviations is 95.4%, and the occurrence probability of x within three standard deviations is 99.7%, the distribution of the number of error bits corresponding to the first physical erase unit is a normal distribution, and the memory management circuit is further configured to determine that the first physical erase unit is not the bad physical erase unit.
25. The memory control circuit unit of claim 21, wherein the memory management circuit is further configured to determine whether the first physical erase cell of the plurality of physical erase cells is the bad physical erase cell during operation according to a distribution of the number of error bits of the upper physical program cells, a distribution of the number of error bits of the middle physical program cells, and a distribution of the number of error bits of the lower physical program cells in each of the plurality of physical erase cells,
The memory management circuit is further configured to determine whether the first physical erase unit is the bad physical erase unit according to an average value of the number of error bits of the first physical erase unit, the number of error bits corresponding to the most physical program units in the first physical erase unit, and a median among a plurality of sets of error bits corresponding to the physical program units in the first physical erase unit.
26. The memory control circuit unit of claim 25, wherein,
if the number of the error bits corresponding to the most physical programming units in the first physical erasing units is greater than the median of the plurality of groups of error bits corresponding to the physical programming units in the first physical erasing units, and the median of the plurality of groups of error bits corresponding to the physical programming units in the first physical erasing units is greater than the average value of the number of error bits of the first physical erasing units, the memory management circuit is further configured to determine that the first physical erasing units are bad physical erasing units.
27. The memory control circuit unit of claim 19, wherein the memory management circuit is further configured to, in operation to perform the data movement operation on the data on the first physical erase unit,
The memory management circuit is also used for moving the data on the first physically erased cell to a second physically erased cell in the plurality of physically erased cells.
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