CN112015327B - Data writing method, memory storage device and memory control circuit unit - Google Patents
Data writing method, memory storage device and memory control circuit unit Download PDFInfo
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- CN112015327B CN112015327B CN201910463469.1A CN201910463469A CN112015327B CN 112015327 B CN112015327 B CN 112015327B CN 201910463469 A CN201910463469 A CN 201910463469A CN 112015327 B CN112015327 B CN 112015327B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
Abstract
The invention provides a data writing method, a memory storage device and a memory control circuit unit. The method comprises the following steps: receiving first data and writing the first data into at least one first physical programming unit of the first physical erasing unit; receiving second data; if the data length of the second data is smaller than the predefined value, temporarily storing the second data into the temporary storage area; receiving third data; if the logical address for storing the first data is continuous with the logical address for storing the third data, writing the third data into at least one second entity programming unit of the first entity erasing unit; if the logical address for storing the first data is not continuous with the logical address for storing the third data, the second data is moved from the temporary storage area to at least one second entity programming unit of the first entity erasing unit.
Description
Technical Field
The present invention relates to a memory management technology, and in particular, to a data writing method, a memory storage device, and a memory control circuit unit.
Background
Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.
Fig. 1 is a schematic diagram of a prior art shown in accordance with an exemplary embodiment of the present invention. As shown in fig. 1, during the data writing process, the system data (e.g., file Allocation Table, FAT) and the user data (e.g., including the first data D1, the second data D2, the third data D3 \8230; nth data Dn) are alternately written into the flash memory 406. The host writes data in a sequence of writing first data D1 to the entity programming unit 6101 of the entity erasing unit 610 (0) in the flash memory 406, then writing system data to the entity programming unit 6102, then writing second data D2 to the entity programming unit 6103, and then updating the system data, such that interleaving the system data and the user data into the flash memory 406 results in physical discontinuity of the user data written into the flash memory 406.
In the algorithm based on the physical programming unit (Page base), the sequence of writing data into the flash memory is the same as the sequence of writing data into the flash memory at the host side. In the same physical erase unit, the old system data becomes invalid due to the update of the system data, so that many invalid data sectors exist in the same physical erase unit. If the invalid data sectors account for 10%, it means that 90% of the data needs to be moved during the garbage collection operation, and since the invalid and physically discontinuous data sectors are too many and distributed relatively dispersedly, a small amount of residue may be caused during the garbage collection, so that the garbage collection efficiency is low. Therefore, how to improve the efficiency of garbage recycling is one of the technologies that people in the field strive to develop.
Disclosure of Invention
The invention provides a data writing method, a memory storage device and a memory control circuit unit.
An exemplary embodiment of the present invention provides a data writing method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of entity-erased cells, and each entity-erased cell has a plurality of entity-programmed cells. The method comprises the following steps: receiving first data from a host system, and writing the first data into at least one first physical programming unit of a first physical erasing unit in a plurality of physical erasing units; second data is received from the host system. The method further comprises the steps of temporarily storing the second data into the temporary storage area, receiving third data from the host system after receiving the second data, and judging whether the logic address for storing the first data and the logic address for storing the third data are continuous or not. The method further includes writing third data into at least one second entity programming unit of the first entity erasing unit if the logical address for storing the first data and the logical address for storing the third data are consecutive, and moving the second data from the temporary storage area to at least one second entity programming unit of the first entity erasing unit if the logical address for storing the first data and the logical address for storing the third data are not consecutive, wherein the at least one second entity programming unit is arranged behind the at least one first entity programming unit.
In an exemplary embodiment of the invention, the step of temporarily storing the second data in the temporary storage area, receiving the third data from the host system after receiving the second data, and determining whether the logical address storing the first data and the logical address storing the third data are consecutive further includes: judging whether the data length of the second data is smaller than a predefined value; if the data length of the second data is smaller than the predefined value, the second data is temporarily stored in the temporary storage area, the third data is received from the host system after the second data is received, and whether the logical address for storing the first data and the logical address for storing the third data are continuous or not is judged.
In an exemplary embodiment of the invention, the data writing method further includes: and recording the logic address for storing the second data and the data length of the second data in the temporary storage area.
In an exemplary embodiment of the invention, the data writing method further includes: if the data length of the second data is not less than the predefined value, the second data is written into the first entity erasing unit continuously according to the first data.
In an exemplary embodiment of the invention, if the logical address for storing the first data is not consecutive to the logical address for storing the third data, the step of moving the second data from the temporary region to at least one second physical program unit of the first physical erase unit, wherein the at least one second physical program unit is arranged after the at least one first physical program unit, further comprises: and writing the third data into the first entity erasing unit after the second data.
In an exemplary embodiment of the invention, the temporary storage area is a volatile memory.
In an exemplary embodiment of the invention, the data writing method further includes: and when the data or the command is not received from the host system within the predefined time, writing the data in the temporary storage area into the rewritable nonvolatile memory module.
In an exemplary embodiment of the invention, the first data and the third data belong to user data, and the second data belongs to system data.
In an exemplary embodiment of the invention, the data writing method further includes: receiving fourth data from the host system subsequent to the third data; if the logical address of the fourth data is the same as the logical address recorded in the temporary storage area and the data length of the fourth data is the same as the data length recorded in the temporary storage area, the fourth data is determined to be the updated system data, and the updated system data is temporarily stored in the temporary storage area to update the system data.
An exemplary embodiment of the present invention provides a memory storage device, which includes: the device comprises a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for electrically connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity erasing units, and each entity erasing unit is provided with a plurality of entity programming units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for receiving first data from a host system and writing the first data into at least one first entity programming unit of a first entity erasing unit in the plurality of entity erasing units. The memory control circuit unit is used for receiving second data from the host system. The memory control circuit unit is used for temporarily storing the second data into the temporary storage area, receiving the third data from the host system after receiving the second data, and judging whether the logic address for storing the first data and the logic address for storing the third data are continuous or not. In addition, the memory control circuit unit is used for writing the third data into at least one second entity programming unit of the first entity erasing unit if the logic address for storing the first data and the logic address for storing the third data are continuous, and moving the second data from the temporary storage area to at least one second entity programming unit of the first entity erasing unit if the logic address for storing the first data and the logic address for storing the third data are discontinuous, wherein the at least one second entity programming unit is arranged behind the at least one first entity programming unit.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to temporarily store the second data in the temporary storage area, receive the third data from the host system after receiving the second data, and determine whether the logical address for storing the first data and the logical address for storing the third data are consecutive, the memory control circuit unit is further configured to determine whether the data length of the second data is smaller than a predefined value, temporarily store the second data in the temporary storage area if the data length of the second data is smaller than the predefined value, receive the third data from the host system after receiving the second data, and determine whether the logical address for storing the first data and the logical address for storing the third data are consecutive.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to record a logical address for storing the second data and a data length of the second data in the temporary storage area.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to write the second data into the first physically erased unit following the first data if the data length of the second data is not less than the predefined value.
In an exemplary embodiment of the invention, if the logical address for storing the first data and the logical address for storing the third data are not consecutive, the memory control circuit unit is further configured to move the second data from the temporary storage area to at least one second physical programming unit of the first physical erase unit, wherein the operation of the at least one second physical programming unit arranged after the at least one first physical programming unit includes: the memory control circuit unit is further used for writing third data into the first entity erasing unit after the second data.
In an exemplary embodiment of the invention, the temporary region is a volatile memory.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to write the data in the temporary storage area to the rewritable nonvolatile memory module when no data or command is received from the host system within a predefined time.
In an exemplary embodiment of the invention, the first data and the third data belong to user data, and the second data belongs to system data.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to receive fourth data from the host system in succession to the third data. If the logical address of the fourth data is the same as the logical address recorded in the temporary storage area and the data length of the fourth data is the same as the data length recorded in the temporary storage area, the memory control circuit unit is further configured to determine that the fourth data is the updated system data and temporarily store the updated system data in the temporary storage area to update the system data.
An exemplary embodiment of the present invention provides a memory control circuit unit for writing data into a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical erase units and each physical erase unit has a plurality of physical program units. The memory control circuit unit includes: a host interface, a memory interface, and memory management circuitry. The host interface is used for electrically connecting to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used for receiving first data from a host system and writing the first data into at least one first entity programming unit of a first entity erasing unit in the plurality of entity erasing units. The memory management circuit is used for receiving second data from the host system. The memory management circuit is used for temporarily storing the second data into the temporary storage area, receiving third data from the host system after receiving the second data, and judging whether the logic address for storing the first data is continuous with the logic address for storing the third data. In addition, if the logical address for storing the first data and the logical address for storing the third data are consecutive, the memory management circuit is used for writing the third data into at least one second entity programming unit of the first entity erasing unit, and if the logical address for storing the first data and the logical address for storing the third data are not consecutive, the memory management circuit is used for moving the second data from the temporary storage area to at least one second entity programming unit of the first entity erasing unit, wherein the at least one second entity programming unit is arranged behind the at least one first entity programming unit.
In an exemplary embodiment of the invention, the memory management circuit is further configured to temporarily store the second data in the temporary storage area, receive the third data from the host system after receiving the second data, and determine whether the logical address for storing the first data and the logical address for storing the third data are consecutive, the memory management circuit is further configured to determine whether the data length of the second data is smaller than a predefined value, temporarily store the second data in the temporary storage area if the data length of the second data is smaller than the predefined value, receive the third data from the host system after receiving the second data, and determine whether the logical address for storing the first data and the logical address for storing the third data are consecutive.
In an exemplary embodiment of the invention, the memory management circuit is further configured to record a logical address for storing the second data and a data length of the second data in the temporary storage area.
In an exemplary embodiment of the invention, the memory management circuit is further configured to write the second data into the first physically erased cell following the first data if the data length of the second data is not less than the predefined value.
In an exemplary embodiment of the invention, if the logical address for storing the first data and the logical address for storing the third data are not consecutive, the memory management circuit is further configured to move the second data from the temporary region to at least one second physical programming unit of the first physical erase unit, wherein the operation of the at least one second physical programming unit arranged after the at least one first physical programming unit further includes: the memory management circuit is further configured to write third data to the first physical erase unit in succession to the second data.
In an exemplary embodiment of the invention, the temporary region is a volatile memory.
In an exemplary embodiment of the invention, the memory management circuit is further configured to write the data in the temporary storage area to the rewritable nonvolatile memory module when no data or command is received from the host system within a predefined time.
In an exemplary embodiment of the invention, the memory management circuit further assigns the first data and the third data to the user data, and the second data to the system data.
In an exemplary embodiment of the invention, the memory management circuit is further configured to receive fourth data from the host system in succession to the third data. If the logical address of the fourth data is the same as the logical address recorded in the temporary storage area and the data length of the fourth data is the same as the data length recorded in the temporary storage area, the memory management circuit is further configured to determine that the fourth data is the updated system data and temporarily store the updated system data in the temporary storage area to update the system data.
Based on the above, in the data writing method, the memory storage device and the memory control circuit unit of the present invention, in the data writing process, the user data with continuous logical addresses is written into the rewritable nonvolatile memory module, the system data with the data length smaller than the predefined value is temporarily stored in the temporary storage area, and when no data or instruction is received from the host system within the predefined time or the logical addresses of the received user data are not continuous, the system data in the temporary storage area is written into the rewritable nonvolatile memory module. Therefore, the user data can be stored on the continuous physical addresses, and the garbage recycling efficiency is improved.
Drawings
FIG. 1 is a diagram illustrating a prior art technique according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention.
FIG. 3 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
FIG. 4 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.
FIG. 5 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
FIG. 6 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
FIG. 7 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an example embodiment of the present invention.
FIG. 8 is a diagram illustrating a data write-in rewritable nonvolatile memory module according to an exemplary embodiment of the present invention.
FIG. 9 is a diagram illustrating a data write-rewritable nonvolatile memory module according to another exemplary embodiment of the present invention.
Fig. 10 is a flowchart illustrating a data writing method according to an example embodiment of the present invention.
[ notation ] to show
10: memory storage device
11: host system
110: system bus
111: processor with a memory having a plurality of memory cells
112: random access memory
113: read-only memory
114: data transmission interface
12: input/output (I/O) device
20: main machine board
201: portable disk
202: memory card
203: solid state disk
204: wireless memory storage device
205: global positioning system module
206: network interface card
207: wireless transmission device
208: keyboard with a keyboard body
209: screen
210: horn (loudspeaker)
32: SD card
33: CF card
34: embedded memory device
341: embedded multimedia card
342: embedded multi-chip packaging storage device
402: connection interface unit
404: memory control circuit unit
406: rewritable nonvolatile memory module
502: memory management circuit
504: host interface
506: memory interface
508: error checking and correcting circuit
510: buffer memory
512: power management circuit
601: storage area
602: idle zone
610 (0) to 610 (B): physical erase unit
612 (0) to 612 (C): logic unit
6101. 6102, 6103: physical programming unit
70: temporary storage area
D1: first data
D2: second data
D3: third data
D4: fourth data
D5: fifth data
Dn: data No. N
FAT: system data
S1001, S1003, S1005, S1007, S1009, S1011, S1013, S1015, S1017, S1019, S1021: step (ii) of
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
FIG. 2 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 3 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
Referring to fig. 2 and 3, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 are all electrically connected to a system bus (system bus) 110.
In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.
In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through the data transmission interface 114 in a wired or wireless manner. The memory storage 10 may be, for example, a flash Drive 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage 204. The wireless memory storage device 204 can be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 4 is a schematic diagram of the host system and the memory storage device according to another exemplary embodiment of the invention. Referring to fig. 4, in another exemplary embodiment, the host system 31 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used therein. The embedded memory device 34 includes embedded Multi-Media Card (eMMC) 341 and/or embedded Multi-Chip Package (eMCP) memory device 342, which electrically connects the memory module directly to the embedded memory device on the substrate of the host system.
Fig. 5 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention.
Referring to fig. 5, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.
The connection interface unit 402 is used to electrically connect the memory storage device 10 to the host system 11. In the exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be compliant with Parallel Advanced Technology Attachment (PATA) standard, institute of Electrical and Electronic Engineers (IEEE) 1394 standard, high-Speed Peripheral Component connection interface (PCI Express) standard, universal Serial Bus (USB) standard, SD interface standard, ultra High Speed-I (UHS-I) interface standard, ultra High Speed-II (UHS-II) interface standard, memory Stick (Memory Stick, MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, universal Flash Memory (Flash) interface standard, CF interface standard, cp standard, device interface (Integrated drive Electronics standard, or other suitable Integrated Electronics standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.
The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.
The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable non-volatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
In the exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical programming cells, and the physical programming cells form a plurality of physical erasing cells. Specifically, the memory cells on the same word line constitute one or more physically programmed cells. For example, if each memory cell can store more than 3 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell, a middle physical program cell and an upper physical program cell. Taking TLC NAND flash memory as an example, the Least Significant Bit (LSB) of the memory cells on the same word line will constitute a next physical programming cell; CSB (Central Significant Bit) of memory cells on the same word line constitute a middle physical program cell; and the Most Significant Bit (MSB) of the memory cells on the same word line constitutes an upper physical programming cell. Generally, in the TLCNAND type flash memory, the writing speed of the bottom-entity program cell is faster than that of the middle-entity program cell and/or the top-entity program cell, and/or the reliability of the bottom-entity program cell is higher than that of the middle-entity program cell and the top-entity program cell.
In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, 8, 16 or more or less physical fans may be included in the data bit region, and the size of each physical fan may also be larger or smaller. On the other hand, a physically erased cell is the smallest unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).
FIG. 6 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
Referring to fig. 6, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.
In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In another example embodiment, the control instructions of the memory management circuit 502 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may include one or more program codes or command codes respectively and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 504 is electrically connected to the memory management circuit 502 and is used for receiving and determining commands and data transmitted by the host system 11. That is, commands and data sent from the host system 11 are sent to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.
The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequence of instructions may include one or more signals, or data, on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes information such as the identification code and the memory address of the read command.
In an exemplary embodiment, the memory control circuit unit 404 further includes an error checking and correcting circuit 508, a buffer memory 510 and a power management circuit 512.
The ECC circuit 508 is electrically connected to the memory management circuit 502 and is configured to perform ECC operations to ensure data correctness. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.
The buffer memory 510 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.
FIG. 7 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention.
It should be noted that, in the following exemplary embodiments, when the management of the physically erased cells of the rewritable non-volatile memory module 406 is described, it is a logical concept to operate the physically erased cells by the words "select" and "group". That is, the physical locations of the physically erased cells of the rewritable nonvolatile memory module 406 are not changed, but the physically erased cells of the rewritable nonvolatile memory module 406 are logically operated.
Referring to FIG. 7, the memory management circuit 502 groups the physically erased cells 610 (0) -610 (B) of the rewritable nonvolatile memory module 406 into a storage area 601 and an idle (spare) area 602. For example, the erase blocks 610 (0) -610 (A) belong to the storage area 601, and the erase blocks 610 (A + 1) -610 (B) belong to the idle area 602. In the present exemplary embodiment, a physically erased cell refers to a physically erased cell. However, in another exemplary embodiment, a physically erased cell may also include a plurality of physically erased cells. In addition, the memory management circuit 502 can associate a physical erase unit with one of the memory area 601 and the idle area 602 by using a flag or the like.
During the operation of the memory storage device 10, the relationship between a physically erased unit and the storage area 601 or the idle area 602 may change dynamically. For example, when receiving write data from the host system 11, the memory management circuit 502 selects a physical erase unit from the idle area 602 to store at least a portion of the write data and associates the physical erase unit with the storage area 601. In addition, after erasing a physical erase unit belonging to the storage area 601 to clear data therein, the memory management circuit 502 associates the erased physical erase unit with the idle area 602.
In the exemplary embodiment, the physical erase cells belonging to the idle region 602 are also referred to as idle physical erase cells, and the physical erase cells belonging to the memory region 601 are also referred to as non-idle (non-spare) physical erase cells. Each of the physically erased cells belonging to the idle area 602 is an erased physically erased cell and does not store any data, and each of the physically erased cells belonging to the storage area 601 stores data. Furthermore, each physical erase unit belonging to the idle area 602 may not store any valid (valid) data, and each physical erase unit belonging to the storage area 601 may store valid data and/or invalid (invalid) data.
In an exemplary embodiment, the memory management circuit 502 configures the logic units 612 (0) -612 (C) to map the physical erase units in the memory area 601. In the exemplary embodiment, the host system 11 accesses the physical erase unit belonging to the storage area 601 by a Logical Address (LA). Thus, each of the logical units 612 (0) -612 (C) refers to a logical address. However, in another exemplary embodiment, each of the logic units 612 (0) -612 (C) may also refer to a logic program unit, a logic erase unit or be composed of a plurality of continuous or discontinuous logic addresses. In addition, each of the logic units 612 (0) -612 (C) may be mapped to one or more physical erase units.
In the present exemplary embodiment, the memory management circuit 502 records the mapping relationship (also referred to as logical-to-physical mapping relationship) between the logical unit and the physical erase unit in at least one logical-to-physical mapping table. When the host system 11 is going to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access to the memory storage device 10 according to the logical-to-physical mapping table.
FIG. 8 is a diagram illustrating a data write-in rewritable nonvolatile memory module according to an exemplary embodiment of the present invention.
Referring to fig. 8, in the data writing process, the memory management circuit 502 receives the first data D1 first, and writes the first data D1 into the entity programming unit 6101 of the entity erasing unit 610 (0) in the rewritable nonvolatile memory module 406.
The memory management circuit 502 receives the second data D2 from the host system in succession to the first data D1.
The memory management circuit 502 determines whether the data of the second data D2 satisfies a predefined value. In an exemplary embodiment, the memory management circuit 502 determines whether the data type of the second data D2 conforms to a predefined pattern for determining whether the second data D2 is a system data. In another exemplary embodiment, the memory management circuit 502 is configured to determine whether the data length of the second data D2 is smaller than a predefined value, wherein the predefined value is set to 16k, for example. If the data length of the second data D2 is smaller than the predefined value, the memory management circuit 502 determines that the second data D2 belongs to the system data, temporarily stores the second data D2 belonging to the system data into the temporary storage area 70, and records the logical address for storing the second data D2 and the data length of the second data D2 in the temporary storage area 70. For example, the temporary storage area 70 is disposed in the buffer memory 510. In another exemplary embodiment, the memory management circuit 502 writes the second data D2 belonging to the system data in the temporary region 70 into the entity programming unit 6102 of the entity erasing unit 610 (0) in the rewritable nonvolatile memory module 406 when the memory management circuit does not receive data or commands from the host system within a predetermined time.
The memory management circuit 502 receives the third data D3 from the host system in succession to the second data D2, and determines whether the logical address storing the first data D1 and the logical address storing the third data D3 are consecutive. If the logical address for storing the first data D1 and the logical address for storing the third data D3 are consecutive, the memory management circuit 502 writes the third data D3 into the entity programming unit 6102 of the entity erasing unit 610 (0), wherein the entity programming unit 6102 is arranged after the entity programming unit 6101.
The memory management circuit 502 receives the fourth data D4 from the host system in succession to the third data D3. In particular, if the logical address of the fourth data D4 is the same as the logical address recorded in the temporary storage area 70 and the data length of the fourth data D4 is the same as the data length recorded in the temporary storage area 70, the memory management circuit 502 determines that the fourth data D4 is the updated system data, and temporarily stores the updated system data in the temporary storage area 70 to update the second data D2 belonging to the system data.
FIG. 9 is a diagram illustrating a data write-rewritable nonvolatile memory module according to another exemplary embodiment of the present invention.
Referring to fig. 9, in the data writing process, the memory management circuit 502 receives the first data D1 first, and writes the first data D1 into the entity programming unit 6101 of the entity erasing unit 610 (0) in the rewritable nonvolatile memory module 406.
The memory management circuit 502 receives the second data D2 from the host system in succession to the first data D1.
The memory management circuit 502 determines whether the data length of the second data D2 is smaller than a predefined value. In an exemplary embodiment, the predefined value is set to 16k. If the data length of the second data D2 is not less than the predefined value, the memory management circuit 502 determines that the second data D2 belongs to the user data, and writes the second data D2 belonging to the user data into the entity programming unit 6102 of the entity erasing unit 610 (0), wherein the entity programming unit 6102 is arranged after the entity programming unit 6101.
The memory management circuit 502 receives the third data D3 from the host system in succession to the second data D2, and the memory management circuit 502 determines whether the data length of the third data D3 is smaller than a predefined value. If the data length of the third data D3 is smaller than the predefined value, the memory management circuit 502 determines that the third data D3 belongs to the system data, temporarily stores the third data D3 belonging to the system data into the temporary storage area 70, and records the logical address for storing the third data D3 and the data length of the third data D3 in the temporary storage area 70.
The memory management circuit 502 receives the fourth data D4 from the host system in succession to the third data D3, and determines whether the logical address storing the second data D2 and the logical address storing the fourth data D4 are consecutive. If the logical address storing the second data D2 is consecutive to the logical address storing the fourth data D4, the memory management circuit 502 writes the fourth data D4 into the entity programming unit 6103 of the entity erasing unit 610 (0), wherein the entity programming unit 6103 is arranged after the entity programming unit 6102.
The memory management circuit 502 receives the fifth data D5 from the host system following the fourth data D4, if the logical address of the stored fifth data D5 is the same as the logical address recorded in the temporary storage area 70 and the data length of the fifth data D5 is the same as the data length recorded in the temporary storage area 70, the fifth data D5 is determined to be the updated system data, and the updated system data is temporarily stored in the temporary storage area 70 to update the third data D3 belonging to the system data.
Fig. 10 is a flowchart illustrating a data writing method according to an example embodiment of the present invention.
Referring to fig. 10, in step S1001, the memory management circuit 502 receives the first data D1 from the host system, and writes the first data D1 into at least one first physical program cell of the first physical erase cell.
In step S1003, the memory management circuit 502 receives the second data D2 from the host system.
In step S1005, the memory management circuit 502 determines whether the data length of the second data D2 is smaller than a predefined value.
If the data length of the second data D2 is smaller than the predefined value, in step S1007, the memory management circuit 502 temporarily stores the second data D2 into the temporary storage area, and records the logical address for storing the second data D2 and the data length of the second data D2 in the temporary storage area. The temporary storage area is a volatile memory. In another exemplary embodiment, the memory management circuit 502 writes the second data D2 in the temporary region to the rewritable nonvolatile memory module when the memory management circuit does not receive data or commands from the host system within a predefined time.
If the data length of the second data D2 is not less than the predefined value, in step S1015, the memory management circuit 502 writes the second data D2 into the first physical erase unit following the first data D1.
In step S1009, the memory management circuit 502 receives the third data D3 from the host system.
In step S1011, the memory management circuit 502 determines whether the logical address storing the first data D1 and the logical address storing the third data D3 are consecutive.
If the logical address for storing the first data D1 and the logical address for storing the third data D3 are consecutive, in step S1013, the memory management circuit 502 writes the third data D3 into at least one second physical programming unit of the first physical erase unit, wherein the second physical programming unit is arranged behind the first physical programming unit.
If the logical address for storing the first data D1 and the logical address for storing the third data D3 are not consecutive, in step S1017, the memory management circuit 502 moves the second data D2 from the temporary storage area to at least one second physical program cell of the first physical erase cell, and the memory management circuit 502 writes the third data D3 into the first physical erase cell following the second data D2. The first data D1 and the third data D3 belong to user data, and the second data D2 belongs to system data.
In step S1019, the memory management circuit 502 receives the fourth data D4 from the host system.
In step S1021, if the logical address of the fourth data D4 is the same as the logical address recorded in the temporary storage area and the data length of the fourth data D4 is the same as the data length recorded in the temporary storage area, the memory management circuit 502 determines that the fourth data D4 is the updated system data, and temporarily stores the updated system data in the temporary storage area to update the system data.
In summary, the present invention provides a data writing method, a memory storage device and a memory control circuit unit. In the process of writing data, the memory management circuit writes user data with continuous logical addresses into the rewritable nonvolatile memory module, temporarily stores system data with data meeting a preset rule into a temporary storage area, and writes the system data in the temporary storage area into the rewritable nonvolatile memory module when no data or instructions are received from a host system within a predefined time or the logical addresses of the received user data are discontinuous. Therefore, the user data written into the rewritable nonvolatile memory module is continuous physically, and the garbage recycling efficiency is improved.
Claims (21)
1. A data writing method is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of entity erasing units, each entity erasing unit is provided with a plurality of entity programming units, and the data writing method comprises the following steps:
receiving first data from a host system, and writing the first data into at least one first physical programming unit of a first physical erasing unit in the plurality of physical erasing units;
receiving second data from the host system;
judging whether the data length of the second data is smaller than a predefined value or not;
if the data length of the second data is smaller than the predefined value, temporarily storing the second data into a temporary storage area, receiving third data from the host system after receiving the second data, and judging whether a logic address for storing the first data and a logic address for storing the third data are continuous or not; and
if the logical address for storing the first data and the logical address for storing the third data are continuous, writing the third data into at least one second entity programming unit of the first entity erasing unit;
if the logical address for storing the first data is not consecutive to the logical address for storing the third data, the second data is moved from the temporary storage region to at least one second physical program cell of the first physical erase cell and the third data is written into the first physical erase cell following the second data, wherein the at least one second physical program cell is arranged behind the at least one first physical program cell.
2. The data writing method of claim 1, further comprising:
and recording a logical address for storing the second data and the data length of the second data in the temporary storage area.
3. The data writing method of claim 2, further comprising:
and if the data length of the second data is not less than the predefined value, continuing to write the second data into the first entity erasing unit by the first data.
4. The data writing method according to claim 3, wherein the temporary storage area is a volatile memory.
5. The data writing method of claim 4, further comprising:
and when data or instructions are not received from the host system within a predefined time, writing the data in the temporary storage area into the rewritable nonvolatile memory module.
6. The data writing method according to claim 1, wherein the first data and the third data belong to user data, and the second data belongs to system data.
7. The data writing method according to claim 1, further comprising:
receiving fourth data from the host system in succession to the third data;
if the logical address for storing the fourth data is the same as the logical address recorded in the temporary storage area and the data length of the fourth data is the same as the data length recorded in the temporary storage area, the fourth data is judged to be updated system data, and the updated system data is temporarily stored in the temporary storage area to update the system data.
8. A storage device, comprising:
the connection interface unit is used for electrically connecting to a host system;
the rewritable nonvolatile memory module comprises a plurality of entity erasing units, wherein each entity erasing unit is provided with a plurality of entity programming units; and
a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is used for receiving first data from a host system, writing the first data into at least one first physical programming unit of a first physical erasing unit in the plurality of physical erasing units,
the memory control circuitry to receive second data from the host system,
the memory control circuit unit is used for judging whether the data length of the second data is smaller than a predefined value,
if the data length of the second data is smaller than the predefined value, the memory control circuit unit is used for temporarily storing the second data into a temporary storage area, receiving third data from the host system after receiving the second data, and judging whether a logical address for storing the first data and a logical address for storing the third data are continuous,
if the logical address for storing the first data and the logical address for storing the third data are consecutive, the memory control circuit unit is used for writing the third data into at least one second physical programming unit of the first physical erasing unit, and
if the logical address for storing the first data is not consecutive to the logical address for storing the third data, the memory control circuit unit is configured to move the second data from the temporary storage region to at least one second physical programming unit of the first physical erase unit and write the third data to the first physical erase unit following the second data, wherein the at least one second physical programming unit is arranged behind the at least one first physical programming unit.
9. The memory device according to claim 8, wherein the memory control circuit unit is further configured to record a logical address at which the second data is stored and a data length of the second data in the temporary storage area.
10. The memory device according to claim 8, wherein the memory control circuit unit is further configured to write the second data into the first physical erase unit subsequent to the first data if the data length of the second data is not less than the predefined value.
11. The storage device of claim 9, wherein the staging area is a volatile memory.
12. The memory device according to claim 11, wherein the memory control circuit unit is further configured to write the data in the temporary storage area to the rewritable non-volatile memory module when no data or command is received from the host system within a predefined time.
13. The storage device of claim 8, wherein the first data and the third data belong to user data and the second data belong to system data.
14. The storage device of claim 8, wherein the memory control circuitry unit is further to receive fourth data from the host system in succession to the third data,
if the logical address for storing the fourth data is the same as the logical address recorded in the temporary storage area and the data length of the fourth data is the same as the data length recorded in the temporary storage area, the memory control circuit unit is further configured to determine that the fourth data is updated system data, and temporarily store the updated system data into the temporary storage area to update the system data.
15. A memory control circuit unit for writing data into a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of entity erasing units and each entity erasing unit comprises a plurality of entity programming units, the memory control circuit unit comprises:
a host interface for electrically connecting to a host system;
a memory interface for electrically connecting to the rewritable nonvolatile memory module; and
a memory management circuit electrically connected to the host interface and the memory interface,
wherein the memory management circuit is configured to receive first data from a host system, write the first data to at least a first physical programming cell of a first physical erase cell of the plurality of physical erase cells,
wherein the memory management circuitry is to receive second data from the host system,
the memory management circuit is used for judging whether the data length of the second data is smaller than a predefined value,
if the data length of the second data is smaller than the predefined value, the memory management circuit is configured to temporarily store the second data in a temporary storage area, receive third data from the host system, and determine whether a logical address for storing the first data and a logical address for storing the third data are consecutive,
if the logical address for storing the first data and the logical address for storing the third data are consecutive, the memory management circuit is used for writing the third data into at least one second entity programming unit of the first entity erasing unit, and
if the logical address for storing the first data is not consecutive to the logical address for storing the third data, the memory management circuit is configured to move the second data from the temporary region to at least one second physical programming unit of the first physical erase unit and write the third data to the first physical erase unit following the second data, wherein the at least one second physical programming unit is arranged in a subsequent operation of the at least one first physical programming unit.
16. The memory control circuit unit according to claim 15, wherein the memory management circuit is further configured to record a logical address at which the second data is stored and a data length of the second data in the temporary storage area.
17. The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to write the second data into the first physically erased unit in succession to the first data if the data length of the second data is not less than the predefined value.
18. The memory control circuit unit of claim 16, wherein the scratch pad area is a volatile memory.
19. The memory control circuit unit of claim 18, wherein the memory management circuit is further configured to write the data in the scratch pad area to the rewritable non-volatile memory module when no data or instructions are received from the host system within a predefined time.
20. The memory control circuit unit according to claim 15, wherein the first data and the third data belong to user data, and the second data belongs to system data.
21. The memory control circuitry unit of claim 15, wherein the memory management circuitry is further to receive fourth data from the host system subsequent to the third data,
if the logical address for storing the fourth data is the same as the logical address recorded in the temporary storage area and the data length of the fourth data is the same as the data length recorded in the temporary storage area, the memory management circuit is further configured to determine that the fourth data is updated system data and temporarily store the updated system data in the temporary storage area to update the system data.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101853138A (en) * | 2009-04-03 | 2010-10-06 | 群联电子股份有限公司 | Flash memory write-in method, storage system and controller using same |
| CN102541755A (en) * | 2010-12-29 | 2012-07-04 | 深圳市硅格半导体有限公司 | Flash memory and data receiving method thereof |
| CN108958657A (en) * | 2018-06-27 | 2018-12-07 | 深圳市德名利电子有限公司 | A kind of date storage method, storage equipment and storage system |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10031850B2 (en) * | 2011-06-07 | 2018-07-24 | Sandisk Technologies Llc | System and method to buffer data |
| KR101997572B1 (en) * | 2012-06-01 | 2019-07-09 | 삼성전자주식회사 | Storage device having nonvolatile memory device and write method tererof |
| TWI571882B (en) * | 2016-02-19 | 2017-02-21 | 群聯電子股份有限公司 | Wear leveling method, memory control circuit unit and memory storage device |
| US10031845B2 (en) * | 2016-04-01 | 2018-07-24 | Intel Corporation | Method and apparatus for processing sequential writes to a block group of physical blocks in a memory device |
-
2019
- 2019-05-30 CN CN201910463469.1A patent/CN112015327B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101853138A (en) * | 2009-04-03 | 2010-10-06 | 群联电子股份有限公司 | Flash memory write-in method, storage system and controller using same |
| CN102541755A (en) * | 2010-12-29 | 2012-07-04 | 深圳市硅格半导体有限公司 | Flash memory and data receiving method thereof |
| CN108958657A (en) * | 2018-06-27 | 2018-12-07 | 深圳市德名利电子有限公司 | A kind of date storage method, storage equipment and storage system |
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