CN114138207B

CN114138207B - Memory control method, memory storage device and memory control circuit unit

Info

Publication number: CN114138207B
Application number: CN202111519922.XA
Authority: CN
Inventors: 苏柏诚; 王志维; 许祐诚; 林纬
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2021-12-13
Filing date: 2021-12-13
Publication date: 2023-06-13
Anticipated expiration: 2041-12-13
Also published as: CN114138207A

Abstract

The invention provides a memory control method, a memory storage device and a memory control circuit unit. The method comprises the following steps: receiving a read instruction from a host system; responding to the first entity erasing unit as a first entity unit, and sending a first operation instruction sequence to instruct the rewritable nonvolatile memory module to read the first entity programming unit based on a first electrical setting; and responding to the first entity erasing unit as the second entity unit, and sending a second operation instruction sequence to instruct the rewritable nonvolatile memory module to read the first entity programming unit based on the second electrical setting. The first electrical setting is different from the second electrical setting. Therefore, the accuracy of the read data can be improved.

Description

Memory control method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a memory control technology, and more particularly, to a memory control method, a memory storage device, and a memory control circuit unit.

Background

Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, such that consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable multimedia devices.

The memory cells in the rewritable nonvolatile memory module are used for storing data by injecting charges into the memory cells. When reading data, a read voltage can be applied to a specific memory cell to read the data stored in the memory cell. However, in practice, according to whether a certain physical block is an open block (i.e. a block which is not yet fully written) or a closed block (i.e. a block which is fully written), the reading errors occurring when the data is read from the physical block are different, so that the difficulty of correcting the read data later is increased.

Disclosure of Invention

In view of the above, the present invention provides a memory control method, a memory storage device and a memory control circuit unit, which can improve the accuracy of reading data.

Example embodiments of the present invention provide a memory control method for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of physical erasing units. The memory control method includes: receiving a read instruction from a host system, wherein the read instruction indicates reading a first logic unit, the first logic unit is mapped to a first physical programming unit, and the first physical programming unit belongs to a first physical erasing unit in the plurality of physical erasing units; responding to the first entity erasing unit as a first entity unit, and sending a first operation instruction sequence to instruct the rewritable nonvolatile memory module to read the first entity programming unit based on a first electrical setting; and responding to the first entity erasing unit as a second entity unit, and sending a second operation instruction sequence to instruct the rewritable nonvolatile memory module to read the first entity programming unit based on a second electrical setting. The first electrical setting is different from the second electrical setting. The first total number of the physical programming units in the erased state in the first type of physical units is different from the second total number of the physical programming units in the erased state in the second type of physical units.

In an example embodiment of the invention, the first total is non-zero and the second total is zero.

In an exemplary embodiment of the invention, the memory control method further includes: and judging the first entity erasing unit as the first entity unit or the second entity unit according to the total number of entity programming units in the erasing state in the first entity erasing unit.

In an exemplary embodiment of the present invention, the step of determining the first physical erased cell as the first type physical cell or the second type physical cell according to the total number of the physical programmed cells in the erased state in the first physical erased cell includes: determining that the first physical erased cell is the first type of physical cell in response to the total number of the physical programmed cells in the erased state in the first physical erased cell being non-zero; and determining that the first physical erased cell is the second type of physical cell in response to the total number of the physical programmed cells in the erased state in the first physical erased cell being zero.

In an example embodiment of the invention, the first electrical setting comprises a first read voltage level. The first sequence of operating instructions directs the rewritable non-volatile memory module to read the first physical programming unit using the first read voltage level. The second electrical setting includes a second read voltage level. The second sequence of operating instructions directs the rewritable non-volatile memory module to read the first physical programming unit using the second read voltage level. The first read voltage level is different from the second read voltage level.

In an exemplary embodiment of the invention, the memory control method further includes: determining the first read voltage level according to the distribution of the physical program units in the program state in the first physical erase unit.

In an exemplary embodiment of the invention, the memory control method further includes: and determining the read voltage level for reading the rest physical programming units in the first physical erasing unit according to the first read voltage level.

In an example embodiment of the present invention, the first electrical setting includes a turn-on voltage applied to a second physical program cell of the first physical erase cell. The first sequence of operating instructions instructs the rewritable non-volatile memory module to adjust the turn-on voltage. The second physical programming unit is not in the programming state.

In an exemplary embodiment of the invention, the second physical programming unit includes a plurality of memory cells, and the turn-on voltage is applied to control gates of the plurality of memory cells.

In an example embodiment of the present invention, the first electrical setting includes a bit line voltage applied to the first physically erased cell, and the first sequence of operating instructions instructs the rewritable non-volatile memory module to adjust the bit line voltage.

In an exemplary embodiment of the invention, the first physical erase unit includes a plurality of memory cells and at least one bit line. The plurality of memory cells are connected to the at least one bit line. The bit line voltage is applied to the at least one bit line.

The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being connected to a host system. The rewritable nonvolatile memory module comprises a plurality of physical erasing units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for: receiving a read instruction from the host system, wherein the read instruction indicates reading a first logical unit, the first logical unit is mapped to a first physical programming unit, and the first physical programming unit belongs to a first physical erasing unit of the plurality of physical erasing units; responding to the first entity erasing unit as a first entity unit, and sending a first operation instruction sequence to instruct the rewritable nonvolatile memory module to read the first entity programming unit based on a first electrical setting; and responding to the first entity erasing unit as a second entity unit, and sending a second operation instruction sequence to instruct the rewritable nonvolatile memory module to read the first entity programming unit based on a second electrical setting. The first electrical setting is different from the second electrical setting. The first total number of the physical programming units in the erased state in the first type of physical units is different from the second total number of the physical programming units in the erased state in the second type of physical units.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: and judging the first entity erasing unit as the first entity unit or the second entity unit according to the total number of entity programming units in the erasing state in the first entity erasing unit.

In an exemplary embodiment of the present invention, determining that the first physical erased cell is the first type of physical cell or the second type of physical cell according to the total number of the physical programmed cells in the erased state in the first physical erased cell comprises: determining that the first physical erased cell is the first type of physical cell in response to the total number of the physical programmed cells in the erased state in the first physical erased cell being non-zero; and determining that the first physical erased cell is the second type of physical cell in response to the total number of the physical programmed cells in the erased state in the first physical erased cell being zero.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: determining the first read voltage level according to the distribution of the physical program units in the program state in the first physical erase unit.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: and determining the read voltage level for reading the rest physical programming units in the first physical erasing unit according to the first read voltage level.

The exemplary embodiments of the present invention further provide a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of physical erasing units. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is to: receiving a read instruction from the host system, wherein the read instruction indicates reading a first logical unit, the first logical unit is mapped to a first physical programming unit, and the first physical programming unit belongs to a first physical erasing unit of the plurality of physical erasing units; responding to the first entity erasing unit as a first entity unit, and sending a first operation instruction sequence to instruct the rewritable nonvolatile memory module to read the first entity programming unit based on a first electrical setting; and responding to the first entity erasing unit as a second entity unit, and sending a second operation instruction sequence to instruct the rewritable nonvolatile memory module to read the first entity programming unit based on a second electrical setting. The first electrical setting is different from the second electrical setting. The first total number of the physical programming units in the erased state in the first type of physical units is different from the second total number of the physical programming units in the erased state in the second type of physical units.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to: and judging the first entity erasing unit as the first entity unit or the second entity unit according to the total number of entity programming units in the erasing state in the first entity erasing unit.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to: determining the first read voltage level according to the distribution of the physical program units in the program state in the first physical erase unit.

Based on the above, after receiving the read command from the host system, the transmitted operation command sequence may instruct the rewritable nonvolatile memory module to read the first physical program unit based on different electrical settings according to the type of the first physical erase unit to which the first physical program unit to be read belongs. In particular, the total number of physical program units in an erased state in different types of physical erase units is different. Therefore, the accuracy of the read data can be effectively improved.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;

FIG. 4A is a schematic diagram of a memory storage device according to an example embodiment of the invention;

FIG. 4B is a schematic diagram of a memory cell array according to an example embodiment of the invention;

FIG. 5 is a schematic diagram of a memory control circuit unit shown according to an example embodiment of the invention;

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a specific electrical configuration for reading data according to different types of physically erased cells according to an exemplary embodiment of the present invention;

fig. 8 is a flowchart of a memory control method according to an exemplary embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system such that the host system may write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be connected to a system bus 110.

In an example embodiment, host system 11 may be coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, host system 11 may be connected to I/O device 12 via system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In an exemplary embodiment, the processor 111, the ram 112, the rom 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 via a wired or wireless connection via the data transmission interface 114.

In an example embodiment, the memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless fidelity (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (such as iBeacon) or the like based on a wide variety of wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention. Referring to fig. 3, the memory storage device 30 may be used with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, video camera, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded memory device 34 used by a host system 31. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342 that directly connect the memory module to a substrate of the host system.

Fig. 4A is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to fig. 4A, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the PCI Express (Peripheral Component Interconnect Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may be a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) compliant standard, a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, UFS) interface standard, an eMCP interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 41 may be packaged in one chip with the memory control circuit unit 42, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.

The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control instructions implemented in hardware or firmware and performing operations of writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a second-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a fourth-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states. By applying the read voltage, it can be determined which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical program units, and the physical program units may constitute a plurality of physical erase units. Specifically, memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In an exemplary embodiment, the physical programming unit is a minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and a physical sector has a size of 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).

Fig. 4B is a schematic diagram of a memory cell array according to an example embodiment of the invention. Referring to fig. 4B, the memory cell array 44 includes a plurality of memory cells 402 for storing data, a plurality of select gate drain (select gate drain, SGD) transistors 412 and a plurality of select gate source (select gate source, SGS) transistors 414, a plurality of bit lines 404, a plurality of word lines 406, and a common source line 408 connecting the memory cells 402. In particular, memory cells 402 are arranged in an array at the intersections of bit lines 404 and word lines 406, as shown in FIG. 4B. In addition, the rewritable nonvolatile memory module 43 may include a plurality of memory cell arrays 44. Such memory cell arrays 44 may be stacked horizontally and/or vertically.

Fig. 5 is a schematic diagram of a memory control circuit unit according to an example embodiment of the invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52 and a memory interface 53.

The memory management circuit 51 is used for controlling the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and when the memory storage device 10 is operated, the control commands are executed to perform operations such as writing, reading and erasing data. The operation of the memory management circuit 51 is explained as follows, which is equivalent to the explanation of the operation of the memory control circuit unit 42.

In an example embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in a program code format in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory control circuit unit 42 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the ram of the memory management circuit 51. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells of the rewritable nonvolatile memory module 43. The memory write circuit is used for issuing a write instruction sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory read circuit is used for issuing a read instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erase circuit is used for issuing an erase command sequence to the rewritable nonvolatile memory module 43 to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 43 to perform corresponding writing, reading, and erasing operations. In an example embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.

The host interface 52 is connected to the memory management circuit 51. Memory management circuitry 51 may communicate with host system 11 through host interface 52. The host interface 52 is used to receive and identify the commands and data transmitted by the host system 11. For example, instructions and data transmitted by host system 11 may be transmitted to memory management circuit 51 via host interface 52. In addition, the memory management circuitry 51 may communicate data to the host system 11 through the host interface 52. In the present example embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with SATA standards, PATA standards, IEEE 1394 standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format acceptable to the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 is to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These sequences of instructions are, for example, generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read command sequence includes information such as the read identification code and the memory address.

In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 54 performs an error check and correction operation on the read data according to the error correction code and/or the error check code.

The buffer memory 55 is connected to the memory management circuit 51 and is used for temporarily storing data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10.

In an example embodiment, the rewritable non-volatile memory module 43 of fig. 4A may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of fig. 4A may include a flash memory controller. In an example embodiment, the memory management circuit 51 of fig. 5 may include a flash memory management circuit.

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention. Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610 (0) -610 (B) in the rewritable nonvolatile memory module 43 into a memory area 601 and a spare (spare) area 602.

In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of a plurality of consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also be referred to as a Virtual Block (VB). A virtual block may include multiple physical addresses or multiple physical programming units.

The physical units 610 (0) -610 (a) in the storage area 601 are configured to store user data (e.g., user data from the host system 11 of fig. 1). For example, the entity units 610 (0) to 610 (a) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610 (a+1) -610 (B) in the free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle area 602. In addition, the physical cells in the free area 602 (or the physical cells that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store the new data. In an exemplary embodiment, the free area 602 is also referred to as a free pool (free pool).

The memory management circuit 51 may configure the logic units 612 (0) through 612 (C) to map the physical units 610 (0) through 610 (A) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (Logical Block Address, LBAs) or other logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic programming unit or be composed of a plurality of consecutive or non-consecutive logic addresses.

It should be noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is currently mapped by a certain logic unit, the data currently stored in the entity unit includes valid data. Otherwise, if a certain entity unit is not mapped by any logic unit, the data stored in the entity unit is invalid.

The memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing a mapping relationship between the logic units and the entity units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.

The memory management circuit 51 may receive a write instruction from the host system 11 of fig. 1. The memory management circuit 51 may send a write command sequence to the rewritable nonvolatile memory module 43 according to the write command to instruct the rewritable nonvolatile memory module 43 to program the specific physical programming unit (i.e. write data to the specific physical programming unit). In particular, a physical programming unit that has not yet been programmed may be in an erased state. The programmed physical programming units (and memory cells) may be transitioned to be in a programmed state. The physical programming cells in the programmed state may be changed back to the erased state after being erased.

The memory management circuit 51 may receive a read instruction from the host system 11 of fig. 1. Such a read instruction may instruct a particular logic unit (also referred to as a first logic unit) to be read. For example, the first logic cell may include at least one of logic cells 612 (0) -612 (C) of FIG. 6. The first logic unit may be mapped to a specific physical programming unit (also referred to as a first physical programming unit) in the rewritable nonvolatile memory module 43. In particular, the first physical program unit may be included in a specific physical erase unit (also referred to as a first physical erase unit) in the rewritable nonvolatile memory module 43. According to the read command, the memory management circuit 51 can obtain the type of the first physical erase unit.

It should be noted that different types of physically erased cells may include different numbers of physically programmed cells in an erased state (or programmed state). For example, in an exemplary embodiment, the total number of physical program cells in an erased state (also referred to as a first total number) in the first type of physical cells may be different from the total number of physical program cells in an erased state (also referred to as a second total number) in the second type of physical cells. For example, the first total may be greater than the second total.

In an example embodiment, the first total number is non-zero and the second total number is zero. That is, in an exemplary embodiment, the first type of physical unit refers to a physical erased unit including at least one physical program unit in an erased state, and the second type of physical unit refers to a physical erased unit not including any physical program unit in an erased state. For example, assuming that the first physical erased cell includes at least one physical programmed cell in an erased state, the first physical erased cell may be determined or identified as a first type of physical cell. Alternatively, the first physical erased cell may be determined or identified as a second type of physical cell provided that the first physical erased cell does not include any physical programmed cells in an erased state (i.e., all physical programmed cells in the first physical erased cell are in a programmed state).

In an exemplary embodiment, the memory management circuit 51 can determine whether the first physical erase unit is a first type of physical unit or a second type of physical unit according to the total number of physical program units in the erased state in the first physical erase unit. For example, in response to the total number of physically programmed cells in the erased state in the first physically erased cell being non-zero, the memory management circuit 51 may determine that the first physically erased cell is a first type of physically erased cell. Or, in response to the total number of the physical program units in the erased state in the first physical erase unit being zero, determining that the first physical erase unit is a second type of physical unit.

In an exemplary embodiment, the first type of physical unit refers to a physically erased unit that is currently being turned on (also referred to as an on block). For example, the physical erase unit, which is the on unit, is the physical erase unit currently used for storing data. Once a certain physical erased cell, which is an on cell, is fully written (e.g., all physical programmed cells in the physical erased cell have been programmed and are in a programmed state), the physical erased cell may become an off cell (also referred to as an off block). In an exemplary embodiment, the second type of physical unit refers to a physical erased unit that is currently the shutdown unit.

In an exemplary embodiment, the memory management circuit 51 may determine whether the first physical erase unit is a first type of physical unit or a second type of physical unit according to whether the first physical erase unit is an on unit. For example, in response to the first physical erased cell being an on cell, the memory management circuit 51 may determine that the first physical erased cell is a first type of physical cell. Alternatively, in response to the first physical erase unit being not an on unit (e.g., an off unit), the memory management circuit 51 may determine that the first physical erase unit is a second type of physical unit.

After obtaining the type of the first physically erased cell, the memory management circuit 51 may send the sequence of operation instructions according to the type of the first physically erased cell. The sequence of operation instructions may be used to instruct the rewritable nonvolatile memory module 43 to read the first physical programming unit based on a specific electrical setting.

In an example embodiment, in response to the first physical erase unit being a first type of physical unit, the memory management circuit 51 may send a specific sequence of operation instructions (also referred to as a first sequence of operation instructions) to the rewritable nonvolatile memory module 43. The first sequence of operating instructions may be used to instruct the rewritable non-volatile memory module 43 to read the first physical programming unit based on a specific electrical setting (also referred to as a first electrical setting). For example, according to the first operation instruction sequence, the rewritable nonvolatile memory module 43 may use an electrical parameter (also referred to as a first electrical parameter) corresponding to the first electrical setting to read data from the first physical programming unit. For example, the first electrical parameter may affect a voltage, current, and/or impedance applied to the first physical erase unit (and/or the first physical program unit) during reading of data from the first physical program unit.

In an example embodiment, in response to the first physical erase unit being a second type of physical unit, the memory management circuit 51 may send a specific sequence of operation instructions (also referred to as a second sequence of operation instructions) to the rewritable nonvolatile memory module 43. The second sequence of operating instructions may be used to instruct the rewritable non-volatile memory module 43 to read the first physical programming unit based on a specific electrical setting (also referred to as a second electrical setting). The first electrical setting is different from the second electrical setting. For example, according to the second operation instruction sequence, the rewritable nonvolatile memory module 43 can use the electrical parameter corresponding to the second electrical setting (also referred to as the second electrical parameter) to read the data from the first physical programming unit. Similar to the first electrical parameter, the second electrical parameter may also affect the voltage, current, and/or impedance applied to the first physical erase unit (and/or the first physical program unit) during reading of data from the first physical program unit. However, the first electrical parameter is different from the second electrical parameter. Therefore, when data is read from different types of physically erased cells, the accuracy of the read data can be improved by applying different voltages, currents and/or impedances to the physically erased cells.

FIG. 7 is a schematic diagram illustrating a specific electrical configuration for reading data according to different types of physically erased cells according to an exemplary embodiment of the present invention. Referring to FIG. 7, the first type of physical erase unit 71 may include at least one physical program unit in a program state (labeled P) and at least one physical program unit in an erase state (labeled Er). The memory cells in each physical programming unit may be serially connected to each other via the word line 406 of fig. 4B. For example, word line 406 may be connected to control gates (control gates) of such memory cells. The second type of physical erase unit 72 may include a plurality of physical program units in a program state (labeled P), but does not include any physical program units in an erase state (labeled Er).

It should be noted that the first type physical erase unit 71 and the second type physical erase unit 72 shown in FIG. 7 are only examples. The present invention is not limited to the distribution states of the different types (i.e., in the programmed state and/or in the erased state) of physical program cells in the first type of physical erase cell 71 and/or the second type of physical erase cell 72. For example, in another exemplary embodiment, the second type of physical erase unit 72 may also include at least one physical program unit in an erased state, so long as the total number of physical program units in an erased state in the second type of physical erase unit 72 is different from the total number of physical program units in an erased state in the first type of physical erase unit 71.

In an exemplary embodiment, the first physical erase unit belongs to the first type of physical erase unit 71. Thus, the memory management circuit 51 may send a first sequence of operation instructions to instruct the rewritable nonvolatile memory module 43 to apply the electrical setting (i.e. the first electrical setting) 701 to read the first physical programming unit. In an exemplary embodiment, reading the first physical program unit based on the electrical setting 701 may reduce the total number of error bits read from the first physical program unit in the case that the first physical erase unit belongs to the first type of physical erase unit 71, as compared to the electrical setting (i.e., the second electrical setting) 702.

In an exemplary embodiment, the first physical erase unit belongs to the second type of physical erase unit 72. Thus, the memory management circuit 51 may send a second sequence of operation instructions to instruct the rewritable nonvolatile memory module 43 to apply the electrical settings 702 to read the first physical programming unit. In an example embodiment, reading the first physical program cell based on the electrical configuration 702 may reduce the total number of error bits read from the first physical program cell in the case that the first physical erase cell belongs to the second type of physical erase cell 72 as compared to the electrical configuration 701.

In an example embodiment, the first sequence of operation instructions may instruct the rewritable nonvolatile memory module 43 to read the first physical programming unit using a specific read voltage level (also referred to as a first read voltage level). In an example embodiment, the second sequence of operation instructions may instruct the rewritable nonvolatile memory module 43 to read the first physical programming unit using a specific read voltage level (also referred to as a second read voltage level). The first read voltage level is different from the second read voltage level.

In an example embodiment, the electrical settings 701 are customized electrical settings that are different from the electrical settings preset for the rewritable non-volatile memory module 43. For example, the memory management circuit 51 may determine or adjust the electrical setting 701 according to the distribution of the physical program cells in the program state (and/or erase state) in the first physical erase cell. The electrical settings 701 may be different depending on the distribution of the physical program cells in the program state (and/or erase state) in the first physical erase cell. In addition, the electrical setting 702 may be an electrical setting preset for the rewritable nonvolatile memory module 43.

In an exemplary embodiment, in the case that the first physically erased cells belong to the first physically erased cells 71, the memory management circuit 51 may determine the first read voltage level according to the distribution of the physically programmed cells in the first physically erased cells that are in a programmed state (and/or erased state). For example, the first read voltage level may be a customized read voltage level that is different from a read voltage level preset to read the first physical programming unit. The memory management circuit 51 may send a first sequence of operating instructions according to the determined first read voltage level. For example, according to the first operation command sequence, the rewritable nonvolatile memory module 43 can set the read voltage level Vread in fig. 7 to the first read voltage level and read the physical program unit 710 (i.e., the first physical program unit) using the first read voltage level.

In an exemplary embodiment, the distribution of the physical program cells in the programmed state (and/or erased state) in the first physical erase cell may reflect the total number of physical program cells in the programmed state and/or erased state in the first physical erase cell. The memory management circuit 51 may determine (including adjust) a first read voltage level (e.g., the read voltage level Vread in fig. 7) based on the total number. For example, the memory management circuit 51 may determine the different first read voltage levels according to the difference of the total number of the physical program units in the program state in the first physical erase unit.

In an exemplary embodiment, after determining the first read voltage level (e.g., the read voltage level Vread in fig. 7), the memory management circuit 51 may determine the read voltage level for reading the remaining physical program cells (e.g., the physical program cell 730) in the first physical erase cell according to the determined first read voltage level. For example, the physical program unit 730 may include any one of the first physical erase units in a programmed state. For example, the memory management circuit 51 may input the voltage value of the first read voltage level to a specific algorithm or table to obtain the voltage value for reading the read voltage level of the physical programming unit 730. The memory management circuit 51 may then read the physical programming unit 730 according to the determined new read voltage level. For example, reading the physical program unit 730 with the new read voltage level helps to reduce the total number of error bits read from the physical program unit 730, compared to the read voltage level preset to read the physical program unit 730. In an exemplary embodiment, the physical programming unit 730 may further include a plurality of physical programming units belonging to different physical erasing units, different planes (also referred to as memory planes), or different Chip Enable (CE) areas.

In an exemplary embodiment, in the case that the first physical erase unit belongs to the second type of physical erase unit 72, the rewritable nonvolatile memory module 43 can read the first physical program unit using another read voltage level (i.e., a second read voltage level) according to the electrical setting 702. The second read voltage level may be a predetermined read voltage level for reading the first physical program unit. For example, according to the second sequence of operation instructions, the rewritable nonvolatile memory module 43 can set the read voltage level Vread in fig. 7 to a second read voltage level and read the physical programming unit 710 using the second read voltage level.

In an example embodiment, the first sequence of operation instructions may instruct the rewritable nonvolatile memory module 43 to adjust the turn-on voltage applied to at least some of the first physical program cells (i.e., the second physical program cells). It should be noted that the second physical programming unit is not in a programmed state. For example, the second physical program unit may include at least a portion of the physical program units in the erased state in the first physical erase unit.

Taking fig. 7 as an example, in the case that the first physical erase unit belongs to the first type of physical erase unit 71, during the period of reading the physical program unit 710 by using the read voltage level Vread, the rewritable nonvolatile memory module 43 can adjust the pass voltage Vpass applied to the physical program unit 720 (i.e., the second physical program unit) according to the first operation command sequence. For example, the pass voltage Vpass may be applied to the control gates of the respective memory cells in the physical programming unit 720. By adjusting the pass voltage Vpass, the resistance of at least some of the memory cells in the physical program unit 720 can be changed, thereby reducing the total number of erroneous bits read by the physical program unit 710 using the read voltage level Vread.

In an example embodiment, the second sequence of operation instructions may not instruct the rewritable nonvolatile memory module 43 to adjust the pass voltage Vpass applied to the physical programming unit 720. Alternatively, in an exemplary embodiment, the second operation command sequence may also instruct the rewritable nonvolatile memory module 43 to adjust the pass voltage Vpass applied to the physical program unit 720 during the period when the physical program unit 710 is read using the read voltage level Vread, but the adjustment amplitude of the pass voltage Vpass indicated by the second operation command sequence may be different from the adjustment amplitude of the pass voltage Vpass indicated by the first operation command sequence.

In an example embodiment, the first sequence of operation instructions may instruct the rewritable nonvolatile memory module 43 to adjust (e.g., decrease) the bit line voltage applied to the first physically erased cell. Taking fig. 7 as an example, in the case that the first physical erase unit belongs to the first type of physical erase unit 71, during the period of reading the physical program unit 710 by using the read voltage level Vread, the rewritable nonvolatile memory module 43 can adjust the bit line voltage Vb applied to at least part (or all) of the bit lines (e.g., the bit line 404 of fig. 4B) in the first physical erase unit according to the first operation command sequence. The bit line may be connected to at least some (or all) of the physical programming units (or memory cells) in the first physical erase unit. By adjusting the bit line voltage Vb, the total number of erroneous bits read by the physical programming unit 710 using the read voltage level Vread can also be reduced.

In an exemplary embodiment, the memory management circuit 51 may determine the adjustment amplitude of the bit line voltage Vb according to the distribution of the physical program units in the program state (and/or the erase state) in the first physical erase unit. For example, the adjustment of the bit line voltage Vb may be different depending on the number of physical program cells in the program state (and/or erase state) in the first physical erase cell. For example, the magnitude of the drop in the bit line voltage Vb can be positive relative to the total number of physically programmed cells in the erased state in the first physically erased cell.

In an example embodiment, the second sequence of operation instructions may not instruct the rewritable nonvolatile memory module 43 to adjust the bit line voltage Vb. Alternatively, in an exemplary embodiment, the second operation command sequence may also instruct the rewritable nonvolatile memory module 43 to adjust the bit line voltage Vb during the period of reading the physical programming unit 710 using the read voltage level Vread, but the adjustment amplitude of the bit line voltage Vb indicated by the second operation command sequence may be different from the adjustment amplitude of the bit line voltage Vb indicated by the first operation command sequence.

It should be noted that the types and adjustment manners of the electrical parameters corresponding to the electrical settings 701 and/or 702 in the foregoing exemplary embodiment are only examples, and are not intended to limit the present invention. In an exemplary embodiment, more electrical parameters that affect the voltage, current and/or impedance of the first physical erase unit to improve the accuracy of the data reading of the first physical program unit may also be adjusted during the reading of the data from the first physical program unit, which is not limited by the present invention.

Fig. 8 is a flowchart of a memory control method according to an exemplary embodiment of the present invention. Referring to fig. 8, in step S801, a read instruction is received from a host system, wherein the read instruction instructs to read a first logic unit. The first logic unit is mapped to a first physical programming unit, and the first physical programming unit belongs to a first physical erasing unit. In step S802, it is determined whether the first physical erase unit is a first type of physical unit. In response to the first physical erasing unit being a first type of physical unit, in step S803, a first operation command sequence is sent to instruct the rewritable nonvolatile memory module to read the first physical programming unit based on the first electrical setting. Or, in response to the first physical erasing unit being the second type of physical unit, in step S804, a second sequence of operation instructions is sent to instruct the rewritable nonvolatile memory module to read the first physical programming unit based on the second electrical setting. The first electrical setting is different from the second electrical setting. The total number of the physical programming units in the erased state in the first type of physical units is different from the total number of the physical programming units in the erased state in the second type of physical units.

However, the steps in fig. 8 are described in detail above, and will not be described again here. It should be noted that each step in fig. 8 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 8 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.

In summary, the exemplary embodiments of the present invention can instruct the rewritable nonvolatile memory module to read data from the physical erase unit based on the customized electrical settings according to the type of the physical erase unit to be read (e.g. whether the physical erase unit belongs to the on unit and/or the distribution of the physical program units in the physical erase unit in the erased state). Therefore, the accuracy of the read data can be effectively improved.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A memory control method for a rewritable non-volatile memory module, the rewritable non-volatile memory module comprising a plurality of physical erase units, the memory control method comprising:

receiving a read instruction from a host system, wherein the read instruction indicates reading a first logic unit, the first logic unit is mapped to a first physical programming unit, and the first physical programming unit belongs to a first physical erasing unit in the plurality of physical erasing units;

responding to the first entity erasing unit as a first entity unit, and sending a first operation instruction sequence to instruct the rewritable nonvolatile memory module to read the first entity programming unit based on a first electrical setting; and

transmitting a second sequence of operation instructions to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electrical setting in response to the first physical erasing unit being a second type of physical unit,

wherein the first electrical setting is different from the second electrical setting, and

the first total number of the physical programming units in the erased state in the first type of physical units is different from the second total number of the physical programming units in the erased state in the second type of physical units.

2. The memory control method of claim 1, wherein the first total is non-zero and the second total is zero.

3. The memory control method according to claim 1, further comprising:

and judging the first entity erasing unit as the first entity unit or the second entity unit according to the total number of entity programming units in the erasing state in the first entity erasing unit.

4. The memory control method of claim 3, wherein determining whether the first physical erased cell is the first type of physical cell or the second type of physical cell based on the total number of the physical programmed cells in the erased state in the first physical erased cell comprises:

determining that the first physical erased cell is the first type of physical cell in response to the total number of the physical programmed cells in the erased state in the first physical erased cell being non-zero; and

and determining that the first physical erased cell is the second type of physical cell in response to the total number of the physical programmed cells in the erased state in the first physical erased cell being zero.

5. The memory control method of claim 1, wherein the first electrical setting comprises a first read voltage level, the first sequence of operating instructions directing the rewritable non-volatile memory module to read the first physical programming unit using the first read voltage level,

the second electrical setting includes a second read voltage level, the second sequence of operating instructions instructs the rewritable non-volatile memory module to read the first physical programming unit using the second read voltage level, and

the first read voltage level is different from the second read voltage level.

6. The memory control method according to claim 5, further comprising:

determining the first read voltage level according to the distribution of the physical program units in the program state in the first physical erase unit.

7. The memory control method according to claim 6, further comprising:

and determining the read voltage level for reading the rest physical programming units in the first physical erasing unit according to the first read voltage level.

8. The memory control method of claim 1, wherein the first electrical setting includes a turn-on voltage applied to a second physical programming unit of the first physical erase unit, the first sequence of operating instructions directs the rewritable non-volatile memory module to adjust the turn-on voltage, and

The second physical programming unit is not in a programmed state.

9. The memory control method according to claim 8, wherein the second physical programming unit includes a plurality of memory units, and

the turn-on voltage is applied to control gates of the plurality of memory cells.

10. The memory control method of claim 1, wherein the first electrical setting comprises a bit line voltage applied to the first physically erased cell, and the first sequence of operating instructions directs the rewritable non-volatile memory module to adjust the bit line voltage.

11. The method of claim 10, wherein the first physically erased cell comprises a plurality of memory cells and at least one bit line,

the plurality of memory cells are connected to the at least one bit line, and

the bit line voltage is applied to the at least one bit line.

12. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

the rewritable nonvolatile memory module comprises a plurality of entity erasing units; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

Wherein the memory control circuit unit is configured to:

receiving a read instruction from the host system, wherein the read instruction indicates reading a first logical unit, the first logical unit is mapped to a first physical programming unit, and the first physical programming unit belongs to a first physical erasing unit of the plurality of physical erasing units;

13. The memory storage device of claim 12, wherein the first total is non-zero and the second total is zero.

14. The memory storage device of claim 12, wherein the memory control circuit unit is further to:

15. The memory storage device of claim 14, wherein determining that the first physical erased cell is the first type of physical cell or the second type of physical cell based on the total number of the physical programmed cells in the erased state in the first physical erased cell comprises:

16. The memory storage device of claim 12 wherein the first electrical setting comprises a first read voltage level, the first sequence of operating instructions directing the rewritable non-volatile memory module to read the first physical programming unit using the first read voltage level,

the first read voltage level is different from the second read voltage level.

17. The memory storage device of claim 16, wherein the memory control circuit unit is further to:

18. The memory storage device of claim 17, wherein the memory control circuit unit is further to:

19. The memory storage device of claim 12, wherein the first electrical setting comprises a turn-on voltage applied to a second physical programming unit of the first physical erase unit, the first sequence of operating instructions directs the rewritable non-volatile memory module to adjust the turn-on voltage, and

the second physical programming unit is not in a programmed state.

20. The memory storage device of claim 19, wherein the second physical programming unit comprises a plurality of memory units, and

21. The memory storage device of claim 12, wherein the first electrical setting comprises a bit line voltage applied to the first physically erased cell, and the first sequence of operating instructions directs the rewritable non-volatile memory module to adjust the bit line voltage.

22. The memory storage device of claim 21, wherein the first physically erased cell comprises a plurality of memory cells and at least one bit line,

the plurality of memory cells are connected to the at least one bit line, and

the bit line voltage is applied to the at least one bit line.

23. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the rewritable nonvolatile memory module comprising a plurality of physical erase units, the memory control circuit unit comprising:

a host interface for connecting to a host system;

a memory interface to connect to the rewritable non-volatile memory module; and

a memory management circuit coupled to the host interface and the memory interface,

wherein the memory management circuit is to:

24. The memory control circuit unit of claim 23, wherein the first total is non-zero and the second total is zero.

25. The memory control circuit unit of claim 23, wherein the memory management circuit is further to:

26. The memory control circuit unit of claim 25, wherein determining whether the first physical erased cell is the first type of physical cell or the second type of physical cell based on the total number of the physical programmed cells in the erased state in the first physical erased cell comprises:

27. The memory control circuit unit of claim 23, wherein the first electrical setting comprises a first read voltage level, the first sequence of operating instructions directing the rewritable non-volatile memory module to read the first physical programming unit using the first read voltage level,

the first read voltage level is different from the second read voltage level.

28. The memory control circuit unit of claim 27, wherein the memory management circuit is further to:

29. The memory control circuit unit of claim 28, wherein the memory management circuit is further to:

30. The memory control circuit unit of claim 23, wherein the first electrical setting includes a turn-on voltage applied to a second one of the first physically erasable units, the first sequence of operating instructions directs the rewritable non-volatile memory module to adjust the turn-on voltage, and

the second physical programming unit is not in a programmed state.

31. The memory control circuit unit of claim 30, wherein the second physical programming unit comprises a plurality of memory cells, and

32. The memory control circuit unit of claim 23, wherein the first electrical setting comprises a bit line voltage applied to the first physical erase unit, and the first sequence of operating instructions instructs the rewritable non-volatile memory module to adjust the bit line voltage.

33. The memory control circuit unit of claim 32, wherein the first physical erase unit comprises a plurality of memory cells and at least one bit line,

The plurality of memory cells are connected to the at least one bit line, and

the bit line voltage is applied to the at least one bit line.