CN112051971B - Data merging method, memory storage device and memory control circuit unit - Google Patents

Data merging method, memory storage device and memory control circuit unit Download PDF

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CN112051971B
CN112051971B CN202010948313.5A CN202010948313A CN112051971B CN 112051971 B CN112051971 B CN 112051971B CN 202010948313 A CN202010948313 A CN 202010948313A CN 112051971 B CN112051971 B CN 112051971B
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data
unit
entity
mapping information
entity unit
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CN112051971A (en
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郭哲岳
潘庆育
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0635—Configuration or reconfiguration of storage systems by changing the path, e.g. traffic rerouting, path reconfiguration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0653—Monitoring storage devices or systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The invention provides a data merging method, a memory storage device and a memory control circuit unit. The method comprises the following steps: selecting at least one first entity unit and at least one second entity unit from entity units of the rewritable nonvolatile memory module; reading first mapping information from the rewritable nonvolatile memory module, wherein the first mapping information comprises mapping information of at least one first entity unit and mapping information of at least one second entity unit; copying the effective data collected from the at least one first entity unit and the effective data collected from the at least one second entity unit to at least one third entity unit in the entity units according to the first mapping information; and stopping collecting the effective data from the at least one second entity unit and continuing to collect the effective data from the at least one first entity unit when the data volume of the effective data copied from the at least one second entity unit to the at least one third entity unit reaches the data volume threshold value.

Description

Data merging method, memory storage device and memory control circuit unit
Technical Field
The present invention relates to flash memory technology, and more particularly, to a data merging method, a memory storage device and a memory control circuit unit.
Background
Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, such that consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable multimedia devices.
When the memory storage device leaves the factory, a part of the entity units in the memory storage device are configured as a plurality of idle entity units so as to use the idle entity units to store new data. After a period of use, the number of idle physical units in the memory storage device is gradually reduced. The memory storage device may copy valid data from a plurality of source nodes to a reclamation node (also referred to as a target node) through a data merge process (or referred to as a garbage collection process) and erase the entity units belonging to the source node to release new idle entity units.
Generally, in the data merging process, the data merging process is performed on the entity units storing less effective data in the source node, so as to ensure that the effective data in the entity units storing less effective data can be copied to the recovery node. Then, the effective data is copied to the residual space of the recovery node from the entity unit storing more effective data in the source node. However, the higher the repetition rate of the logical units mapped by the plurality of physical units selected as the source node, the more the same table describing the management information (e.g., mapping information) of the logical units will be repeatedly loaded in the data merging process of the two stages, thereby increasing the access times of the memory storage device and resulting in the overall performance of the memory storage device being reduced.
Disclosure of Invention
The invention provides a data merging method, a memory storage device and a memory control circuit unit, which can improve the problems and effectively reduce the access times to the memory storage device in a data merging program.
Exemplary embodiments of the present invention provide a data consolidation method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units. The data integration method comprises the following steps: selecting at least one first entity unit and at least one second entity unit from the entity units; reading first mapping information from the rewritable non-volatile memory module, wherein the first mapping information comprises mapping information of the at least one first entity unit and mapping information of the at least one second entity unit; copying the effective data collected from the at least one first entity unit and the effective data collected from the at least one second entity unit to at least one third entity unit in the entity units according to the first mapping information; and stopping collecting the effective data from the at least one second entity unit and continuing to collect the effective data from the at least one first entity unit when the data volume of the effective data copied from the at least one second entity unit to the at least one third entity unit reaches a data volume threshold value.
In an exemplary embodiment of the present invention, the size of the at least one third entity unit is a target data size, and the data size threshold is a remaining data size obtained by subtracting a total data size of the effective data in the at least one first entity unit from the target data size.
In an exemplary embodiment of the present invention, the first data amount of the valid data collected from the at least one first entity unit is equal to the total data amount of the valid data in the at least one first entity unit, and the second data amount of the valid data collected from the at least one second entity unit is smaller than the total data amount of the valid data in the at least one second entity unit.
In an exemplary embodiment of the present invention, a sum of the first data amount and the second data amount is a size of the at least one third entity unit.
In an exemplary embodiment of the present invention, the step after reading the first mapping information from the rewritable nonvolatile memory module includes: and identifying the effective data in the at least one first entity unit and the effective data in the at least one second entity unit according to the first mapping information, wherein the data volume of the effective data in each at least one first entity unit is smaller than the data volume of the effective data in each at least one second entity unit.
In an exemplary embodiment of the present invention, when the data amount of the valid data copied from the at least one second entity unit to the at least one third entity unit reaches the data amount threshold, stopping collecting valid data from the at least one second entity unit and continuing to collect valid data from the at least one first entity unit includes: reading second mapping information from the rewritable non-volatile memory module, wherein the second mapping information comprises mapping information of the at least one first entity unit; and copying the effective data collected from the at least one first entity unit to at least one third entity unit in the entity units according to the second mapping information.
In an exemplary embodiment of the present invention, wherein the first table mapping information reflects the mapping information of the at least one first physical unit and the second table mapping information reflects the mapping information of the at least one second physical unit and the step of reading the first mapping information from the rewritable non-volatile memory module includes: and reading the first mapping information according to the first table mapping information and the second table mapping information, wherein the first mapping information reflects overlapping information between the at least one first logic-to-entity mapping table and the at least one second logic-to-entity mapping table.
The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being connected to a host system. The rewritable nonvolatile memory module includes a plurality of physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is configured to select at least one first entity unit and at least one second entity unit from the entity units, where the first mapping information includes mapping information of the at least one first entity unit and mapping information of the at least one second entity unit. The memory control circuit unit is further configured to copy the valid data collected from the at least one first entity unit and the valid data collected from the at least one second entity unit to at least one third entity unit of the entity units according to the first mapping information, and the memory control circuit unit is further configured to stop collecting valid data from the at least one second entity unit and continue collecting valid data from the at least one first entity unit when a data volume of the valid data copied from the at least one second entity unit to the at least one third entity unit reaches a data volume threshold value.
In an exemplary embodiment of the present invention, the size of the at least one third entity unit is a target data size, and the data size threshold is a remaining data size obtained by subtracting a total data size of the effective data in the at least one first entity unit from the target data size.
In an exemplary embodiment of the present invention, the first data amount of the valid data collected from the at least one first entity unit is equal to the total data amount of the valid data in the at least one first entity unit, and the second data amount of the valid data collected from the at least one second entity unit is smaller than the total data amount of the valid data in the at least one second entity unit.
In an exemplary embodiment of the present invention, a sum of the first data amount and the second data amount is a size of the at least one third entity unit.
In an example embodiment of the present invention, the operations after reading the first mapping information from the rewritable nonvolatile memory module include: and identifying the effective data in the at least one first entity unit and the effective data in the at least one second entity unit according to the first mapping information, wherein the data volume of the effective data in each at least one first entity unit is smaller than the data volume of the effective data in each at least one second entity unit.
In an exemplary embodiment of the present invention, when the data amount of the valid data copied from the at least one second entity unit to the at least one third entity unit reaches the data amount threshold, stopping the collection of valid data from the at least one second entity unit and continuing the collection of valid data from the at least one first entity unit includes: reading second mapping information from the rewritable non-volatile memory module, wherein the second mapping information comprises mapping information of the at least one first entity unit; and copying the effective data collected from the at least one first entity unit to at least one third entity unit in the entity units according to the second mapping information.
In an exemplary embodiment of the present invention, the first table mapping information reflects mapping information of the at least one first entity unit and the second table mapping information reflects mapping information of the at least one second entity unit and is recorded in at least one second logic to entity mapping table, wherein the operation of reading the first mapping information from the rewritable non-volatile memory module includes: and reading the first mapping information according to the first table mapping information and the second table mapping information, wherein the first mapping information reflects overlapping information between the at least one first logic-to-entity mapping table and the at least one second logic-to-entity mapping table.
The exemplary embodiments of the present invention further provide a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module includes a plurality of physical units. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is configured to read first mapping information from the rewritable nonvolatile memory module, wherein the first mapping information includes mapping information of the at least one first entity unit and mapping information of the at least one second entity unit. The memory management circuit is further configured to copy the valid data collected from the at least one first entity unit and the valid data collected from the at least one second entity unit to at least one third entity unit of the entity units according to the first mapping information, and the memory management circuit is further configured to stop collecting valid data from the at least one second entity unit and continue collecting valid data from the at least one first entity unit when a data amount of the valid data copied from the at least one second entity unit to the at least one third entity unit reaches a data amount threshold.
In an exemplary embodiment of the present invention, the size of the at least one third entity unit is a target data size, and the data size threshold is a remaining data size obtained by subtracting a total data size of the effective data in the at least one first entity unit from the target data size.
In an exemplary embodiment of the present invention, the first data amount of the valid data collected from the at least one first entity unit is equal to the total data amount of the valid data in the at least one first entity unit, and the second data amount of the valid data collected from the at least one second entity unit is smaller than the total data amount of the valid data in the at least one second entity unit.
In an exemplary embodiment of the present invention, a sum of the first data amount and the second data amount is a size of the at least one third entity unit.
In an example embodiment of the present invention, the operations after reading the first mapping information from the rewritable nonvolatile memory module include: and identifying the effective data in the at least one first entity unit and the effective data in the at least one second entity unit according to the first mapping information, wherein the data volume of the effective data in each at least one first entity unit is smaller than the data volume of the effective data in each at least one second entity unit.
In an exemplary embodiment of the present invention, when the data amount of the valid data copied from the at least one second entity unit to the at least one third entity unit reaches the data amount threshold, stopping the collection of valid data from the at least one second entity unit and continuing the collection of valid data from the at least one first entity unit includes: reading second mapping information from the rewritable non-volatile memory module, wherein the second mapping information comprises mapping information of the at least one first entity unit; and copying the effective data collected from the at least one first entity unit to at least one third entity unit in the entity units according to the second mapping information.
In an exemplary embodiment of the present invention, the first table mapping information reflects mapping information of the at least one first entity unit and the second table mapping information reflects mapping information of the at least one second entity unit and is recorded in at least one second logic to entity mapping table, wherein the operation of reading the first mapping information from the rewritable non-volatile memory module includes: and reading the first mapping information according to the first table mapping information and the second table mapping information, wherein the first mapping information reflects overlapping information between the at least one first logic-to-entity mapping table and the at least one second logic-to-entity mapping table.
Based on the above, the memory management circuit can use the mapping information shared by the at least one first entity unit and the at least one second entity unit, copy the valid data in the at least one first entity unit and the at least one second entity unit to the at least one third entity unit of the recovery node at the same time, and limit the data amount copied from the at least one second entity unit with relatively more data amount of the valid data in the source node to the recovery node by setting the data amount threshold value, so as to avoid the repeated reading of the logical-to-entity mapping table used for accessing the at least one first entity unit and the at least one second entity unit in the data merging operation. Therefore, the access times of the memory storage device in the data integration operation can be effectively reduced, and the overall operation efficiency of the memory storage device is further improved.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention;
FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to another example embodiment of the invention;
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an example embodiment of the invention;
FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;
FIGS. 7A-7C are diagrams illustrating a data merge operation according to an example embodiment of the invention;
FIG. 8 is a diagram illustrating table mapping information according to an example embodiment of the present invention;
fig. 9A to 9B are diagrams illustrating obtaining a logical-to-physical mapping table according to mapping information according to an exemplary embodiment of the present invention;
fig. 10A to 10B are diagrams illustrating obtaining a logical-to-physical mapping table according to mapping information according to a conventional data merging operation;
FIG. 11 is a flowchart of a method for merging data according to an exemplary embodiment of the present invention.
Description of the reference numerals
10. 30: a memory storage device;
11. 31: a host system;
110: a system bus;
111: a processor;
112: a random access memory;
113: a read-only memory;
114: a data transmission interface;
12: input/output (I/O) devices;
20: a motherboard;
201: USB flash disk;
202: a memory card;
203: a solid state disk;
204: a wireless memory storage device;
205: a global positioning system module;
206: a network interface card;
207: a wireless transmission device;
208: a keyboard;
209: a screen;
210: a horn;
32: an SD card;
33: a CF card;
34: an embedded storage device;
341: an embedded multimedia card;
342: an embedded multi-chip package memory device;
402: a connection interface unit;
404: a memory control circuit unit;
406: a rewritable nonvolatile memory module;
502: a memory management circuit;
504: a host interface;
506: a memory interface;
508: an error checking and correcting circuit;
510: a buffer memory;
512: a power management circuit;
601: a storage area;
602: a replacement area;
603: a system area;
610 (0) to 610 (C), 710 (0) to 710 (3), 720 (0), 810 (0) to 810 (1): a physical unit;
612 (0) to 612 (D): a logic unit;
700A, 700B: data;
701: a source node;
702: recovering the nodes;
801. 802, 910 (0) to 910 (3): form mapping information;
830: a logical to physical mapping table;
901. 902, 1001: mapping information;
90: a logic module;
s1101: selecting at least one first entity unit and at least one second entity unit from the entity units;
s1103: reading first mapping information from the rewritable non-volatile memory module, wherein the first mapping information includes mapping information of the at least one first entity unit and mapping information of the at least one second entity unit;
s1105: copying the effective data collected from the at least one first entity unit and the effective data collected from the at least one second entity unit to at least one third entity unit in the entity units according to the first mapping information;
s1107: and stopping collecting the valid data from the at least one second entity unit and continuing to collect the valid data from the at least one first entity unit when the data amount of the valid data copied from the at least one second entity unit to the at least one third entity unit reaches a data amount threshold.
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Memory storage devices are typically used with host systems so that the host system can write data to or read data from the memory storage device.
FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 are all connected to a system bus 110.
In the present exemplary embodiment, host system 11 is coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. The host system 11 is connected to the I/O device 12 via a system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.
In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 via a wired or wireless connection via the data transmission interface 114. The memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field wireless communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (such as iBeacon) or the like based on a variety of wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.
In an example embodiment, the host system referred to is any system that can cooperate with substantially a memory storage device to store data. Although the host system is described in the above exemplary embodiment as a computer system, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may be a system such as a Digital camera, a video camera, a communication device, an audio player, a video player or a tablet computer, and the memory storage device 30 may be a variety of nonvolatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33 or an embedded storage device 34. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342 that directly connect the memory module to a substrate of the host system.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable nonvolatile memory module 406.
The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 402. In the present exemplary embodiment, the connection interface unit 402 is compatible with the serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a standard compliant with a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a High-Speed peripheral component interconnect (Peripheral Component Interconnect Express, PCI Express) standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, s) interface standard, an ehcp interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in a single chip, or the connection interface unit 402 may be disposed off-chip with the memory control circuit unit 404.
The memory control circuit unit 404 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to the instructions of the host system 11.
The rewritable nonvolatile memory module 406 is connected to the memory control circuit unit 404 and is used to store data written by the host system 11. The rewritable nonvolatile memory module 406 may be a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a fourth-Level memory Cell (TLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. By applying the read voltage, it can be determined which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.
In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 may constitute a plurality of physical program cells, and the physical program cells may constitute a plurality of physical erase cells. Specifically, memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.
In the present exemplary embodiment, the physical programming unit is the minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased. For example, the physical erased cells are physical blocks (blocks).
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504 and a memory interface 506.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform writing, reading and erasing operations of data while the memory storage device 10 is operating. The operation of the memory management circuit 502 is described as follows, which is equivalent to the description of the operation of the memory control circuit unit 404.
In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.
In another example embodiment, the control instructions of the memory management circuit 502 may also be stored in program code form in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area of the memory module dedicated to storing system data). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit 404 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.
Furthermore, in another example embodiment, the control instructions of the memory management circuit 502 may also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage memory cells or groups of memory cells of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read instruction sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erase circuit is configured to issue an erase command sequence to the rewritable nonvolatile memory module 406 to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 406 to perform the corresponding write, read, erase, etc. In an example embodiment, the memory management circuitry 502 may also issue other types of sequences of instructions to the rewritable non-volatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 504 is coupled to the memory management circuitry 502. The memory management circuitry 502 may communicate with the host system 11 through a host interface 504. The host interface 504 is used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transferred by host system 11 may be transferred to memory management circuitry 502 via host interface 504. In addition, the memory management circuitry 502 may communicate data to the host system 11 through the host interface 504. In the present exemplary embodiment, host interface 504 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with PATA standards, IEEE 1394 standards, PCI Express standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.
The memory interface 506 is coupled to the memory management circuitry 502 and is used to access the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format acceptable to the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 is to access the rewritable nonvolatile memory module 406, the memory interface 506 will transmit the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These sequences of instructions are, for example, generated by memory management circuitry 502 and transferred to rewritable non-volatile memory module 406 through memory interface 506. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.
In an example embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508, a buffer memory 510, and a power management circuit 512.
The error checking and correction circuit 508 is connected to the memory management circuit 502 and is used for performing error checking and correction operations to ensure the correctness of the data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 406. Then, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 508 performs an error check and correction operation on the read data according to the error correction code and/or the error check code.
The buffer memory 510 is connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is coupled to the memory management circuit 502 and is used to control the power of the memory storage device 10.
In an example embodiment, the rewritable non-volatile memory module 406 of fig. 4 is also referred to as a flash memory module, the memory control circuit unit 404 is also referred to as a flash memory controller for controlling the flash memory module, and/or the memory management circuit 502 of fig. 5 is also referred to as a flash memory management circuit.
FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention.
Referring to FIG. 6, the memory management circuit 502 can logically group the physical units 610 (0) -610 (C) of the rewritable nonvolatile memory module 406 into a memory area 601, a spare (spare) area 602 and a system area 603. The entity units 610 (0) to 610 (a) in the storage area 601 store data. For example, the entity units 610 (0) to 610 (a) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610 (a+1) -610 (B) in the free area 602 are not yet used to store data (e.g., valid data). The entity units 610 (b+1) -610 (C) in the system area 603 are configured to store system data, such as a logical-to-entity mapping table, a bad block management table, a device model, or other types of management data.
The memory management circuit 502 may select one entity from the entity units 610 (a+1) -610 (B) of the spare area 602 and store data from the host system 11 or from at least one entity in the storage area 601 into the selected entity. At the same time, the selected entity units are associated to the storage area 601. In addition, after erasing a physical cell in the memory area 601, the erased physical cell is re-associated with the spare area 602.
In the exemplary embodiment, each entity belonging to the memory area 601 is also referred to as a non-idle (non-spare) entity, and each entity belonging to the idle area 602 is also referred to as an idle entity. In the present exemplary embodiment, a physical cell refers to a physical erase cell. However, in another exemplary embodiment, one physical cell may also include a plurality of physical erase units.
The memory management circuit 502 may configure the logic units 612 (0) -612 (D) to map the physical units 610 (0) -610 (A) in the memory area 601. In the present exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logic unit may also refer to a logic program unit, a logic erase unit, or be composed of a plurality of consecutive or non-consecutive logic addresses. In addition, each of logic cells 612 (0) -612 (D) may be mapped to one or more physical cells. It should be noted that the memory management circuit 502 may not be configured with logic units mapped to the system area 603 to prevent the system data stored in the system area 603 from being modified by a user.
The memory management circuit 502 records mapping information (also called logical-to-physical mapping information) between logical units and physical units in at least one logical-to-physical mapping table. The mapping information may reflect a mapping relationship between a certain entity unit and a certain logical unit in the storage area 601. The logical-to-physical mapping table is stored in the physical units 610 (b+1) to 610 (C) of the system area 603. The memory management circuitry 502 may perform data access operations for the memory storage device 10 according to this logical-to-physical mapping table. For example, the memory management circuit 502 may obtain a mapping relationship between a certain entity unit and a certain logic unit in the memory area 601 according to a certain logic-to-entity mapping table. The memory management circuit 502 can access the physical unit according to the mapping relationship.
In the present exemplary embodiment, valid data is the latest data belonging to a certain logical unit, and invalid data is not the latest data belonging to any logical unit. For example, if the host system 11 stores a new data in a logical unit and overwrites old data originally stored in the logical unit (i.e., updates data belonging to the logical unit), the new data stored in the storage area 601 is the latest data belonging to the logical unit and is marked as valid, and the overwrites old data may still be stored in the storage area 601 but marked as invalid.
In the exemplary embodiment, if the data belonging to a certain logical unit is updated, the mapping relationship between the logical unit and the physical unit storing the old data belonging to the logical unit is removed, and the mapping relationship between the logical unit and the physical unit storing the latest data belonging to the logical unit is established. However, in another exemplary embodiment, if the data belonging to a certain logical unit is updated, the mapping relationship between the logical unit and the physical unit storing the old data belonging to the logical unit can be maintained.
When the memory storage device 10 leaves the factory, the total number of physical units belonging to the idle area 602 is a predetermined number (e.g., 30). In operation of the memory storage device 10, more and more physical units are selected from the inactive area 602 and associated with the memory area 601 to store data (e.g., user data from the host system 11). Thus, the total number of physical units belonging to the free area 602 may gradually decrease with the use of the memory storage device 10.
In operation of the memory storage device 10, the memory management circuit 502 can continuously update the total number of physical units belonging to the idle region 602. The memory management circuit 502 may perform a data merge operation based on the number of physical units in the free area 602 (i.e., the total number of free physical units). For example, the memory management circuit 502 can determine whether the total number of physical units belonging to the idle region 602 is less than or equal to a threshold (also referred to as a first threshold). The first threshold is, for example, 2 or greater (e.g., 10), and the present invention is not limited. If the total number of physical units belonging to the idle area 602 is less than or equal to the first threshold, the memory management circuit 502 may perform the data merging operation. In an example embodiment, the data consolidation operation is also referred to as a garbage collection (garbage collection) operation.
In a data merging operation, the memory management circuit 502 may select at least one entity unit from the memory area 601 as a source node. The memory management circuitry 502 may copy valid data from the selected entity unit (i.e., source node) to at least one entity unit that is a reclamation node. The entity units (i.e., reclamation nodes) used to store the copied valid data are selected from the free area 602 and are associated with the storage area 601. If valid data stored in a physical cell has been copied to the recovery node, the physical cell may be erased and associated with the spare area 602. In an exemplary embodiment, the re-association of a physical unit from the memory area 601 to the spare area 602 (or the erasing of a physical unit) is also referred to as releasing a spare physical unit. By performing the data merge operation, one or more idle physical units are released and the total number of physical units belonging to the idle region 602 is gradually increased.
After the data merging operation is started, if the entity units belonging to the idle area 602 meet a specific condition, the data merging operation may be stopped. For example, the memory management circuit 502 can determine whether the total number of physical units belonging to the idle region 602 is greater than or equal to a threshold (hereinafter also referred to as a second threshold). For example, the second threshold may be greater than or equal to the first threshold. If the total number of physical units belonging to the idle region 602 is greater than or equal to the second threshold, the memory management circuit 502 may stop the data merge operation. It should be noted that, stopping the data merging operation refers to ending the currently executing data merging operation. After stopping one data merging operation, if the total number of physical units belonging to the idle area 602 is again less than or equal to the first threshold value, the next data merging operation can be performed again to release new idle physical units.
Fig. 7A to 7C are schematic diagrams illustrating a data merging operation according to an exemplary embodiment of the present invention.
Referring to fig. 7A, in the data merging operation of the exemplary embodiment of the present invention, the memory management circuit 502 selects a plurality of physical units 710 (0) to 710 (3) from the physical units of the memory area 601 in the rewritable nonvolatile memory module 406 as the source node 701, and selects a physical unit 720 (0) (also referred to as at least one third physical unit 720 (0)) from the physical units of the idle area 602 as the recovery node 702. Specifically, in the present exemplary embodiment, the selected plurality of entity units 710 (0) -710 (3) includes entity units 710 (0) -710 (2) (also referred to as at least one first entity unit 710 (0) -710 (2)) having a relatively smaller data size of the valid data in the source node 701, and entity units 710 (3) (also referred to as at least one second entity unit 710 (3)) having a relatively larger data size of the valid data in the source node 701. In other words, the data size of the effective data in each of the at least one first physical unit 710 (0) to 710 (2) is smaller than the data size of the effective data in each of the at least one second physical unit 710 (3).
The memory management circuit 502 then reads mapping information (also referred to as first mapping information) shared by at least one first physical unit 710 (0) -710 (2) and at least one second physical unit 710 (3) from the rewritable nonvolatile memory module 406, wherein the first mapping information comprises mapping information of at least one first physical unit 710 (0) -710 (2) and mapping information of at least one second physical unit 710 (3). The memory management circuit 502 identifies the valid data in the at least one first entity unit 710 (0) to 710 (2) and the valid data in the at least one second entity unit 710 (3) according to the first mapping information, and indicates to collect the valid data 700A of the at least one first entity unit 710 (0) to 710 (2) and the at least one second entity unit 710 (3) as the source node 701, so as to save the valid data 700A in the buffer memory 510. The memory management circuit 502 may then instruct to write the valid data 700A to at least one third physical unit 720 (0) as the reclamation node 702. That is, the memory management circuit 502 copies the valid data collected from the at least one first physical unit 710 (0) to 710 (2) of the source node 701 and the valid data collected from the at least one second physical unit 710 (3) of the source node 701 to the at least one third physical unit 720 (0) of the reclamation node 702.
In an example embodiment, the memory management circuit 502 stops collecting valid data from the at least one second physical unit 710 (3) of the source node 701 and continues to collect valid data from the at least one first physical unit 710 (0) -710 (2) of the source node 701 when the data size of valid data copied from the at least one second physical unit 710 (3) of the source node 701 to the at least one third physical unit 720 (0) reaches the data size threshold. Specifically, the data size that can be accommodated by the at least one third entity unit 720 (0) of the recovery node 702 is a target data size, and the data size threshold is a remaining data size obtained by subtracting the total data size of the valid data in the at least one first entity units 710 (0) to 710 (2) from the target data size. In other words, in the data merging operation of the present invention, the memory management circuit 502 reserves enough space in the at least one third physical unit 720 (0) of the reclamation node 702 to enable the valid data in the at least one first physical unit 710 (0) to 710 (2) to be copied to the reclamation node 702, and only the valid data with the remaining data size in the at least one second physical unit 710 (3) to be copied to the reclamation node 702. That is, in the exemplary embodiment of the present invention, the data amount of the effective data collected from the at least one first entity unit 710 (0) to 710 (2) (also referred to as a first data amount) is equal to the total data amount of the effective data in the at least one first entity unit 710 (0) to 710 (2), the data amount of the effective data collected from the at least one second entity unit 710 (3) (also referred to as a second data amount) is smaller than the total data amount of the effective data in the at least one second entity unit 710 (3), and the sum of the first data amount and the second data amount is the size of the at least one third entity unit.
It should be noted that, in the operation that the memory management circuit 502 reads the first mapping information including the first physical units 710 (0) -710 (2) and the second physical unit 710 (3) from the rewritable nonvolatile memory module 406, the memory management circuit 502 obtains the first mapping information according to the table mapping information (also referred to as the first table mapping information) of the first physical units 710 (0) -710 (2) and the table mapping information (also referred to as the second table mapping information) of the second physical unit 710 (3). How to obtain the common mapping information between the entity units will be described below with reference to fig. 8.
Fig. 8 is a diagram illustrating table mapping information according to an exemplary embodiment of the present invention.
Referring to fig. 8, the table mapping information 801 corresponds to the entity unit 810 (0), and the table mapping information 802 corresponds to the entity unit 810 (1). The logical to physical mapping table 830 may be stored in the system area 603 of fig. 6. The logical-to-physical mapping table 830 includes a logical-to-physical mapping table TB 1 ～TB M . Logical to physical mapping table TB 1 ～TB M The method is used for recording logic-to-entity mapping information of at least one logic unit in a certain number range.
The table mapping information 801 reflects that the logical-to-physical mapping information of the logical unit mapped by the physical unit 810 (0) is stored in the logical-to-physical mapping table TB 1 ～TB M At least one of (2). The table mapping information 802 may reflect that the logical-to-physical mapping information of the logical unit mapped by the physical unit 810 (1) is stored in the logical-to-physical mapping table TB 1 ～TB M At least one of (2). For example, both table mapping information 801 and 802 may have bit b 1 ～b M . Bit b i The value of (1) may be 0 or 1 to reflect the logical-to-physical mapping table TB i Whether or not to be used. The value i is between 1 and M.
In an exemplary embodiment, assuming that physical unit 810 (0) is mapped to logical units 612 (1) and 612 (3) of FIG. 6, bit b in table mapping information 801 1 And b 3 The value of (1) may be 1 (the remaining bits may be 0) to reflect that the logical-to-physical mapping information of logical units 612 (1) and 612 (3) is recorded in logical-to-physical mapping table TB 1 With TB 3 . Logical to physical mapping table TB 1 With TB 3 May be loaded into the buffer memory 510 of fig. 5 to access the physical unit 810 (0). In addition, assuming that the physical unit 810 (1) is mapped to the logical units 612 (1), 612 (3) and 612 (8) of fig. 6, bit b in the table mapping information 802 1 、b 3 B 8 The value of (1) may be 1 (the remaining bits may be 0) to reflect that the logical-to-physical mapping information of the logical units 612 (1), 612 (3) and 612 (8) is recorded in the logical-to-physical mapping table TB 1 、TB 3 TB (TB) 8 . Logical to physical mapping table TB 1 、TB 3 TB (TB) 8 May be loaded into the buffer memory 510 to access the physical unit 810 (1).
In the foregoing exemplary embodiment, bit b in table mapping information 801 and 802 1 And b 3 Are all 1's representing the logical-to-physical mapping table TB of the multiple logical-to-physical mapping tables for accessing physical units 810 (0) and 810 (1) 1 With TB 3 Is repeated. When accessing the physical unit 810 (0), the logical-to-physical mapping table TB 1 With TB 3 May be loaded into the buffer memory 510 to query for relevant mapping information. Then, if the physical unit 810 (1) is accessed, only the additional loading of logic into the physical mapping table TB is required 8 。
In the example embodiment of fig. 7A, the memory management circuit 502 may obtain the first mapping information according to the first table mapping information corresponding to the at least one first entity unit 710 (0) to 710 (2) and the second table mapping information corresponding to the at least one second entity unit 710 (3). As shown in fig. 8, since the first table mapping information reflects what mapping information of at least one first entity unit is recorded in what logical-to-entity mapping table (also referred to as at least one first logical-to-entity mapping table), and the second table mapping information reflects what mapping information of at least one second entity unit is recorded in what logical-to-entity mapping table (also referred to as at least one second logical-to-entity mapping table), the first mapping information obtained by the first table mapping information and the second table mapping information reflects overlapping information between at least one first logical-to-entity mapping table and at least one second logical-to-entity mapping table, and the memory management circuit 502 can read the logical-to-entity mapping tables commonly used by the at least one first entity unit 710 (0) -710 (2) and the at least one second entity unit 710 (3) according to the overlapping information.
Fig. 9A to 9B are schematic diagrams illustrating obtaining a logical-to-physical mapping table according to mapping information according to an exemplary embodiment of the present invention.
The data consolidation operation of the present invention will be described in more detail below by way of example with reference to fig. 7A to 7C and fig. 9A to 9B. Referring to fig. 7A, in the operation of the memory management circuit 502 selecting at least one first entity unit 710 (0) -710 (2) and at least one second entity unit 710 (3) as the source node 701, it is assumed that the data size (i.e., the target data size) of the at least one third entity unit 720 (0) of the recovery node 702 is 100%, the data size of the effective data in the first entity unit 710 (0) of the selected source node 701 is 20% of the target data size, the data size of the effective data in the first entity unit 710 (1) is 20% of the target data size, the data size of the effective data in the first entity unit 710 (2) is 37% of the target data size, and the data size of the effective data in the second entity unit 710 (3) is 60% of the target data size, wherein the data size of the effective data in each at least one first entity unit 710 (0) -710 (2) is smaller than the data size of the effective data in each at least one second entity unit 710 (3).
The memory management circuit 502 reads the first mapping information including the at least one first physical unit 710 (0) -710 (2) and the at least one second physical unit 710 (3) from the rewritable nonvolatile memory module 406. Referring to fig. 7A and 9A, it is assumed that the table mapping information 910 (0) (also referred to as the first table mapping information 910 (0)) corresponds to the first entity unit 710 (0) and the tableMapping information 910 (1) (also referred to as first table mapping information 910 (1)) corresponds to first entity unit 710 (1), table mapping information 910 (2) (also referred to as first table mapping information 910 (2)) corresponds to first entity unit 710 (2), and table mapping information 910 (3) (also referred to as second table mapping information 910 (3)) corresponds to second entity unit 710 (3). The table mapping information 910 (0) to 910 (3) each has 16 bits. Bit b in first table mapping information 910 (0) 1 ～b 5 、b 9 、b 11 B 15 ～b 16 1, which reflects the logical-to-physical mapping table TB 1 ～TB 5 、TB 9 、TB 11 TB (TB) 15 ～TB 16 May be queried to access the first physical unit 710 (0). Bit b in first table mapping information 910 (1) 1 ～b 5 、b 9 B 16 1, which reflects the logical-to-physical mapping table TB 1 ～TB 5 、TB 9 TB (TB) 16 May be queried to access the first physical unit 710 (1). Bit b in first table mapping information 910 (2) 1 ～b 2 、b 4 ～b 6 B 15 1, which reflects the logical-to-physical mapping table TB 1 ～TB 2 、TB 4 ～TB 6 TB (TB) 15 May be queried to access the first physical unit 710 (2). Further, bit b in the second table mapping information 910 (3) 1 ～b 6 、b 9 、b 11 B 15 ～b 16 1, which reflects the logical-to-physical mapping table TB 1 ～TB 6 、TB 9 、TB 11 TB (TB) 15 ～TB 16 May be queried to access the second physical unit 710 (3). After OR operation is performed on the table mapping information 910 (0) -910 (3) by the logic module 90, the first mapping information 901 shared by at least one first entity unit 710 (0) -710 (2) and at least one second entity unit 710 (3) can be obtained, and the memory management circuit 502 can load the logic-to-entity mapping table TB shared by at least one first entity unit 710 (0) -710 (2) and at least one second entity unit 710 (3) according to the first mapping information 901 1 ～TB 6 、TB 9 、TB 11 TB (TB) 15 ～TB 16 。
Then, the memory management circuit 502 can determine the first mapping information 901 (or the logical-to-physical mapping table TB 1 ～TB 6 、TB 9 、TB 11 TB (TB) 15 ～TB 16 ) The collected valid data 700A from the at least one first physical unit 710 (0) -710 (2) and the at least one second physical unit 710 (3) of the source node 701 is copied to the at least one third physical unit 720 (0) of the reclamation node 702. Here, the valid data 700A includes valid data from at least one first entity unit 710 (0) to 710 (2) and valid data from at least one second entity unit 710 (3).
Specifically, in the exemplary embodiment of the present invention, when the data size of the valid data copied from the at least one second entity unit 710 (3) of the source node 701 to the at least one third entity unit 720 (0) of the recovery node 702 reaches the data size threshold, the memory management circuit 502 stops collecting valid data from the at least one second entity unit 710 (3) and continues collecting valid data from the at least one first entity unit 710 (0) to 710 (2). Specifically, the data size threshold is a remaining data size obtained by subtracting a total data size of the effective data in the at least one first entity unit 710 (0) to 710 (2) from a target data size (i.e., a data size that can be accommodated in the at least one third entity unit 720 (0)). In this example embodiment, the remaining data amount is 23% (i.e., 100% - (20% +20% + 37%) =23%), and the memory management circuit 502 sets the remaining data amount (i.e., 23%) to the data amount threshold value. In other words, when the data size of the valid data copied from the at least one second entity unit 710 (3) of the source node 701 to the at least one third entity unit 720 (0) of the recovery node 702 is 23% of the size of the at least one third entity unit 720 (0), the data size corresponding to the valid data copied from the at least one second entity unit 710 (3) to the at least one third entity unit 720 (0) reaches the data size threshold. At this time, the memory management circuit 502 will not collect valid data from the at least one second entity unit 710 (3).
Referring to fig. 7B, in the exemplary embodiment of the present invention, when the data size of the effective data copied from the at least one second entity unit 710 (3) to the at least one third entity unit 720 (0) reaches the data size threshold (i.e., 23%), the data size of the effective data remaining in the at least one second entity unit 710 (3) is reduced to 37% (i.e., 60% -23% = 37%) of the target data size. In particular, at this point in time, some of the valid data in at least one of the first physical units 710 (0) -710 (2) has also been copied into at least one of the third physical units 720 (0) of the recovery node 702. For example, the data amount of the effective data remaining in the first entity unit 710 (0) is reduced to 10% of the target data amount, the data amount of the effective data remaining in the first entity unit 710 (1) is reduced to 10% of the target data amount, and the data amount of the effective data remaining in the first entity unit 710 (2) is reduced to 27% of the target data amount.
As described above, when the data size of the valid data copied from the at least one second entity unit 710 (3) to the at least one third entity unit 720 (0) reaches the data size threshold (i.e., 23%), the memory management circuit 502 stops collecting valid data from the at least one second entity unit 710 (3) and continues collecting valid data from the at least one first entity unit 710 (0) to 710 (2). Therefore, as shown in fig. 7B, the memory management circuit 502 takes only at least one first physical unit 710 (0) to 710 (2) as the source node 701, and reads mapping information (also referred to as second mapping information) corresponding to only at least one first physical unit 710 (0) to 710 (2) from the rewritable nonvolatile memory module 406.
Referring to fig. 7B and fig. 9B, in the operation of the memory management circuit 502 reading the second mapping information corresponding to only the at least one first physical unit 710 (0) to 710 (2) from the rewritable nonvolatile memory module 406, part of the valid data in the at least one first physical unit 710 (0) to 710 (2) is copied to the at least one third physical unit 720 (0) of the recycling node 702. Therefore, the table mapping information of at least one first entity unit 710 (0) to 710 (2) is updated to the first table mapping information 910 (0) to 910 (2) as shown in fig. 9B. For example, the updated first table mapping information 910 (0) reflects the logical-to-entity mapping table TB 9 、TB 11 TB (TB) 15 ～TB 16 Can be queried to access the first entity unit 710 (0), the updated first table mapping information 910 (1) reflects the logical-to-entity mapping table TB 9 TB (TB) 16 Can be queried to access the first entity unit 710 (1), and the updated first table mapping information 910 (2) reflects the logical-to-entity mapping table TB 6 TB (TB) 15 May be queried to access the first physical unit 710 (2). Similarly, the memory management circuit 502 may perform an OR operation on the table mapping information 910 (0) to 910 (3) by the logic module 90 to obtain the second mapping information 902 of the at least one first entity unit 710 (0) to 710 (2), and the memory management circuit 502 may load only the logic-to-entity mapping table TB of the at least one first entity unit 710 (0) to 710 (2) according to the second mapping information 902 6 、TB 9 、TB 11 TB (TB) 15 ～TB 16 . It can be seen that the number of logical-to-physical mapping tables (i.e., the logical-to-physical mapping table TB) that the memory management circuit 502 needs to access before the data size of the valid data copied to the at least one third physical unit 720 (0) in the at least one second physical unit 710 (3) reaches the data size threshold is 10 1 ～TB 6 、TB 9 、TB 11 TB (TB) 15 ～TB 16 ) After the data size of the valid data copied to the at least one third physical unit 720 (0) in the at least one second physical unit 710 (3) reaches the data size threshold, the number of logical-to-physical mapping tables (i.e., the logical-to-physical mapping table TB) that the memory management circuit 502 needs to access is 5 6 、TB 9 、TB 11 TB (TB) 15 ～TB 16 )。
The memory management circuit 502 can then determine the second mapping information 902 (or the logical-to-physical mapping table TB 6 、TB 9 、TB 11 TB (TB) 15 ～TB 16 ) The valid data 700B collected from the at least one first physical unit 710 (0) -710 (2) of the source node 701 is copied to the at least one third physical unit 720 (0) of the reclamation node 702. Here, the valid data 700B includes valid data from at least one first entity unit 710 (0) to 710 (2).
Referring to fig. 7A to 7C, in an exemplary embodiment of the present invention, since the data volume threshold is a remaining data volume obtained by subtracting a total data volume of the valid data in the at least one first entity unit 710 (0) to 710 (2) from a data volume (i.e., a target data volume) that can be accommodated by the at least one third entity unit 720 (0) of the recovery node 702, a space corresponding to the remaining data volume in the at least one third entity unit 720 (0) is used for storing the valid data in the at least one second entity unit 710 (3), and thus a space other than the corresponding remaining data volume in the at least one third entity unit 720 (0) can just store all the valid data in the at least one first entity unit 710 (0) to 710 (2). That is, the effective data of 20% of the target data amount in the first entity unit 710 (0), the effective data of 20% of the target data amount in the first entity unit 710 (1), and the effective data of 37% of the target data amount in the first entity unit 710 (2) as shown in fig. 7A can be copied to at least one third entity unit 720 (0) of the recovery node 702 as shown in fig. 7C.
Fig. 10A to 10B are diagrams illustrating obtaining a logical-to-physical mapping table according to mapping information according to a conventional data merging operation.
The differences between the conventional data merging operation and the data merging operation of the present invention will be described with reference to fig. 7A and 10A to 10B. In the conventional data merging operation, the memory management circuit 502 performs a data merging operation on the entity units 710 (0) to 710 (2) storing less valid data in the source node 701 to copy the valid data in the entity units 710 (0) to 710 (2) storing less valid data to the entity unit 720 (0) of the recovery node 702. Next, the valid data is copied from the entity unit 710 (3) storing more valid data from the source node 701 to the remaining space of the entity unit 720 (0) in the reclamation node 702. Therefore, as shown in FIG. 10A, the memory management circuit 502 loads the logical-to-physical mapping tables TB of the physical units 710 (0) to 710 (2) based only on the mapping information 1001 of the physical units 710 (0) to 710 (2) 1 ～TB 6 、TB 9 、TB 11 TB (TB) 15 ～TB 16 And according to the logical-to-physical mapping table TB 1 ～TB 6 、TB 9 、TB 11 TB (TB) 15 ～TB 16 The valid data in each of the physical units 710 (0) through 710 (2) is copied to the physical unit 720 (0) of the reclamation node 702. Then, the memory management circuit 502 loads the logical-to-physical mapping table TB of the physical unit 710 (3) according to the mapping information 910 (3) of the physical unit 710 (3) storing more valid data 1 ～TB 6 、TB 9 、TB 11 TB (TB) 15 ～TB 16 And according to the logical-to-physical mapping table TB 1 ～TB 6 、TB 9 、TB 11 TB (TB) 15 ～TB 16 The valid data in entity unit 710 (3) is copied to the remaining space of entity unit 720 (0) in reclamation node 702. It can be seen that, in the case that the logical-to-physical mapping table used when accessing the entity units 710 (0) to 710 (2) storing less valid data and the logical-to-physical mapping table used when accessing the entity unit 710 (3) storing more valid data are repeated, the memory management circuit 502 performs two-stage operation of the conventional data merging operation, the number of logical-to-physical mapping tables to be accessed is 10 (i.e., the logical-to-physical mapping table TB 1 ～TB 6 、TB 9 、TB 11 TB (TB) 15 ～TB 16 ). However, in the foregoing exemplary embodiment of the present invention, after the data size of the effective data copied from the entity unit 710 (3) to the entity unit 720 (0) of the reclamation node 702 reaches the data size threshold, the number of logical-to-entity mapping tables required to be accessed by the memory management circuit 502 can be reduced to 5, which is less than 10 logical-to-entity mapping tables required to be accessed by the conventional data merging operation.
The following will describe in more detail the performance improvement of the memory storage device achieved by the data consolidation method of the present invention by reducing the number of logical-to-physical mapping tables that need to be loaded during the data consolidation operation, assuming that the memory management circuit 502 performs a round of data consolidation operations to process 1000 logical-to-physical mapping tables. Referring to fig. 7A to 7C again, in fig. 7A, it is assumed that the logical-to-physical mapping table required for accessing the valid data in the at least one first entity unit 710 (0) to 710 (2) is 6000 pieces, and the logical-to-physical mapping table required for accessing the valid data in the at least one second entity unit 710 (3) is also 6000 pieces repeated for this purpose, so that the number of logical-to-physical mappings shared by the at least one first entity unit 710 (0) to 710 (2) and the at least one second entity unit 710 (3) is 6000 pieces in the operation of the memory management circuit 502 reading the first mapping information shared by the at least one first entity unit 710 (0) to 710 (2) and the at least one second entity unit 710 (3) from the rewritable nonvolatile memory module 406. Next, the memory management circuit 502 copies the collected valid data 700A from the at least one first physical unit 710 (0) -710 (2) and the at least one second physical unit 710 (3) of the source node 701 to the at least one third physical unit 720 (0) of the reclamation node 702 according to the 6000 logical-to-physical mapping table. If the data size of the valid data copied from the at least one second physical unit 710 (3) of the source node 701 to the at least one third physical unit 720 (0) of the recovery node 702 reaches the data size threshold after the memory management circuit 502 finishes processing 3000 logical-to-physical mapping tables, the memory management circuit 502 performs 3 data merging operations, and only 3000 (6000-3000=3000) logical-to-physical mapping tables remain to be processed. In other words, in fig. 7B to 7C, the logic-to-physical mapping table of the memory management circuit 502 corresponding to the at least one first physical unit 710 (0) to 710 (2) read from the rewritable nonvolatile memory module 406 is the remaining 3000 pieces, so that the memory management circuit 502 can copy the remaining valid data in the at least one first physical unit 710 (0) to 710 (2) of the source node 701 to the at least one third physical unit 720 (0) of the recovery node 702 only by performing the data merging operation for 3 more times. That is, in this exemplary embodiment of the present invention, the memory management circuit 502 performs 6 data merging operations, i.e. copies all the valid data in the at least one first entity unit 710 (0) to 710 (2) of the source node 701 to the at least one third entity unit 720 (0) of the recovery node 702, and copies the valid data with the remaining data amount corresponding to the data amount threshold value in the at least one second entity unit 710 (3) to the at least one third entity unit 720 (0) of the recovery node 702.
In contrast, in the conventional data merging operation, under the above assumption, since the memory management circuit 502 can copy the valid data in the physical units 710 (0) to 710 (2) storing less valid data to the physical unit 720 (0) of the recovery node 702, the memory management circuit 502 performs the data merging operation on only the physical units 710 (0) to 710 (2) storing less valid data in the source node 701. That is, the memory management circuit 502 processes 6000 logical-to-physical mapping tables corresponding to the physical units 710 (0) to 710 (2) to copy all the valid data in the physical units 710 (0) to 710 (2) to the physical unit 720 (0) of the reclamation node 702, and this corresponds to the memory management circuit 502 performing 6 data merging operations. Thereafter, the memory management circuit 502 further processes 6000 pieces of the logical-to-physical mapping table corresponding to the physical unit 720 (0) to copy the valid data in the physical unit 710 (3) to the remaining space of the physical unit 720 (0) in the reclamation node 702. At this time, the memory management circuit 502 also performs 6 data merging operations. That is, in the conventional data merging method, the memory management circuit 502 performs 12 times of data merging operations in total.
Therefore, by the mechanism for setting the threshold value of the data quantity in the data merging operation, the number of the logic-to-entity mapping tables which need to be loaded in the data merging operation can be reduced, and the frequency of executing the data merging operation by the memory management circuit can be reduced under the condition that the number of the logic-to-entity mapping tables corresponding to the source node is huge and the repetition rate is high. Therefore, the number of accesses to the rewritable nonvolatile memory module 406 of fig. 4 can be effectively reduced, and the overall operation performance of the memory device can be further improved.
FIG. 11 is a flowchart of a method for merging data according to an exemplary embodiment of the present invention. Referring to fig. 11, in step S1101, the memory management circuit 502 selects at least one first physical unit and at least one second physical unit from the physical units. In step S1103, the memory management circuit 502 reads first mapping information from the rewritable non-volatile memory module, wherein the first mapping information includes mapping information of the at least one first entity unit and mapping information of the at least one second entity unit. In step S1105, the memory management circuit 502 copies the valid data collected from the at least one first entity unit and the valid data collected from the at least one second entity unit to at least one third entity unit of the entity units according to the first mapping information. In step S1107, when the data size of the valid data copied from the at least one second entity unit to the at least one third entity unit reaches the data size threshold, the memory management circuit 502 stops collecting valid data from the at least one second entity unit and continues collecting valid data from the at least one first entity unit.
However, the steps in fig. 11 are described in detail above, and will not be described again here. It should be noted that each step in fig. 11 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 11 may be used with the above exemplary embodiment, or may be used alone, which is not limited by the present invention.
In summary, in the exemplary embodiments of the present invention, the data merging method, the memory storage device and the memory control circuit unit set the data volume threshold to limit the data volume copied from the physical unit having a relatively large data volume of the valid data in the source node to the recovery node, so that the logical-to-physical mapping table used for accessing the source node in the data merging operation is not repeatedly read. In this way, the access times of the memory storage device in the data integration operation can be effectively reduced, and the service life of the memory storage device can be further prolonged. Particularly, under the condition that the number of the logic-to-entity mapping tables corresponding to the source node is huge and the repetition rate is high, the number of the logic-to-entity mapping tables required to be loaded in the data merging operation and the number of times of executing the data merging operation by the memory management circuit can be reduced by the data merging method, so that the overall operation efficiency of the memory storage device is improved.

Claims (21)

1. A data consolidation method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, the data consolidation method comprising:
selecting at least one first entity unit and at least one second entity unit from the plurality of entity units;
reading first mapping information from the rewritable non-volatile memory module, wherein the first mapping information comprises mapping information of the at least one first entity unit and mapping information of the at least one second entity unit;
copying the effective data collected from the at least one first entity unit and the effective data collected from the at least one second entity unit to at least one third entity unit of the plurality of entity units according to the first mapping information; and
and stopping collecting the effective data from the at least one second entity unit and continuing to collect the effective data from the at least one first entity unit when the data volume of the effective data copied from the at least one second entity unit to the at least one third entity unit reaches a data volume threshold value in the at least one third entity unit.
2. The data merging method according to claim 1, wherein the size of the at least one third entity unit is a target data amount, and the data amount threshold is a remaining data amount obtained by subtracting a total data amount of valid data in the at least one first entity unit from the target data amount.
3. The data consolidation method according to claim 1, wherein a first data amount of the valid data collected from the at least one first entity unit is equal to a total data amount of the valid data in the at least one first entity unit, and a second data amount of the valid data collected from the at least one second entity unit is smaller than the total data amount of the valid data in the at least one second entity unit.
4. The data merging method according to claim 3, wherein a sum of the first data amount and the second data amount is a size of the at least one third entity unit.
5. The data consolidation method according to claim 1, wherein the step after reading the first mapping information from the rewritable non-volatile memory module comprises:
and identifying the effective data in the at least one first entity unit and the effective data in the at least one second entity unit according to the first mapping information, wherein the data volume of the effective data in each at least one first entity unit is smaller than the data volume of the effective data in each at least one second entity unit.
6. The data consolidation method according to claim 1, wherein the step of stopping collecting valid data from the at least one second entity unit and continuing collecting valid data from the at least one first entity unit when the data amount of valid data copied from the at least one second entity unit to the at least one third entity unit reaches the data amount threshold value comprises:
reading second mapping information from the rewritable non-volatile memory module, wherein the second mapping information comprises mapping information of the at least one first entity unit; and
and copying the effective data collected from the at least one first entity unit to at least one third entity unit in the plurality of entity units according to the second mapping information.
7. The data consolidation method according to claim 1, wherein the first table mapping information reflects the mapping information of the at least one first physical unit is recorded in at least one first logical-to-physical mapping table, and the second table mapping information reflects the mapping information of the at least one second physical unit is recorded in at least one second logical-to-physical mapping table, wherein the step of reading the first mapping information from the rewritable non-volatile memory module comprises:
And reading the first mapping information according to the first table mapping information and the second table mapping information, wherein the first mapping information reflects overlapping information between the at least one first logic-to-entity mapping table and the at least one second logic-to-entity mapping table.
8. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units; and
a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is used for selecting at least one first entity unit and at least one second entity unit from the plurality of entity units,
the memory control circuit unit is further configured to read first mapping information from the rewritable nonvolatile memory module, wherein the first mapping information includes mapping information of the at least one first entity unit and mapping information of the at least one second entity unit,
the memory control circuit unit is further configured to copy the valid data collected from the at least one first entity unit and the valid data collected from the at least one second entity unit to at least one third entity unit of the plurality of entity units according to the first mapping information, and
The memory control circuit unit is further configured to stop collecting valid data from the at least one second entity unit and continue collecting valid data from the at least one first entity unit when an amount of valid data copied from the at least one second entity unit to the at least one third entity unit reaches a data amount threshold within the at least one third entity unit.
9. The memory storage device of claim 8, wherein the size of the at least one third entity unit is a target data amount and the data amount threshold is a remaining data amount obtained by subtracting a total data amount of valid data in the at least one first entity unit from the target data amount.
10. The memory storage device of claim 8, wherein a first amount of valid data collected from the at least one first entity unit is equal to a total amount of valid data in the at least one first entity unit and a second amount of valid data collected from the at least one second entity unit is less than the total amount of valid data in the at least one second entity unit.
11. The memory storage device of claim 10, wherein a sum of the first amount of data and the second amount of data is a size of the at least one third physical unit.
12. The memory storage device of claim 8, wherein the operation after reading the first mapping information from the rewritable non-volatile memory module comprises:
and identifying the effective data in the at least one first entity unit and the effective data in the at least one second entity unit according to the first mapping information, wherein the data volume of the effective data in each at least one first entity unit is smaller than the data volume of the effective data in each at least one second entity unit.
13. The memory storage device of claim 8, wherein stopping collecting valid data from the at least one second entity unit and continuing to collect valid data from the at least one first entity unit when an amount of valid data copied from the at least one second entity unit to the at least one third entity unit reaches the data amount threshold comprises:
reading second mapping information from the rewritable non-volatile memory module, wherein the second mapping information comprises mapping information of the at least one first entity unit; and
and copying the effective data collected from the at least one first entity unit to at least one third entity unit in the plurality of entity units according to the second mapping information.
14. The memory storage device of claim 8, wherein first table mapping information reflects mapping information of the at least one first physical unit is recorded in at least one first logical-to-physical mapping table, and second table mapping information reflects mapping information of the at least one second physical unit is recorded in at least one second logical-to-physical mapping table, wherein reading the first mapping information from the rewritable non-volatile memory module comprises:
and reading the first mapping information according to the first table mapping information and the second table mapping information, wherein the first mapping information reflects overlapping information between the at least one first logic-to-entity mapping table and the at least one second logic-to-entity mapping table.
15. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, wherein the memory control circuit unit comprises:
a host interface for connecting to a host system;
a memory interface to connect to the rewritable non-volatile memory module; and
A memory management circuit coupled to the host interface and the memory interface,
wherein the memory management circuit is used for selecting at least one first entity unit and at least one second entity unit from the plurality of entity units,
the memory management circuit is also configured to read first mapping information from the rewritable non-volatile memory module, wherein the first mapping information includes mapping information of the at least one first physical unit and mapping information of the at least one second physical unit,
the memory management circuit is further configured to copy the valid data collected from the at least one first entity unit and the valid data collected from the at least one second entity unit to at least one third entity unit of the plurality of entity units according to the first mapping information, and
the memory management circuit is further configured to stop collecting valid data from the at least one second entity unit and continue collecting valid data from the at least one first entity unit when an amount of valid data copied from the at least one second entity unit to the at least one third entity unit reaches a data amount threshold within the at least one third entity unit.
16. The memory control circuit unit of claim 15, wherein a size of the at least one third entity unit is a target data amount, and the data amount threshold is a remaining data amount obtained by subtracting a total data amount of valid data in the at least one first entity unit from the target data amount.
17. The memory control circuit unit of claim 15, wherein a first amount of valid data collected from the at least one first entity unit is equal to a total amount of valid data in the at least one first entity unit and a second amount of valid data collected from the at least one second entity unit is less than the total amount of valid data in the at least one second entity unit.
18. The memory control circuit unit of claim 17, wherein a sum of the first amount of data and the second amount of data is a size of the at least one third physical unit.
19. The memory control circuit unit of claim 15, wherein the operation after reading the first mapping information from the rewritable non-volatile memory module comprises:
and identifying the effective data in the at least one first entity unit and the effective data in the at least one second entity unit according to the first mapping information, wherein the data volume of the effective data in each at least one first entity unit is smaller than the data volume of the effective data in each at least one second entity unit.
20. The memory control circuit unit of claim 15, wherein stopping collecting valid data from the at least one second entity unit and continuing to collect valid data from the at least one first entity unit when an amount of valid data copied from the at least one second entity unit to the at least one third entity unit reaches the data amount threshold comprises:
reading second mapping information from the rewritable non-volatile memory module, wherein the second mapping information comprises mapping information of the at least one first entity unit; and
and copying the effective data collected from the at least one first entity unit to at least one third entity unit in the plurality of entity units according to the second mapping information.
21. The memory control circuit unit of claim 15, wherein the first table mapping information reflects mapping information of the at least one first physical unit is recorded in at least one first logical-to-physical mapping table, and the second table mapping information reflects mapping information of the at least one second physical unit is recorded in at least one second logical-to-physical mapping table, wherein the reading the first mapping information from the rewritable non-volatile memory module comprises:
And reading the first mapping information according to the first table mapping information and the second table mapping information, wherein the first mapping information reflects overlapping information between the at least one first logic-to-entity mapping table and the at least one second logic-to-entity mapping table.
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