CN110390985A - Storage management method, memory storage apparatus and memorizer control circuit unit - Google Patents

Storage management method, memory storage apparatus and memorizer control circuit unit Download PDF

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Publication number
CN110390985A
CN110390985A CN201810358395.0A CN201810358395A CN110390985A CN 110390985 A CN110390985 A CN 110390985A CN 201810358395 A CN201810358395 A CN 201810358395A CN 110390985 A CN110390985 A CN 110390985A
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data
unit
physical unit
count value
event
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CN201810358395.0A
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CN110390985B (en
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郭哲岳
李文晋
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits

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Abstract

Exemplary embodiment of the invention provides a kind of storage management method, memory storage apparatus and memorizer control circuit unit, and the storage management method is used for the memory storage apparatus including reproducible nonvolatile memorizer module.The described method includes: correspond to a write instruction from host system, it is whole and operate that data are executed at least one physical unit of reproducible nonvolatile memorizer module；And the dispersion of multiple logic units according to corresponding to the first data that the first kind physical unit in reproducible nonvolatile memorizer module is stored, adjustment execute the number that the data are whole and operate.

Description

Storage management method, memory storage apparatus and memorizer control circuit unit
Technical field
The present invention relates to a kind of memory management mechanism more particularly to a kind of storage management methods, memory storage dress It sets and memorizer control circuit unit.
Background technique
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, so that consumer is to storage The demand of media also rapidly increases.Due to reproducible nonvolatile memorizer module (rewritable non-volatile Memory module) (for example, flash memory) have data non-volatile, power saving, small in size, and without mechanical structure etc. Characteristic, so being very suitable to be built into above-mentioned illustrated various portable multimedia devices.
It is idle in memory storage apparatus with being increased using time and/or frequency of use for memory storage apparatus The number of physical unit can gradually decrease.When the number of idle physical unit is less than a preset number, memory storage apparatus It can start to execute garbage collection program.However, during executing garbage collection program, host system may be persistently to depositing Reservoir storage device assigns data write instruction.Therefore, during executing garbage collection program, memory storage apparatus Data write-in efficiency may fly up or decline, to influence the data write-in stability of memory storage apparatus.
Summary of the invention
The present invention provides a kind of storage management method, memory storage apparatus and memorizer control circuit unit, can have Stability is written in the data that effect improves memory storage apparatus.
One example of the present invention embodiment provides a kind of storage management method, is used to include that duplicative is non-volatile The memory storage apparatus of memory module, wherein the reproducible nonvolatile memorizer module includes multiple physics lists Member, at least first kind physical unit in the physical unit has the first data, and first data correspond to multiple patrol Collect unit.The storage management method includes: to correspond to the write instruction from host system, extremely to the physical unit At least a data are whole and operate for few one of them execution；And the logic unit according to corresponding to first data from Divergence, adjustment execute the number that the data are whole and operate.
In one example of the present invention embodiment, instruct corresponding to the said write from the host system to the object The one at least within execution data of reason unit are whole and include: to correspond to from the host system the step of operation Said write instruction, at least one access event is executed to the person of the physical unit.The access event includes data Reading event, data writing events and table read at least one of event.
In one example of the present invention embodiment, according to the logic unit corresponding to first data from Divergence adjustment execute the data it is whole and operate number the step of include: to obtain first event according to the dispersion to count Value；And correspond to the number of the access event of said write instruction execution according to first event count value adjustment.
In one example of the present invention embodiment, wrapped according to the step of dispersion acquisition first event count value It includes: being counted according to first event described in the valid data of the dispersion and first kind physical unit storage information acquisition Value.Storage state of the valid data storage message reflection valid data in the first kind physical unit.
In one example of the present invention embodiment, according to the dispersion and the first kind physical unit it is described effectively The step of data storage information acquisition first event count value includes: according to the dispersion, the first kind physics list Described in the valid data storage information of member and the number of at least one second class physical unit in the physical unit obtain First event count value.The not stored valid data of second class physical unit.
In one example of the present invention embodiment, wrapped according to the step of dispersion acquisition first event count value It includes: second event count value is obtained according to the dispersion, wherein the second event count value corresponds to for by the object The second class physical unit in reason unit writes the number of at least one full access event；And according to the second event count value Obtain the first event count value.
Another example of the present invention embodiment provides a kind of memory storage apparatus comprising connecting interface unit can answer Write formula non-volatile memory module and memorizer control circuit unit.The connecting interface unit is to be connected to host system System.The reproducible nonvolatile memorizer module includes multiple physical units.At least one first in the physical unit Class physical unit has the first data, and first data correspond to multiple logic units.The memorizer control circuit unit It is connected to the connecting interface unit and the reproducible nonvolatile memorizer module.The memorizer control circuit unit To correspond to the write instruction from the host system, indicate to execute at least the one at least within of the physical unit One data are whole and operate.The memorizer control circuit unit is also to the logic list according to corresponding to first data The dispersion of member, adjustment execute the number that the data are whole and operate.
In one example of the present invention embodiment, the memorizer control circuit unit, which corresponds to, comes from the host system Said write instruction to described in the physical unit at least within one execute the data it is whole and operate operation include: Corresponding to the said write instruction from the host system, indicate to execute at least one access to the person of the physical unit Event.The access event includes at least one that reading data event, data writing events and table read event.
In one example of the present invention embodiment, the memorizer control circuit unit is according to corresponding to first data The logic unit dispersion adjustment execute that the data are whole and the operation of number that operates include: according to it is described from Divergence obtains first event count value；And said write instruction execution is corresponded to according to first event count value adjustment The number of the access event.
In one example of the present invention embodiment, the memorizer control circuit unit is according to dispersion acquisition The operation of first event count value includes: to store information according to the valid data of the dispersion and the first kind physical unit Obtain the first event count value.The valid data storage message reflection valid data are in the first kind physical unit Storage state.
In one example of the present invention embodiment, the memorizer control circuit unit is according to the dispersion and described the The operation of first event count value described in the valid data storage information acquisition of a kind of physical unit include: according to it is described from At least one second class object in divergence, the valid data storage information of the first kind physical unit and the physical unit The number for managing unit obtains the first event count value.The not stored valid data of second class physical unit.
In one example of the present invention embodiment, the memorizer control circuit unit is according to dispersion acquisition The operation of first event count value includes: to obtain second event count value according to the dispersion, wherein the second event meter Numerical value corresponds to the number for the second class physical unit in the physical unit to be write at least one full access event；And The first event count value is obtained according to the second event count value.
Another example of the present invention embodiment provides a kind of memorizer control circuit unit, is used to control duplicative non- Volatile.The memorizer control circuit unit includes host interface, memory interface and memory management electricity Road.The host interface is to be connected to host system.The memory interface is non-volatile to be connected to the duplicative Property memory module.The reproducible nonvolatile memorizer module includes multiple physical units.In the physical unit An at least first kind physical unit has the first data, and first data correspond to multiple logic units.The memory pipe Circuit connection is managed to the host interface and the memory interface.The memory management circuitry is to correspond to from described The write instruction of host system, at least a data are whole and operate for the execution of one at least within of the instruction to the physical unit.Institute Dispersion of the memory management circuitry also to the logic unit according to corresponding to first data is stated, adjustment executes institute State the number that data are whole and operate.
In one example of the present invention embodiment, the dispersion of the logic unit, which is positively correlated with record, described The logic of one data to physical mapping information an at least table number.
In one example of the present invention embodiment, the memory management circuitry corresponds to the institute from the host system State write instruction to described in the physical unit at least within one execute the data it is whole and operate operation include: correspondence In the said write instruction from the host system, indicate to execute the person of the physical unit at least one access thing Part.The access event includes at least one that reading data event, data writing events and table read event.
In one example of the present invention embodiment, memory management circuitry institute according to corresponding to first data The dispersion adjustment for stating logic unit executes that the data are whole and the operation of number that operates includes: according to the dispersion Obtain first event count value；And corresponded to described in said write instruction execution according to first event count value adjustment The number of access event.
In one example of the present invention embodiment, the memory management circuitry obtains described first according to the dispersion The operation of event counter value includes: to store information acquisition according to the valid data of the dispersion and the first kind physical unit The first event count value.The valid data store message reflection valid data depositing in the first kind physical unit Storage state.
In one example of the present invention embodiment, the memory management circuitry is according to the dispersion and the first kind The operation of first event count value described in the valid data storage information acquisition of physical unit includes: according to described discrete Degree, the valid data storage information of the first kind physical unit and at least one second class physics in the physical unit The number of unit obtains the first event count value.The not stored valid data of second class physical unit.
In one example of the present invention embodiment, the memory management circuitry obtains described first according to the dispersion The operation of event counter value includes: to obtain second event count value according to the dispersion, wherein the second event count value Corresponding to the number for the second class physical unit in the physical unit to be write at least one full access event；And according to The second event count value obtains the first event count value.
It, can be to reproducible nonvolatile memorizer module corresponding to the write instruction from host system based on above-mentioned At least one physical unit to execute data whole and operate.In addition, according in reproducible nonvolatile memorizer module The dispersion of logic unit corresponding to the first data that a kind of physical unit is stored executes time that the data are whole and operate Number can be adjusted.Whereby, the data write-in stability of memory storage apparatus can be effectively improved.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is host system, memory storage apparatus and input shown by an exemplary embodiment according to the present invention/defeated The schematic diagram of (I/O) device out.
Fig. 2 is host system shown by another exemplary embodiment according to the present invention, memory storage apparatus and I/O dress The schematic diagram set.
Fig. 3 is the signal of host system and memory storage apparatus shown by another exemplary embodiment according to the present invention Figure.
Fig. 4 is the schematic block diagram of memory storage apparatus shown by an exemplary embodiment according to the present invention.
Fig. 5 is the schematic block diagram of memorizer control circuit unit shown by an exemplary embodiment according to the present invention.
Fig. 6 is management reproducible nonvolatile memorizer module shown by an exemplary embodiment according to the present invention Schematic diagram.
Fig. 7 is the signal that host write operation shown by an exemplary embodiment according to the present invention is whole with data and operates Figure.
Fig. 8 is physical unit shown by an exemplary embodiment according to the present invention and corresponding logic distribution information Schematic diagram.
Fig. 9 is logic distribution information shown by an exemplary embodiment according to the present invention and corresponding second event The schematic diagram of count value.
Figure 10 is the number of the second class physical unit shown by an exemplary embodiment according to the present invention and corresponding number According to the schematic diagram of operation mode that is whole and operating.
Figure 11 is the flow chart of storage management method shown by an exemplary embodiment according to the present invention.
Description of symbols
10,30: memory storage apparatus；
11,31: host system；
110: system bus；
111: processor；
112: random access memory；
113: read-only memory；
114: data transmission interface；
12: input/output (I/O) device；
20: motherboard；
201:U disk；
202: storage card；
203: solid state hard disk；
204: radio memory storage device；
205: GPS module；
206: network interface card；
207: radio transmitting device；
208: keyboard；
209: screen；
210: loudspeaker；
32:SD card；
33:CF card；
34: embedded storage device；
341: embedded multi-media card；
342: embedded type multi-core piece sealed storage device；
402: connecting interface unit；
404: memorizer control circuit unit；
406: reproducible nonvolatile memorizer module；
502: memory management circuitry；
504: host interface；
506: memory interface；
508: error checking and correcting circuit；
510: buffer storage；
512: electric power management circuit；
601: memory block；
602: idle area；
603: system area；
610 (0)~610 (C), 710 (0), 721 (0)~721 (E), 731 (0)~731 (F), 810 (0), 810 (1): object Manage unit；
612 (0)~612 (D): logic unit；
701,702,801~804,811~818: data；
720: source Nodes；
730: recycling node；
821 (0), 821 (1): logic distribution information；
910: form data；
S1101: step is (corresponding to a write instruction from host system, to type nonvolatile At least one physical unit execution data of module are whole and operate)；
S1102: step (stored according to the first kind physical unit in reproducible nonvolatile memorizer module The dispersion of multiple logic units corresponding to one data, adjustment execute the number that the data are whole and operate).
Specific embodiment
In general, memory storage apparatus (also referred to as, storage system) includes duplicative non-volatile memories Device module (rewritable non-volatile memory module) and controller (also referred to as, control circuit).It is commonly stored Device storage device is used together with host system, so that host system can write data into memory storage apparatus or from depositing Data are read in reservoir storage device.
Fig. 1 is host system, memory storage apparatus and input shown by an exemplary embodiment according to the present invention/defeated The schematic diagram of (I/O) device out.Fig. 2 is that host system shown by another exemplary embodiment according to the present invention, memory are deposited The schematic diagram of storage device and I/O device.
Fig. 1 and Fig. 2 are please referred to, host system 11 generally comprises processor 111, random access memory (random Access memory, RAM) 112, read-only memory (read only memory, ROM) 113 and data transmission interface 114.Place Reason device 111, random access memory 112, read-only memory 113 and data transmission interface 114 are all connected to system bus (system bus)110。
In this exemplary embodiment, host system 11 is connected by data transmission interface 114 and memory storage apparatus 10 It connects.For example, host system 11 can store data to memory storage apparatus 10 or from memory via data transmission interface 114 Data are read in storage device 10.In addition, host system 11 is to be connect by system bus 110 with I/O device 12.For example, main Output signal can be sent to I/O device 12 via system bus 110 or receive input signal from I/O device 12 by machine system 11.
In this exemplary embodiment, processor 111, random access memory 112, read-only memory 113 and data transmission Interface 114 may be provided on the motherboard 20 of host system 11.The number of data transmission interface 114 can be one or more.It is logical Data transmission interface 114 is crossed, motherboard 20 can be connected to memory storage apparatus 10 via wired or wireless way.Memory Storage device 10 can be for example USB flash disk 201, storage card 202, solid state hard disk (Solid State Drive, SSD) 203 or wirelessly deposit Reservoir storage device 204.Radio memory storage device 204 can be for example close range wireless communication (Near Field Communication, NFC) memory storage apparatus, radio facsimile (WiFi) memory storage apparatus, bluetooth (Bluetooth) Memory storage apparatus or low-power consumption bluetooth memory storage apparatus (for example, iBeacon) etc. are with various wireless communication technique The memory storage apparatus on basis.In addition, motherboard 20 can also be connected to global positioning system by system bus 110 (Global Positioning System, GPS) module 205, network interface card 206, radio transmitting device 207, keyboard 208, The various I/O device such as screen 209, loudspeaker 210.For example, motherboard 20 can pass through radio transmitting device in an exemplary embodiment 207 access wireless memory storage apparatus 204.
In an exemplary embodiment, mentioned host system is substantially to cooperate with memory storage apparatus to store The arbitrary system of data.Although host system is explained with computer system, however, Fig. 3 is in above-mentioned exemplary embodiment The schematic diagram of host system and memory storage apparatus shown by another exemplary embodiment according to the present invention.Referring to figure 3., In another exemplary embodiment, host system 31 is also possible to digital camera, video camera, communication device, audio player, video The systems such as player or tablet computer, and memory storage apparatus 30 can be its used secure digital (Secure Digital, SD) card 32, compact flash (Compact Flash, CF) block 33 or embedded storage device 34 etc. it is various non-volatile Property memory storage apparatus.Embedded storage device 34 includes embedded multi-media card (embedded Multi Media Card, eMMC) 341 and/or embedded type multi-core piece encapsulate (embedded Multi Chip Package, eMCP) storage device The all types of embedded storage devices being directly connected in memory module on the substrate of host system such as 342.
Fig. 4 is the schematic block diagram of memory storage apparatus shown by an exemplary embodiment according to the present invention.
Referring to figure 4., memory storage apparatus 10 include connecting interface unit 402, memorizer control circuit unit 404 with Reproducible nonvolatile memorizer module 406.
Connecting interface unit 402 is to be connected to host system 11 for memory storage apparatus 10.In this exemplary embodiment In, connecting interface unit 402 is to be compatible to Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not limited thereto, and connecting interface unit 402 is also possible to Meet parallel advanced technology annex (Parallel Advanced Technology Attachment, PATA) standard, it is electrical and Electronic Engineering Association (Institute of Electrical and Electronic Engineers, IEEE) 1394 marks Quasi-, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, SD interface standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II, UHS-II) interface Standard, MCP interface standard, MMC interface standard, eMMC interface standard, is led at memory stick (Memory Stick, MS) interface standard With flash memory (Universal Flash Storage, UFS) interface standard, eMCP interface standard, CF interface standard, whole Box-like driving electrical interface (Integrated Device Electronics, IDE) standard or other suitable standards.Connection Interface unit 402 can be encapsulated in memorizer control circuit unit 404 in a chip or connecting interface unit 402 is cloth Outside a chip comprising memorizer control circuit unit 404.
Memorizer control circuit unit 404 is to execute multiple logic gates or control with hardware pattern or Solid form implementation System instructs and carries out writing for data in reproducible nonvolatile memorizer module 406 according to the instruction of host system 11 The running such as enter, read and erase.
Reproducible nonvolatile memorizer module 406 is to be connected to memorizer control circuit unit 404 and to deposit The data that storage host system 11 is written.Reproducible nonvolatile memorizer module 406 can be single-order storage unit (Single Level Cell, SLC) NAND type flash memory module is (that is, can store 1 bit in a storage unit Flash memory module), multi-level cell memory (Multi Level Cell, MLC) NAND type flash memory module is (that is, one The flash memory module of 2 bits can be stored in a storage unit), Complex Order storage unit (Triple Level Cell, TLC) NAND type flash memory module (that is, flash memory module that 3 bits can be stored in a storage unit), other Flash memory module or other memory modules with the same characteristics.
Each of reproducible nonvolatile memorizer module 406 storage unit (is hereinafter also referred to faced with voltage Boundary's voltage) change store one or more bits.Specifically, the control grid (control of each storage unit Gate) there is an electric charge capture layer between channel.By bestowing a write-in voltage to controlling grid, thus it is possible to vary charge benefit is caught The amount of electrons of layer, and then change the critical voltage of storage unit.This change storage unit critical voltage operation be also referred to as " Data are written to storage unit " or " sequencing (programming) storage unit ".With the change of critical voltage, can make carbon copies Each of formula non-volatile memory module 406 storage unit has multiple storage states.It can by bestowing reading voltage To judge a storage unit is which storage state belonged to, one or more ratios that this storage unit is stored are obtained whereby It is special.
In this exemplary embodiment, the storage unit of reproducible nonvolatile memorizer module 406 can constitute multiple objects Programmed cell is managed, and these physical procedures units can constitute multiple physical erase units.Specifically, same wordline On storage unit can form one or more physical procedures units.If each storage unit can store 2 or more bits, Then the physical procedures unit in same wordline can at least be classified as lower physical procedures unit and upper physical procedures list Member.For example, the minimum effective bit (Least Significant Bit, LSB) of a storage unit is to belong to lower physical procedures Unit, and the highest significant bit (Most Significant Bit, MSB) of a storage unit is to belong to physical procedures Unit.In general, in MLC NAND type flash memory, the writing speed of lower physical procedures unit can be greater than upper physics What the reliability of the writing speed of programmed cell and/or lower physical procedures unit was above physical procedures unit can By degree.
In this exemplary embodiment, physical procedures unit is the minimum unit of sequencing.That is, physical procedures unit is The minimum unit of data is written.For example, physical procedures unit is physical page (page) or physics fan (sector).If object Reason programmed cell is physical page, then these physical procedures units generally include data bit area and redundancy (redundancy) bit area.Data bit area is fanned comprising multiple physics, and to store user's data, and redundancy ratio special zone is used With memory system data (for example, error correcting code etc. manages data).In this exemplary embodiment, data bit area includes 32 Physics fan, and the size of physics fan is 512 bytes (byte, B).However, in other exemplary embodiments, data bit area In also may include 8,16 or number more or fewer physics fan, and the size of each physics fan be also possible to it is bigger Or it is smaller.On the other hand, physical erase unit is the minimum unit erased.That is, each physical erase unit contains minimum number The storage unit of mesh being erased together.For example, physical erase unit is physical blocks (block).
Fig. 5 is the schematic block diagram of memorizer control circuit unit shown by an exemplary embodiment according to the present invention.
Referring to figure 5., memorizer control circuit unit 404 includes memory management circuitry 502, host interface 504 and deposits Memory interface 506.
Overall operation of the memory management circuitry 502 to control memorizer control circuit unit 404.Specifically, it deposits Reservoir, which manages circuit 502, has multiple control instructions, and when memory storage apparatus 10 operates, these control instructions can quilt It executes the running such as to carry out the write-in of data, read and erase.It is equivalent when illustrating the operation of memory management circuitry 502 below In the operation for illustrating memorizer control circuit unit 404.
In this exemplary embodiment, the control instruction of memory management circuitry 502 is to carry out implementation with Solid form.For example, Memory management circuitry 502 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to Order is programmed in so far read-only memory.When memory storage apparatus 10 operates, these control instructions can be by microprocessor Unit is executed the running such as to carry out the write-in of data, read and erase.
In another exemplary embodiment, the control instruction of memory management circuitry 502 can also be stored in procedure code pattern The specific region of reproducible nonvolatile memorizer module 406 is (for example, be exclusively used in storage system data in memory module System area) in.In addition, memory management circuitry 502 have microprocessor unit (not shown), read-only memory (not shown) and Random access memory (not shown).In particular, this read-only memory has boot code (boot code), and work as memory When control circuit unit 404 is enabled, microprocessor unit can first carry out this boot code, and will to be stored in duplicative non-volatile Control instruction in property memory module 406 is loaded into the random access memory of memory management circuitry 502.Later, micro- Processor unit such as can operate these control instructions to carry out the write-in of data, read and erase at the running.
In addition, the control instruction of memory management circuitry 502 can also be come in another exemplary embodiment with a hardware pattern Implementation.For example, memory management circuitry 502 includes microcontroller, Storage Unit Management circuit, memory write circuit, storage Device reading circuit, memory are erased circuit and data processing circuit.Storage Unit Management circuit, memory write circuit, storage Device reading circuit, memory erase circuit and data processing circuit is to be connected to microcontroller.Storage Unit Management circuit to Manage storage unit or its group of reproducible nonvolatile memorizer module 406.Memory write circuit is to can answer It writes formula non-volatile memory module 406 and assigns write instruction sequence to write data into type nonvolatile In module 406.Memory reading circuitry to reproducible nonvolatile memorizer module 406 assign read instruction sequence with Data are read from reproducible nonvolatile memorizer module 406.Memory erases circuit to non-volatile to duplicative Property memory module 406, which is assigned, erases instruction sequence so that data to be erased from reproducible nonvolatile memorizer module 406. Data processing circuit is intended to be written data to reproducible nonvolatile memorizer module 406 and from duplicative to handle The data read in non-volatile memory module 406.Write instruction sequence reads instruction sequence and instruction sequence of erasing can be each It Bao Kuo not one or more procedure codes or instruction code and to indicate that reproducible nonvolatile memorizer module 406 executes relatively The write-in answered such as reads and erases at the operation.In an exemplary embodiment, memory management circuitry 502 can also assign other classes The instruction sequence of type indicates to execute corresponding operation to reproducible nonvolatile memorizer module 406.
Host interface 504 is to be connected to memory management circuitry 502 and passed to receive with identification host system 11 The instruction and data sent.That is, the instruction that host system 11 is transmitted can be sent to data by host interface 504 Memory management circuitry 502.In this exemplary embodiment, host interface 504 is to be compatible to SATA standard.However, it is necessary to understand Be that the invention is not limited thereto, host interface 504 is also possible to be compatible to PATA standard, 1394 standard of IEEE, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS mark Standard, CF standard, IDE standard or other suitable data transmission standards.
Memory interface 506 is to be connected to memory management circuitry 502 and duplicative is non-volatile to be deposited to access Memory modules 406.It can be via memory to the data of reproducible nonvolatile memorizer module 406 that is, being intended to be written Interface 506 is converted to the 406 receptible format of institute of reproducible nonvolatile memorizer module.Specifically, if memory pipe Reason circuit 502 will access reproducible nonvolatile memorizer module 406, and memory interface 506 can transmit corresponding sequence of instructions Column.For example, these instruction sequences may include the reading sequence of instructions of the write instruction sequence of instruction write-in data, instruction reading data Column, instruction erase data erase instruction sequence and to indicate various storage operations (for example, change read voltage electricity It is flat or execute garbage collection operations etc.) corresponding instruction sequence.These instruction sequences are, for example, by memory management electricity Road 502 generates and is sent to reproducible nonvolatile memorizer module 406 by memory interface 506.These sequence of instructions Column may include one or more signals, or the data in bus.These signals or data may include instruction code or procedure code.Example Such as, in reading instruction sequence, the information such as identification code, the storage address of reading be will include.
In an exemplary embodiment, memorizer control circuit unit 404 further includes error checking and correcting circuit 508, delays Rush memory 510 and electric power management circuit 512.
Error checking and correcting circuit 508 be connected to memory management circuitry 502 and to execute error checking with Correct operation is to ensure the correctness of data.Specifically, it is write when memory management circuitry 502 is received from host system 11 When entering to instruct, error checking can generate corresponding error correcting code with correcting circuit 508 for the data of this corresponding write instruction (error correcting code, ECC) and/or error checking code (error detecting code, EDC), and store Device management circuit 502 data of this corresponding write instruction and corresponding error correcting code and/or error checking code can be written to In reproducible nonvolatile memorizer module 406.Later, when memory management circuitry 502 is deposited from duplicative is non-volatile The corresponding error correcting code of this data and/or error checking code can be read when reading data in memory modules 406 simultaneously, and wrong Erroneous detection, which is looked into, can execute mistake inspection to read data according to this error correcting code and/or error checking code with correcting circuit 508 It looks into and correct operation.
Buffer storage 510 is connected to memory management circuitry 502 and is configured to temporarily store from host system 11 Data and instruction or the data from reproducible nonvolatile memorizer module 406.Electric power management circuit 512 is to be connected to Memory management circuitry 502 and the power supply to control memory storage apparatus 10.
Fig. 6 is management reproducible nonvolatile memorizer module shown by an exemplary embodiment according to the present invention Schematic diagram.
Fig. 6 is please referred to, memory management circuitry 502 can be by the physics list of reproducible nonvolatile memorizer module 406 First 610 (0)~610 (C) are logically grouped to memory block 601, idle area (spare) 602 and system area 603.In memory block 601 Physical unit 610 (0)~610 (A) be stored with data.For example, physical unit 610 (0)~610 (A) in memory block 601 can Store effectively (valid) data and invalid (invalid) data.Physical unit 610 (A+1)~610 (B) in idle area 602 Not yet it is used to storing data (such as valid data).Physical unit 610 (B+1)~610 (C) in memory block 601 is to store System data, such as logic is to physical mappings table, bad block management table, device model or other kinds of management data.
When being intended to storing data, memory management circuitry 502 can be from the physical unit 610 (A+1)~610 in idle area 602 (B) one physical unit of selection and by at least number of a physical unit from host system 11 or in memory block 601 in According to storing into selected physical unit.Meanwhile selected physical unit can be associated to memory block 601.In addition, being deposited erasing After some physical unit in storage area 601, the physical unit erased can be associated with again to idle area 602.
In this exemplary embodiment, each physical unit for belonging to memory block 601 is also referred to as non-idle (non-spare) Physical unit or first kind physical unit, and the also referred to as idle physical unit of each physical unit that belongs to idle area 602 or Second class physical unit.In this exemplary embodiment, a physical unit refers to a physical erase unit.However, another In exemplary embodiment, a physical unit also may include multiple physical erase units.
The meeting of memory management circuitry 502 configuration logic unit 612 (0)~612 (D) is with the physics in mapped memory region 601 Unit 610 (0)~610 (A).In this exemplary embodiment, each logic unit refers to a logical address.However, another In one exemplary embodiment, a logic unit may also mean that a logical program unit, a logic erased cell or It is made of multiple continuous or discontinuous logical addresses.In addition, each of logic unit 612 (0)~612 (D) can be reflected It is incident upon one or more physical units.It is noted that memory management circuitry 502, which can not configure, maps to patrolling for system area 603 Unit is collected, to prevent the system data for being stored in system area 603 from being modified by user.
Memory management circuitry 502 can be by mapping relations (the also referred to as logic to object between logic unit and physical unit Reason map information) an at least logic is recorded in physical mappings table.Logic is stored in the object of system area 603 to physical mappings table It manages in unit 610 (B+1)~610 (C).When host system 11 is intended to read data from memory storage apparatus 10 or writes data to When memory storage apparatus 10, memory management circuitry 502 can be executed to physical mappings table for memory according to this logic The data access operation of storage device 10.
In this exemplary embodiment, valid data are the latest datas for belonging to some logic unit, and invalid data is then It is not the latest data for belonging to any one logic unit.For example, if host system 11 stores a new data to a certain logic Unit and override the legacy data (that is, updating the data for belonging to this logic unit) that this logic unit originally stored, then store to This new data in memory block 601 is to belong to the latest data of this logic unit and can be marked as effectively, and be coated The legacy data that lid falls may be still stored in memory block 601 but be marked as in vain.
In this exemplary embodiment, if the data for belonging to a certain logic unit are updated, this logic unit be stored with The mapping relations belonged between the physical unit of the legacy data of this logic unit can be removed, and this logic unit be stored with The mapping relations belonged between the physical unit of the latest data of this logic unit can be established.However, implementing in another example In example, if the data for belonging to a certain logic unit are updated, this logic unit and it is stored with the old number for belonging to this logic unit According to physical unit between mapping relations can still be maintained.
When memory storage apparatus 10 dispatches from the factory, the sum for the physical unit for belonging to idle area 602 can be a present count Mesh (for example, 30).In the running of memory storage apparatus 10, more and more physical units can be selected from idle area 602 And memory block 601 is associated to storing data (for example, user's data from host system 11).Therefore, belong to the spare time The sum for setting the physical unit in area 602 can be gradually decreased with the use of memory storage apparatus 10.
In the running of memory storage apparatus 10, the meeting continuous updating of memory management circuitry 502 belongs to idle area 602 The sum of physical unit.Memory management circuitry 502 can be according to the number of physical unit in area 602 of leaving unused (that is, idle physics list The sum of member) data of execution at least once are whole and operate.For example, memory management circuitry 502 can determine whether to belong to idle area 602 Physical unit sum whether be less than or equal to a threshold value (also referred to as the first threshold value).This first threshold value is, for example, 2 or bigger value (for example, 10), the present invention is without restriction.If the sum for the physical unit for belonging to idle area 602 be less than or Equal to the first threshold value, it is whole and operate that data can be performed in memory management circuitry 502.In an exemplary embodiment, data are whole simultaneously Operation is also referred to as garbage collection (garbage collection) operation.
In and operation whole in data, memory management circuitry 502 can select at least one physical unit from memory block 601 (also referred to as source Nodes) and attempt by valid data from selected physical unit concentration copy to another physical unit ( Referred to as recycle node).It is then selection and meeting quilt from idle area 602 for storing the physical unit of replicated valid data It is associated with to memory block 601.If the valid data that some physical unit is stored all have been copied to recycling node, this physics Unit can be erased and be associated to idle area 602.In an exemplary embodiment, by some physical unit from memory block 601 operations (or the operation for some physical unit of erasing) for being associated with go back to idle area 602 again also referred to as discharge a unused material Manage unit.Whole and operate by executing data, one or more idle physical units can be released and to belong to idle area 602 The sum of physical unit gradually increase.
Start execute data it is whole and operate after, if the physical unit for belonging to idle area 602 meets a specified conditions, data It is whole and operate and can stop.For example, memory management circuitry 502 can determine whether the physical unit for belonging to idle area 602 sum whether More than or equal to one threshold value (hereinafter also referred to the second threshold value).For example, the second threshold value can be greater than or equal to first Threshold value.If the sum for belonging to the physical unit in idle area 602 is greater than or equal to the second threshold value, memory management circuitry 502 It is whole and operate can to stop data.It is noted that stopping data are whole and operation refers to that the current data in execution of end are whole and grasp Make.Stopping, a data are whole and after operating, if belong to the sum of the physical unit in idle area 602 again less than or be equal to the One threshold value, then next data are whole and operate and can be performed again, to attempt the idle physical unit of release new.
Fig. 7 is the signal that host write operation shown by an exemplary embodiment according to the present invention is whole with data and operates Figure.Fig. 7 is please referred to, in host write operation, host system 11 can send at least one write instruction to indicate data 701 It is written to some logic unit.According to this write instruction, data 701 can be stored to the physics list for mapping so far logic unit First 710 (0).It is selected from the idle area 602 of Fig. 6 for example, physical unit 710 (0) can be.In an exemplary embodiment, when The preceding physical unit 710 (0) for being used to store the data 701 from host system 11 also referred to as opens block (open block). It is noted that a unlatching block also may include multiple physical units in another exemplary embodiment.
When executing host write operation, at least one data is whole and operates and can be performed.It is whole in data and operate In, physical unit 721 (0)~721 (E) that data 702 can be subordinated to source Nodes 720 are collected and are written into belonging to back Receive physical unit 731 (0)~731 (F) of node 730.Data 702 are valid data.Belong to the physical unit of source Nodes 720 721 (0)~721 (E) are physical unit 731 (0)~731 for selecting from the memory block of Fig. 6 601, and belonging to recycling node 730 It (F) is selected from the idle area 602 of Fig. 6.In an exemplary embodiment, physical unit 721 (0)~721 (E) is depositing for Fig. 6 E+1 physical unit of minimum valid data is stored in storage area 601.In an exemplary embodiment, physical unit 721 (0)~721 It (E) is to be selected from the memory block of Fig. 6 601 according to other rules, the present invention is without restriction.
In an exemplary embodiment, memory management circuitry 502 can obtain reproducible nonvolatile memorizer module 406 In first kind physical unit logic distribution information.For example, memory management circuitry 502, which can be analyzed, is stored in the first kind Logic unit belonging to data (also referred to as the first data) in physical unit is distributed with the logic for obtaining first kind physical unit Status information.The logic distribution information of first kind physical unit can reflect the first number being stored in first kind physical unit According to the dispersion of corresponding multiple logic units.
In an exemplary embodiment, the first data refer at least a part of significant figure for being stored in first kind physical unit According to.Therefore, the dispersion of logic unit corresponding to the first data, which can reflect, is stored at least one of first kind physical unit The degree of scatter (i.e. dispersion) of multiple logic units belonging to the valid data of part.For example, if being stored in first kind physics list Multiple logic units belonging to the valid data of member are that more dispersed (such as valid data are largely to correspond to multiple not connect Continuous logic unit), then it can determine that the dispersion of logic unit corresponding to the first data is higher.Alternatively, if being stored in first Multiple logic units belonging to the valid data of class physical unit be more concentrate (such as valid data largely correspond to Multiple continuous logic units), then it can determine that the dispersion of logic unit corresponding to the first data is lower.
In an exemplary embodiment, according to the dispersion of logic unit corresponding to the first data, memory management circuitry 502 can get and operating efficiency of operation relevant information whole to the data executed for first kind physical unit.For example, according to The dispersion of logic unit corresponding to first data, memory management circuitry 502 can get an assessed value.This assessed value is visual For first kind physical unit logic distribution information and to indicate the dispersion.In an exemplary embodiment, this Assessed value can reflect that record has the number of an at least table for the access information of the first data.For example, this assessed value can be positively correlated In the number of the table.For example, this is commented if record has the number of an at least table for the access information of the first data more Valuation can be bigger.Alternatively, memory management circuitry 502 can have the access of the first data to believe according to record from the point of view of another angle An at least table for breath obtains this assessed value.
In an exemplary embodiment, the access information of the first data includes the logic of the first data to physical mapping information. In an exemplary embodiment, logic to the physical mappings table for being stored in the system area 603 of Fig. 6 may be partitioned into multiple sublists, and record Record a sublist for having a table of the access information of the first data that can refer to logic to physical mappings table.Logic is to physics Each sublist of mapping table can record the logics of multiple continuous logic units in some logic scope to physical mappings Information.
In an exemplary embodiment, the dispersion of logic unit corresponding to the first data, which is positively correlated with record, the first number According to logic to physical mapping information an at least table number.For example, if the logic of the first data is to physical mapping information Logic is recorded in into multiple sublists of physical mappings table, then the dispersion of logic unit corresponding to the first data can be positively correlated In the sum of these sublists.
In an exemplary embodiment, if corresponding to logic distribution the first data of message reflection of first kind physical unit Logic unit dispersion it is higher (i.e. logic unit belonging to the first data is more dispersed or discontinuous), then the first data institute The logic of the logic unit of category to physical mapping information may be dispersedly recorded in multiple sublists.Therefore, to the first data It is whole and when operating to execute data, it may be necessary to execute more multiple table accessing operation with the sublist by logic to physical mappings table It is loaded into buffer storage (such as buffer storage 510 of Fig. 5).The sublist for being loaded into buffer storage can be used for inquiring first The access information of data.In this situation, due to needing to be implemented more multiple table accessing operation, normally to the first data (or first kind physical unit) execute data it is whole and operate may result in data it is whole and operate operating efficiency it is low.
On the contrary, if logic unit corresponding to logic distribution the first data of message reflection of first kind physical unit Dispersion it is lower (i.e. logic unit belonging to the first data more concentrate or continuous), then logic unit belonging to the first data Being recorded in a small number of sublists of may more concentrating of logic to physical mapping information.Therefore, data are being executed to the first data Whole and when operating, may only need to be implemented a small number of table accessing operations several times can inquire the access information of the first data, from And data it is whole and operate operating efficiency it is often higher.It follows that being distributed shape in the logic for not considering first kind physical unit State information and/or data are whole and in operating in the case where the table accessing operation that may need to be implemented, and data are whole and the behaviour that operates The data write-in stability for making efficiency and memory storage apparatus is not easily controlled.
Fig. 8 is physical unit shown by an exemplary embodiment according to the present invention and corresponding logic distribution information Schematic diagram.Please refer to Fig. 8, it is assumed that be stored with data 801~804 in physical unit 810 (0), deposit in physical unit 810 (1) Data 811~818 are contained, and data 801~804 and 811~818 are all valid data.Logic distribution information 821 (0) For the logic distribution information of physical unit 810 (0).Logic distribution information 821 (1) is patrolling for physical unit 810 (1) Collect distribution information.Each of table 001~005 and 011~018 is a sublist of the logic to physical mappings table.
According to logic distribution information 821 (0), the logic of an at least logic unit belonging to data 801,803 and 804 It is to be recorded in table 001,004 and 005, and an at least logic unit belonging to data 802 is patrolled respectively to physical mapping information Collecting to physical mapping information is to be recorded in table 002 and 003.According to logic distribution information 821 (0), for physics list The data of first 810 (0) are whole and operate, and 5 tables (i.e. table 001~005) can be loaded on buffer storage to provide number According to 801~804 access information (such as logic to physical mapping information).For example, data 801 are copied to some recycling When node, table 001 can be loaded on buffer storage to obtain according to the logic corresponding to data 801 to physical mapping information Obtain the physical unit 810 (0) for being currently stored with data 801.In other words, the table sum in logic distribution information 821 (0) 5 can be used for obtaining the assessed value for corresponding to physical unit 810 (0) and can be used to indicate fully to move or replicate data 801 ~804 need to read at least five table 001~005.
Similarly, according to logic distribution information 821 (1), the logic of logic unit belonging to data 811~818 is extremely Physical mapping information is recorded in table 011~018 respectively.According to logic distribution information 821 (1), for physical unit The data of 810 (1) are whole and operate, at least N number of table (i.e. table 011~018, and N be greater than or equal to 8) can be loaded on it is slow Memory is rushed at least to provide the access information of data 811~818 (such as logic to physical mapping information).In other words, logic Table sum N in distribution information 821 (1) can be used for obtaining the assessed value for corresponding to physical unit 810 (1) and can be used To indicate fully to move or replicate data 811~818 needs to read at least eight table 011~018.
It is noted that the present invention is not intended to limit the data content and format of logic distribution information.For example, in Fig. 8 Another exemplary embodiment in, logic distribution information 821 (0) can also only record numerical value 5 with provide correspond to physics list The assessed value and/or logic distribution information 821 (1) of first 810 (0) can also record numerical value of N only to provide and correspond to physics The assessed value of unit 810 (1).In an exemplary embodiment, correspond to physical unit 810 (0) assessed value (such as 5) be less than pair It should indicate that the dispersion of logic unit corresponding to data 801~804 is low in the assessed value (such as N) of physical unit 810 (1) The dispersion of the logic unit corresponding to data 811~818.
In an exemplary embodiment, corresponding to a write instruction from host system 11, memory management circuitry 502 To at least one physical unit execution in the memory block 601 and/or idle area 602 of Fig. 6, at least a data are whole and operate for meeting.This Outside, the dispersion of the logic unit according to corresponding to the first data, it is whole that memory management circuitry 502 can adjust the execution data And the number operated.
In an exemplary embodiment, corresponding to a write instruction from host system 11, memory management circuitry 502 It can indicate that at least one physical unit execution in memory block 601 and idle area 602 to Fig. 6 meets an event counter value At least one access event of (also referred to as first event count value).For example, it is assumed that first event count value is M, then correspond to From a write instruction of host system 11, M access event can be performed according to first event count value.Complete a certain write After entering instruction, if receiving from the next write instruction of host system 11, M additional access event, which can connect, to be performed. According to the dispersion of logic unit corresponding to the first data, parameter M (i.e. first event count value) can be adjusted.
It is noted that an access event can be the arbitrary data access event executed in and operation whole in data. For example, access event can be read for a reading data event, a data writing events, a table event or other The data access event of type.Reading data event is used to read valid data from source Nodes.Data writing events are used for will Collected valid data are written to recycling node.Table reads event and is used for the sublist of logic to physical mappings table at least Partial information is loaded into buffer storage.
In an exemplary embodiment, the logic distribution information of first kind physical unit can reflect multiple physical units Assessed value is averaged.That is, the dispersion of logic unit corresponding to the first data can be to be stored in multiple first kind physics lists Member the first data pair logic unit mean square.By taking Fig. 8 as an example, if the first kind physics list as source Nodes The sum of member (i.e. physical unit 810 (0) and 810 (1)) is 2, then the logic distribution information of first kind physical unit can wrap Include assessed value (5+N)/2.In addition, the average value may also mean that weighted average or median etc., the present invention is without restriction.
In an exemplary embodiment, first event count value is positively correlated with the discrete of logic unit corresponding to the first data Degree.By taking Fig. 8 as an example, if assessed value (5+N)/2 is bigger, first event count value M obtained may be bigger.In example reality It applies in example, the logic distribution information (such as assessed value) of first kind physical unit can be input to an algorithm or a lookup Table.According to the output of this algorithm or look-up table, first event count value can be obtained.
In an exemplary embodiment, memory management circuitry 502 can also according to corresponding to the first data logic unit Dispersion obtains another event counter value (also referred to as second event count value).Second event count value can be reacted for making For source Nodes an at least first kind physical unit carry out data it is whole and operate in, outline needs to be implemented P access event Collected valid data to be filled up to single the second class physical unit as recycling node.In an exemplary embodiment, The logic distribution information (such as assessed value) of first kind physical unit can be input to an algorithm by memory management circuitry 502 An or look-up table.According to the output of this algorithm or look-up table, second event count value can be obtained.
Fig. 9 is logic distribution information shown by an exemplary embodiment according to the present invention and corresponding second event The schematic diagram of count value.Fig. 9 is please referred to, in an exemplary embodiment, is obtaining the first kind physical unit as recycling node Logic distribution information (such as assessed value) after, according to form data 910,2000 and be less than if this assessed value is greater than 10000, then can get corresponding second event count value is 600；If this assessed value is greater than 500 and less than 2000, can get Corresponding second event count value is 400；If this assessed value is greater than 100 and less than 500, corresponding second event meter can get Numerical value is 200；If it is 100 that this assessed value, which less than 100, can get corresponding second event count value,.It is greater than 100 with assessed value And for the situation less than 500, second event count value 200 obtained can indicate carrying out first kind physical unit Data it is whole and operate in, outline need to be implemented 200 access events using by collected valid data fill up as recycling node Single the second class physical unit.
In the exemplary embodiment of Fig. 9, second event count value is positively correlated with logic unit corresponding to the first data Dispersion.For example, if the assessed value for corresponding to first kind physical unit is bigger, second event count value obtained It is bigger.
In an exemplary embodiment, memory management circuitry 502 can obtain first event meter according to second event count value Numerical value.For example, second event count value can be input to an algorithm or a look-up table in an exemplary embodiment.According to this calculation The output of method or look-up table, first event count value can be obtained.
In an exemplary embodiment, the valid data that memory management circuitry 502 also can get first kind physical unit are deposited Store up information.Storage state of the valid data storage message reflection valid data in first kind physical unit.For example, described Valid data storage information can reflect the significant figure for storing how many data volume respectively as multiple physical units of source Nodes According to, or averagely store as multiple physical units of source Nodes the valid data of how many data volume.
In an exemplary embodiment, memory management circuitry 502 can the logic unit according to corresponding to the first data from The valid data of divergence and first kind physical unit store information acquisition first event count value.For example, memory management circuitry 502 can store another event counter value of information acquisition according to the valid data of second event count value and first kind physical unit (also referred to as third event counter value).Third event counter value can be reacted for at least first kind object as source Nodes Manage unit carry out data it is whole and operate in, outline need to be implemented Q access event with discharge one additionally the second class physics Unit (i.e. idle physical unit).Wherein, the value that the value of Q is approximately equal to P is multiplied by the value of R.Parameter R is represented for saving as source Point an at least first kind physical unit carry out data it is whole and operate in, need to fill up as recycling node R physics list Member is to discharge a second additional class physical unit.
In an exemplary embodiment, memory management circuitry 502 can be stored according to the valid data of first kind physical unit Information acquisition parameter R.For example, it is assumed that valid data occupy respectively in 3 first kind physical units as recycling node 60%, 70% and 70% memory space is then filling up 2 using the valid data collected from this 3 first kind physical units After a second class physical unit, this 3 first kind physical units can be erased and become the second new class physical unit.In addition, 2 the second class physical units being fully written can become new first kind physical unit.Therefore, full this 2 the second class physics are being write After unit, the sum of the second class physical unit will increase 1 (3-2=1).In this exemplary embodiment, the value of R is 2, indicates to fill up 2 the second class physical units as recycling node can discharge an additional second class physical unit.
In an exemplary embodiment, memory management circuitry 502 can obtain first event meter according to third event counter value Numerical value.For example, third event counter value can be input to an algorithm or a look-up table in an exemplary embodiment.According to this calculation The output of method or look-up table, first event count value can be obtained.
In an exemplary embodiment, memory management circuitry 502 also can get reproducible nonvolatile memorizer module The number of the second class physical unit (i.e. idle physical unit) in 406.By taking Fig. 6 as an example, the number etc. of the second class physical unit It is same as the sum of the physical unit 610 (A+1)~610 (B) in idle area 602.Memory management circuitry 502 can be according to the first number Information and the second class physical unit are stored according to the valid data of the dispersion of corresponding logic unit, first kind physical unit Number obtains first event count value.
In an exemplary embodiment, data it is whole and operate operation mode include dynamic mode (also referred to as first operation mould Formula), at least two behaviour in normal mode (also referred to as second operator scheme) and emergency mode (also referred to as third operation mode) Operation mode.It is whole and grasp that memory management circuitry 502 dynamically can determine or adjust data according to the number of the second class physical unit The operation mode of work.
Figure 10 is the number of the second class physical unit shown by an exemplary embodiment according to the present invention and corresponding number According to the schematic diagram of operation mode that is whole and operating.Figure 10 is please referred to, in an exemplary embodiment, if current second class physical unit Number between 0 and numerical value Z, data it is whole and operate operation mode can be set to emergency mode.If current second class The number of physical unit between numerical value Z and numerical value Y, data it is whole and operate operation mode can be set to normal mode. If the number of current second class physical unit between numerical value Y and numerical value X, data it is whole and operate operation mode can be set For dynamic mode.If the number of current second class physical unit is greater than numerical value X, it is whole and operate that data can not be executed.
In an exemplary embodiment, memory management circuitry 502 can the logic unit according to corresponding to the first data from Divergence, first kind physical unit valid data storage information and current data it is whole and operate operation mode obtain first event Count value.For example, operation mode that is whole according to current data and operating, memory management circuitry 502 can get a percent information. This percent information to control open block and idle physical unit exchange ratio.Wherein, block and idle physical unit are opened Exchange ratio be reflected in execute host write operation during, corresponding to K unlatching block is filled up, need to discharge one additionally Second class physical unit.
In an exemplary embodiment, if current data is whole and the operation mode that operates is dynamic mode, parameter K can be determined It is set to S, and this percent information can reflect that opening exchanging for block and the second class physical unit compares for S than 1 (i.e. corresponding to filling up S A unlatching block needs to discharge a second additional class physical unit).In addition, if current data it is whole and operate operation mould Formula is normal mode, and parameter K can be decided to be 1.
In an exemplary embodiment, if current data it is whole and operate operation mode be dynamic mode, memory management electricity Road 502 can also dynamically be determined according to the valid data of first kind physical unit storage information or adjusting parameter S.For example, depositing Reservoir management circuit 502 can determine whether the parameter R for storing information according to the valid data of first kind physical unit and obtaining is big In a preset value.If parameter R is greater than this preset value, parameter S can be set greater than 1 value, example by memory management circuitry 502 Such as, 2~4 etc..Conversely, parameter S can be set as 1 by memory management circuitry 502 if parameter R is not more than this preset value.
In an exemplary embodiment, memory management circuitry 502 can the logic unit according to corresponding to the first data from Divergence, the valid data storage information of first kind physical unit and the percent information obtain first event count value.In a model In example embodiment, first event count value can also be according to current type (the i.e. SLC NAND as the physical unit for opening block Type, MLC NAND type or TLC NAND type) and obtain or adjust.In an exemplary embodiment, first event count value can also root According to the write-in data volume of single a write instruction from host system 11 or the average write-in data volume of multiple write instructions It obtains or adjusts.
It include below assessed value 400 as example using the logic distribution information of first kind physical unit.According to assessment Value 400, can such as query graph 9 form data 910 and obtain second event count value be 200.This second event count value is anti- It mirrors under the logic distribution of current first kind physical unit, needs to be implemented 200 access events about with will be from first The valid data that class physical unit is collected fill up single the second class physical unit as recycling node.According to first kind physics The valid data of unit store information, can get parameter R.Wherein parameter R, for example, 3 reflect in current first kind physics Under the valid data storage state of unit, needing to fill up could discharge additionally as 3 the second class physical units of recycling node A second class physical unit.Therefore, second event count value 200 can be multiplied by parameter R, for example, 3, to obtain third thing Part count value 600.
Information, parameter are stored according to the valid data of the number of current second class physical unit and first kind physical unit K can be determined, and for example, 1, indicate to open block and the second class physical unit exchanges that compare be 1 to 1.That is, executing During host write operation, corresponding to a unlatching block is filled up, need to discharge a second additional class physical unit.
Assuming that belonging to TLC NAND type flash memory, the capacity of a unlatching block as the physical unit for opening block About 72MB, and data of from host system 11 write instruction to indicate storage 1MB.Therefore, it can get and come from The indicated data stored of 72 (72/1=72) a write instructions of host system 11 can fill up a unlatching block.Then, It divided by 72 available first event count values is about 9 (600/72=8.333) by third event counter value 600.
That is, in previous cases, host write operation is executed and data are whole and during operate synchronous, it is right A write instruction of the Ying Yu from host system 11 can correspond to and execute 9 access events, open block and second to reach The effect of exchange of class physical unit is than being written stability for the data of 1 to 1 and raising memory storage apparatus.
Figure 11 is the flow chart of storage management method shown by an exemplary embodiment according to the present invention.Please refer to figure 11, in step S1101, corresponding to a write instruction from host system, to type nonvolatile mould At least one physical unit execution data of block are whole and operate.In step S1102, according to type nonvolatile The dispersion of multiple logic units corresponding to the first data that first kind physical unit in module is stored, adjustment execute institute State the number that data are whole and operate.
However, each step has been described in detail as above in Figure 11, just repeat no more herein.It is worth noting that, each in Figure 11 Step can be implemented as multiple procedure codes or circuit, and the present invention is without restriction.In addition, more than the method for Figure 11 can arrange in pairs or groups Exemplary embodiment uses, and also can be used alone, and the present invention is without restriction.
In conclusion correspond to the write instruction from host system, it can be to reproducible nonvolatile memorizer module At least one physical unit to execute data whole and operate.In addition, according in reproducible nonvolatile memorizer module The dispersion of logic unit corresponding to the first data that a kind of physical unit is stored executes time that the data are whole and operate Number can be adjusted.In an exemplary embodiment, in the first kind physical unit for considering the source Nodes as valid data After logic distribution information (the i.e. described dispersion), first event count value obtained can it is whole according to data and operate in compared with For time-consuming operation (such as table accessing operation) estimated execution number and adjust, to effectively improve memory storage apparatus Data be written stability.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field Middle technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore protection of the invention Range is subject to view as defined in claim.

Claims (21)

1. a kind of storage management method, which is characterized in that for the storage including reproducible nonvolatile memorizer module Device storage device, wherein the reproducible nonvolatile memorizer module includes multiple physical units, the multiple physics list An at least first kind physical unit in member has the first data, and first data correspond to multiple logic units, described to deposit Reservoir management method includes:
Corresponding to the write instruction from host system, at least one number is executed to the one at least within of the multiple physical unit According to whole and operate；And
According to the dispersion of the multiple logic unit corresponding to first data, it is whole that adjustment executes an at least data And the number operated.
2. storage management method according to claim 1, wherein the dispersion positive of the multiple logic unit There is the number of an at least table of the logic of first data to physical mapping information about record.
3. storage management method according to claim 1, wherein corresponding to the said write from the host system Instruction is to one executes that described at least a data are whole and include: the step of operation at least within described in the multiple physical unit
Corresponding to the said write instruction from the host system, at least one execution described in the multiple physical unit At least one access event,
Wherein an at least access event include reading data event, data writing events and table read event at least its One of.
4. storage management method according to claim 1, wherein the multiple according to corresponding to first data The dispersion adjustment of logic unit execute an at least data it is whole and operate number the step of include:
First event count value is obtained according to the dispersion；And
Correspond to the number of at least one access event described in said write instruction execution according to first event count value adjustment Mesh.
5. storage management method according to claim 4, wherein obtaining the first event meter according to the dispersion The step of numerical value includes:
According to the first thing described in the valid data of the dispersion and at least first kind physical unit storage information acquisition Part count value,
Wherein storage shape of the valid data storage message reflection valid data in an at least first kind physical unit State.
6. storage management method according to claim 5, wherein according to the dispersion and an at least first kind Physical unit the valid data storage information acquisition described in first event count value the step of include:
Information and the multiple object are stored according to the valid data of the dispersion, an at least first kind physical unit The number for managing at least one second class physical unit in unit obtains the first event count value,
The wherein not stored valid data of at least one second class physical unit.
7. storage management method according to claim 4, wherein obtaining the first event meter according to the dispersion The step of numerical value includes:
Second event count value is obtained according to the dispersion, wherein the second event count value corresponds to for will be described more The second class physical unit in a physical unit writes the number of at least one full access event；And
The first event count value is obtained according to the second event count value.
8. a kind of memory storage apparatus characterized by comprising
Connecting interface unit, to be connected to host system；
Reproducible nonvolatile memorizer module, wherein the reproducible nonvolatile memorizer module includes multiple physics Unit, at least first kind physical unit in the multiple physical unit has the first data, and first data are corresponding Multiple logic units；And
Memorizer control circuit unit is connected to the connecting interface unit and the type nonvolatile mould Block,
Wherein the memorizer control circuit unit is indicated to correspond to the write instruction from the host system to described At least a data are whole and operate for the execution of one at least within of multiple physical units,
Wherein the memorizer control circuit unit is also to the multiple logic unit according to corresponding to first data Dispersion, adjustment executes the number that an at least data are whole and operate.
9. memory storage apparatus according to claim 8, wherein the dispersion positive of the multiple logic unit There is the number of an at least table of the logic of first data to physical mapping information about record.
10. memory storage apparatus according to claim 8 comes from wherein the memorizer control circuit unit corresponds to The said write instruction of the host system is to one executes described at least one at least within described in the multiple physical unit Data it is whole and operate operation include:
Corresponding to from the host system said write instruction, instruction to described in the multiple physical unit at least one At least one access event is executed,
Wherein an at least access event include reading data event, data writing events and table read event at least its One of.
11. memory storage apparatus according to claim 8, wherein the memorizer control circuit unit is according to described The dispersion adjustment of the multiple logic unit corresponding to one data executes time that an at least data are whole and operate Several operations include:
First event count value is obtained according to the dispersion；And
Correspond to the number of at least one access event described in said write instruction execution according to first event count value adjustment Mesh.
12. memory storage apparatus according to claim 11, wherein the memorizer control circuit unit is according to The operation that dispersion obtains the first event count value includes:
According to the first thing described in the valid data of the dispersion and at least first kind physical unit storage information acquisition Part count value,
Wherein storage shape of the valid data storage message reflection valid data in an at least first kind physical unit State.
13. memory storage apparatus according to claim 12, wherein the memorizer control circuit unit is according to First event count value described in the valid data of dispersion and at least first kind physical unit storage information acquisition Operation include:
Information and the multiple object are stored according to the valid data of the dispersion, an at least first kind physical unit The number for managing at least one second class physical unit in unit obtains the first event count value,
The wherein not stored valid data of at least one second class physical unit.
14. memory storage apparatus according to claim 11, wherein the memorizer control circuit unit is according to The operation that dispersion obtains the first event count value includes:
Second event count value is obtained according to the dispersion, wherein the second event count value corresponds to for will be described more The second class physical unit in a physical unit writes the number of at least one full access event；And
The first event count value is obtained according to the second event count value.
15. a kind of memorizer control circuit unit, which is characterized in that for controlling reproducible nonvolatile memorizer module, Wherein the memorizer control circuit unit includes:
Host interface, to be connected to host system；
Memory interface, to be connected to the reproducible nonvolatile memorizer module, wherein the duplicative is non-easily The property lost memory module includes multiple physical units, and at least first kind physical unit in the multiple physical unit has the One data, and first data correspond to multiple logic units；And
Memory management circuitry is connected to the host interface and the memory interface,
Wherein the memory management circuitry is indicated to correspond to the write instruction from the host system to the multiple At least a data are whole and operate for the execution of one at least within of physical unit,
Wherein the memory management circuitry also to according to corresponding to first data the multiple logic unit from Divergence, adjustment execute the number that an at least data are whole and operate.
16. memorizer control circuit unit according to claim 15, wherein the multiple logic unit is described discrete Degree is positively correlated with the number that record has an at least table of the logic of first data to physical mapping information.
17. memorizer control circuit unit according to claim 15 comes wherein the memory management circuitry corresponds to It instructs from the said write of the host system to one execution is described at least at least within described in the multiple physical unit One data it is whole and operate operation include:
Corresponding to from the host system said write instruction, instruction to described in the multiple physical unit at least one At least one access event is executed,
Wherein an at least access event include reading data event, data writing events and table read event at least its One of.
18. memorizer control circuit unit according to claim 15, wherein the memory management circuitry is according to It is whole and operate that the dispersion adjustment of the multiple logic unit corresponding to first data executes an at least data The operation of number includes:
First event count value is obtained according to the dispersion；And
Correspond to the number of at least one access event described in said write instruction execution according to first event count value adjustment Mesh.
19. memorizer control circuit unit according to claim 18, wherein the memory management circuitry is according to The operation that dispersion obtains the first event count value includes:
According to the first thing described in the valid data of the dispersion and at least first kind physical unit storage information acquisition Part count value,
Wherein storage shape of the valid data storage message reflection valid data in an at least first kind physical unit State.
20. memorizer control circuit unit according to claim 19, wherein the memory management circuitry is according to First event count value described in the valid data of dispersion and at least first kind physical unit storage information acquisition Operation include:
Information and the multiple object are stored according to the valid data of the dispersion, an at least first kind physical unit The number for managing at least one second class physical unit in unit obtains the first event count value,
The wherein not stored valid data of at least one second class physical unit.
21. memorizer control circuit unit according to claim 18, wherein the memory management circuitry is according to The operation that dispersion obtains the first event count value includes:
Second event count value is obtained according to the dispersion, wherein the second event count value corresponds to for will be described more The second class physical unit in a physical unit writes the number of at least one full access event；And
The first event count value is obtained according to the second event count value.
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