CN107102951B

CN107102951B - Storage management method, memorizer control circuit unit and memorizer memory devices

Info

Publication number: CN107102951B
Application number: CN201610093873.0A
Authority: CN
Inventors: 陈国荣; 颜鸿圣
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2016-02-19
Filing date: 2016-02-19
Publication date: 2019-08-06
Anticipated expiration: 2036-02-19
Also published as: CN107102951A

Abstract

The present invention is provided to a kind of storage management method of reproducible nonvolatile memorizer module, memorizer control circuit unit and memorizer memory devices.The method includes receiving adjustment instruction from host system, wherein the adjustment instruction is invalid to indicate the data stored by at least logic unit in multiple logic units；According to the adjustment instruction more new logical addresses state table, wherein the logical address state table reflects the data mode of the data stored by each logic unit in the logic unit；And if conform to a predetermined condition, physical address state table is updated according to the logical address state table and the physical address state table.The present invention can be according to the received adjustment instruction more new logical addresses state table of institute, and physical address state table is updated by updated logical address state table in system spare time, to reduce the time spent by processing adjustment instruction, and then promotes working efficiency.

Description

Storage management method, memorizer control circuit unit and memorizer memory devices

Technical field

The present invention relates to a kind of storages of a kind of storage management method more particularly to type nonvolatile Device management method, memorizer control circuit unit and memorizer memory devices.

Background technique

Digital camera, mobile phone and MP3 are very rapid in growth over the years, so that demand of the consumer to storage media Also rapidly increase.Since type nonvolatile (rewritable non-volatile memory) has data Non-volatile, power saving, it is small in size, without the characteristics such as mechanical structure, read or write speed be fast, be most suitable for these electronic products.Therefore, in recent years Flash memory industry becomes a ring quite popular in electronic industry.For example, being widely used in embedded more matchmakers on action electronic device Body card (embedded Multi Media Card, eMMC) is exactly a kind of storage device using flash memory as storage media.

In general, host system can transmit adjustment instruction to the storage device for using type nonvolatile (e.g., solid state hard disk), Lai Tongzhi storage device go to remove the data block no longer needed in storage device to increase available space. However, storage device has in addition expend resource and time to handle adjustment instruction in response to this adjustment instruction.Therefore, The time spent by processing adjustment instruction how is saved, and then the effect of adjustment instruction is performed into maximum, is this field technology The target that personnel are endeavoured.

Summary of the invention

The present invention provides a kind of storage management method, memorizer control circuit unit and memorizer memory devices, can have The time of processing adjustment instruction is saved on effect ground.

One example of the present invention embodiment provides a kind of memory pipe for being used for reproducible nonvolatile memorizer module Reason method, wherein the reproducible nonvolatile memorizer module includes multiple entity erased cells, wherein the entity is smeared Except each entity erased cell of unit has multiple entity program units, wherein the entity program unit image is at most A logic unit.The storage management method include from host system receive adjustment instruction, wherein the adjustment instruction to Indicate that the data at least stored by a logic unit in the logic unit are invalid；It is patrolled according to adjustment instruction update Address state table is collected, wherein the logical address state table is stored up to each logic unit reflected in the logic unit The data mode for the data deposited, wherein the data mode includes first state or the second state；If conforming to a predetermined condition, root The physical address state table is updated according to the comparison result of the logical address state table and physical address state table, wherein institute Physical address state table is stated to reflect the multiple realities for corresponding to the physical address state table in the entity program unit The data mode of the data stored by each entity program unit in body programmed cell；And according to updated The physical address state table erases to an at least invalid data.

In one embodiment of this invention, if wherein above-mentioned meet the predetermined condition, according to the logical address shape If the comparison result of state table and the physical address state table the step of updating the physical address state table includes Meet the predetermined condition, according to the physical address state table, multiple realities for being reflected from the physical address state table Select the data mode for the first instance address of the first state in body address；And logical address is turned according to entity and is reflected As table, the logical address state table and the first instance address are to determine whether need to update in the physical address state table The data mode of the corresponding first instance address.

In one embodiment of this invention, wherein it is above-mentioned according to the logical address state table and the first instance address To determine whether the step of data mode for corresponding to the first instance address in the physical address state table need to be updated The first logical address of first instance address institute image is recognized including turning logical address mapping table according to the entity；Root It is compared with first logical address in the logical address state table according to the logical address state table and corresponds to described first The data shape of the first instance address is corresponded in the data mode of logical address and the physical address state table State；And if corresponding to the data mode of first logical address in the logical address state table different from the reality The data mode of the first instance address is corresponded in body address state table, judgement need to update the physical address state table The data mode of the middle correspondence first instance address, and it is real that described first will be corresponded in the physical address state table The data mode of body address is adjusted to correspond to first logic in the logical address state table from the first state The data mode of address, wherein corresponding to the data mode of first logical address in the logical address state table For second state.

In one embodiment of this invention, if wherein above-mentioned meet the predetermined condition, according to the physical address shape State table selects the data mode for first shape from the physical address that the physical address state table is reflected The step of first instance address of state includes according to the physical address reflected and respectively corresponding the physical address The data mode time, with oldest to newest sequence, the data shape of the corresponding physical address of sequentially judgement State；And selecting the data mode is the physical address of the first state as the first instance address.

In one embodiment of this invention, if above-mentioned storage management method further includes that the host system is idle, rubbish When rubbish reclaimer operation or the operation for having resource that can be updated physical address state table, judgement meets the predetermined condition.

In one embodiment of this invention, wherein the logical address state table reflects the multiple of the logic unit patrols The data mode of address and the corresponding logical address is collected, wherein corresponding to the data mode is patrolling for the first state It is effective for collecting the data stored by the logic unit of address, and the corresponding data mode is the logic of second state Data stored by the logic unit of address are invalid, wherein the physical address state table reflects the entity program The data mode of multiple physical address of unit and the corresponding physical address, wherein it is described for corresponding to the data mode Data stored by the entity program unit of the physical address of first state are effective, and the corresponding data mode is Data stored by the entity program unit of the physical address of second state are invalid.

In one embodiment of this invention, wherein it is above-mentioned according to the updated physical address state table to it is described at least The step of one invalid data is erased include recognized according to the updated physical address state table it is updated described An at least second instance address and the data mode of the data mode described in physical address state table for second state For an at least third physical address for the first state；And according to an at least second instance address and described at least one Third physical address executes a garbage collection operation, wherein according at least second instance address and described at least 1 the Three physical address are including collecting to be stored in an at least third physical address the step of executing the garbage collection operation An at least valid data；And at least invalid data being stored in an at least second instance address of erasing.

In one embodiment of this invention, the storage management method further includes will have storage valid data at least An at least solid element for one entity program unit is divided into data link, wherein the data-link knot is configured with the entity Address state table, wherein multiple entity programs of the physical address state table to reflect an at least solid element Multiple entity program lists of the physical address of each entity program unit in unit and an at least solid element The data mode of the data stored by each entity program unit in member, if wherein above-mentioned meet the predetermined item Part updates the physical address according to the comparison result of the logical address state table and the physical address state table The step of state table includes being checked described in data link at least via the physical address state table with predetermined order One solid element.

In one embodiment of this invention, wherein above-mentioned examined via the physical address state table with the predetermined order The step of looking into an at least solid element for data link includes sequentially checking the entity with the predetermined order The physical address that address state table is reflected and the corresponding data mode, with the corresponding physical address shape of identification Data mode described in state table is multiple physical address of the first state；And from the data mode be first shape Select an at least physical address in the physical address of state, and according to an at least physical address, image to it is described extremely An at least logical address for a few physical address, to compare the institute of an at least logical address described in the logical address state table State the data mode of data mode Yu an at least physical address.

One example of the present invention embodiment provides a kind of memorizer control circuit list for controlling memorizer memory devices Member.The memorizer control circuit unit includes host interface, memory interface and memory management circuitry.Host interface is electrical It is connected to host system.Memory interface is electrically connected to reproducible nonvolatile memorizer module, wherein described can make carbon copies Formula non-volatile memory module includes multiple entity erased cells, the list wherein each entity of the entity erased cell is erased Member has multiple entity program units, wherein the entity program unit image is to multiple logic units.Memory management Circuit is electrically connected to the host interface and the memory interface.The memory management circuitry from host system to connect Adjustment instruction is received, wherein the adjustment instruction is to indicate the data stored by at least logic unit in the logic unit It is invalid.The memory management circuitry is more to according to the adjustment instruction more new logical addresses state table, wherein described Data mode of the logical address state table to reflect the data stored by each logic unit in the logic unit, Described in data mode include first state or the second state.If conforming to a predetermined condition, the memory management circuitry is more used To update the physical address state table according to the comparison result of the logical address state table and physical address state table, Described in physical address state table to reflect the more of the physical address state table are corresponded in the entity program unit The data mode of the data stored by each entity program unit in a entity program unit.Also, it is described to deposit Reservoir manages circuit more to erase according to the updated physical address state table to an at least invalid data.

In one embodiment of this invention, if meeting the predetermined condition, the memory management circuitry is according to Physical address state table, selected from multiple physical address that the physical address state table is reflected the data mode for The first instance address of the first state, and according to entity turn logical address mapping table, the logical address state table with The first instance address is to determine whether the institute for corresponding to the first instance address in the physical address state table need to be updated State data mode.

In one embodiment of this invention, the memory management circuitry according to the entity turn logical address mapping table come The first logical address of first instance address institute image is recognized, and according to the logical address state table and described first Logical address corresponds to the data mode and the reality of first logical address to compare in the logical address state table The data mode of the first instance address is corresponded in body address state table.If corresponding in the logical address state table The data mode of first logical address is different from corresponding to the first instance address in the physical address state table The data mode, memory management circuitry judgement, which need to update, correspond to first reality in the physical address state table The data mode of body address, and the data for the first instance address being corresponded in the physical address state table State is adjusted to correspond to the data shape of first logical address in the logical address state table from the first state State, wherein the data mode for corresponding to first logical address in the logical address state table is second state.

In one embodiment of this invention, the memory management circuitry is according to the physical address and difference reflected The time of the data mode of the corresponding physical address, with oldest to newest sequence, the corresponding entity of sequentially judgement The data mode of address, wherein the memory management circuitry selects the data mode for the entity of the first state Address is as the first instance address.

In one embodiment of this invention, if wherein the host system is idle, garbage collection operation or has resource can To be updated the operation of physical address state table, the memory management circuitry judgement meets the predetermined condition.

In one embodiment of this invention, the memory management circuitry is according to the updated physical address state table To recognize at least second instance that data mode described in the updated physical address state table is second state Address and the data mode are an at least third physical address for the first state, and real according to described at least one second Body address executes garbage collection operation with an at least third physical address.Also, in the memory management circuitry root The running of the garbage collection operation is executed according to an at least second instance address and an at least third physical address In, the memory management circuitry collects at least valid data being stored in an at least third physical address, wherein The memory management circuitry is erased at least invalid data being stored in an at least second instance address.

In one embodiment of this invention, wherein the memory management circuitry will have store valid data at least one An at least solid element for entity program unit is divided into data link, wherein the data-link knot configured with it is described physically Location state table, wherein multiple entity program lists of the physical address state table to reflect an at least solid element Multiple entity program units of the physical address of each entity program unit in member and an at least solid element In each entity program unit stored by data the data mode.Also, the memory management circuitry via The physical address state table checks an at least solid element described in data link with predetermined order.

In one embodiment of this invention, the memory management circuitry sequentially checks the reality with the predetermined order The physical address that body address state table is reflected and the corresponding data mode, with the corresponding physical address of identification Data mode described in state table is multiple physical address of the first state.The memory management circuitry is from the data State be the first state the physical address in select an at least physical address, and physically according to described at least one Location, image to an at least physical address an at least logical address, to compare described in the logical address state table extremely The data mode of a few logical address and the data mode of an at least physical address.

One example of the present invention embodiment provides a kind of memorizer memory devices comprising connecting interface unit, host system System, reproducible nonvolatile memorizer module and memorizer control circuit unit.Connecting interface unit is electrically connected to host System.Reproducible nonvolatile memorizer module includes multiple entity erased cells, wherein the entity erased cell is every One entity erased cell has multiple entity program units, wherein the entity program unit image is to multiple logic lists Member.Memorizer control circuit unit is electrically connected to the connecting interface unit and the type nonvolatile mould Block.The memorizer control circuit unit to from the host system receive adjustment instruction, wherein the adjustment instruction to Indicate that the data at least stored by a logic unit in the logic unit are invalid.The memorizer control circuit unit More to according to the adjustment instruction more new logical addresses state table, wherein the logical address state table is described to reflect The data mode of the data stored by each logic unit in logic unit, wherein the data mode include first state or Second state.If conforming to a predetermined condition, the memorizer control circuit unit is more to according to the logical address state table Update the physical address state table with the comparison result of physical address state table, wherein the physical address state table to It reflects each in the multiple entity program units for corresponding to the physical address state table in the entity program unit The data mode of data stored by entity program unit, wherein the memorizer control circuit unit is more to basis The updated physical address state table erases to an at least invalid data.

In one embodiment of this invention, if meeting the predetermined condition, the memorizer control circuit unit according to The physical address state table selects the data shape from multiple physical address that the physical address state table is reflected State is the first instance address of the first state.Also, the memorizer control circuit unit turns logical address according to entity Mapping table, the logical address state table and the first instance address are to determine whether the physical address state table need to be updated The data mode of the middle correspondence first instance address.

In one embodiment of this invention, the memorizer control circuit unit turns logical address image according to the entity Table recognizes the first logical address of first instance address institute image, and according to the logical address state table with it is described First logical address corresponds to the data mode and the institute of first logical address to compare in the logical address state table State the data mode that the first instance address is corresponded in physical address state table.If in the logical address state table The data mode of corresponding first logical address is different from corresponding to the first instance in the physical address state table The data mode of address, the memorizer control circuit unit judgement, which need to update in the physical address state table, corresponds to institute The data mode of first instance address is stated, and the first instance address will be corresponded in the physical address state table The data mode is adjusted to correspond to the institute of first logical address in the logical address state table from the first state Data mode is stated, wherein the data mode for corresponding to first logical address in the logical address state table is described the Two-state.

In one embodiment of this invention, the memorizer control circuit unit according to the physical address that reflects with The time of the data mode of the physical address is respectively corresponded, with oldest to newest sequence, sequentially described in judgement correspondence The data mode of physical address, wherein data mode described in the memorizer control circuit Unit selection is first shape The physical address of state is as the first instance address.

In one embodiment of this invention, if the host system is idle, garbage collection operation or has resource can be into Row updates the operation of physical address state table, and the memorizer control circuit unit judgement meets the predetermined condition.

In one embodiment of this invention, the memorizer control circuit unit is according to the updated physical address shape State table come recognize data mode described in the updated physical address state table be second state at least one second Physical address and the data mode are an at least third physical address for the first state, and according to described at least 1 the Two physical address execute garbage collection operation with an at least third physical address.In the memorizer control circuit unit The fortune of the garbage collection operation is executed according to an at least second instance address and an at least third physical address In work, the memorizer control circuit unit collects at least significant figure being stored in an at least third physical address According to.And the memorizer control circuit cell erasure be stored in an at least second instance address it is at least one invalid Data.

In one embodiment of this invention, wherein the memorizer control circuit unit will have storage valid data extremely An at least solid element for a few entity program unit is divided into data link, wherein the data-link knot is configured with the reality Body address state table, wherein multiple entity programs of the physical address state table to reflect an at least solid element Change the physical address of each entity program unit in unit and multiple entity programs of an at least solid element The data mode of the data stored by each entity program unit in unit.If meeting the predetermined item above-mentioned Part, the memorizer control circuit unit is more to the institute according to the logical address state table and the physical address state table Comparison result is stated to update in the running of the physical address state table, the memorizer control circuit unit is via the entity Address state table checks an at least solid element described in data link with predetermined order.

In one embodiment of this invention, the memorizer control circuit unit sequentially checks institute with the predetermined order The physical address that physical address state table is reflected and the corresponding data mode are stated, with the corresponding entity of identification Data mode described in address state table is multiple physical address of the first state.The memorizer control circuit unit from The data mode be the first state the physical address in select an at least physical address, and according to it is described at least An at least logical address for one physical address, image to an at least physical address, to compare the logical address state table Described in an at least logical address the data mode and an at least physical address the data mode.

Based on storage management method provided by above-mentioned, of the invention exemplary embodiment, memorizer control circuit unit With memorizer memory devices, can according to the received adjustment instruction more new logical addresses state table of institute, and system spare time by Physical address state table is updated by updated logical address state table, to reduce the time spent by processing adjustment instruction, And then promote working efficiency.

To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.

Detailed description of the invention

Fig. 1 is host system, memorizer memory devices and input shown by an exemplary embodiment according to the present invention/defeated The schematic diagram of (I/O) device out；

Fig. 2 is host system shown by another exemplary embodiment according to the present invention, memorizer memory devices and I/O dress The schematic diagram set；

Fig. 3 is the signal of host system and memorizer memory devices shown by another exemplary embodiment according to the present invention Figure；

Fig. 4 is the summary block diagram of memorizer memory devices shown by an exemplary embodiment according to the present invention；

Fig. 5 is the summary block diagram of the memorizer control circuit unit according to an exemplary embodiment；

Fig. 6 is the device of the management reproducible nonvolatile memorizer module according to the first exemplary embodiment Schematic diagram；

Fig. 7 is the device of the management reproducible nonvolatile memorizer module according to the first exemplary embodiment Schematic diagram；

Fig. 8 is that logic shown by an exemplary embodiment according to the present invention turns physical address mapping table and entity turns logic The schematic diagram of address mapping table；

Fig. 9 is shown by an exemplary embodiment according to the present invention according to adjustment instruction more new logical addresses state table Schematic diagram；

Figure 10 is the schematic diagram of physical address state table shown by an exemplary embodiment according to the present invention；

Figure 11 is the schematic diagram that physical address state table is updated shown by an exemplary embodiment according to the present invention；

Figure 12 is the flow chart of storage management method shown by an exemplary embodiment according to the present invention.

Appended drawing reference:

10: memorizer memory devices

11: host system

110: system bus

111: processor

112: random access memory

113: read-only memory

114: data transmission interface

12:I/O device

20: mainboard

201: Portable disk

202: memory card

203: solid state hard disk

204: radio memory storage device

205: GPS module

206: network adapter

207: radio transmitting device

208: keyboard

209: screen

210: loudspeaker

211: mouse

30: memorizer memory devices

31: host system

32:SD card

33:CF card

34: embedded storage device

341: embedded multi-media card

342: embedded type multi-core piece encapsulates storage device

402: connecting interface unit

404: memorizer control circuit unit

406: reproducible nonvolatile memorizer module

410 (0)~410 (N): entity erased cell

502: memory management circuitry

504: host interface

506: memory interface

508: buffer storage

510: electric power management circuit

512: error checking and correcting circuit

602: information data area

604: idle area

606: system area

608: replacing area

LBA (0), LBA (H), A~H: logic unit

A~h: entity program unit

820: logic turns physical address mapping table

830: entity turns logical address mapping table

801 (0)~801 (7): logical address

901 (0)~901 (7): physical address

910: adjustment instruction

920,921: logical address state table

802 (0)~802 (7), 902 (0)~902 (7): data mode

1010,1020: physical address state table

1101,1102,1103: arrow

S1201: adjustment instruction is received from host system, wherein the adjustment instruction is to indicate in multiple logic units Data at least stored by a logic unit are invalid

S1203: according to the adjustment instruction more new logical addresses state table, wherein the logical address state table is to anti- The data mode stored by each logic unit in the logic unit should be gone out, wherein the data mode includes first state Or second state

S1205: if conforming to a predetermined condition, according to the logical address state table and physical address state table to update Physical address state table is stated, wherein the physical address state table is to reflect each reality in multiple entity program units The data mode of data stored by body programmed cell

S1207: it erases according to the updated physical address state table to an at least invalid data

Specific embodiment

Fig. 1 is host system, memorizer memory devices and input shown by an exemplary embodiment according to the present invention/defeated The schematic diagram of (I/O) device out.Fig. 2 is host system shown by another exemplary embodiment according to the present invention, memory storage The schematic diagram of cryopreservation device and I/O device.

Fig. 1 and Fig. 2 are please referred to, host system 11 generally comprises processor 111, random access memory (random Access memory, RAM) 112, read-only memory (read only memory, ROM) 113 and data transmission interface 114.Place Reason device 111, random access memory 112, read-only memory 113 and data transmission interface 114 are all electrically connected to system bus (system bus)110。

In this exemplary embodiment, host system 11 is by 10 electricity of data transmission interface 114 and memorizer memory devices Property connection.For example, host system 11 can write data into memorizer memory devices 10 via data transmission interface 114 or from depositing Data are read in reservoir storage device 10.In addition, host system 11 is electrically connected by system bus 110 and I/O device 12. For example, output signal can be sent to I/O device 12 via system bus 110 or received from I/O device 12 defeated by host system 11 Enter signal.

In this exemplary embodiment, processor 111, random access memory 112, read-only memory 113 and data transmission Interface 114 may be provided on the mainboard 20 of host system 11.The number of data transmission interface 114 can be one or more.Pass through Data transmission interface 114, mainboard 20 can be electrically connected to memorizer memory devices 10 via wired or wireless way.Memory Storage device 10 can be for example Portable disk 201, memory card 202, solid state hard disk (Solid State Drive, SSD) 203 or nothing Linear memory storage device 204.Radio memory storage device 204 can be for example wireless near field communication (Near Field Communication, NFC) memorizer memory devices, radio facsimile (WiFi) memorizer memory devices, bluetooth (Bluetooth) Memorizer memory devices or low-power consumption bluetooth memorizer memory devices (for example, iBeacon) etc. are with various wireless communication technique The memorizer memory devices on basis.In addition, mainboard 20 can also be electrically connected to global positioning system by system bus 110 (Global Positioning System, GPS) module 205, network adapter 206, radio transmitting device 207, keyboard 208, The various I/O device such as screen 209, loudspeaker 210, mouse 211.For example, mainboard 20 can be by wirelessly passing in an exemplary embodiment Defeated 207 access wireless memorizer memory devices 204 of device.

In an exemplary embodiment, mentioned host system is substantially to cooperate with memorizer memory devices to store The arbitrary system of data.Although host system is explained with computer system, however, Fig. 3 in above-mentioned exemplary embodiment It is the schematic diagram of host system and memorizer memory devices shown by another exemplary embodiment according to the present invention.Please refer to figure 3, in another exemplary embodiment, host system 31 is also possible to digital camera, video camera, communication device, audio player, view The systems such as frequency player or tablet computer, and memorizer memory devices 30 can be its used SD card 32, CF card 33 or insertion The various non-volatile memory storage device such as formula storage device 34.Embedded storage device 34 includes embedded multi-media card (embedded MMC, eMMC) 341 and/or embedded type multi-core piece encapsulate storage device (embedded Multi Chip Package, eMCP) embedded storage on all types of substrates that memory module is directly electrically connected to host system such as 342 Cryopreservation device.

Fig. 4 is the summary block diagram of memorizer memory devices shown by an exemplary embodiment according to the present invention.

Referring to figure 4., memorizer memory devices 10 include connecting interface unit 402, memorizer control circuit unit 404 with Reproducible nonvolatile memorizer module 406.

In this exemplary embodiment, connecting interface unit 402 is compatible with the advanced attachment of sequence (Serial Advanced Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not limited thereto, connecting interface unit 402 can also meet advanced attachment (Parallel Advanced Technology Attachment, PATA) mark side by side Quasi-, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, secure digital (Secure Digital, SD) interface standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory Stick, MS) interface standard, multi-chip envelope Fill (Multi-Chip Package) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, down Enter formula Multi Media Card (Embedded Multimedia Card, eMMC) interface standard, Common Flash Memory (Universal Flash Storage, UFS) interface standard, embedded type multi-core piece encapsulation (embedded Multi Chip Package, eMCP) Interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other suitable standards.Connecting interface unit 402 can be with memorizer control circuit Unit 404 is encapsulated in a chip or connecting interface unit 402 is to be laid in one to include memorizer control circuit unit Outside 404 chip.

Memorizer control circuit unit 404 is to execute multiple logic gates or control with hardware pattern or firmware pattern implementation System instruction, and writing for data is carried out in reproducible nonvolatile memorizer module 406 according to the instruction of host system 11 The running such as enter, read and erase.

Reproducible nonvolatile memorizer module 406 is electrically connected to memorizer control circuit unit 404, and uses To store the data that host system 11 is written.Reproducible nonvolatile memorizer module 406 has entity erased cell 410 (0)~410 (N).For example, entity erased cell 410 (0)~410 (N) can belong to the same memory crystal grain (die) or belong to In different memory crystal grains.Each entity erased cell is respectively provided with multiple entity program units, wherein belonging to same The entity program unit of entity erased cell can be written independently and simultaneously be erased.However, it is necessary to be appreciated that, this Invent it is without being limited thereto, each entity erased cell be can by 64 entity program units, 256 entity program units or its He is formed any entity program unit.

In more detail, entity erased cell is the minimum unit erased.That is, each entity erased cell contains minimum number The memory cell of mesh being erased together.Entity program unit is the minimum unit of sequencing.That is, entity program unit is to write Enter the minimum unit of data.Each entity program unit generally includes data bit area and redundant digit area.Data bit area includes more Data of a entity access address to store user, and redundant digit area to stocking system data (for example, control information with Error correcting code).In this exemplary embodiment, it can be deposited comprising 8 entities in the data bit area of each entity program unit Address is taken, and the size of an entity access address is 512 bytes (byte).However, in other exemplary embodiments, data bit Also may include the more or fewer entity access addresses of number in area, the present invention be not intended to limit entity access address size and Number.For example, entity erased cell is physical blocks, and entity program unit is physical page in an exemplary embodiment Face or entity sector, but invention is not limited thereto.

In this exemplary embodiment, reproducible nonvolatile memorizer module 406 is multistage memory cell (Multi Level Cell, MLC) NAND-type flash memory module (that is, flash memory module that 2 data bit can be stored in a memory cell).However, The invention is not limited thereto, and reproducible nonvolatile memorizer module 406 also can be single-order memory cell (Single Level Cell, SLC) NAND-type flash memory module (that is, flash memory module that 1 data bit can be stored in a memory cell), three rank memory cells (Trinary Level Cell, TLC) NAND-type flash memory module is (that is, can store the flash memory mould of 3 data bit in a memory cell Block), other flash memory modules or other memory modules with the same characteristics.

Fig. 5 is the summary block diagram of the memorizer control circuit unit according to an exemplary embodiment.

Referring to figure 5., memorizer control circuit unit 404 includes memory management circuitry 502, host interface 504 and deposits Memory interface 506.

Overall operation of the memory management circuitry 502 to control memorizer control circuit unit 404.Specifically, it deposits Reservoir, which manages circuit 502, has multiple control instructions, and when memorizer memory devices 10 operate, these control instructions can quilt It executes the running such as to carry out the write-in of data, read and erase.

In this exemplary embodiment, the control instruction of memory management circuitry 502 is to carry out implementation with firmware pattern.For example, Memory management circuitry 502 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to Order is by imprinting so far read-only memory.When memorizer memory devices 10 operate, these control instructions can be by microprocessor Unit is executed the running such as to carry out the write-in of data, read and erase.

In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 502 also can be with program code type Formula is stored in the specific region of reproducible nonvolatile memorizer module 406 (for example, being exclusively used in storage system in memory module The system area for data of uniting) in.In addition, memory management circuitry 502 has microprocessor unit (not shown), read-only memory (not shown) and random access memory (not shown).In particular, this read-only memory has driving code, and work as memory control When circuit unit 404 processed is enabled, microprocessor unit can first carry out this driving code section, and will to be stored in duplicative non-volatile Control instruction in property memory module 406 is loaded onto the random access memory of memory management circuitry 502.Later, micro- Processor unit such as can operate these control instructions to carry out the write-in of data, read and erase at the running.

Host interface 504 is electrically connected to memory management circuitry 502 and is electrically connected to connecting interface list Member 402, to receive and identify instruction and data that host system 11 is transmitted.That is, the finger that host system 11 is transmitted Order and data can be sent to memory management circuitry 502 by host interface 504.In this exemplary embodiment, host interface 504 are compatible with eMMC standard.However, it is necessary to be appreciated that the invention is not limited thereto, host interface 504 can also be compatible with PATA standard, 1394 standard of IEEE, PCI Express standard, UFS standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, SATA standard, CF standard, IDE standard or other suitable data transmission standards.

Memory interface 506 is electrically connected to memory management circuitry 502 and non-volatile to access duplicative Property memory module 406.That is, the data for being intended to be written to reproducible nonvolatile memorizer module 406 can be via depositing Memory interface 506 is converted to the 406 receptible format of institute of reproducible nonvolatile memorizer module.

In an exemplary embodiment, memorizer control circuit unit 404 further includes buffer storage 508, power management electricity Road 510 and error checking and correcting circuit 512.

Buffer storage 508 is electrically connected to memory management circuitry 502 and is configured to temporarily store from host system 11 data and instruction or the data from reproducible nonvolatile memorizer module 406.

Electric power management circuit 510 is electrically connected to memory management circuitry 502 and to control memory storage dress Set 10 power supply.

Error checking and correcting circuit 512 are electrically connected to memory management circuitry 502 and to execute wrong inspection It looks into and correction program is to ensure the correctness of data.Specifically, when memory management circuitry 502 is received from host system 11 When to write instruction, error checking can be the corresponding error checking of data generation of this corresponding write instruction with correcting circuit 512 With correcting code (Error Checking and Correcting Code, ECC Code), and 502 meeting of memory management circuitry The data of this corresponding write instruction are written with corresponding error checking and correcting code to type nonvolatile mould In block 406.Later, meeting when reading data from reproducible nonvolatile memorizer module 406 when memory management circuitry 502 The corresponding error checking of this data and correcting code are read simultaneously, and error checking and correcting circuit 512 can be examined according to this mistake It looks into and error checking and correction program is executed to read data with correcting code.

Fig. 6 is the device of the management reproducible nonvolatile memorizer module according to the first exemplary embodiment Schematic diagram.

It will be appreciated that when being described herein the running of reproducible nonvolatile memorizer module 406, " selection ", " point The words such as group ", " division ", " association " are concepts in logic.That is, the entity of reproducible nonvolatile memorizer module The physical location of erased cell is not changed, but is erased list to the entity of reproducible nonvolatile memorizer module in logic Member is operated.

Please refer to Fig. 6, reproducible nonvolatile memorizer module 406 have multiple entity erased cells 410 (0)~ 410 (N), each entity erased cell have multiple entity program units.In this exemplary embodiment, entity program unit For the minimum unit of sequencing.That is, entity program unit is the minimum unit that data are written.For example, entity program unit It is physical page or entity fan (sector).If entity program unit is physical page, each entity program list Member generally includes data bit area and redundant digit area.Data bit area includes multiple entities fan, to store the data of user, and redundancy Data (for example, error correcting code or other systems data for management) of the position area to stocking system.On the other hand, entity Erased cell is the minimum unit erased.That is, each entity erased cell contains the memory cell of minimal amount being erased together. For example, entity erased cell is physical blocks.

Memorizer control circuit unit 404 (or memory management circuitry 502) can be by type nonvolatile Entity erased cell 410 (0)~410 (N) of module 406 are logically grouped into data field 602, idle area 604, system area 606 With substitution area 608.

The entity erased cell for logically belonging to data field 602 and idle area 604 is to store from host system 11 data, and the entity erased cell in data field 602 and idle area 604 can be mapped to the multiple of host system 11 and patrol Collect unit (e.g., the logical blocks that the physical blocks in data field 602 and idle area 604 are mapped to host system 11).It is specific next It says, the entity erased cell of data field 602 is regarded as having stored the entity erased cell of data, and the entity in idle area 604 Erased cell is the entity erased cell to replacement data area 602.That is, it is assumed that memorizer control circuit unit 404 (or memory management circuitry 502) receives the number to be written of the write instruction with this corresponding write instruction from host system 11 According to.Said write instruction instruction is intended to the data storage being written at least one first logic unit.This write instruction is reacted, is stored Device control circuit unit 404 (or memory management circuitry 502) can be by this data storage to be written to image at least 1 the An at least first instance erased cell for the reproducible nonvolatile memorizer module 406 of one logic unit.Alternatively, if data Area 602) without any image to the entity erased cell of at least one first logic unit, memorizer control circuit unit 404 (or memory management circuitry 502) can select an at least entity erased cell as an at least first instance from idle area 604 Erased cell, then write data into a selected at least first instance erased cell, it is smeared with the entity in replacement data area 602 Except unit.

The entity erased cell for logically belonging to system area 606 is to record about type nonvolatile The system data of module 406.For example, system data includes the manufacturer about reproducible nonvolatile memorizer module 406 With the number of memory crystal grain belonging to model, reproducible nonvolatile memorizer module 406, entity erased cell number, each Entity program unit number of entity erased cell etc..

Logically belonging to replace the entity erased cell in area 608 is to replace program for bad entity erased cell, to take The entity erased cell of generation damage.Specifically, still there are normal entity erased cell and data if replacing in area 608 When the entity erased cell damage in area 602, memorizer control circuit unit 404 (or memory management circuitry 502) can be from substitution Normal entity erased cell is selected in area 608 to replace the entity erased cell of damage.

In particular, the data field 602 of reproducible nonvolatile memorizer module 406, idle area 604, system area 606 with Replace the quantity of the entity erased cell in area 608 can be different according to different memory specifications.Further, it is necessary to understand It is that in the running of memorizer memory devices 10, entity erased cell is associated with to data field 602, idle area 604, system area 606 It can dynamically be changed with the grouping relationship in substitution area 608.For example, when the entity erased cell damage in idle area 604 is taken For area 608 entity erased cell replace when, then originally replace area 608 entity erased cell can be associated to idle area 604. Or from idle area 604 entity erased cell is selected come after storing write-in data, memorizer control circuit unit 404 (or is deposited Reservoir manages circuit 502) this entity erased cell can be associated with to data field 602 and will be corresponded to the logic of data be written Unit image so far entity erased cell.

Fig. 7 is the device of the management reproducible nonvolatile memorizer module according to the first exemplary embodiment Schematic diagram.Fig. 6, Fig. 7 is cooperated to illustrate the management framework of the device of reproducible nonvolatile memorizer module below.

Please refer to Fig. 7, it is assumed that the configured logic list of memorizer control circuit unit 404 (or memory management circuitry 502) First LBA (0)~LBA (H) comes entity erased cell 410 (0)~410 (F-1) in Image Data area 602, and host system 11 It is that the data in data field 602 are accessed by logic unit LBA (0)~LBA (H).Here, each logic unit LBA (0) ~LBA (H) can be to be made of one or more logical addresses.For example, logic unit can be logical blocks (logical Block), logical page (LPAGE) (logical page) or logic sector (logical sector).One logic unit can be Image to one or more solid elements, wherein solid element can be one or more physical address, one or more entities fan, one or Multiple entity program units or one or more entity erased cells.

In this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) can establish logic Turn physical address mapping table (logical to physical address mapping table) and turn logical address with entity to reflect As table (physical to logical address mapping table), with record logic unit (e.g., logical blocks, patrol Volume page or logic sector) with reflecting between solid element (e.g., entity erased cell, entity program unit, entity sector) As relationship.In other words, memorizer control circuit unit 404 (or memory management circuitry 502) can turn physical address by logic Mapping table searches the solid element of a logic unit institute image, and memorizer control circuit unit 404 (or memory management Circuit 502) logical address mapping table can be turned by entity to search the logic unit of a solid element institute image.When memory control When circuit unit 404 (or memory management circuitry 502) processed is intended to update the image of some logic unit, this corresponding logic unit institute The logic of category, which turns physical address mapping table, can be loaded on buffer storage to be updated.Similarly, memorizer control circuit list Member 404 also accordingly can turn logical address mapping table by more novel entities.

As an example it is assumed that memorizer control circuit unit 404 (or memory management circuitry 502) configured logic unit LBA (0)~LBA (H) comes entity erased cell 410 (0)~410 (F-1) in Image Data area 602, and there are a data to be intended to It is written to logic unit LBA (0).If when logic unit LBA (0) not yet image to any entity erased cell, memory control Circuit unit 404 (or memory management circuitry 502) processed can select entity erased cell (e.g. a, entity from idle area 604 Erased cell 410 (F)) store this data.Also, after this data to entity erased cell 410 (F) are written, memory control Entity erased cell 410 (F) can be associated with to data field 602 by circuit unit 404 (or memory management circuitry 502) processed, will be patrolled Volume unit LBA (0) image records the logical address and logic list of logic unit LBA (0) to entity erased cell 410 (F) The physical address of the entity erased cell 410 (F) of first LBA (0) institute image, turns physical address mapping table and entity with more new logic Turn logical address mapping table.

Fig. 8 is that logic shown by an exemplary embodiment according to the present invention turns physical address mapping table and entity turns logic The schematic diagram of address mapping table.

Fig. 8 is please referred to, in this exemplary embodiment, it is assumed that logic unit is, for example, logical page (LPAGE), and memory controls Circuit unit 404 (or memory management circuitry 502) can configure multiple entity program units to be mapped to host system Multiple logic units (logical page (LPAGE)).For ease of description, turn physical address mapping table 820 and entity in this simple hypothesis logic Turn the image relationship between 8 logic units of record of logical address mapping table 830 and 8 entity program units.

As an example it is assumed that the logical address of 8 logic unit A~H is respectively logical address 801 (0)~801 (7), and And the physical address of 8 entity program unit a~h is respectively physical address 901 (0)~901 (7).Logic turns physical address Mapping table 820 has recorded logical address 801 (0)~801 (7) of 8 logic unit A~H and is respectively mapped to 8 logics Physical address 901 (0)~901 (7) of 8 entity program unit a~h of unit A~H.In simple terms, also referred to as logic Address 801 (0)~801 (7) images to physical address 901 (0)~901 (7).For example, can be searched by logical address 801 (0) To physical address 901 (7), and may know that image to counterlogic address 801 (0) logic unit A entity program list Member is the entity program unit h that physical address is physical address 901 (7).And so on, physical address image is turned according to logic Table 820, it is known that logical address 801 (1) image to physical address 901 (3)；Logical address 801 (2) image is to physical address 901 (4)；Logical address 801 (3) image is to physical address 901 (5)；Logical address 801 (4) image is to physical address 901 (2)；It patrols Address 801 (5) image is collected to physical address 901 (1)；Logical address 801 (6) image is to physical address 901 (6)；Logical address 801 (7) images are to physical address 901 (0).In other words, physical address mapping table 820 is turned according to logic, it is known that logic unit A reflects As to entity program unit h；Logic unit B image is to entity program unit d；Logic unit C image is to entity program Unit e；Logic unit D image is to entity program unit f；Logic unit E image is to entity program unit c；Logic unit F Image is to entity program unit b；Logic unit G image is to entity program unit g；Logic unit H image is to entity program Change unit a.

Relatively, entity turns the physical address that logical address mapping table 830 has recorded 8 entity program unit a~h 901 (0)~901 (7) and respectively image to 8 entity program units a~h 8 logic unit A~H logically Location 801 (0)~801 (7).

For example, turning logical address mapping table 830 according to entity, it is known that physical address 901 (0) image to logical address 801 (7)；Physical address 901 (1) image is to logical address 801 (5)；Physical address 901 (2) image is to logical address 801 (4)；It is real Body address 901 (3) image is to logical address 801 (1)；Physical address 901 (4) image is to logical address 801 (2)；Physical address 901 (5) images are to logical address 801 (3)；Physical address 901 (6) image is to logical address 801 (6)；Physical address 901 (7) Image is to logical address 801 (0).In other words, logical address mapping table 830 is turned according to entity, it is known that entity program unit a reflects As to logic unit H；Entity program unit b image is to logic unit F；Entity program unit c image is to logic unit E； Entity program unit d image is to logic unit B；Entity program unit e image is to logic unit C；Entity program unit f Image is to logic unit D；Entity program unit g image is to logic unit G；Entity program unit h image is to logic unit A。

It should be noted that above-mentioned logic turns physical address mapping table and entity turns component possessed by logical address mapping table Number be it is illustrative, limit the present invention.Manufacturer can take the logical address of other numbers, the quantity of entity state and shape Formula comes that design logic turns physical address mapping table and entity turns logical address mapping table.

In this exemplary embodiment, when memorizer control circuit unit 404 (or memory management circuitry 502) is intended to data When write-in to an entity erased cell, memorizer control circuit unit 404 (or memory management circuitry 502) judges this reality Whether body erased cell or will be fully written.If this entity erased cell or will be fully written, memory control electricity Road unit 404 (or memory management circuitry 502) can select another entity erased cell as making at present from idle area 604 Entity erased cell, to continue to write to data so far entity erased cell used at present.In addition, memorizer control circuit The entity that unit 404 (or memory management circuitry 502) can store valid data to one or more in data field 602 is erased Unit executes data and merges (merging) program or garbage reclamation (garbage collection) program, with release one or Multiple entity erased cells are simultaneously associated with to idle area 604.For example, memorizer control circuit unit 404 (or memory management Circuit 502) data for belonging to a logic unit can be written to the entity erased cell selected from idle area 604 and The partial data of image original in a data field 602 so far entity erased cell of logic unit is denoted as invalid data. Then, memorizer control circuit unit 404 (or memory management circuitry 502) can be by the reality of this original image so far logic unit It is from the selected entity erased cell in idle area 604 and this is original to copy to this for remaining valid data in body erased cell One entity erased cell of image so far logic unit is associated with to idle area 604.Whereby, primary data are completed and merge journey Sequence.In garbage reclamation program, the valid data stored by one or more entity program units in data field 602 can be answered Make the reality that one or more the entity erased cells selected from idle area 604 and stored valid data have all been replicated Body erased cell can be associated to idle area 604.The entity erased cell for being associated to idle area 604 can close again after being erased It erases again after being coupled to idle area 604 or association to idle area 604, does not limit the time point erased herein.

In general, record valid data are associated with the method for invalid data with garbage collection operation.According to this Storage management method provided by exemplary embodiment, can only expend the short time and can be certainly according to adjustment instruction come more (record is about the logical address and physical address for storing invalid data for the logical address and physical address of new storage invalid data Information).In this way, can be according to updating/record about the logical address and physical address that store invalid data Information executes garbage collection operation, to promote the efficiency of garbage reclamation.Wherein, in this exemplary embodiment, adjustment instruction is used To indicate that the data stored by at least logic unit in the logic unit are invalid, and adjustment instruction can be arrangement Instruct (trim command), deletion instruction (delete command) ... or other instructions.Below for ease of description, will It is explained using housekeeping instruction (trim command) as adjustment instruction.

Specifically, in this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) It will use multiple logics that logical address state table (logical valid table) Lai Fanying (record) is stored in host system The data mode (e.g., effective status or invalid state) of data in unit, with thereafter can via search logical address shape State table judges whether the data being stored in multiple logic units of host system are effective.Similarly, memory controls Circuit unit 404 (or memory management circuitry 502) will use physical address state table (physical valid table) Reaction (record) is stored in data mode (e.g., the effective status or invalid of the data in multiple solid elements of host system State), can judge in the multiple solid elements for being stored in host system via physical address state table is searched thereafter Whether data are effective.In other words, when memorizer control circuit unit 404 (or memory management circuitry 502) receives After adjustment instruction, memorizer control circuit unit 404 (or memory management circuitry 502) can the nothing according to indicated by adjustment instruction The logical address of effect data comes accordingly more new logical addresses state table and physical address state table.In this way, memory control Circuit unit 404 (or memory management circuitry 502) processed can utilize logical address state table and physical address state table institute anti- What should be gone out is stored in the data mode of the data of logical address or physical address further to be managed (for example, garbage reclamation Operation).Can arrange in pairs or groups below Fig. 9, Figure 10, with Figure 11 carry out storage management method provided by the present invention will be described in detail, can have The received adjustment instruction of effect ground processing institute.

Fig. 9 is shown by an exemplary embodiment according to the present invention according to adjustment instruction more new logical addresses state table Schematic diagram.

Referring to FIG. 9, as an example it is assumed that logical address state table 920 records the logical address for having logic unit A~H 801 (0)~801 (7) and data mode 802 (0)~802 for being separately stored in logical address 801 (0)~801 (7) data (7).Wherein, data mode may include first state (e.g., first state is marked as " 1 ") or second state (e.g., the second state It is marked as " 0 ").In the present embodiment, first state is to indicate that the data for being stored in logical address are effective, and the Two-state is to indicate that the data for being stored in logical address are invalid, however, the present invention is not limited theretos.For example, in another embodiment In, first state is to indicate that the data for being stored in logical address are invalid, and the second state is patrolled to indicate to be stored in It is effective for collecting the data of address.In addition, manufacturer can also indicate first state and the second state using other suitable methods. For example, first state can be marked as " 1 " or " 00 ", and the second state can be marked as " 0 " or " 11 ".

From Fig. 9, it can be seen that, being stored in logical address 801 (0)~801 (7) data is all first state (e.g., " 1 "), That is it is all effective for being stored in logical address 801 (0)~801 (7) data.Assuming that memorizer control circuit unit 404 (or memory management circuitry 502) receives adjustment instruction 910 from host system 11, and the wherein instruction of adjustment instruction 910 is stored in Logic unit 801 (0), the data of 801 (1) have become invalid (e.g., the data mode of this data is the second state).Then, Memorizer control circuit unit 404 (or memory management circuitry 502) can be according to adjustment instruction 910 come more new logical addresses state Table 920.Specifically, memorizer control circuit unit 404 (or memory management circuitry 502) can be according to this adjustment instruction, will Counterlogic address 801 (0), the data mode 802 (0) of 801 (1), 802 (1) are adjusted to " 0 " from " 1 ", with more new logical addresses State table 920 is updated logical address state table (updated logical valid table) 921.

It should be noted that component count possessed by above-mentioned adjustment instruction and logical address state table is illustrative, and Do not limit the present invention.Manufacturer can take the logical address of other numbers, the quantity of data mode and form to design adjustment instruction Or logical address state table.

Figure 10 is the schematic diagram of physical address state table shown by an exemplary embodiment according to the present invention.

Figure 10 is please referred to, in this exemplary embodiment, as described above, memorizer control circuit unit 404 (or memory pipe Reason circuit 502) an at least physical address state table can be established to record the data shape for the data being stored in multiple solid elements State can determine whether the data being stored in these solid elements are effective whereby.Specifically, memorizer control circuit unit 404 (or memory management circuitries 502) can be real by least one of an at least entity program unit with storage valid data Body unit (also known as super block, super block) is divided into data link (Data link).The solid element example Entity erased cell in this way or physical blocks.In this exemplary embodiment, there is the solid element 1 entity to erase list Member.However, in other embodiments, the solid element can also have other several destination entity erased cells.The data-link Knot one physical address state table of configuration.The physical address state table records multiple entity programs of an at least solid element Change the physical address of each entity program unit in unit and multiple entity programs of an at least solid element The data mode of the data stored by each entity program unit in unit.In other words, real in this exemplary embodiment Body address state table can reflect the physical address of multiple entity program units in corresponding data link with it is corresponding Data mode.It should be noted that in another embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) It can be multiple data link by multiple entity program dividing elements of image to the logic unit, wherein the data-link knot Each data link may be configured with a physical address state table.For simple illustration, below in an example, with right There should be the entity journey of the physical address state table of the data link an of solid element, the solid element of corresponding this data link Sequence unit makees example with image logic unit A~H that so far data chain, and wherein this solid element has 5 entity journeys Sequence unit a~h.

For example, the logical address state table being similar in Fig. 9, it is assumed that memorizer control circuit unit 404 (or storage Device manages circuit 502) physical address state table 1010 has had been established, wherein physical address state table has recorded correspondent entity program Change physical address 901 (0)~901 (7) and the number for the data being stored in physical address 901 (0)~901 (7) of unit a~h According to state 902 (0)~902 (7).According to the mode for judging data mode in the example of above-mentioned Fig. 9, it is to be understood that the logic in Figure 10 Data stored by unit A~C are invalid (e.g., being labeled as " 0 "), and the data stored by logic unit D~H are effective (e.g., be labeled as " 1 ").It should be noted that component count possessed by above-mentioned physical address state table be it is illustrative, not Limit the present invention.Manufacturer can take the physical address of other numbers, the quantity of data mode and form to carry out design entity address shape State table.

In this exemplary embodiment, when memorizer control circuit unit 404 (or memory management circuitry 502) receives tune After whole instruction, memorizer control circuit unit 404 (or memory management circuitry 502) understands first more new logical addresses state table.It changes Sentence is talked about, and reacts on the received adjustment instruction of institute, memorizer control circuit unit 404 (or memory management circuitry 502) can more New logical addresses state table, but physical address state table is not updated.Also, after having updated logical address state table, memory Control circuit unit 404 (or memory management circuitry 502) can respond to host system and handle the received adjustment instruction of institute It finishes.

It is noted that multiple logical addresses as indicated by adjustment instruction be all mostly continuous and image so far The physical address of a little logical addresses is possible to discontinuous.Therefore, by only more new logical addresses state table without updating physically Location state table can be effectively saved the time for completing processing adjustment instruction.

However, memorizer control circuit unit 404 (or memory management circuitry 502) meeting exists in this exemplary embodiment Scheduled opportunity point updates physical address state table.Specifically, (or the memory management of memorizer control circuit unit 404 Circuit 502) it can be according to judging whether host system meets a predetermined condition, to determine whether to update physical address state table. For example, if host system 11 is idle (for example, host system does not carry out write-in and read action grasped a predetermined time) When, memorizer control circuit unit 404 (or memory management circuitry 502) can determine to conform to a predetermined condition.In another example storing Device control circuit unit 404 (or memory management circuitry 502) determines that garbage collection operation should be carried out to storage device at present, sentences Surely it conforms to a predetermined condition.In another example if memorizer control circuit unit 404 (or memory management circuitry 502) has resource can be with When being updated operation (e.g., carry out continuous read operation, or carry out power operation) of physical address state table, symbol is determined Close predetermined condition.

If it is determined that conforming to a predetermined condition, memorizer control circuit unit 404 (or memory management circuitry 502) can be according to The logical address state table 921 of update updates physical address state table 1010 with physical address state table 1010.Specifically, If conforming to a predetermined condition, memorizer control circuit unit 404 (or memory management circuitry 502) can be according to the logical address The comparison result of state table and physical address state table updates the physical address state table.In more detail, if meeting Predetermined condition, memorizer control circuit unit 404 (or memory management circuitry 502) can be from the selections of physical address state table at least One physical address, and according to selected physical address and logical address state table, to compare corresponding selected physical address Logical address data mode and selected physical address data mode.

In this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) can be via entity Address state table sequentially checks an at least solid element described in data link with predetermined order.Memorizer control circuit Unit 404 (or memory management circuitry 502) can select the physical address being compared whereby.

In more detail, memorizer control circuit unit 404 (or memory management circuitry 502) can with predetermined order come according to Sequence checks the multiple physical address that are recorded of physical address state table 1010 and corresponding multiple data modes, with the corresponding reality of identification Data mode is multiple physical address of first state in body address state table 1010.Wherein, the predetermined order be, for example, from The provider location of foremost to rearmost physical address, from rearmost provider location to the physical address of foremost, or The time of the physical address and data mode that are recorded according to physical address state table, by the earliest time to time the latest Sequentially.

For example, if it is determined that conforming to a predetermined condition, memorizer control circuit unit 404 (or memory management circuitry It 502) can be according to selection data mode in multiple physical address 901 (0)~901 (7) that physical address state table 1010 is recorded For the physical address (following to be also known as, first instance address) of first state (e.g., " 1 ").For ease of description, first selected The quantity of physical address is set as 1 herein, however, the present invention is not limited thereto, manufacturer can the suitable quantity of sets itself select One physical address.For example, memorizer control circuit unit 404 (or memory management circuitry 502) can select data mode for The physical address 901 (3) of one state is used as first instance address.

In this exemplary embodiment, it is assumed herein that the predetermined order is the entity recorded according to physical address state table The time of address and data mode, by the earliest time to the sequence of time the latest.In above-mentioned memorizer control circuit unit 404 (or memory management circuitries 502) can sequentially check that physical address state table 1010 is recorded multiple with predetermined order Physical address in the running of corresponding multiple data modes, (or the memory management circuitry of memorizer control circuit unit 404 502) first instance sequentially can be selected and (to be checked) according to record physical address with the time order and function of corresponding data mode Address.In more detail, it is assumed that the physical address 901 (0) that physical address state table 1010 is recorded~901 (7) are according to note The time order and function of record records down since the first column of physical address state table.In other words, in physical address state table In 1010, physical address 901 (0) is one be recorded in physical address state table earliest with corresponding data mode 902 (0) Notes record, and physical address 901 (7) is to be recorded in physical address state table the latest with corresponding data mode 902 (7) One notes record.Accordingly, memorizer control circuit unit 404 (or memory management circuitry 502) can be according to physical address 901 (0)~901 (7) sequentially judge that physical address 901 (0)~901 (7) are corresponding with the position of corresponding data mode from top to bottom Data mode whether be first state.For example, memorizer control circuit unit 404 (or memory management circuitry 502) can be from Physical address 901 (0) starts to judge with data mode 902 (0), and memorizer control circuit unit 404 (or memory pipe Reason circuit 502) physical address of found first data mode for first state can be physical address 901 (3).It connects , it is real as first that memorizer control circuit unit 404 (or memory management circuitry 502) can select physical address 901 (3) Body address, with compared according to logical address state table image to first instance address the first logical address data mode with The data mode of first instance address, and then execute the subsequent update for physical address state table 1010 and operate.It should be noted that , operated when having handled the update by physical address 901 (3) as the physical address state table 1010 of first instance address Afterwards, memorizer control circuit unit 404 (or memory management circuitry 502) can connect judgement pair according to judgement sequence above-mentioned Answer the data mode 902 (4) of physical address 901 (4).And so on, memorizer control circuit unit 404 (or memory management Circuit 502) it can determine whether physical address 901 (0)~901 (7) data mode 902 in all physical address state tables 1010 (0)~902 (7), and then completion operates the update of physical address state table 1010.

It is noted that the present invention is not limited to the modes of above-mentioned selection first instance address.For example, in another implementation Example in, memorizer control circuit unit 404 (or memory management circuitry 502) will record physical address 901 (0)~901 (7) with Corresponding data mode 902 (0)~902 (7) are in physical address state table 1020, and memorizer control circuit unit 404 (or memory management circuitry 502) can also will record physical address 901 (0)~901 (7) and corresponding data mode 902 (0)~ The time of 902 (7) is recorded in time label 1001 (0)~1001 (7).In this way, memorizer control circuit unit 404 (or memory management circuitry 502) can be come sequentially by the time order and function for judging that time label 1001 (0)~1001 (7) are recorded Judge the data mode of physical address.For example, correspondent entity address 901 (0)~901 (7) and corresponding data mode 902 (0)~902 the time label 1001 (0) of (7)~1001 (7) are respectively (" 1 ", " 2 ", " 3 ", " 4 ", " 5 ", " 6 ", " 7 ", " 8 "), Wherein the digital smaller time for indicating record is more early.That is, memorizer control circuit unit 404 (or memory management electricity Road 502) whether data mode can be judged to physical address 901 (0) from physical address 901 (7) according to the time of record For first state.For example, memorizer control circuit unit 404 (or memory management circuitry 502) can first judge physical address 901 (0) data mode 1001 (0), and finally judge the data mode 1001 (7) of physical address 901 (7).In this way, by In the physical address that first data mode is first state be 901 (3), (or the memory pipe of memorizer control circuit unit 404 Reason circuit 502) physical address 901 (3) can be selected as first instance address.

In this exemplary embodiment, after selecting first instance address, memorizer control circuit unit 404 (or memory Management circuit 502) according to entity can turn logical address mapping table, logical address state table and first instance address to determine whether The data mode that first instance address is corresponded in physical address state table need to be updated.

Specifically, memorizer control circuit unit 404 (or memory management circuitry 502) can turn logically according to entity Location mapping table recognizes the first logical address of first instance address institute image.Then, memorizer control circuit unit 404 (or Memory management circuitry 502) corresponding first logical address can be judged with the first logical address according to logical address state table Whether data mode is the second state.If the data mode of corresponding first logical address is second in logical address state table (e.g., the data mode of corresponding first logical address is different from corresponding in physical address state table state in logical address state table The data mode of first instance address), memorizer control circuit unit 404 (or memory management circuitry 502) can determine to need It updates and corresponds to the data mode of first instance address in physical address state table, and memorizer control circuit unit 404 (or deposit Reservoir manages circuit 502) data mode that first instance address is corresponded in physical address state table can be adjusted from first state For the data mode (e.g., the second state) of the first logical address corresponding in logical address state table.

Figure 11 is the schematic diagram that physical address state table is updated shown by an exemplary embodiment according to the present invention.

For example, Figure 11 is please referred to, it is assumed that memorizer control circuit unit 404 (or memory management circuitry 502) is Select data mode for the first instance address 901 (3) of first state (e.g., " 1 ") from physical address state table 1010.It deposits Memory control circuit unit 404 (or memory management circuitry 502) can turn logical address mapping table 830 and first in fact according to entity The logical address 801 (1) (also known as, the first logical address) of body address 901 (3) identification first instance address 901 (3) institute image (as shown in arrow 1101).Then, memorizer control circuit unit 404 (or memory management circuitry 502) can be according to logically Location state table 921 and the first logical address 801 (1) judge the number of the first logical address 801 (1) in logical address state table It whether is the second state (e.g., " 0 ") (as shown in arrow 1102) according to state 802 (1).In this example, due to logical address 801 (1) data mode 802 (1) is the second state (being the data mode of first state different from first instance address), therefore, Memorizer control circuit unit 404 (or memory management circuitry 502) can be by the first instance in physical address state table 1010 The data mode 902 (3) of address 901 (3) is adjusted to the second state from first state (as shown in arrow 1103).In this way, Via above-mentioned process, memorizer control circuit unit 404 (or memory management circuitry 502) is just completed for physical address The update of the data mode of first instance address 901 (3) selected in state table 1010 operates.

As described above, memorizer control circuit unit 404 (or memory management circuitry 502) can continue to select physical address State table is other physical address (e.g., physical address 901 (4)~901 (7)) of first state to be updated operation, side Method is similar to above-mentioned example, repeats no more in this.

It is noted that the utilisation system idle time comes more according to above-mentioned provided storage management method Novel entities address state table is returned when memorizer control circuit unit 404 (or memory management circuitry 502) carries out rubbish whereby It brings drill to an end when making, memorizer control circuit unit 404 (or memory management circuitry 502) can directly be distinguished via physical address state table The physical address (e.g., the physical address that corresponding data state is the second state) for knowing storage invalid data, is not required to expend other moneys Source judges in current storage device the address of stored invalid data, and then promotes the efficiency of garbage reclamation.

Please refer to Figure 12, in step S1201, memorizer control circuit unit 404 (or memory management circuitry 502) from Host system receives adjustment instruction, wherein the adjustment instruction is to indicate at least logic unit institute in multiple logic units The data of storage are invalid.In step S1203, memorizer control circuit unit 404 (or memory management circuitry 502) meeting According to the adjustment instruction more new logical addresses state table, wherein the logical address state table is to reflect the logic list The data mode of the data stored by each logic unit in member, wherein the data mode includes first state or the second shape State.In step S1205, if conforming to a predetermined condition, memorizer control circuit unit 404 (or memory management circuitry 502) The physical address state table can be updated according to the logical address state table and physical address state table, wherein the entity Institute of the address state table to reflect the data stored by each entity program unit in multiple entity program units State data mode.In step S1207, memorizer control circuit unit 404 (or memory management circuitry 502) has understood foundation more The new physical address state table erases to an at least invalid data.

As described above, the storage management method according to provided by this exemplary embodiment, it can be according to the pass for updating/recording Garbage collection operation is executed in the information of the logical address and physical address that store invalid data, to promote garbage reclamation Efficiency.Specifically, in this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) can root Physical address state table is certainly updated according to adjustment instruction, wherein updated physical address state table (also known as, has updated reality Body address state table) recorded data state truly (reliably) can reflect to be stored in and updated physical address state table In the data of physical address be effective or invalid.In this way, in garbage collection operation, memorizer control circuit list First 404 (or memory management circuitries 502) can store significant figure recorded in physical address state table according to having updated According to an at least physical address come (part or whole) live data of collecting at least one, and then avoid meaningless collection (that is, the data being collected actually invalid data).In addition, in garbage collection operation, memorizer control circuit unit 404 (or memory management circuitry 502) can also recognize its for having updated and having stored invalid data recorded in physical address state table A his at least physical address erase to the invalid data of at least one (all or part of), and then releases more Physical storage space.As for, about the collection of the valid data in conventional rubbish reclaimer operation and erasing for invalid data, For those skilled in the art institute conventional techniques, repeat no more in this.

In conclusion storage management method provided by exemplary embodiment of the invention, memorizer control circuit unit With memorizer memory devices, can according to the received adjustment instruction more new logical addresses state table of institute, and system spare time by Physical address state table is updated by updated logical address state table, to reduce the time spent by processing adjustment instruction, And then promote working efficiency.

Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field Middle those of ordinary skill, it is without departing from the spirit and scope of the present invention, therefore of the invention when can make a little change and retouching Protection scope is subject to view appended claims confining spectrum.

Claims

1. a kind of storage management method is used for a reproducible nonvolatile memorizer module, which is characterized in that described to answer The formula non-volatile memory module of writing includes multiple entity erased cells, wherein each entity of the multiple entity erased cell Erased cell has multiple entity program units, wherein the multiple entity program unit image is to multiple logic units, The storage management method includes:

An adjustment instruction is received from a host system, wherein the adjustment instruction is to indicate in the multiple logic unit extremely Data stored by a few logic unit are invalid；

A logical address state table is updated according to the adjustment instruction, wherein the logical address state table is described to reflect One data mode of the data stored by each logic unit in multiple logic units, wherein the data mode includes one the One state or one second state；

If meeting a predetermined condition, according to a comparison result of the logical address state table and a physical address state table come The physical address state table is updated, wherein the physical address state table is to reflect the multiple entity program unit The number stored by each entity program unit in multiple entity program units of the middle correspondence physical address state table According to the data mode, wherein according to the comparison result of the logical address state table and the physical address state table Include: the step of the physical address state table to update

If meeting the predetermined condition, according to the physical address state table, reflected from the physical address state table Multiple physical address in select the data mode for a first instance address of the first state；And

The first instance is corresponded to determine whether need to update in the physical address state table according to the first instance address The data mode of address；And

It is erased according to the updated physical address state table to an at least invalid data.

2. storage management method according to claim 1, which is characterized in that if above-mentioned meet the predetermined condition, The physical address shape is updated according to the comparison result of the logical address state table and the physical address state table The step of state table includes:

According to an entity turn logical address mapping table, the logical address state table and the first instance address to determine whether The data mode that the first instance address is corresponded in the physical address state table need to be updated.

3. storage management method according to claim 2, which is characterized in that above-mentioned to turn logical address according to the entity Mapping table, the logical address state table and the first instance address are to determine whether the physical address state table need to be updated The step of data mode of the middle correspondence first instance address includes:

Turn logical address mapping table according to the entity to recognize one first logical address of first instance address institute image；

It is compared with first logical address in the logical address state table according to the logical address state table and corresponds to institute It states in the data mode and the physical address state table of the first logical address and corresponds to the described of the first instance address Data mode；And

If the data mode for corresponding to first logical address in the logical address state table is different from the entity The data mode of the first instance address is corresponded in address state table, judgement need to update in the physical address state table The data mode of the corresponding first instance address, and the first instance will be corresponded in the physical address state table The data mode of address is adjusted to correspond to described first logically in the logical address state table from the first state The data mode of location, wherein the data mode for corresponding to first logical address in the logical address state table is Second state.

4. storage management method according to claim 1, which is characterized in that if above-mentioned meet the predetermined condition, According to the physical address state table, institute is selected from the multiple physical address that the physical address state table is reflected Data mode, which is stated, as the step of first instance address of the first state includes:

According to the multiple physical address that reflects and the data mode for respectively corresponding the multiple physical address when Between, with oldest to newest sequence, the data mode of the corresponding the multiple physical address of sequentially judgement；And

Selecting the data mode is a physical address of the first state as the first instance address.

5. storage management method according to claim 1, which is characterized in that further include:

If the host system is idle, garbage collection operation or the operation for having resource that can be updated physical address state table When, judgement meets the predetermined condition.

6. storage management method according to claim 1, which is characterized in that the logical address state table reflects institute Multiple logical addresses of multiple logic units and the data mode of corresponding the multiple logical address are stated, wherein described in corresponding Data mode is that the data stored by a logic unit of a logical address of the first state are effective, and correspond to institute State data mode be second state a logical address a logic unit stored by data be it is invalid,

Wherein the physical address state table reflects multiple physical address of the multiple entity program unit and corresponding institute The data mode of multiple physical address is stated, wherein corresponding to the physical address that the data mode is the first state Data stored by one entity program unit are effective, and the correspondence data mode is a reality of second state Data stored by one entity program unit of body address are invalid.

7. storage management method according to claim 6, which is characterized in that it is above-mentioned according to it is updated it is described physically Location state table includes: to described the step of at least an invalid data is erased

Data described in the updated physical address state table are recognized according to the updated physical address state table State is an at least second instance address for second state and the data mode is at least the 1 the of the first state Three physical address；And

A garbage collection operation is executed according to an at least second instance address and an at least third physical address, A middle at least second instance address according to executes the garbage collection operation with an at least third physical address Step includes:

Collect at least valid data being stored in an at least third physical address；And

It erases at least invalid data being stored in an at least second instance address.

8. storage management method according to claim 1, which is characterized in that further include:

An at least solid element for at least entity program unit for having storage valid data is divided into data link, Wherein the data-link knot is configured with the physical address state table, wherein the physical address state table is described to reflect The physical address of each entity program unit in multiple entity program units of an at least solid element and it is described extremely The data of the data stored by each entity program unit in multiple entity program units of a few solid element State,

If wherein above-mentioned meet the predetermined condition, according to the logical address state table and the physical address state table The comparison result includes: the step of the physical address state table to update

An at least solid element described in data link is checked in a predetermined order via the physical address state table.

9. storage management method according to claim 8, which is characterized in that above-mentioned via the physical address state table Include: the step of an at least solid element described in the data link to check with the predetermined order

With the predetermined order come sequentially check the multiple physical address that the physical address state table is reflected with it is right The multiple data modes answered are the more of the first state to recognize data mode described in the corresponding physical address state table A physical address；And

An at least physical address, and root is selected from the multiple physical address that the data mode is the first state According to an at least logical address for an at least physical address, image to an at least physical address, to compare the logic The data shape of the data mode of an at least logical address described in address state table and an at least physical address State.

10. a kind of memorizer control circuit unit, for controlling a memorizer memory devices, which is characterized in that the memory Control circuit unit includes:

One host interface is electrically connected to a host system；

One memory interface is electrically connected to a reproducible nonvolatile memorizer module, wherein the duplicative is non-easily The property lost memory module includes multiple entity erased cells, wherein each entity erased cell of the multiple entity erased cell With multiple entity program units, wherein the multiple entity program unit image is to multiple logic units；

One memory management circuitry is electrically connected to the host interface and the memory interface, wherein the memory pipe Circuit is managed to receive an adjustment instruction from the host system, wherein the adjustment instruction is to indicate the multiple logic list The data at least stored by a logic unit in member be it is invalid,

Wherein the memory management circuitry is more to update a logical address state table according to the adjustment instruction, wherein described A data of the logical address state table to reflect the data stored by each logic unit in the multiple logic unit State, wherein the data mode includes a first state or one second state,

If wherein meeting a predetermined condition, the memory management circuitry is more to according to the logical address state table and one One comparison result of physical address state table updates the physical address state table, wherein the physical address state table to It reflects in the multiple entity program units for corresponding to the physical address state table in the multiple entity program unit The data mode of data stored by each entity program unit, wherein the memory management circuitry is more to basis The comparison result of the logical address state table and the physical address state table updates the physical address state table Running in,

If meeting the predetermined condition, the memory management circuitry is according to the physical address state table, from the entity Select the data mode for a first instance of the first state in multiple physical address that address state table is reflected Address,

The memory management circuitry is according to the first instance address to determine whether the physical address state table need to be updated The data mode of the middle correspondence first instance address,

Wherein the memory management circuitry more to according to the updated physical address state table to an at least invalid number According to erasing.

11. memorizer control circuit unit according to claim 10, which is characterized in that if it is above-mentioned meet it is described pre- Fixed condition, the memory management circuitry is more to the institute according to the logical address state table and the physical address state table Comparison result is stated to update in the running of the physical address state table,

Wherein the memory management circuitry according to an entity turn logical address mapping table, the logical address state table with it is described First instance address is to determine whether the number for corresponding to the first instance address in the physical address state table need to be updated According to state.

12. memorizer control circuit unit according to claim 11, which is characterized in that in memory management described above Circuit turns logical address mapping table, the logical address state table with the first instance address to judge to be according to the entity In the no running that need to update the data mode for corresponding to the first instance address in the physical address state table,

The memory management circuitry turns logical address mapping table according to the entity to recognize the first instance address and be reflected One first logical address of picture,

Wherein the memory management circuitry compares described according to the logical address state table and first logical address The data mode that first logical address is corresponded in logical address state table is corresponding with the physical address state table The data mode of the first instance address,

If the data mode for wherein corresponding to first logical address in the logical address state table is different from described The data mode of the first instance address is corresponded in physical address state table, the memory management circuitry determines to need more Correspond to the data mode of the first instance address in the new physical address state table, and by the physical address shape The data mode that the first instance address is corresponded in state table is adjusted to the logical address state from the first state The data mode of first logical address is corresponded in table, is patrolled wherein corresponding to described first in the logical address state table The data mode for collecting address is second state.

13. memorizer control circuit unit according to claim 10, which is characterized in that if it is above-mentioned meet it is described pre- Fixed condition, the memory management circuitry are reflected according to the physical address state table from the physical address state table The multiple physical address in select in running of the data mode for the first instance address of the first state,

The memory management circuitry is according to the multiple physical address reflected and respectively corresponds the multiple physical address The data mode time, with oldest to newest sequence, the number of the corresponding the multiple physical address of sequentially judgement According to state,

Wherein the memory management circuitry selects described in physical address conduct of the data mode for the first state First instance address.

14. memorizer control circuit unit according to claim 10, which is characterized in that

If the host system is idle, garbage collection operation or the behaviour for having resource that can be updated physical address state table Make, the memory management circuitry judgement meets the predetermined condition.

15. memorizer control circuit unit according to claim 10, which is characterized in that the logical address state table is anti- Multiple logical addresses of the multiple logic unit and the data mode of corresponding the multiple logical address should be gone out, wherein right It is effective for answering the data stored by the logic unit that the data mode is a logical address of the first state, and The corresponding data mode be the data stored by a logic unit of a logical address of second state be it is invalid,

16. memorizer control circuit unit according to claim 15, which is characterized in that in memory management described above Circuit more to according to the updated physical address state table in the running that an invalid data is erased described at least,

The memory management circuitry recognized according to the updated physical address state table it is updated it is described physically Data mode described in the state table of location is an at least second instance address for second state and the data mode is described An at least third physical address for first state,

Wherein the memory management circuitry is according to an at least second instance address and an at least third physical address Execute a garbage collection operation, wherein the memory management circuitry according at least second instance address with it is described In running of at least third physical address to execute the garbage collection operation,

The memory management circuitry collects at least valid data being stored in an at least third physical address,

Wherein the memory management circuitry is erased at least invalid data being stored in an at least second instance address.

17. memorizer control circuit unit according to claim 10, which is characterized in that

At least entity list that the memory management circuitry will have at least entity program unit for storing valid data Member is divided into data link, wherein the data-link knot is configured with the physical address state table, wherein the physical address Each entity program unit in multiple entity program units of the state table to reflect an at least solid element Physical address and an at least solid element multiple entity program units in each entity program unit institute The data mode of the data of storage,

If wherein meeting the predetermined condition above-mentioned, the memory management circuitry is more to according to the logical address shape In running of the comparison result of state table and the physical address state table to update the physical address state table,

The memory management circuitry checks data link in a predetermined order via the physical address state table An at least solid element.

18. memorizer control circuit unit according to claim 17, which is characterized in that in memory management described above Circuit checks an at least entity list described in data link via the physical address state table with the predetermined order In the running of member,

The memory management circuitry sequentially checks institute that the physical address state table is reflected with the predetermined order Multiple physical address and corresponding multiple data modes are stated, with data mode described in the corresponding physical address state table of identification For multiple physical address of the first state,

Wherein the memory management circuitry is selected from the multiple physical address that the data mode is the first state An at least physical address is selected, and according to an at least physical address, image at least the one of an at least physical address Logical address, come compare the data mode of an at least logical address described in the logical address state table and it is described at least The data mode of one physical address.

19. a kind of memorizer memory devices characterized by comprising

One connecting interface unit, is electrically connected to a host system；

One reproducible nonvolatile memorizer module, including multiple entity erased cells, the list wherein the multiple entity is erased Each entity erased cell of member has multiple entity program units, wherein the multiple entity program unit image is at most A logic unit；And

One memorizer control circuit unit is electrically connected to the connecting interface unit and the duplicative non-volatile memories Device module, wherein the memorizer control circuit unit to from the host system receive an adjustment instruction, wherein the tune It is whole instruction to indicate the data stored by at least logic unit in the multiple logic unit be it is invalid,

Wherein the memorizer control circuit unit more to according to the adjustment instruction update a logical address state table, wherein The logical address state table is to reflect one of the data stored by each logic unit in the multiple logic unit Data mode, wherein the data mode includes a first state or one second state,

If wherein meeting a predetermined condition, the memorizer control circuit unit is more to according to the logical address state table The physical address state table is updated with a comparison result of a physical address state table, wherein the physical address state table To reflect the multiple entity program units for corresponding to the physical address state table in the multiple entity program unit In each entity program unit stored by data the data mode, wherein the memorizer control circuit unit is more To updated according to the comparison result of the logical address state table and the physical address state table it is described physically In the running of location state table,

If meeting the predetermined condition, the memorizer control circuit unit is according to the physical address state table, from described Select the data mode for the one first of the first state in multiple physical address that physical address state table is reflected Physical address,

The memorizer control circuit unit is according to the first instance address to determine whether the physical address shape need to be updated The data mode of the first instance address is corresponded in state table,

Wherein the memorizer control circuit unit more to according to the updated physical address state table to an at least nothing Effect data are erased.

20. memorizer memory devices according to claim 19, which is characterized in that if meeting the predetermined item above-mentioned Part, the memorizer control circuit unit is more to the institute according to the logical address state table and the physical address state table Comparison result is stated to update in the running of the physical address state table,

Wherein the memorizer control circuit unit according to an entity turn logical address mapping table, the logical address state table with The first instance address is to determine whether the institute for corresponding to the first instance address in the physical address state table need to be updated State data mode.

21. memorizer memory devices according to claim 20, which is characterized in that in memorizer control circuit described above Unit turns logical address mapping table, the logical address state table with the first instance address to judge to be according to the entity In the no running that need to update the data mode for corresponding to the first instance address in the physical address state table,

The memorizer control circuit unit turns logical address mapping table according to the entity to recognize the first instance address One first logical address of institute's image,

Wherein the memorizer control circuit unit is compared according to the logical address state table with first logical address It is corresponded in the logical address state table in the data mode and the physical address state table of first logical address The data mode of the corresponding first instance address,

If the data mode for wherein corresponding to first logical address in the logical address state table is different from described The data mode of the first instance address is corresponded in physical address state table, the memorizer control circuit unit determines The data mode that the first instance address is corresponded in the physical address state table need to be updated, and by described in physically The data mode that the first instance address is corresponded in the state table of location is adjusted to the logical address from the first state The data mode of first logical address is corresponded in state table, wherein corresponding to described in the logical address state table The data mode of one logical address is second state.

22. memorizer memory devices according to claim 21, which is characterized in that if meeting the predetermined item above-mentioned Part, the memorizer control circuit unit are reflected according to the physical address state table from the physical address state table The multiple physical address in select in running of the data mode for the first instance address of the first state,

The memorizer control circuit unit is according to the multiple physical address reflected and respectively corresponds the multiple entity The time of the data mode of address, with oldest to newest sequence, the institute of the corresponding the multiple physical address of sequentially judgement Data mode is stated,

Wherein data mode described in the memorizer control circuit Unit selection is a physical address conduct of the first state The first instance address.

23. memorizer memory devices according to claim 19, which is characterized in that

If the host system is idle, garbage collection operation or the behaviour for having resource that can be updated physical address state table Make, the memorizer control circuit unit judgement meets the predetermined condition.

24. memorizer memory devices according to claim 19, which is characterized in that wherein the logical address state table is anti- Multiple logical addresses of the multiple logic unit and the data mode of corresponding the multiple logical address should be gone out, wherein right It is effective for answering the data stored by the logic unit that the data mode is a logical address of the first state, and The corresponding data mode be the data stored by a logic unit of a logical address of second state be it is invalid,

25. memorizer memory devices according to claim 24, which is characterized in that in memorizer control circuit described above Unit more to according to the updated physical address state table in the running that an invalid data is erased described at least,

The memorizer control circuit unit recognizes the updated reality according to the updated physical address state table Data mode described in body address state table is that an at least second instance address for second state is with the data mode An at least third physical address for the first state,

Wherein the memorizer control circuit unit is according to an at least second instance address and an at least third entity Address executes a garbage collection operation, wherein the memorizer control circuit unit according at least second instance In location and the running of at least third physical address to execute the garbage collection operation,

The memorizer control circuit unit collects at least valid data being stored in an at least third physical address,

What wherein the memorizer control circuit cell erasure was stored in an at least second instance address is at least one invalid Data.

26. memorizer memory devices according to claim 19, which is characterized in that

The memorizer control circuit unit is real by least one of an at least entity program unit with storage valid data Body unit is divided into data link, wherein the data-link knot is configured with the physical address state table, wherein the entity Each entity program in multiple entity program units of the address state table to reflect an at least solid element Each entity program list in multiple entity program units of the physical address of unit and an at least solid element The data mode of data stored by member,

If wherein meeting the predetermined condition above-mentioned, the memorizer control circuit unit is more described logically to basis In running of the comparison result of location state table and the physical address state table to update the physical address state table,

The memorizer control circuit unit checks the data-link in a predetermined order via the physical address state table An at least solid element for knot.

27. memorizer memory devices according to claim 26, which is characterized in that in memorizer control circuit described above Unit checks an at least entity list described in data link via the physical address state table with the predetermined order In the running of member,

The memorizer control circuit unit sequentially checks that the physical address state table is reflected with the predetermined order The multiple physical address and corresponding multiple data modes, with data described in the corresponding physical address state table of identification State is multiple physical address of the first state,

Wherein the memorizer control circuit unit from the data mode be the first state the multiple physical address A middle selection at least physical address, and extremely according to an at least physical address, image to an at least physical address A few logical address, come compare the data mode of an at least logical address described in the logical address state table with it is described The data mode of an at least physical address.