CN107122308A

CN107122308A - Average abrasion method, memory control circuit unit and internal storing memory

Info

Publication number: CN107122308A
Application number: CN201610103788.8A
Authority: CN
Inventors: 黄俊凯
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2016-02-25
Filing date: 2016-02-25
Publication date: 2017-09-01

Abstract

The present invention provides a kind of average abrasion method, memory control circuit unit and internal storing memory.The method includes choosing first instance erased cell from without the entity erased cell for having valid data according to number of times of erasing, and selection valid data amount is less than the second instance erased cell of the capacity of an entity erased cell from the entity erased cell for having valid data.The method also includes the 3rd entity erased cell for choosing capacity of the valid data amount less than an entity erased cell from the entity erased cell for having valid data according to number of times of erasing.The method also includes at least part valid data of the valid data of second instance erased cell and the 3rd entity erased cell writing first instance erased cell.The present invention can be effectively prevented from the speed for influenceing to be continuously written into because performing refuse collection.

Description

Average abrasion method, memory control circuit unit and internal storing memory

Technical field

The present invention relates to a kind of average abrasion method, more particularly to a kind of average mill for duplicative Nonvolatile memory module Damage method, memory control circuit unit and internal storing memory.

Background technology

Digital camera, mobile phone and MP3 player are very rapid in growth over the years so that consumer is to store media Demand also rapidly increase.Because duplicative Nonvolatile memory module (for example, flash memory) has data non-volatile, province Electricity, small volume, and without characteristics such as mechanical structures, so being especially suitable for being built into above-mentioned illustrated various portable multimedias In device.

In general, duplicative Nonvolatile memory module can be used with host computer system collocation.And to write non-to duplicative The data of volatile ram module can include belonging to the data of continuation address and belong to the data of discontinuous address.Therefore, correspond to not Same write-in data, the write operation of duplicative Nonvolatile memory module may include to be continuously written into (sequential write) behaviour Make to operate with random writing (random write).Under general running, host computer system will first can be belonged in the way of being continuously written into Write in the data of continuation address into duplicative Nonvolatile memory module in a part of entity erased cell.Then, main frame System can change in the way of discontinuous write-in (for example, random writing operation) and write the data for belonging to discontinuous address to can answer Write in formula Nonvolatile memory module in another part entity erased cell.And under general running, host computer system performs discontinuous The probability of write-in is likely to be greater than the probability for performing and being continuously written into.Therefore, after the discontinuous write operation of a period of time is performed, The number of times of erasing of the entity erased cell of data is write using discontinuous write operation to be continuously written into operation write-in data higher than using Entity erased cell number of times of erasing.When the gap for number of times of erasing reaches to a certain degree, duplicative will be performed non-volatile Property memory modules average abrasion (wear leveling) operation, with avoid occur only because of the number of times of erasing of part entity erased cell Performance degradation that is too high and causing whole duplicative Nonvolatile memory module, or even the problem of can not be continuing with.

Average abrasion operation is the entity erased cell that average abrasion operation to be performed is determined according to the number for number of times of erasing.Therefore, It is secondary using erasing for the entity erased cell for being continuously written into operation write-in data after the average abrasion for performing a period of time is operated Number may be close with the number of times of erasing for the entity erased cell that data are write using discontinuous write operation.Hereafter, it is flat in execution When abrasion is operated, the entity erased cell of data is write and using discontinuous write operation write-in data using operation is continuously written into Entity erased cell may be picked as the entity erased cell of average abrasion to be performed operation together.Consequently, it is possible to originally Belonging to the data of continuation address may be written into same entity erased cell together with belonging to the data of discontinuous address. , may be because of can not efficiently perform refuse collection (garbage when execution is continuously written into operation however, in this case Collection) reduce and be continuously written into the execution speed of operation, and then can not make to be continuously written into operation and maintain and certain perform speed Degree.Base this, how to avoid influenceing the speed that is continuously written into because performing refuse collection, be this art personnel view of concern Topic.

The content of the invention

The present invention provides a kind of average abrasion method, memory control circuit unit and internal storing memory, can be effectively prevented from because Perform the speed that refuse collection and influenceing is continuously written into.

One example of the present invention embodiment proposes a kind of average abrasion method for duplicative Nonvolatile memory module, wherein Duplicative Nonvolatile memory module has multiple entity erased cells, and each entity erased cell has identical appearance Amount.This method includes：Entity erased cell is divided into the first group and the second group, the list wherein entity of the first group is erased Member nothing has valid data, and the entity erased cell of the second group stores valid data.This method also includes：To be each Individual entity erased cell records number of times of erasing, and according to the entity erased cell of the second group of number of times arrangement of erasing recorded. This method also includes：Number of times of erasing according to being recorded extracts an entity erased cell from the entity erased cell of the first group Smeared as first instance erased cell, and according to the entity put in order from the second group of the entity erased cell of the second group Except in unit choose an entity erased cell as second instance erased cell, wherein second instance erased cell valid data Amount is less than the capacity.This method also includes：According to the reality put in order from the second group of the entity erased cell of the second group Another entity erased cell that valid data amount is only chosen in body erased cell less than the capacity is erased list as one the 3rd entity Member, and by least part valid data sequencing of the valid data of second instance erased cell and the 3rd entity erased cell extremely First instance erased cell.

In one example of the present invention embodiment, the above-mentioned entity erased cell according to the second group puts in order from the second group Entity erased cell in only choose valid data amount and erased list as the 3rd entity less than another entity erased cell of the capacity The step of member includes：Chosen according to putting in order for the entity erased cell of the second group from the entity erased cell of the second group One entity erased cell judges whether the valid data amount of candidate's entity erased cell is small as candidate's entity erased cell In the capacity；If the valid data amount of candidate's entity erased cell is not less than the capacity, according to the entity of the second group The putting in order of erased cell is chosen another entity erased cell from the entity erased cell of the second group and smeared as candidate's entity Except unit；And if the valid data amount of candidate's entity erased cell be less than the capacity when, determine candidate's entity erased cell For the 3rd entity erased cell.

It is above-mentioned by the valid data of second instance erased cell and the 3rd entity erased cell in one example of the present invention embodiment At least part valid data sequencing to first instance erased cell the step of include：According to the effective of second instance erased cell Data volume and the valid data amount of the 3rd entity erased cell calculate valid data amount summation, and judge that valid data amount summation is It is no to be less than the capacity；If valid data amount summation is not less than the capacity, by the valid data of second instance erased cell And the 3rd entity erased cell the sequencing of at least part valid data to first instance erased cell；If valid data amount summation During less than the capacity, by the valid data sequencing of the valid data of second instance erased cell and the 3rd entity erased cell extremely First instance erased cell, according to putting in order from the entity erased cell of the second group for the entity erased cell of the second group Only choose valid data amount and be used as the 4th entity erased cell less than another entity erased cell of the capacity；And by second At least part of the valid data of entity erased cell, the valid data of the 3rd entity erased cell and the 4th entity erased cell has Data programming is imitated to first instance erased cell.

In one example of the present invention embodiment, the above-mentioned entity erased cell that the second group is arranged according to the number of times of erasing recorded The step of include：According to the entity erased cell of the second group of the ascending arrangement of the number of times of erasing recorded.

It is above-mentioned to erase number of times from the entity erased cell of the first group according to what is recorded in one example of the present invention embodiment Extracting a step of entity erased cell is as first instance erased cell includes：Carried from the entity erased cell of the first group The entity erased cell with maximum number of times of erasing is taken as first instance erased cell.

In one example of the present invention embodiment, the valid data and the 3rd entity erased cell of above-mentioned second instance erased cell Valid data be to belong to multiple discontinuous logical addresses.

One example of the present invention embodiment proposes a kind of memory control circuit list for being used to control duplicative Nonvolatile memory module Member, wherein duplicative Nonvolatile memory module have multiple entity erased cells, and each entity erased cell has Identical capacity.This memory control circuit unit includes HPI, memory interface and memory management circuit.HPI is used to It is electrically connected to host computer system.Memory interface is electrically connected to duplicative Nonvolatile memory module.Memory management circuit HPI and memory interface are electrically connected to, and entity erased cell is divided into the first group and the second group, its In the first group entity erased cell without there being valid data, and the entity erased cell of the second group stores valid data. Furthermore, memory management circuit for each entity erased cell more to record number of times of erasing, and secondary according to erasing for being recorded The entity erased cell of the second group of number arrangement.In addition, memory management circuit is more used to according to the number of times of erasing recorded from first An entity erased cell is extracted in the entity erased cell of group as first instance erased cell, and according to the second group Putting in order for entity erased cell chooses an entity erased cell as second instance from the entity erased cell of the second group The valid data amount of erased cell, wherein second instance erased cell is less than the capacity.In addition, memory management circuit is more used to Put in order that valid data amount is only chosen from the entity erased cell of the second group is small according to the entity erased cell of the second group The 3rd entity erased cell is used as in another entity erased cell of the capacity.Moreover, memory management circuit is more to assign Command sequence by least part valid data sequencing of the valid data of second instance erased cell and the 3rd entity erased cell extremely First instance erased cell.

In one example of the present invention embodiment, in putting in order from second group for the above-mentioned entity erased cell according to the second group Another entity erased cell that valid data amount is only chosen in the entity erased cell of group less than the capacity is smeared as the 3rd entity Except in the running of unit, memory management circuit is more used to putting in order from the second group according to the entity erased cell of the second group Entity erased cell in choose an entity erased cell as candidate's entity erased cell, and judge that candidate's entity is erased list Whether the valid data amount of member is less than the capacity.If wherein the valid data amount of candidate's entity erased cell is not less than the capacity When, memory management circuit is more used to be erased list from the entity of the second group according to putting in order for the entity erased cell of the second group Another entity erased cell is chosen in member as candidate's entity erased cell；If the valid data amount of candidate's entity erased cell During less than the capacity, memory management circuit is more to determine that candidate's entity erased cell is the 3rd entity erased cell.

In one example of the present invention embodiment, in above-mentioned command sequence of assigning by the valid data of second instance erased cell and At least part valid data sequencing of three entity erased cells is into the running of first instance erased cell, and memory management circuit is more Valid data amount is calculated to the valid data amount according to second instance erased cell and the valid data amount of the 3rd entity erased cell Summation, and judge whether valid data amount summation is less than the capacity.If wherein valid data amount summation is held not less than described During amount, memory management circuit more erases the valid data of second instance erased cell and the 3rd entity list to assign command sequence At least part valid data sequencing of member is to first instance erased cell；If valid data amount summation is less than the capacity, Memory management circuit more putting in order from the entity erased cell of the second group to the entity erased cell according to the second group Only choose valid data amount and be used as the 4th entity erased cell less than another entity erased cell of the capacity.In addition, internal memory Circuit is managed more to assign command sequence by the valid data of second instance erased cell, the significant figure of the 3rd entity erased cell According to and the 4th entity erased cell the sequencing of at least part valid data to first instance erased cell.

In one example of the present invention embodiment, in the above-mentioned solid element that the second group is arranged according to the number of times of erasing recorded In running, memory management circuit is more used to the entity erased cell according to the second group of the ascending arrangement of the number of times of erasing recorded.

In one example of the present invention embodiment, above-mentioned according to entity erased cell of the number of times from the first group of erasing recorded In the middle running for extracting an entity erased cell as first instance erased cell, memory management circuit is more used to from the first group Entity erased cell in extract with maximum erase number of times entity erased cell as first instance erased cell.

One example of the present invention embodiment proposes a kind of internal storing memory, and it is non-volatile that it includes connecting interface unit, duplicative Property memory modules and memory control circuit unit.Connecting interface unit is electrically connected to host computer system.Duplicative is non-volatile Property memory modules include multiple entity erased cells.Memory control circuit unit is electrically connected to connecting interface unit and duplicative Nonvolatile memory module, and entity erased cell is divided into the first group and the second group, wherein the first group Entity erased cell is without there being valid data, and the entity erased cell of the second group stores valid data.Furthermore, internal memory Control circuit unit for each entity erased cell more to record number of times of erasing, and according to the number of times arrangement of erasing recorded The entity erased cell of second group.In addition, memory control circuit unit is more used to according to the number of times of erasing recorded from first group An entity erased cell is extracted in the entity erased cell of group as first instance erased cell, and according to the reality of the second group The one entity erased cell of selection from the entity erased cell of the second group that puts in order of body erased cell is smeared as second instance Except unit, the wherein valid data amount of second instance erased cell is less than the capacity.In addition, memory control circuit unit is more used Valid data amount is only chosen from the entity erased cell of the second group with putting in order for the entity erased cell according to the second group Another entity erased cell less than the capacity is used as the 3rd entity erased cell.Moreover, memory control circuit unit is more used To assign command sequence by least part valid data journey of the valid data of second instance erased cell and the 3rd entity erased cell Sequence is to first instance erased cell.

In one example of the present invention embodiment, in putting in order from second group for the above-mentioned entity erased cell according to the second group Another entity erased cell that valid data amount is only chosen in the entity erased cell of group less than the capacity is smeared as the 3rd entity Except in the running of unit, memory control circuit unit is more used to putting in order from second according to the entity erased cell of the second group An entity erased cell is chosen in the entity erased cell of group as candidate's entity erased cell, and judges that candidate's entity is smeared Except whether the valid data amount of unit is less than the capacity.If wherein the valid data amount of candidate's entity erased cell is not less than described During capacity, memory control circuit unit is more used to the reality put in order from the second group of the entity erased cell according to the second group Another entity erased cell is chosen in body erased cell as candidate's entity erased cell；If candidate's entity erased cell has When imitating data volume less than the capacity, memory control circuit unit is more to determine that candidate's entity erased cell is erased for the 3rd entity Unit.

In one example of the present invention embodiment, in above-mentioned command sequence of assigning by the valid data of second instance erased cell and At least part valid data sequencing of three entity erased cells is into the running of first instance erased cell, memory control circuit list Member is more used to calculate significant figure according to the valid data amount of second instance erased cell and the valid data amount of the 3rd entity erased cell According to amount summation, and judge whether valid data amount summation is less than the capacity.If wherein valid data amount summation is not less than institute When stating capacity, memory control circuit unit is more real by the valid data of second instance erased cell and the 3rd to assign command sequence At least part valid data sequencing of body erased cell is to first instance erased cell；If valid data amount summation is less than described During capacity, memory control circuit unit is more used to the reality put in order from the second group of the entity erased cell according to the second group Another entity erased cell is chosen in body erased cell as the 4th entity erased cell, wherein being smeared from the entity of the second group It is less than another entity erased cell of the capacity as the 4th entity erased cell except valid data amount is only chosen in unit.This Outside, memory control circuit unit more erases the valid data of second instance erased cell, the 3rd entity to assign command sequence At least part valid data sequencing of the valid data of unit and the 4th entity erased cell is to first instance erased cell.

In one example of the present invention embodiment, in the above-mentioned solid element that the second group is arranged according to the number of times of erasing recorded In running, memory control circuit unit is more used to be erased according to the entity of the second group of the ascending arrangement of the number of times of erasing recorded Unit.

In one example of the present invention embodiment, above-mentioned according to entity erased cell of the number of times from the first group of erasing recorded In the middle running for extracting an entity erased cell as first instance erased cell, memory control circuit unit is more used to from first The entity erased cell with maximum number of times of erasing is extracted in the entity erased cell of group as first instance erased cell.

Based on above-mentioned, when average abrasion to be performed is operated, if having chosen one from the entity erased cell for having valid data When entity erased cell and its valid data amount are less than the capacity of entity erased cell, the present invention is that have by skipping to have Imitate side of the valid data amount not less than the entity erased cell of the capacity of an entity erased cell in the entity erased cell of data Formula, selects many of capacity of the valid data amount less than an entity erased cell from the entity erased cell for having valid data Individual entity erased cell operates to perform average abrasion in the lump.So the efficiency of refuse collection can be effectively lifted, and ensured continuous The speed of write-in can be maintained more than desired value.

For the features described above and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to elaborate It is as follows.

Brief description of the drawings

Fig. 1 is showing for host computer system according to an exemplary embodiment, internal storing memory and input/output (I/O) device It is intended to；

Fig. 2 is host computer system, internal storing memory and input/output (I/O) device according to another exemplary embodiment Schematic diagram；

Fig. 3 is the schematic diagram of host computer system according to another exemplary embodiment and internal storing memory；

Fig. 4 is the summary block diagram of host computer system according to an exemplary embodiment and internal storing memory；

Fig. 5 is the summary block diagram of the memory control circuit unit according to an exemplary embodiment；

Fig. 6 and Fig. 7 is the example schematic of the management entity erased cell according to an exemplary embodiment；

Fig. 8 be basis according to an exemplary embodiment erase number of times arrange the second group entity erased cell schematic diagram；

Fig. 9 is the schematic diagram that second instance erased cell performs average abrasion operation of choosing according to an exemplary embodiment；

Figure 10 is that selection second instance erased cell and the 3rd entity erased cell according to an exemplary embodiment are performed averagely Wear and tear the schematic diagram operated；

Figure 11 is the flow chart of the average abrasion method according to an exemplary embodiment；

Figure 12 is the detailed step that the 3rd entity erased cell is chosen in average abrasion method according to an exemplary embodiment Flow chart.

Reference：

10：Internal storing memory

11：Host computer system

12：Input/output (I/O) device

110：System bus

111：Processor

112：Random access memory (RAM)

113：Read-only storage (ROM)

114：Data transmission interface

20：Mainboard

201：Portable disk

202：Memory card

203：Solid state hard disc

204：Wireless internal storing memory

205：GPS module

206：Network adapter

207：Radio transmitting device

208：Keyboard

209：Screen

210：Loudspeaker

30：Internal storing memory

31：Host computer system

32：SD card

33：CF cards

34：Embedded storage device

341：Embedded multi-media card

342：Embedded type multi-core piece encapsulates storage device

402：Connecting interface unit

404：Memory control circuit unit

406：Duplicative Nonvolatile memory module

410 (0)~410 (N), 810 (0)~810 (5), 910 (0)~910 (5), 920 (0)~920 (N), 1010 (0)~1010 (5), 1020 (0)~1020 (N)：Entity erased cell

502：Memory management circuit

504：HPI

506：Memory interface

508：Buffer storage

510：Electric power management circuit

512：Error checking and correcting circuit

602：Information data area

604：Idle area

606：System area

608：Replace area

LBA (0)~LBA (H)：Logic unit

LZ (0)~LZ (M)：Logic region

801：Erase frequency table

810、910、1010：Second group

920、1020：First group

S1、S2、S3：Put in order

S1101：Entity erased cell is divided into the first group and the second group, wherein the entity erased cell of the first group is without depositing There are valid data, the step of entity erased cell of the second group has valid data

S1103：Number of times of erasing is recorded for each entity erased cell, and the second group is arranged according to the number of times of erasing recorded The step of entity erased cell

S1105：Number of times of erasing according to being recorded extracts an entity erased cell from the first group and erased list as first instance The step of member

S1107：One entity erased cell work is chosen from the second group according to putting in order for the entity erased cell of the second group The step of for second instance erased cell

S1109：The step of whether the valid data amount of second instance erased cell is less than the capacity of entity erased cell judged

S1111：The step that the valid data of second instance erased cell are write into first instance erased cell

S1113：One entity erased cell work is chosen from the second group according to putting in order for the entity erased cell of the second group For the 3rd entity erased cell, wherein not less than one entity erased cell of valid data amount in the entity erased cell of the second group The entity erased cell of capacity the step of will not be selected as the 3rd entity erased cell

S1115：By at least part valid data sequencing of the valid data of second instance erased cell and the 3rd entity erased cell The step of to first instance erased cell

S1201：One entity erased cell work is chosen from the second group according to putting in order for the entity erased cell of the second group The step of for candidate's entity erased cell

S1203：The step of whether the valid data amount of candidate's entity erased cell is less than the capacity of entity erased cell judged

S1205：Determine the step of candidate's entity erased cell is the 3rd entity erased cell

Embodiment

In general, internal storing memory (also known as, memory storage system) includes duplicative Nonvolatile memory module and control Device (also known as, controlling circuit unit) processed.Usual internal storing memory is used together with host computer system, so that host computer system can Write data into internal storing memory or data are read from internal storing memory.

Fig. 1 is showing for host computer system according to an exemplary embodiment, internal storing memory and input/output (I/O) device It is intended to, and Fig. 2 is host computer system, internal storing memory and input/output (I/O) dress according to another exemplary embodiment The schematic diagram put.

Refer to Fig. 1 and Fig. 2, host computer system 11 generally comprise processor 111, random access memory (random access memory, RAM) 112, read-only storage (read only memory, ROM) 113 and data transmission interface 114.Processor 111, Random access memory 112, read-only storage 113 and data transmission interface 114 are all electrically connected to system bus (system bus) 110。

In this exemplary embodiment, host computer system 11 is to be electrically connected with by data transmission interface 114 with internal storing memory 10. For example, host computer system 11 can write data into internal storing memory 10 via data transmission interface 114 or be filled from memory storage Data are read in putting 10.In addition, host computer system 11 is electrically connected with by system bus 110 and I/O devices 12.For example, Output signal can be sent to I/O devices 12 via system bus 110 or receive input letter from I/O devices 12 by host computer system 11 Number.

In this exemplary embodiment, processor 111, random access memory 112, read-only storage 113 and data transmission interface 114 It is on the mainboard 20 for may be provided at host computer system 11.The number of data transmission interface 114 can be one or more.Pass through data Coffret 114, mainboard 20 can be electrically connected to internal storing memory 10 via wired or wireless way.Internal storing memory 10 can be for example Portable disk 201, memory card 202, solid state hard disc (Solid State Drive, SSD) 203 or wireless memory storage Device 204.Wireless internal storing memory 204 can be for example wireless near field communication (Near Field Communication Storage, NFC) internal storing memory, radio facsimile (WiFi) internal storing memory, bluetooth (Bluetooth) internal storing memory or The internal storing memory based on various wireless communication technology such as low-power consumption bluetooth internal storing memory (for example, iBeacon). In addition, mainboard 20 can also be electrically connected to by system bus 110 global positioning system (Global Positioning System, GPS) module 205, network adapter 206, radio transmitting device 207, keyboard 208, screen 209, loudspeaker 210 etc. are various I/O devices.For example, in an exemplary embodiment, mainboard 20 can be filled by the access wireless memory storage of radio transmitting device 207 Put 204.

In an exemplary embodiment, mentioned host computer system is that substantially can coordinate store appointing for data with internal storing memory Meaning system.Although in above-mentioned exemplary embodiment, host computer system is explained with computer system, however, Fig. 3 is basis The schematic diagram of host computer system and internal storing memory shown by another exemplary embodiment.Fig. 3 is refer to, in another exemplary embodiment In, host computer system 31 can also be digital camera, video camera, communicator, audio player, video player or flat board electricity The systems such as brain, and internal storing memory 30 can be its used SD card 32, CF cards 33 or embedded storage device 34 etc. Various nonvolatile memory storage device.Embedded storage device 34 include embedded multi-media card (embedded MMC, EMMC) 341 and/or embedded type multi-core piece encapsulation storage device (embedded Multi Chip Package, eMCP) 342 etc. The all types of embedded storage devices being directly electrically connected at memory modules on the substrate of host computer system.

Fig. 4 is the summary block diagram of host computer system according to an exemplary embodiment and internal storing memory.

Fig. 4 is refer to, internal storing memory 10 includes connecting interface unit 402, memory control circuit unit 404 with that can make carbon copies Formula Nonvolatile memory module 406.

In this exemplary embodiment, connecting interface unit 402 is compatible with the advanced annex of sequence (Serial Advanced Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not restricted to this, connecting interface unit 402 can also It is to meet advanced annex (Parallel Advanced Technology Attachment, PATA) standard, Electrical and Electronic work arranged side by side SCTE (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, the connection of high-speed peripheral part Interface (Peripheral Component Interconnect Express, PCI Express) standard, USB (Universal Serial Bus, USB) standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) interface standard, ultrahigh speed two generations (Ultra High Speed-II, UHS-II) interface standard, secure digital (Secure Digital, SD) interface standard, memory stick (Memory Stick, MS) interface standard, multi-chip package (Multi-Chip Package) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, built-in multimedia memory card (Embedded Multimedia Card, eMMC) interface standard, Common Flash Memory (Universal Flash Storage, UFS) interface standard, embedded type multi-core piece encapsulation (embedded Multi Chip Package, eMCP) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other suitable standards.In this exemplary embodiment, connecting interface Unit 402 can be encapsulated in a chip with memory control circuit unit 404, or connecting interface unit 402 is to be laid in one Outside chip comprising memory control circuit unit.

Memory control circuit unit 404 to perform multiple gates or control instruction with hardware pattern or firmware pattern implementation, And the write-in of data is carried out in duplicative Nonvolatile memory module 406 according to the instruction of host computer system 11, reads and smears Operated except waiting.

Duplicative Nonvolatile memory module 406 is electrically connected to memory control circuit unit 404, and to store main frame The data that system 11 is write.Duplicative Nonvolatile memory module 406 has entity erased cell 410 (0)~410 (N).Example Such as, entity erased cell 410 (0)~410 (N) can belong to same internal memory crystal grain (die) or belong to different internal memory crystal grain.Often One entity erased cell has multiple entity program units respectively, wherein belonging to the entity program of same entity erased cell Unit can be written independently and simultaneously be erased.However, it is necessary to be appreciated that, the invention is not restricted to this, each entity is smeared Except unit be can be by 64 entity program units, 256 entity program units or other any entity program unit institute Composition.

In more detail, entity erased cell is the least unit erased.That is, each entity erased cell contain minimal amount it The memory cell being erased in the lump.Entity program unit is the minimum unit of sequencing.That is, entity program unit is write-in number According to minimum unit.Each entity program unit generally includes data bit area and redundant digit area.Data bit area includes multiple entities Data of the access address to store user, and redundant digit area is used to the data of stocking system (for example, control information and mistake are more Code).In this exemplary embodiment, 8 entity access addresses can be included in the data bit area of each entity program unit, And the size of an entity access address is 512 bytes (byte).However, in other exemplary embodiments, in data bit area The more or less entity access addresses of number can be included, the present invention is not intended to limit the size and number of entity access address.Example Such as, in an exemplary embodiment, entity erased cell is physical blocks, and entity program unit is physical page or entity Sector, but the present invention is not limited.

In this exemplary embodiment, duplicative Nonvolatile memory module 406 be multistage memory cell (Multi Level Cell, MLC) NAND-type flash memory module (that is, can store the flash memory module of 2 data bit in one memory cell).However, this hair Bright not limited to this, duplicative Nonvolatile memory module 406 also can be single-order memory cell (Single Level Cell, SLC) NAND-type flash memory module (that is, can store the flash memory module of 1 data bit in one memory cell), three rank memory cell (Trinary Level Cell, TLC) NAND-type flash memory module (that is, can store the flash memory module of 3 data bit in one memory cell), Other flash memory modules or other there are the memory modules of identical characteristic.

Fig. 5 is the summary block diagram of the Memory control circuit unit according to an exemplary embodiment.

Refer to Fig. 5, memory control circuit unit 404 include memory management circuit 502, HPI 504 and memory interface 506, Buffer storage 508, electric power management circuit 510 and error checking and correcting circuit 512.

Overall operation of the memory management circuit 502 to control memory control circuit unit 404.Specifically, memory management electricity Road 502 has multiple control instructions, and when internal storing memory 10 is operated, this little control instruction can be performed to enter line number According to write-in, read and the running such as erase.

In this exemplary embodiment, the control instruction of memory management circuit 502 is to carry out implementation with firmware pattern.For example, internal memory pipe Managing circuit 502 has microprocessor unit (not shown) and a read-only storage (not shown), and this little control instruction be by Imprinting is so far in read-only storage.When internal storing memory 10 is operated, this little control instruction can be performed by microprocessor unit To carry out the write-in of data, read and the running such as erase.

In another exemplary embodiment of the invention, the control instruction of memory management circuit 502 can also program code pattern be stored in The specific region of duplicative Nonvolatile memory module 406 is (for example, be exclusively used in the system of storage system data in memory modules Area) in.In addition, memory management circuit 502 have microprocessor unit (not shown), read-only storage (not shown) and Random access memory (not shown).Particularly, this read-only storage has driving code, and when memory control circuit unit 404 When being enabled, microprocessor unit can first carry out this driving code section and will be stored in duplicative Nonvolatile memory module 406 Control instruction be loaded onto in the random access memory of memory management circuit 502.Afterwards, microprocessor unit can operate this little control System instruction to carry out the write-in of data, read and the running such as erase.

In addition, in another exemplary embodiment of the invention, the control instruction of memory management circuit 502 can also a hardware pattern Implementation.Read for example, memory management circuit 502 includes microcontroller, memory cell management circuit, internal memory write circuit, internal memory Circuit, internal memory are erased circuit and data processing circuit.It is memory cell management circuit, internal memory write circuit, internal memory reading circuit, interior Deposit circuit of erasing and be electrically connected to microcontroller with data processing circuit.Wherein, memory cell management circuit can be made carbon copies to manage The entity erased cell of formula Nonvolatile memory module 406；Internal memory write circuit is to duplicative Nonvolatile memory module 406 assign write instruction to write data into duplicative Nonvolatile memory module 406；Internal memory reading circuit is to pair can Manifolding formula Nonvolatile memory module 406 assigns reading instruction to read data from duplicative Nonvolatile memory module 406； Internal memory erases circuit to assign instruction of erasing to duplicative Nonvolatile memory module 406 so that data are non-easily from duplicative Erased in the property lost memory modules 406；And data processing circuit is intended to write to duplicative Nonvolatile memory module 406 to handle Data and the data that are read from duplicative Nonvolatile memory module 406.

HPI 504 is electrically connected to memory management circuit 502 and is electrically connected to connecting interface unit 402, with Receive the instruction transmitted with identification host computer system 11 and data.That is, instruction that host computer system 11 is transmitted and data Memory management circuit 502 can be sent to by HPI 504.In this exemplary embodiment, HPI 504 is compatible with SATA standard.However, it is necessary to be appreciated that the invention is not restricted to this, HPI 504 can also be compatible with PATA marks Standard, the standards of IEEE 1394, PCI Express standards, USB standard, UHS-I interface standards, UHS-II interface standards, SD Standard, MS standards, MMC standards, CF standards, IDE standards or other suitable data transmission standards.

Memory interface 506 is electrically connected to memory management circuit 502 and to access duplicative Nonvolatile memory module 406.That is, being intended to write to the data of duplicative Nonvolatile memory module 406 can be converted to via memory interface 506 The receptible form of the institute of duplicative Nonvolatile memory module 406.

Buffer storage 508 is electrically connected to memory management circuit 502 and is configured to temporarily store the data for coming from host computer system 11 Data with instructing or coming from duplicative Nonvolatile memory module 406.

Electric power management circuit 510 is electrically connected to memory management circuit 502 and the power supply to control internal storing memory 10.

Error checking is electrically connected to memory management circuit 502 and to perform error checking and correction with correcting circuit 512 Program is to ensure the correctness of data.Specifically, when memory management circuit 502 receives write instruction from host computer system 11 When, error checking can produce corresponding error checking and correcting code (Error with correcting circuit 512 for the data of this corresponding write instruction Checking and Correcting Code, ECC Code), and memory management circuit 502 can be by the number of this write instruction of correspondence Write according to corresponding error checking and correcting code into duplicative Nonvolatile memory module 406.Afterwards, memory management is worked as Circuit 502 can read the corresponding error checking of this data simultaneously when data are read from duplicative Nonvolatile memory module 406 With correcting code, and error checking and correcting circuit 512 can perform mistake according to this error checking and correcting code to the data read Flase drop is looked into and correction program.

Fig. 6 and Fig. 7 is the example schematic of the management entity erased cell according to an exemplary embodiment.

It will be appreciated that when being described herein the running of the entity erased cell of duplicative Nonvolatile memory module 406, " to carry Take ", " packet ", " division ", the word such as " association " carrys out application entity erased cell is concept in logic.That is, can make carbon copies The physical location of the entity erased cell of formula Nonvolatile memory module is not changed, but non-volatile to duplicative in logic The entity erased cell of memory modules is operated.

Fig. 6 is refer to, memory control circuit unit 404 (or memory management circuit 502) can be by entity erased cell 410 (0)~410 (N) Logically it is grouped into data field 602, idle area 604, system area 606 and substitution area 608.

The entity erased cell for logically belonging to data field 602 and idle area 604 is to store the number for coming from host computer system 11 According to.Specifically, the entity erased cell of data field 602 is regarded as having stored the entity erased cell of data, and idle area 604 entity erased cell is the entity erased cell to replacement data area 602.Connect that is, working as from host computer system 11 When receiving write instruction with the data to be write, memory management circuit 502 can extract entity erased cell from idle area 604, And write data into the entity erased cell extracted, with the entity erased cell in replacement data area 602.

The entity erased cell for logically belonging to system area 606 is to be used to record system data.For example, system data include on The manufacturer of duplicative Nonvolatile memory module and model, the entity erased cell number of duplicative Nonvolatile memory module, Entity program unit number of each entity erased cell etc..

It is to be used to bad entity erased cell replace program to logically belong to replace the entity erased cell in area 608, with replacing damaged Entity erased cell.Specifically, if still having normal entity erased cell and data field 602 in substitution area 608 Entity erased cell when damaging, memory management circuit 502 can extract normal entity erased cell and comes more from substitution area 608 Change the entity erased cell of damage.

Particularly, the quantity of data field 602, idle area 604, system area 606 and the entity erased cell in substitution area 608 can root It is different according to different memory standards.Further, it is necessary to be appreciated that, in the running of internal storing memory 10, entity is smeared Except unit is associated to data field 602, idle area 604, system area 606 with replacing the packet relation in area 608 dynamically to change. For example, when the entity erased cell in idle area 604 is damaged and the entity erased cell in substituted area 608 replaces, then originally The entity erased cell in substitution area 608 can be associated to idle area 604.

Fig. 7 is refer to, memory control circuit unit 404 (or memory management circuit 502) can configuration logic unit LBA (0)~LBA (H) With the entity erased cell in Image Data area 602, each of which logic unit has multiple logical subunits with the corresponding reality of image The entity program unit of body erased cell.Also, when the logic unit to be write data to of host computer system 11 or renewal are stored in and patrolled When collecting the data in unit, memory control circuit unit 404 (or memory management circuit 502) can extract one from idle area 604 Individual entity erased cell writes data, with the entity erased cell for data field 602 of rotating.In this exemplary embodiment, logic Subelement can be logical page (LPAGE) or logic sector.

In order to recognize the data of each logic unit are stored in which entity erased cell, in this exemplary embodiment, internal memory control Circuit unit 404 (or memory management circuit 502) processed can record the image between logic unit and entity erased cell.Also, When host computer system 11 is intended to access data in logical subunit, memory control circuit unit 404 (or memory management circuit 502) The logic unit belonging to this logical subunit can be confirmed, and number is accessed in the entity erased cell of this logic unit institute image According to.For example, in this exemplary embodiment, memory control circuit unit 404 (or memory management circuit 502) can be in duplicative Stored logic-solid mapping table records the entity erased cell of each logic unit institute image in Nonvolatile memory module 406, And memory control circuit unit 404 (or memory management circuit 502) can load logic-solid mapping table when data to be accessed Safeguarded to buffer storage 508.

It is noted that because the finite capacity of buffer storage 508 can not store the image relation of all logic units of recording Mapping table, therefore, in this exemplary embodiment, memory control circuit unit 404 (or memory management circuit 502) will can be patrolled Collect unit LBA (0)~LBA (H) and be grouped into multiple logic region LZ (0)~LZ (M), and one is configured for each logic region and patrol Volume-solid mapping table.Particularly, when memory control circuit unit 404 (or memory management circuit 502) is intended to update some logic list During the image of member, buffer storage 508 can be loaded on by corresponding to logic-solid mapping table of the logic region belonging to this logic unit To be updated.

Internal storing memory 10 is after running after a while, the entity in duplicative Nonvolatile memory module 406 Erased cell can be divided into without the entity erased cell (the following entity erased cell for being also known as the first group) for having valid data With there being the entity erased cell of valid data (the following entity erased cell for being also known as the second group).In general, idle Entity erased cell in area 604 is that, without the entity erased cell for having valid data, and the entity in data field 602 is erased list Member can have valid data after user operates.

The write operation of host computer system 11, which can be simply divided into, is continuously written into operation and discontinuous write operation.It is continuously written into finger Be many write instruction logical addresses to be write be it is continuous, it is on the contrary then be non-be continuously written into.In other words, the second group Entity erased cell in, the valid data that some entity erased cells have are to belong to continuous logical address, and some entities The valid data that erased cell has are to belong to discontinuous logical address.In this exemplary embodiment, belong to company in execution every time During the write-in program of continuous write operation, the entity erased cell to store write-in data can be belonging to the effective of continuous logic address Data are filled up.And when performing the write-in program of discontinuous write operation, memory control circuit unit 404 (or memory management circuit 502) it is sustainable assign write instruction with the data for belonging to discontinuous logical address are write do not have into entity erased cell effectively In the entity program unit (also referred to as idle entity program unit) of data.Patrolled when host computer system 11 is intended to update some When collecting the data of address, memory control circuit unit 404 (or memory management circuit 502), which will can be updated the data, to be write to idle In entity program unit, and it is invalid number by the data markers stored by the entity program unit of this logical address script image According to.Therefore, after the discontinuous write operation of a period of time is performed, it there may be in the entity erased cell of the second group same The entity erased cell of Shi Cunyou valid data and invalid data, in other words, this is a little while having valid data and invalid data Entity erased cell storage area in be not filled with valid data.In this exemplary embodiment, this is not filled with valid data a bit Entity erased cell in valid data can belong to discontinuous address.However, the present invention is not limited thereto.

When in an entity erased cell without there being valid data (for example, the data having all have been labeled as invalid data), Memory control circuit unit 404 (or memory management circuit 502) can perform to this entity erased cell and erase operation to write again Data.In this exemplary embodiment, memory control circuit unit 404 (or memory management circuit 502) can erase for each entity Unit 410 (0)~410 (N) record corresponding number of times of erasing.Specifically, each entity erased cell 410 (0)~410 (N) erases Number of times is limited.For example, entity erased cell will be damaged after erasing 10,000 times, and when the abrasion of entity erased cell When causing portion capacity loss or the performance significant degradation of storage volume, the Missing data stored by user can be caused or can not be stored Data etc. are adversely affected.Particularly, the abrasion system of entity erased cell depends on being programmed or smearing in each entity erased cell The number of times removed.If that is, an entity erased cell is only programmed (or write-in) once, then not by secondary program again During change, the degree of wear of this entity erased cell will be relatively low.If conversely, an entity erased cell is by repeatedly sequencing During with erasing, then the degree of wear of this entity erased cell will be relatively high.For example, when duplicative Nonvolatile memory mould When an entity erased cell in block 406 is erased, memory control circuit unit 404 (or memory management circuit 502) can be by The number of times of erasing of this entity erased cell of correspondence plus 1.Erased here, number of times of erasing can be recorded in one in frequency table or its institute is right In the entity erased cell answered.

After the discontinuous write operation of a period of time is performed, the entity of part may be made to erase because repeating write-in program The number of times of erasing of unit continues to increase.In this exemplary embodiment, the difference between the number of times of erasing of entity erased cell is judged When reaching certain numerical value, memory control circuit unit 404 (or memory management circuit 502) can start to perform average abrasion operation. When performing average abrasion operation, memory control circuit unit 404 (or memory management circuit 502) can be according to entity erased cell Number of times of erasing from the entity erased cell (i.e. without the entity erased cell for having valid data) of the first group and the second group Entity erased cell is chosen in entity erased cell (the entity erased cell for having valid data) to swap.For example, Memory control circuit unit 404 (or memory management circuit 502) is carried according to number of times of erasing from the entity erased cell of the first group An entity erased cell (being also known as first instance erased cell below) is taken, and according to reality of the number of times from the second group of erasing An entity erased cell (being also known as second instance erased cell below) is chosen in body erased cell.

In this exemplary embodiment, entity of memory control circuit unit 404 (or the memory management circuit 502) meeting from the first group The entity erased cell with maximum number of times of erasing is chosen in erased cell as first instance erased cell.On the other hand, internal memory Control circuit unit can choose the entity erased cell with minimum number of times of erasing from the second group and be erased list as second instance Member.For example, memory control circuit unit 404 (or memory management circuit 502) first can erase according to the entity of the second group The entity erased cell of second group is ranked up by the number of times of erasing of unit, and record the entity erased cell of the second group Put in order.Then, the entity that memory control circuit unit 404 (or memory management circuit 502) can be again according to the second group is smeared Except putting in order for unit starts anew to choose entity erased cell.For example, according to the second group of the ascending arrangement of number of times of erasing Entity erased cell, thus, memory control circuit unit 404 (or memory management circuit 502) just can be arrived according to number of times of erasing is small Big order chooses entity erased cell.However, erase number of times and the second instance erased cell of first instance erased cell Number of times of erasing can also be set as being different from above-mentioned condition according to actual demand, of the invention not to be any limitation as.

Fig. 8 be basis according to an exemplary embodiment erase number of times arrange the second group entity erased cell schematic diagram.

It refer to Fig. 8, the entity erased cell 810 (0) of the second group 810~810 (5) is the entity erased cell for having valid data (stored valid data are represented with oblique line in entity erased cell).In this exemplary embodiment, entity erased cell The number of times of erasing of 810 (0)~810 (5) is recorded in frequency table 801 of erasing.Memory control circuit unit 404 (or memory management electricity Road 502) can erase list according to the entity of second group 810 of the ascending arrangement of the number of times of erasing erased recorded in frequency table 801 First 810 (0)~810 (5).As shown in figure 8, entity erased cell 810 (0)~810 (5) be arranged such as the S1 that puts in order.That is, In the S1 that puts in order, the entity erased cell that primary entity erased cell 810 (5) is the second group 810 is arranged in There is minimum to erase the entity erased cell of number of times in 810 (0)~810 (5)；The entity erased cell 810 (3) for being arranged in last position is There is maximum to erase the entity erased cell of number of times in the entity erased cell 810 (0) of two groups 810~810 (5).After the completion of sequence, Memory control circuit unit 404 (or memory management circuit 502) just can be chosen according to the S1 that puts in order and be arranged in primary reality Body erased cell 810 (5) is as second instance erased cell to carry out average abrasion operation.

Due to there may be in the second group while there is the entity erased cell of valid data and invalid data, therefore, when from It has chosen in two groups after second instance erased cell, memory control circuit unit 404 (or memory management circuit 502) can be sentenced Whether the valid data amount of disconnected second instance erased cell is less than the capacity of an entity erased cell.Here, an entity is erased The capacity of unit refers to that an entity erased cell can store the total amount of data of data, and the valid data of an entity erased cell Amount refers to the data volume for the valid data having in an entity erased cell.In this exemplary embodiment, each entity is smeared Except unit all has identical capacity.

If the valid data amount of second instance erased cell is not less than the capacity of (for example, being equal to) entity erased cell, Represent that second instance erased cell has the valid data of a writeable full empty entity erased cell.In the case, internal memory control Circuit unit 404 (or memory management circuit 502) processed can assign command sequence directly by the significant figure in second instance erased cell According to write-in first instance erased cell in, and by the valid data in second instance erased cell be labeled as invalid data.

Fig. 9 is the schematic diagram that second instance erased cell performs average abrasion operation of choosing according to an exemplary embodiment.

Fig. 9 is refer to, memory control circuit unit 404 (or memory management circuit 502) extracts real from the first storage area 920 Body erased cell 920 (0) is used as first instance erased cell.In this exemplary embodiment, it is assumed that the entity of the second storage area 910 is smeared Except unit 910 (0)~910 (5) the ranked S2 that such as puts in order.Memory control circuit unit 404 (or memory management circuit 502) Entity erased cell 910 (0) is chosen as second instance erased cell according to the S2 that puts in order.Due to entity erased cell 910 (0) All entity program units all have valid data, in other words, the storage area of entity erased cell 910 (0) has been filled with Data are imitated, therefore memory control circuit unit 404 (or memory management circuit 502) understands having for decision entities erased cell 910 (0) Imitate the capacity that data volume D (0) is equal to (i.e. a not less than) entity erased cell.Base this, memory control circuit unit 404 (or Memory management circuit 502) it command sequence can be assigned will be stored in entity erased cell 910 (0) (i.e. second instance erased cell) Valid data write to extracted from the first storage area 920 entity erased cell 920 (0) (i.e. first instance erased cell example As) in.

On the other hand, if the valid data amount of second instance erased cell is less than the capacity of an entity erased cell, represent Second instance erased cell does not have the valid data of a writeable full empty entity erased cell.In other words, second instance is smeared Except the storage area of unit is not filled with valid data.Now, memory control circuit unit 404 (or memory management circuit 502) meeting Other entity erased cells are chosen from the second group again to be collected into the significant figure of a writeable full empty entity erased cell According to.Specifically, memory control circuit unit 404 (or memory management circuit 502) can erase list according to the entity of the second group Putting in order for member sequentially chooses another entity erased cell as candidate's entity erased cell from the second group.For example, interior The latter entity for controlling circuit unit 404 (or memory management circuit 502) sequentially to choose second instance erased cell is deposited to erase Unit is used as candidate's entity erased cell.Further, memory control circuit unit 404 (or memory management circuit 502) can be sentenced Whether the valid data amount of disconnected candidate's entity erased cell is less than the capacity of an entity erased cell.

If the valid data amount of current candidate's entity erased cell is not less than (for example, being equal to) entity erased cell Capacity, represents that current candidate's entity erased cell has the valid data of a writeable full empty entity erased cell.Now, Memory control circuit unit 404 (or memory management circuit 502) can ignore current candidate's entity erased cell, and sequentially from Another entity erased cell is chosen in second group as new candidate's entity erased cell.For example, memory control circuit unit 404 (or memory management circuits 502) can sequentially choose the latter entity erased cell conduct of current candidate's entity erased cell New candidate's entity erased cell, and perform whether the above-mentioned valid data amount for judging candidate's entity erased cell is less than one again The operation of the capacity of individual entity erased cell.If in addition, the valid data amount of current candidate's entity erased cell is less than one The capacity of entity erased cell, represents that current candidate's entity erased cell does not have a writeable full empty entity erased cell Valid data.Base this, memory control circuit unit 404 (or memory management circuit 502) can determine that current candidate's entity is erased Unit is the 3rd entity erased cell, and assigns command sequence and smear the valid data of second instance erased cell with the 3rd entity Except at least part of valid data of unit write in first instance erased cell together.

Erased list it is noted that memory control circuit unit 404 (or memory management circuit 502) can also calculate second instance Whether the valid data amount summation of the valid data amount and the valid data amount of the 3rd entity erased cell of member erases less than an entity The capacity of unit.In other words, memory control circuit unit 404 (or memory management circuit 502) can be total according to valid data amount With determine to write to the valid data of first instance erased cell.If for example, valid data amount summation is equal to an entity The capacity of erased cell, memory control circuit unit 404 (or memory management circuit 502) can assign command sequence by second instance Whole valid data of erased cell and whole valid data of the 3rd entity erased cell are write into first instance erased cell； If valid data amount summation is more than the capacity of entity erased cell, memory control circuit unit 404 (or memory management circuit 502) command sequence can be assigned by whole valid data of second instance erased cell and the part significant figure of the 3rd entity erased cell According to write-in into first instance erased cell.On the other hand, when valid data amount summation is less than the capacity of an entity erased cell When, memory control circuit unit 404 (or memory management circuit 502), which may proceed to choose suitable entity from the second group, erases Unit (be also known as below the 4th entity erased cell) is to continue to collect valid data.The selection mode of 4th entity erased cell It is identical with the selection mode of above-mentioned 3rd entity erased cell, it will not be described in great detail herein.

Figure 10 is that selection second instance erased cell and the 3rd entity erased cell according to an exemplary embodiment are performed averagely Wear and tear the schematic diagram operated.

Figure 10 is refer to, memory control circuit unit 404 (or memory management circuit 502) is extracted from the first storage area 1020 Entity erased cell 1020 (1) is used as first instance erased cell.Assuming that the entity erased cell of the second storage area 1010 1010 (0)~1010 (5) have been ordered as the S3 that puts in order.Memory control circuit unit 404 (or memory management circuit 502) foundation The S3 that puts in order chooses entity erased cell 1010 (0) and is used as second instance erased cell.Due in entity erased cell 1010 (0) There are invalid data and valid data simultaneously, in other words, the storage area of entity erased cell 1010 (0) is not filled with significant figure According to, therefore the significant figure of memory control circuit unit 404 (or memory management circuit 502) meeting decision entities erased cell 1010 (0) It is less than the capacity of an entity erased cell according to amount.Base this, memory control circuit unit 404 (or memory management circuit 502) meeting The latter entity erased cell that entity erased cell 1010 (0) is arranged in the second group 1010 is chosen according to the S3 that puts in order 1010 (2) are used as candidate's entity erased cell.However, because the valid data amount of entity erased cell 1010 (2) is equal to an entity The capacity (i.e. all entity program units all have valid data) of erased cell, therefore, memory control circuit unit 404 (or memory management circuit 502) can ignore entity erased cell 1010 (2) and choose the second group 1010 according to the S3 that puts in order In be arranged in the latter entity erased cell 1010 (1) of entity erased cell 1010 (2) as new candidate's entity erased cell.By It is less than the capacity of an entity erased cell, therefore, memory control circuit list in the valid data amount of entity erased cell 1010 (1) First 404 (or memory management circuits 502) can determine that entity erased cell 1010 (1) is the 3rd entity erased cell.

In this exemplary embodiment, it is assumed that the valid data amount of entity erased cell 1010 (0) and having for entity erased cell 1010 (1) Imitate the half that data volume is respectively equal to the capacity of an entity erased cell, that is to say, that the significant figure of entity erased cell 1010 (0) Valid data amount summation according to amount and the valid data amount of entity erased cell 1010 (1) can be equal to the appearance of an entity erased cell Amount.Therefore, memory control circuit unit 404 (or memory management circuit 502) can assign command sequence by entity erased cell 1010 (0) Whole valid data write together with whole valid data of entity erased cell 1010 (1) to the institute from the first storage area 1020 In the entity erased cell 1020 (1) of extraction.Then, memory control circuit unit 404 (or memory management circuit 502) can be by reality Whole valid data of body erased cell 1010 (0) are labeled as invalid data with whole valid data of entity erased cell 1010 (1).

In addition, in this exemplary embodiment, if assuming, the valid data amount of entity erased cell 1010 (0) is equal to an entity The half capacity of erased cell, and four points of valid data amount equal to an entity erased cell of entity erased cell 1010 (1) Three capacity, then the valid data amount of entity erased cell 1010 (0) and the valid data amount of entity erased cell 1010 (1) is effective Data volume summation can be more than the capacity of an entity erased cell.Therefore, (or the memory management circuit of memory control circuit unit 404 502) command sequence can be assigned by the part of whole valid data of entity erased cell 1010 (0) and entity erased cell 1010 (1) Valid data write into the entity erased cell 1020 (1) extracted from the first storage area 1020 together.Then, Memory control Circuit unit 404 (or memory management circuit 502) can erase whole valid data of entity erased cell 1010 (0) and entity list Had been written into first 1010 (1) to the valid data of entity erased cell 1020 (1) and be labeled as invalid data.

In addition, in this exemplary embodiment, if assuming, the valid data amount of entity erased cell 1010 (0) is erased equal to an entity The half capacity of unit, and a quarter of the valid data amount equal to an entity erased cell of entity erased cell 1010 (1) The valid data of capacity, then the valid data amount of entity erased cell 1010 (0) and the valid data amount of entity erased cell 1010 (1) The capacity of an entity erased cell can be less than by measuring summation.Therefore, memory control circuit unit 404 (or memory management circuit 502) The latter entity erased cell that entity erased cell 1010 (1) is arranged in the second group 1010 can be chosen according to the S3 that puts in order 1010 (4) are used as candidate's entity erased cell.However, because the valid data amount of entity erased cell 1010 (4) is equal to an entity The capacity (i.e. the storage area of entity erased cell 1010 (4) has been filled with valid data) of erased cell, therefore, Memory control electricity Road unit 404 (or memory management circuit 502) can ignore entity erased cell 1010 (4) and choose the according to the S3 that puts in order The latter entity erased cell 1010 (5) of entity erased cell 1010 (4) is arranged in two groups 1010 as new candidate's entity Erased cell.It is therefore, interior because the valid data amount of entity erased cell 1010 (5) is less than the capacity of an entity erased cell Depositing control circuit unit 404 (or memory management circuit 502) can determine that entity erased cell 1010 (5) is the 4th entity erased cell. Assuming that the valid data amount of entity erased cell 1010 (5) is equal to a quarter capacity of an entity erased cell.That is, The valid data amount of entity erased cell 1010 (0), the valid data amount of entity erased cell 1010 (1) and entity erased cell The valid data amount summation of the valid data amount of 1010 (5) is equal to the capacity of an entity erased cell, therefore memory control circuit list First 404 (or memory management circuits 502) can then assign command sequence by whole valid data of entity erased cell 1010 (0), reality Whole valid data of body erased cell 1010 (1) are write together with whole valid data of entity erased cell 1010 (5) to from In the entity erased cell 1020 (1) extracted in one storage area 1020 (figure is not shown).Memory control circuit unit 404 (or Memory management circuit 502) and can by whole valid data of entity erased cell 1010 (0), entity erased cell 1010 (1) it is complete Whole valid data of portion's valid data and entity erased cell 1010 (5) are labeled as invalid data.

In above-mentioned exemplary embodiment, when the valid data amount of second instance erased cell is less than the capacity of an entity erased cell When, memory control circuit unit 404 (or memory management circuit 502) can also be by the valid data of second instance erased cell with after The valid data for continuing selected entity erased cell (such as the 3rd entity erased cell and the 4th entity erased cell) are first kept in Into a working area (for example, buffer storage 508).Reach when the valid data being temporarily stored in working area and (be equal to or greatly In) capacity of entity erased cell when, that is, when being collected into the valid data of a writeable full empty entity erased cell, The valid data in working area are write into first instance erased cell again.Furthermore, choose the 3rd entity erased cell (or 4th entity erased cell) during the entity erased cell ignored can be still selected follow-up using as performing average mill Damage the second instance erased cell of operation.

In other words, when performing average abrasion operation, if the valid data amount of second instance erased cell is less than an entity The capacity of erased cell, the entity that memory control circuit unit 404 (or memory management circuit 502) can continue from the second group is smeared The entity erased cell being adapted to except unit selection (i.e. less than the entity of the capacity of entity erased cell erase list by valid data amount Member), until the capacity that the valid data amount summation of selected multiple entity erased cells is not less than an entity erased cell is Only.And during suitable entity erased cell is chosen, capacity of the valid data amount not less than an entity erased cell Entity erased cell can be ignored without being selected as suitable entity erased cell.Can be from selected multiple realities when When the valid data of a writeable full empty entity erased cell are collected into body erased cell, memory control circuit unit 404 (or Memory management circuit 502) can determine to write from this some selected entity erased cell it is effective to first instance erased cell Data.

Figure 11 is the flow chart of the average abrasion method according to an exemplary embodiment.

Figure 11 is refer to, in step S1101, memory control circuit unit 404 (or memory management circuit 502) smears entity Except unit divides into the first group and the second group, wherein the entity erased cell of the first group is without having valid data, second group The entity erased cell of group has valid data.

In step S1103, memory control circuit unit 404 (or memory management circuit 502) is each entity erased cell Number of times of erasing is recorded, and according to the entity erased cell of the second group of number of times arrangement of erasing recorded.

In step S1105, memory control circuit unit 404 (or memory management circuit 502) is according to the number of times of erasing recorded An entity erased cell is extracted from the first group and is used as first instance erased cell.

In step S1107, memory control circuit unit 404 (or memory management circuit 502) is smeared according to the entity of the second group Except putting in order for unit chooses an entity erased cell as second instance erased cell from the second group.

In step S1109, memory control circuit unit 404 (or memory management circuit 502) judges second instance erased cell Valid data amount whether be less than the capacity of entity erased cell.

If the valid data amount of second instance erased cell is not less than the capacity of an entity erased cell, in step S1111, Memory control circuit unit 404 (or memory management circuit 502) assigns command sequence by the valid data of second instance erased cell Write-in is into first instance erased cell.

If the valid data amount of second instance erased cell is less than the capacity of an entity erased cell, in step S1113, Memory control circuit unit 404 (or memory management circuit 502) puts in order from according to the entity erased cell of the second group An entity erased cell is chosen in two groups as the 3rd entity erased cell, wherein having in the entity erased cell of the second group Effect data volume will not be selected not less than the entity erased cell of the capacity of entity erased cell and be erased list as the 3rd entity Member.In other words, entity erased cell of memory control circuit unit 404 (or the memory management circuit 502) meeting from the second group The middle entity erased cell for choosing the capacity that valid data amount is less than an entity erased cell is used as the 3rd entity erased cell.

In step S1115, it is real by second that memory control circuit unit 404 (or memory management circuit 502) assigns command sequence At least part valid data sequencing to the first instance of the valid data of body erased cell and the 3rd entity erased cell is erased list Member.

In step S1201, memory control circuit unit 404 (or memory management circuit 502) is smeared according to the entity of the second group Except putting in order for unit chooses an entity erased cell as candidate's entity erased cell from the second group.

In step S1203, memory control circuit unit 404 (or memory management circuit 502) judges candidate's entity erased cell Valid data amount whether be less than the capacity of entity erased cell.

If the valid data amount of candidate's entity erased cell is not less than the capacity of an entity erased cell, memory control circuit list First 404 (or memory management circuits 502) can perform step S1201 again.

If the valid data amount of candidate's entity erased cell is less than the capacity of an entity erased cell, in step S1205, Memory control circuit unit 404 (or memory management circuit 502) determines that candidate's entity erased cell is the 3rd entity erased cell.

After above-mentioned step S1205, memory control circuit unit 404 (or memory management circuit 502) can also be calculated effectively Data volume summation, and decide whether to be further continued for choosing the entity erased cell being adapted to according to valid data amount summation.This part Describe in detail, will not be repeated here in foregoing exemplary embodiment.

In summary, the present invention can first choose one according to the size for number of times of erasing from the entity erased cell for having valid data Entity erased cell operates to perform average abrasion.If the valid data amount of selected entity erased cell is smeared less than an entity Except unit capacity when, the present invention can choose other entity erased cell with one from the entity erased cell for having valid data And perform average abrasion operation.And during other entity erased cell is chosen, the entity for having valid data is erased list Valid data amount will not be selected not less than the entity erased cell of the capacity of an entity erased cell in member.Thereby can be from storage Space is not all filled with the valid data that a writeable full entity erased cell is collected in the entity erased cell of valid data.Such one Come, can avoid when performing average abrasion operation by entity erased cell using be continuously written into operate write valid data with The valid data write using discontinuous write operation are stored in same entity erased cell, thus can lift refuse collection Efficiency, and ensure that the speed being continuously written into can be maintained more than desired value.

Although the present invention is disclosed as above with embodiment, so it is not limited in the present invention, any art commonly Technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore the protection model of the present invention Enclose to work as and be defined depending on appended claims confining spectrum.

Claims

1. a kind of average abrasion method, for a duplicative Nonvolatile memory module, it is characterised in that described to make carbon copies Formula Nonvolatile memory module has multiple entity erased cells, and each entity erased cell has the capacity of identical one, described Average abrasion method includes：

The multiple entity erased cell is divided into one first group and one second group, wherein the entity of first group is smeared Except unit is without there being valid data, and the entity erased cell of second group stores valid data；

Erased number of times for each entity erased cell record one, and second group is arranged according to the number of times of erasing recorded Entity erased cell；

Number of times of erasing according to being recorded extracts an entity erased cell as one from the entity erased cell of first group One entity erased cell；

Put in order and chosen from the entity erased cell of second group according to the one of the entity erased cell of second group One entity erased cell is as a second instance erased cell, wherein the valid data amount of the second instance erased cell is less than institute State capacity；

Put in order according to the entity erased cell of second group from the entity erased cell of second group only Another entity erased cell that valid data amount is chosen less than the capacity is used as one the 3rd entity erased cell；And

By at least part valid data program of the valid data of the second instance erased cell and the 3rd entity erased cell Change to the first instance erased cell.

2. average abrasion method according to claim 1, it is characterised in that erased list according to the entity of second group Being put in order described in member, it is another less than the capacity that valid data amount is only chosen from the entity erased cell of second group The step of entity erased cell is as the 3rd entity erased cell includes：

Put in order and selected from the entity erased cell of second group according to the entity erased cell of second group An entity erased cell is taken as candidate's entity erased cell, and judges the valid data amount of candidate's entity erased cell Whether the capacity is less than；

If the valid data amount of candidate's entity erased cell is not less than the capacity, according to the entity of second group Described put in order of erased cell chooses another entity erased cell as described from the entity erased cell of second group Candidate's entity erased cell；And

If the valid data amount of candidate's entity erased cell is less than the capacity, candidate's entity erased cell is determined For the 3rd entity erased cell.

3. average abrasion method according to claim 1, it is characterised in that by the effective of the second instance erased cell The step of at least part valid data sequencing to first instance erased cell of data and the 3rd entity erased cell, wraps Include：

One is calculated according to the valid data amount of the second instance erased cell and the valid data amount of the 3rd entity erased cell Valid data amount summation, and judge whether the valid data amount summation is less than the capacity；

If the valid data amount summation is not less than the capacity, by the valid data of the second instance erased cell and institute At least part valid data sequencing of the 3rd entity erased cell is stated to the first instance erased cell；

If the valid data amount summation is less than the capacity, according to the row of the entity erased cell of second group Row order chooses another entity erased cell that valid data amount is less than the capacity from the entity erased cell of second group It is used as one the 4th entity erased cell；And

By the valid data of the second instance erased cell, the valid data of the 3rd entity erased cell and the described 4th in fact At least part valid data sequencing of body erased cell is to the first instance erased cell.

4. average abrasion method according to claim 1, it is characterised in that erased according to what is recorded described in number of times arrangement The step of entity erased cell of second group, includes：

According to the entity erased cell of ascending arrangement second group of the number of times of erasing recorded.

5. average abrasion method according to claim 1, it is characterised in that according to the number of times of erasing recorded from described A step of entity erased cell is as the first instance erased cell is extracted in the entity erased cell of one group to be included：

Extracted from the entity erased cell of first group with maximum erase number of times an entity erased cell as described the One entity erased cell.

6. average abrasion method according to claim 1, it is characterised in that the significant figure of the second instance erased cell It is to belong to multiple discontinuous logical addresses according to the valid data with the 3rd entity erased cell.

7. a kind of memory control circuit unit, for controlling a duplicative Nonvolatile memory module, it is characterised in that institute Stating duplicative Nonvolatile memory module has multiple entity erased cells, and each entity erased cell has the appearance of identical one Amount, the memory control circuit unit includes：

One HPI, is electrically connected to a host computer system；

One memory interface, is electrically connected to the duplicative Nonvolatile memory module；And

One memory management circuit, is electrically connected to the HPI and the memory interface,

Wherein described memory management circuit the multiple entity erased cell is divided into one first group and one second group, The entity erased cell of wherein described first group is without there being a valid data, and the entity erased cell storage of second group There are valid data,

Wherein described memory management circuit for each entity erased cell record one more to erase number of times, and according to being recorded Number of times of erasing arrange the entity erased cell of second group,

Wherein described memory management circuit according to what is recorded more to erase number of times from the entity erased cell of first group An entity erased cell is extracted as a first instance erased cell,

Wherein described memory management circuit is more used to put in order from described the according to the one of the entity erased cell of second group An entity erased cell is chosen in the entity erased cell of two groups as a second instance erased cell, wherein the second instance The valid data amount of erased cell is less than the capacity,

Wherein described memory management circuit according to the entity erased cell of second group more to put in order from described Another entity erased cell of the valid data amount less than the capacity is only chosen in the entity erased cell of second group as one the 3rd Entity erased cell,

Wherein described memory management circuit is more to assign command sequence by valid data of the second instance erased cell and described At least part valid data sequencing of 3rd entity erased cell is to the first instance erased cell.

8. memory control circuit unit according to claim 7, it is characterised in that in the entity according to second group Described put in order of erased cell only chooses valid data amount less than the capacity from the entity erased cell of second group Running of another entity erased cell as the 3rd entity erased cell in, the memory management circuit is more used to according to institute Described put in order for stating the entity erased cell of the second group is chosen an entity from the entity erased cell of second group and smeared Except unit is as candidate's entity erased cell, and judge whether the valid data amount of candidate's entity erased cell is less than institute State capacity,

If the valid data amount of wherein described candidate's entity erased cell is not less than the capacity, the memory management circuit is more Selected to be put in order described in the entity erased cell according to second group from the entity erased cell of second group Another entity erased cell is taken as candidate's entity erased cell,

If the valid data amount of wherein described candidate's entity erased cell is less than the capacity, the memory management circuit is more used To determine candidate's entity erased cell as the 3rd entity erased cell.

9. memory control circuit unit according to claim 7, it is characterised in that assigning command sequence by described second At least part valid data sequencing of the valid data of entity erased cell and the 3rd entity erased cell is to described first real In the running of body erased cell, the memory management circuit be more used to according to the valid data amount of the second instance erased cell and The valid data amount of the 3rd entity erased cell calculates a valid data amount summation, and judges the valid data amount summation Whether the capacity is less than,

If wherein described valid data amount summation is not less than the capacity, the memory management circuit is more to assign sequence of instructions Arrange at least part valid data sequencing of the valid data of the second instance erased cell and the 3rd entity erased cell To the first instance erased cell,

If wherein described valid data amount summation is less than the capacity, the memory management circuit is more used to according to described second Being put in order described in the entity erased cell of group, it is small only to choose valid data amount from the entity erased cell of second group In the capacity another entity erased cell as one the 4th entity erased cell,

Wherein described memory management circuit is more to assign command sequence by valid data of the second instance erased cell, described At least part valid data sequencing of the valid data of 3rd entity erased cell and the 4th entity erased cell is to described One entity erased cell.

10. memory control circuit unit according to claim 7, it is characterised in that according to the number of times of erasing recorded In the running for the entity erased cell for arranging second group, the memory management circuit is more used to be erased time according to what is recorded The entity erased cell of ascending arrangement second group of number.

11. memory control circuit unit according to claim 7, it is characterised in that according to the number of times of erasing recorded An entity erased cell is extracted from the entity erased cell of first group as the running of the first instance erased cell In, the memory management circuit is more used to extract that there is maximum to erase the one of number of times from the entity erased cell of first group Entity erased cell is used as the first instance erased cell.

12. memory control circuit unit according to claim 7, it is characterised in that the second instance erased cell The valid data of valid data and the 3rd entity erased cell are to belong to multiple discontinuous logical addresses.

13. a kind of internal storing memory, it is characterised in that including：

One connecting interface unit, is electrically connected to a host computer system；

One duplicative Nonvolatile memory module, including multiple entity erased cells；And

One memory control circuit unit, is electrically connected to the connecting interface unit and the duplicative Nonvolatile memory module,

Wherein described memory control circuit unit by the multiple entity erased cell to divide into one first group and one second group Group, wherein the entity erased cell of first group is without having valid data, and the entity erased cell of second group Store valid data,

Wherein described memory control circuit unit for each entity erased cell record one more to erase number of times, and according to institute The number of times of erasing of record arranges the entity erased cell of second group,

Wherein described memory control circuit unit is more used to be erased list from the entity of first group according to the number of times of erasing recorded An entity erased cell is extracted in member as a first instance erased cell,

Wherein described memory control circuit unit is more used to put in order from institute according to the one of the entity erased cell of second group An entity erased cell is chosen in the entity erased cell for stating the second group as a second instance erased cell, wherein described second The valid data amount of entity erased cell is less than the capacity,

Wherein described memory control circuit unit more to put in order according to the entity erased cell of second group from Another entity erased cell of the valid data amount less than the capacity is only chosen in the entity erased cell of second group as one 3rd entity erased cell,

Wherein described memory control circuit unit more to assign command sequence by the valid data of the second instance erased cell and At least part valid data sequencing of the 3rd entity erased cell is to the first instance erased cell.

14. internal storing memory according to claim 13, it is characterised in that smeared according to the entity of second group Valid data amount is only chosen from the entity erased cell of second group except being put in order described in unit less than the capacity In running of another entity erased cell as the 3rd entity erased cell, the memory control circuit unit is more used to basis Described put in order of the entity erased cell of second group chooses an entity from the entity erased cell of second group Erased cell judges whether the valid data amount of candidate's entity erased cell is less than as candidate's entity erased cell The capacity,

If the valid data amount of wherein described candidate's entity erased cell is not less than the capacity, the memory control circuit list Entity erased cell of the member more to be put in order according to the entity erased cell of second group from second group It is middle to choose another entity erased cell as candidate's entity erased cell,

If the valid data amount of wherein described candidate's entity erased cell is less than the capacity, the memory control circuit unit More to determine that candidate's entity erased cell is the 3rd entity erased cell.

15. internal storing memory according to claim 13, it is characterised in that real by described second assigning command sequence At least part valid data sequencing of the valid data of body erased cell and the 3rd entity erased cell is to the first instance In the running of erased cell, the memory control circuit unit is more used to the valid data amount according to the second instance erased cell And the valid data amount of the 3rd entity erased cell calculates a valid data amount summation, and judge that the valid data amount is total Whether the capacity is less than,

If wherein described valid data amount summation is not less than the capacity, the memory control circuit unit is more to assign finger Sequence is made by least part valid data journey of the valid data of the second instance erased cell and the 3rd entity erased cell Sequence to the first instance erased cell,

If wherein described valid data amount summation is less than the capacity, the memory control circuit unit is more used to according to described Described put in order of the entity erased cell of second group only chooses valid data from the entity erased cell of second group Amount is less than another entity erased cell of the capacity as one the 4th entity erased cell,

Wherein described memory control circuit unit more to assign command sequence by the valid data of the second instance erased cell, Described at least part valid data sequencing of the valid data and the 4th entity erased cell of the 3rd entity erased cell First instance erased cell.

16. internal storing memory according to claim 13, it is characterised in that according to the number of times arrangement of erasing recorded In the running of the entity erased cell of second group, the memory control circuit unit is more used to be erased time according to what is recorded The entity erased cell of ascending arrangement second group of number.

17. internal storing memory according to claim 13, it is characterised in that according to the number of times of erasing recorded from institute Extracted in the entity erased cell for stating the first group in running of the entity erased cell as the first instance erased cell, institute State memory control circuit unit more real to extract one with maximum number of times of erasing from the entity erased cell of first group Body erased cell is used as the first instance erased cell.

18. internal storing memory according to claim 13, it is characterised in that the second instance erased cell it is effective The valid data of data and the 3rd entity erased cell are to belong to multiple discontinuous logical addresses.