CN106776376A - Buffer storage supervisory method, memorizer control circuit unit and storage device - Google Patents

Buffer storage supervisory method, memorizer control circuit unit and storage device Download PDF

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Publication number
CN106776376A
CN106776376A CN201510820913.2A CN201510820913A CN106776376A CN 106776376 A CN106776376 A CN 106776376A CN 201510820913 A CN201510820913 A CN 201510820913A CN 106776376 A CN106776376 A CN 106776376A
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area
buffer unit
buffer
mapping table
unit
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CN106776376B (en
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陈国荣
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

The present invention provides a kind of buffer storage supervisory method, memorizer control circuit unit and storage device.The method includes：First area is marked off with second area with temporary multiple logical address physical address mapping table in buffer storage, and copy-back operation is performed to first area.The method also includes：A write instruction is received, the logical address physical address mapping table belonging to logical address that wherein this write instruction is indicated has been temporarily stored in first area.The method also includes：This logical address physical address mapping table is copied into second area, and updates this logical address physical address mapping table in second area.The present invention can be lifted by logical address physical address mapping table from buffer storage restore to reproducible nonvolatile memorizer module when operational paradigm and the stability of a system.

Description

Buffer storage supervisory method, memorizer control circuit unit and storage device
Technical field
The invention relates to a kind of buffer storage supervisory method, and deposited in particular to one kind buffering Reservoir management method, memorizer control circuit unit and storage device.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years so that disappear Expense person also rapidly increases the demand of storage media.Due to reproducible nonvolatile memorizer module (example Such as, flash memory) there is data non-volatile, power saving, small volume, and the spy such as mechanical structure Property, so being especially suitable for being built into above-mentioned illustrated various portable multimedia devices.
In general, memory of the reproducible nonvolatile memorizer module as storage media is being used In storage device, buffer storage can be generally also configured, be configured to temporarily store procedure code, data or for depositing Reservoir storage device is performing the staging area of background (background) work hours evidence.For example, depositing The controller of reservoir storage device can by logical address-physical address mapping table be loaded into buffer storage with Profit access data.And when write instruction is received and perform write operation, the control of memory storage apparatus Device processed can update the logical address-physical address mapping table being temporarily stored in buffer storage.And when buffering is deposited Kept in reservoir it is substantial amounts of be updated logical address-physical address mapping table when, memory storage dress Logical address-physical address mapping table that the controller put will can be updated in buffer storage is restored to In reproducible nonvolatile memorizer module.Due to the logical address-physical address mapping table being updated Be possible to be temporarily stored in buffer storage in continuous buffer unit, and duplicative is non-volatile deposits It with physics programming unit is minimum write-in unit that memory modules are again, therefore, it is necessary to by patrolling for being updated Volume address-physical address mapping table first copies to the staging area in buffer storage, be concentrated into equivalent to One size of physics programming unit can just restore to reproducible nonvolatile memorizer module.However, Substantial amounts of duplication operation will cause system load overweight, restore overlong time, decline overall performance.
Additionally, the logical address-physical address mapping table that will be updated in buffer storage be stored back to During reproducible nonvolatile memorizer module, if receiving write instruction again and need to update again Above-mentioned logical address-the physical address mapping table being just stored back, now the controller meeting of memory storage apparatus First pause receives the data of this write instruction and the execution of write operation.Thus, it may occur however that because etc. The situation treated overlong time and cause write-in to fail.Therefore, how to be lifted and reflect logical address-physical address Firing table from buffer storage restore to reproducible nonvolatile memorizer module when operational paradigm and system Stability, is this art personnel's subject under discussion of concern.
The content of the invention
The present invention provides a kind of buffer storage supervisory method, memorizer control circuit unit and storage device, It to lift logical address-physical address mapping table that restore to duplicative from buffer storage non-volatile Operational paradigm and the stability of a system during property memory module.
One example of the present invention embodiment proposes a kind of buffer storage supervisory method, for memory storage The buffer storage of device.This memory storage apparatus has reproducible nonvolatile memorizer module. This buffer storage supervisory method marks off first area and second area in being included in buffer storage, its Middle first area and second area respectively have a continuous multiple buffer units, and first area and the At least a portion buffer unit in buffer unit in two regions has kept in multiple logical addresses-physically Location mapping table.This buffer storage supervisory method also includes the buffer unit of first area is performed to restore grasping Make with will be stored in first area that logical address-physical address mapping table restores to duplicative is non-volatile In property memory module.This buffer storage supervisory method also includes that receiving the first write-in from host computer system refers to Order, and the first write instruction indicates to write first data into the first logical address, and first logically The first logical address-physical address mapping table belonging to location be temporarily stored in first area buffer unit it In the first buffer unit in.This buffer storage supervisory method also includes that the first data of write-in can extremely make carbon copies Formula non-volatile memory module, and the first logical address in first area-physical address mapping table is multiple In making the second buffer unit among the buffer unit in second area.This buffer storage supervisory method Also include updating the first logical address-physical address in temporary the second buffer unit in the second area Mapping table.
In one example of the present invention embodiment, temporary the second caching in the second area of above-mentioned renewal is single The step of the first logical address-physical address mapping table in unit, also includes being denoted as the second buffer unit More new state, and second area is set as update area, and update area is to be configured to temporarily store multiple Logical address-the physical address mapping table being updated.
In one example of the present invention embodiment, above-mentioned buffer storage supervisory method is additionally included in second When all buffer units in region are all for more new state, by patrolling in all buffer units of second area Volume address-physical address mapping table is restored in reproducible nonvolatile memorizer module.
In one example of the present invention embodiment, above-mentioned buffer storage supervisory method is also included according to the The order of the buffer unit in two regions, first buffer unit chosen in second area is slow as second Memory cell, and set the first index the second buffer unit of sensing.Furthermore, by the first logical address-physics Address mapping table is copied to after the second buffer unit in second area, and the first index of setting points to second Another buffer unit among the buffer unit in region, wherein this another buffer unit are the second caching Latter of unit is not the buffer unit of more new state.
In one example of the present invention embodiment, above-mentioned buffer storage supervisory method is also included from main frame System receives the second write instruction, and the second write instruction indicates to write the second data to second logically Location, and the second logical address-physical address mapping table belonging to the second logical address has been temporarily stored in second In the 3rd buffer unit among the buffer unit in region.Furthermore, the second data of write-in are non-to duplicative Volatile, and update the second logic in temporary the 3rd buffer unit in the second area Address-physical address mapping table.
In one example of the present invention embodiment, above-mentioned buffer storage supervisory method is also included from main frame System receives the 3rd write instruction, wherein the 3rd write instruction indicates to write the 3rd data to the 3rd logic Address, and three logical addresses-physical address mapping table belonging to the 3rd logical address is not yet loaded into and reflects Firing table area.Furthermore, the 3rd logical address-physically is loaded into from reproducible nonvolatile memorizer module Location mapping table, and three logical addresses-physical address mapping table is temporarily stored in the buffer unit of second area Among the 4th buffer unit in.Additionally, writing the 3rd data to type nonvolatile mould Three logical addresses-physical address in block, and temporary the 4th buffer unit in the second area of renewal reflects Firing table.
One example of the present invention embodiment proposes a kind of memorizer control circuit unit, for controlling to make carbon copies Formula non-volatile memory module.Memorizer control circuit unit include HPI, memory interface, Buffer storage and memory management circuitry.HPI is electrically connected to host computer system, memory interface Reproducible nonvolatile memorizer module is electrically connected to, buffer storage is electrically connected to HPI And memory interface, memory management circuitry is electrically connected to HPI, memory interface and buffering and deposits Reservoir.Memory management circuitry can mark off first area and second area in buffer storage, wherein First area respectively has continuous multiple buffer unit, and first area and second with second area At least a portion buffer unit in buffer unit in region has kept in multiple logical address-physical address Mapping table.Furthermore, memory management circuitry can perform copy-back operation to the buffer unit of first area to incite somebody to action Store the logical address-physical address mapping table in first area and restore to duplicative non-volatile memories In device module.Also, memory management circuitry more receives the first write instruction from host computer system, and this first Write instruction indicates to write first data into the first logical address, and belonging to the first logical address the What one logical address-physical address mapping table had been temporarily stored among the buffer unit of first area first delays In memory cell.Also, memory management circuitry more writes the first data to duplicative non-volatile memories Device module, and the first logical address in first area-physical address mapping table copied into second area Buffer unit among the second buffer unit in.Additionally, memory management circuitry updates is temporarily stored in second The the first logical address-physical address mapping table in the second buffer unit in region.
In one example of the present invention embodiment, above-mentioned memory management circuitry is also by the second buffer unit More new state is denoted as, and second area is set as update area, and update area is configured to temporarily store Logical address-physical address mapping table that multiple is updated.
In one example of the present invention embodiment, above-mentioned memory management circuitry is also in the institute of second area When having buffer unit all for more new state, by the logical address-thing in all buffer units of second area Reason address mapping table is restored in reproducible nonvolatile memorizer module.
In one example of the present invention embodiment, above-mentioned memory management circuitry is always according in second area Buffer unit order, choose second area in first buffer unit as the second buffer unit, And set the first index the second buffer unit of sensing.Furthermore, by the first logical address in first area- After physical address mapping table is copied in the second buffer unit in second area, above-mentioned memory pipe Reason circuit more sets another buffer unit among the buffer unit of the first index sensing second area, and This another buffer unit is that the latter of the second buffer unit is the buffer unit of more new state.
In one example of the present invention embodiment, above-mentioned memory management circuitry is also received from host computer system Second write instruction, this second write instruction indicates to write the second data to the second logical address, and The second logical address-physical address mapping table belonging to second logical address has been temporarily stored in second area In the 3rd buffer unit among buffer unit.Furthermore, above-mentioned memory management circuitry is also used to write Second data to reproducible nonvolatile memorizer module, and update it is temporary in the second area the 3rd The second logical address-physical address mapping table in buffer unit.
In one example of the present invention embodiment, above-mentioned memory management circuitry is also received from host computer system 3rd write instruction, this 3rd write instruction indicates to write the 3rd data to the 3rd logical address, and Three logical addresses-physical address mapping table belonging to 3rd logical address is not yet loaded into mapping table area.Again Person, above-mentioned memory management circuitry is loaded into the 3rd more from reproducible nonvolatile memorizer module and patrols Address-physical address mapping table is collected, and three logical addresses-physical address mapping table is temporarily stored in the secondth area In the 4th buffer unit among the buffer unit in domain.Additionally, above-mentioned memory management circuitry also writes 3rd data to reproducible nonvolatile memorizer module, and update it is temporary in the second area the 4th Three logical addresses-physical address mapping table in buffer unit.
One example of the present invention embodiment proposes a kind of memory storage apparatus, it include connecting interface unit, Reproducible nonvolatile memorizer module and above-mentioned memorizer control circuit unit.Connecting interface unit Host computer system is electrically connected to, memorizer control circuit unit is electrically connected to connecting interface unit and can answer Formula non-volatile memory module is write, and including buffer storage.
Based on above-mentioned, memorizer control circuit unit that exemplary embodiment of the present invention is proposed, memory are deposited Storage device and its buffer storage supervisory method for using can be saved logical address-physical address effectively Mapping table restores to the time of reproducible nonvolatile memorizer module, and is persistently received during restoring Write-in data from host computer system, can lift the operational paradigm and stability of total system.
It is that features described above of the invention and advantage can be become apparent, special embodiment below, and coordinate Accompanying drawing is described in detail below.
Brief description of the drawings
Fig. 1 is the signal of the host computer system according to shown by an exemplary embodiment and memory storage apparatus Figure；
Fig. 2 is computer according to shown by an exemplary embodiment, input/output device and memory storage dress The schematic diagram put；
Fig. 3 is host computer system according to shown by exemplary embodiment of the present invention and memory storage apparatus show It is intended to；
Fig. 4 is the schematic block diagram of the memory storage apparatus according to shown by an exemplary embodiment；
Fig. 5 is the schematic block diagram of the memorizer control circuit unit according to shown by an exemplary embodiment；
Fig. 6 and Fig. 7 is that the example of the management physics erasing unit according to shown by an exemplary embodiment is illustrated Figure；
Fig. 8 is the schematic diagram of the buffer storage according to shown by an exemplary embodiment；
Fig. 9 A~9F is the schematic diagram of the buffer storage supervisory method according to shown by an exemplary embodiment；
Figure 10 A~10D is showing for the buffer storage supervisory method according to shown by another exemplary embodiment It is intended to；
Figure 11 A and 11B are the flows of the buffer storage supervisory method according to shown by an exemplary embodiment Figure.
Description of reference numerals：
10：Memory storage apparatus；
11：Host computer system；
12：Computer；
13：Input/output device；
122：Microprocessor；
124：Random access memory (RAM)；
126：System bus；
128：Data transmission interface；
21：Mouse；
22：Keyboard；
23：Display；
24：Printer；
25：Portable disk；
26：Memory card；
27：Solid state hard disc；
31：Digital camera；
32：SD card；
33：Mmc card；
34：Memory stick；
35：CF cards；
36：Embedded storage device；
402：Connecting interface unit；
404：Memorizer control circuit unit；
406：Reproducible nonvolatile memorizer module；
410 (0)~410 (N)：Physics wipes unit；
502：Memory management circuitry；
504：HPI；
506：Memory interface；
508：Buffer storage；
510：Electric power management circuit；
512：Error checking and correcting circuit；
602：Data field；
604：Idle area；
606：System area；
608：Substitution area；
LBA (0)~LBA (H)：Logic unit；
LZ (0)~LZ (M)：Logic region；
810 (1-0)~810 (1-n), 810 (2-0)~810 (2-n)：Buffer unit；
MTZ：Mapping table area；
Z1：First area；
Z2：Second area；
P1：First index；
P2：Second index；
MT (0)~MT (2n), MT (k), MT (k) ', MT (s), MT (x)：Logical address-physical address reflects Firing table；
S1101、S1103、S1105、S1107、S1109、S1111、S1113、S1115、S1117、 S1119、S1121、S1123、S1125、S1127、S1129：The step of buffer storage supervisory method.
Specific embodiment
In general, memory storage apparatus (also referred to as, storage system) include that duplicative is non- Volatile and controller (also referred to as, controlling circuit unit).It is commonly stored device storage device To be used together with host computer system so that host computer system can write data into memory storage apparatus or from Data are read in memory storage apparatus.
Fig. 1 is the signal of the host computer system according to shown by an exemplary embodiment and memory storage apparatus Figure, and Fig. 2 is computer according to shown by an exemplary embodiment, input/output device and memory storage The schematic diagram of device.
Fig. 1 is refer to, host computer system 11 generally comprises computer 12 with input/output (input/output, letter Claim：I/O) device 13.Computer 12 includes microprocessor 122, random access memory (random access Memory, referred to as：RAM) 124, system bus 126 and data transmission interface 128.Input/output Device 13 includes such as mouse 21 of Fig. 2, keyboard 22, display 23 and printer 24.Have to be understood that , the unrestricted input/output device 13 of device shown in Fig. 2, input/output device 13 can also include Other devices.
In this exemplary embodiment, memory storage apparatus 10 are by data transmission interface 128 and main frame The other elements of system 11 are electrically connected with.By microprocessor 122, random access memory 124 with it is defeated Enter/running of output device 13 can be write data into memory storage apparatus 10 or from memory storage dress Data are read in putting 10.For example, memory storage apparatus 10 can be Portable disk 25 as shown in Figure 2, Memory card 26 or solid state hard disc (Solid State Drive, abbreviation：SSD) duplicative of 27 grades is non-easily The property lost memory storage apparatus.
Fig. 3 is host computer system according to shown by exemplary embodiment of the present invention and memory storage apparatus show It is intended to.
In general, host computer system 11 is substantially to coordinate to store number with memory storage apparatus 10 According to any system.Although in this exemplary embodiment, host computer system 11 is explained with computer system, However, in another exemplary embodiment host computer system 11 can be digital camera, video camera, communicator, The system such as audio player or video player.For example, the digital camera in host computer system is for Fig. 3 (is taken the photograph Shadow machine) 31 when, SD card 32 that type nonvolatile storage device is then used for it, Mmc card 33, memory stick (memory stick) 34, CF cards 35 or embedded storage device 36 are (such as Shown in Fig. 3).Embedded storage device 36 includes embedded multi-media card (Embedded MMC, letter Claim：EMMC), general flash memory (Universal Flash Storage, abbreviation：UFS).Value Obtain one and be mentioned that embedded multi-media card or general flash memory are directly to be electrically connected at host computer system Substrate on.
Fig. 4 is the schematic block diagram of the memory storage apparatus according to shown by an exemplary embodiment.
Fig. 4 is refer to, memory storage apparatus 10 include that connecting interface unit 402, memory controls electricity Road unit 404 and reproducible nonvolatile memorizer module 406.
In this exemplary embodiment, connecting interface unit 402 is compatible with Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, referred to as：SATA) standard.However, it is necessary to be appreciated that, The invention is not restricted to this, connecting interface unit 402 can also meet parallel advanced technology annex (Parallel Advanced Technology Attachment, referred to as：PATA) standard, Electrical and Electronic engineer association Meeting (Institute of Electrical and Electronic Engineers, referred to as：IEEE) 1394 standards, High-speed peripheral component connecting interface (Peripheral Component Interconnect Express, referred to as：PCI Express) standard, universal serial bus (Universal Serial Bus, abbreviation：USB) standard, super A high speed generation (Ultra High Speed-I, referred to as：UHS-I) interface standard, the generation of ultrahigh speed two (Ultra High Speed-II, referred to as：UHS-II) interface standard, secure digital (Secure Digital, abbreviation：SD) Interface standard, memory stick (Memory Stick, abbreviation：MS) interface standard, multimedia storage card (Multi Media Card, referred to as：MMC) interface standard, compact flash (Compact Flash, abbreviation：CF) Interface standard, integrated form drive electrical interface (Integrated Device Electronics, abbreviation：IDE) Standard or other suitable standards.In this exemplary embodiment, connecting interface unit can be with memory control Circuit unit is encapsulated in a chip, or is laid in outside a chip comprising memorizer control circuit unit.
Memorizer control circuit unit 404 is used to perform is patrolled with the multiple of hardware pattern or software pattern implementation Volume lock or control instruction, and according to the instruction of host computer system 11 in type nonvolatile mould The write-in of data is carried out in block 406, is read and the running such as erase.
Reproducible nonvolatile memorizer module 406 is electrically connected to memorizer control circuit unit 404, and the data write to host system 11.Type nonvolatile mould There is block 406 physics to wipe unit 410 (0)~410 (N).For example, physics wipes unit 410 (0)~410 (N) Same memory crystal grain (die) can be belonged to or belong to different memory crystal grains.Each physics erasing Unit has multiple physics programming units respectively, wherein belonging to the physics programming of same physics erasing unit Unit can be written independently and simultaneously be erased.However, it is necessary to be appreciated that, the invention is not restricted to This, each physics erasing unit be can by 64 physics programming units, 256 physics programming units or its He is constituted any physics programming unit.
In more detail, physics erasing unit is the least unit erased.That is, each physics erasing is single First memory cell being erased in the lump containing minimal amount.Physics programming unit is the minimum unit of programming. That is, physics programming unit is the minimum unit for writing data.Each physics programming unit generally includes data Bit area and redundancy ratio special zone.Data bit area includes multiple physics access addresses and is used to store user's Data, and redundancy ratio special zone is to the data (for example, control information and error correcting code) of storage system. In this exemplary embodiment, can be deposited comprising 8 physics in the data bit area of each physics programming unit Address is taken, and a size for physics access address is 512 bytes (byte).However, in other models In example embodiment, the more or less physics access address of number, this hair can be also included in data bit area The bright size and number for being not intended to limit physics access address.For example, in an exemplary embodiment, physics Erasing unit be physical blocks, and physics programming unit be physical page or physical sector, but the present invention It is not limited.
In this exemplary embodiment, reproducible nonvolatile memorizer module 406 is multi-level cell memory (Multi Level Cell, referred to as：MLC) NAND type flash memory module (that is, one storage 2 flash memory modules of data bit can be stored in unit).However, the invention is not restricted to this, Reproducible nonvolatile memorizer module 406 may also be single-order memory cell (Single Level Cell, Referred to as：SLC) NAND type flash memory module (that is, can store 1 number in one memory cell According to the flash memory module of bit), multi-level cell memory (Trinary Level Cell, referred to as：TLC) NAND type flash memory module (that is, can store 3 quick flashings of data bit in one memory cell Memory module), other flash memory modules or other there is the memory module of identical characteristics.
Fig. 5 is the schematic block diagram of the memorizer control circuit unit according to shown by an exemplary embodiment.
Fig. 5 is refer to, memorizer control circuit unit 404 connects including memory management circuitry 502, main frame Mouthfuls 504 with memory interface 506, buffer storage 508, electric power management circuit 510 and error checking with Correcting circuit 512.
Memory management circuitry 502 controls the overall operation of circuit unit 404 to control memory.Tool For body, memory management circuitry 502 has multiple control instructions, and in memory storage apparatus 10 During running, the running such as this little control instruction can be performed carrying out the write-in of data, reads and erase.
In this exemplary embodiment, the control instruction of memory management circuitry 502 is to come real with software pattern Make.For example, memory management circuitry 502 has microprocessor unit (not shown) and read-only storage (not shown), and this little control instruction is programmed in so far read-only storage.Work as memory storage Device 10 operate when, this little control instruction can be performed by microprocessor unit with carry out data write-in, The running such as read and erase.
Fig. 6 and Fig. 7 is that the example of the management physics erasing unit according to shown by an exemplary embodiment is illustrated Figure.
It will be appreciated that being described herein the physics erasing of reproducible nonvolatile memorizer module 406 During the running of unit, operating physical erasing unit is come with the word such as " extraction ", " packet ", " division ", " association " It is concept in logic.That is, the physics erasing unit of reproducible nonvolatile memorizer module Physical location do not change, but the physics of reproducible nonvolatile memorizer module is wiped in logic Except unit is operated.
Fig. 6 is refer to, memorizer control circuit unit 404 (or memory management circuitry 502) can be by thing Reason erasing unit 410 (0)~410 (N) is logically grouped into data field 602, idle area 604, system area 606 With substitution area 608.
The physics erasing unit that data field 602 is logically belonged to idle area 604 is to store to come from The data of host computer system 11.Specifically, the physics erasing unit of data field 602 is regarded as having stored The physics erasing unit of data, and the physics erasing unit in idle area 604 is to replacement data area 602 Physics erasing unit.That is, work as receiving write instruction with the number to be write from host computer system 11 According to when, memory management circuitry 502 can from idle area 604 extracts physical erasing unit, and by number According to write-in to the physics erasing unit for being extracted, unit is wiped with the physics in replacement data area 602.
The physics erasing unit for logically belonging to system area 606 is to record system data.For example, being System data include that the manufacturer on reproducible nonvolatile memorizer module is non-with model, duplicative The physics erasing unit number of volatile, each physics wipe the physics programming unit number of unit Deng.
It is for bad physics erasing unit substitution journey to logically belong to replace the physics erasing unit in area 608 Sequence, unit is wiped with replacing damaged physics.Specifically, if still having in substitution area 608 normal Physics erasing unit and data field 602 physics erasing unit damage when, memory management circuitry 502 Normal physics erasing unit can be extracted from substitution area 608 to change the physics erasing unit of damage.
Particularly, data field 602, idle area 604, system area 606 and the physics in substitution area 608 are wiped The quantity of unit can be different according to different memory specifications.Further, it is necessary to be appreciated that, In the running of memory storage apparatus 10, physics erasing unit associate to data field 602, idle area 604, System area 606 can dynamically change with the packet relation in substitution area 608.For example, when in idle area 604 Physics erasing unit damage and the physics erasing unit in substituted area 608 when replacing, then substitution area originally 608 physics erasing unit can be associated to idle area 604.
Fig. 7 is refer to, memorizer control circuit unit 404 (or memory management circuitry 502) can be configured Logic unit LBA (0)~LBA (H) wipes unit, each of which logic to map the physics of data field 602 Unit has multiple logical subunits to map the physics programming unit that corresponding physics wipes unit.Also, When the data during the logic unit to be write data to of host computer system 11 or renewal are stored in logic unit, deposit Memory control circuit unit 404 (or memory management circuitry 502) can extract one from idle area 604 Physics wipes unit to write data, and unit is wiped with the physics of data field 602 of rotating.In this example reality Apply in example, logical subunit can be logical page (LPAGE) or logic sector.
In order to which physics erasing unit is the data for recognizing each logic unit be stored in, in this example reality Apply in example, memorizer control circuit unit 404 (or memory management circuitry 502) can record logic unit With the mapping between physics erasing unit.Also, when host computer system 11 is intended to access number in logical subunit According to when, memorizer control circuit unit 404 (or memory management circuitry 502) can confirm that this logic is single Logic unit belonging to unit, and data are accessed in physics that this logic unit the is mapped erasing unit. For example, in this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) Can logical address-physical address mapping table be stored in reproducible nonvolatile memorizer module 406 to remember Record the physics erasing unit that each logic unit is mapped, and the memory control electricity when data to be accessed Can be loaded into for logical address-physical address mapping table by road unit 404 (or memory management circuitry 502) Buffer storage 508 is safeguarded.
It is noted that because the finite capacity of buffer storage 508 cannot all logics of stored record The mapping table of the mapping relations of unit, therefore, in this exemplary embodiment, memorizer control circuit unit Logic unit LBA (0)~LBA (H) can be grouped into multiple logics by 404 (or memory management circuitries 502) Region LZ (0)~LZ (M), and for each logic region configures a logical address-physical address mapping table. Particularly, patrolled when memorizer control circuit unit 404 (or memory management circuitry 502) is intended to update certain When collecting the mapping of unit, the logical address-physical address map of the logic region belonging to this logic unit is corresponded to Table can be loaded on buffer storage 508 to be updated.
In another exemplary embodiment of the invention, the control instruction of memory management circuitry 502 can also journey Sequence pattern formula is stored in the specific region of reproducible nonvolatile memorizer module 406 (for example, storage The system area of storage system data is exclusively used in device module) in.Additionally, memory management circuitry 502 has There are microprocessor unit (not shown), read-only storage (not shown) and random access memory (not Show).Particularly, this read-only storage has driving code, and when memorizer control circuit unit 404 When being enabled, microprocessor unit can first carry out this and drive code section non-volatile will be stored in duplicative Control instruction in memory module 406 is loaded into the random access memory of memory management circuitry 502 In.Afterwards, microprocessor unit can operate this little control instruction carrying out the write-in of data, read and smear Operated except waiting.
Additionally, in another exemplary embodiment of the invention, the control instruction of memory management circuitry 502 Implementation can be come with a hardware pattern.For example, memory management circuitry 502 includes that microcontroller, storage are single First management circuit, memory write circuit, memory reading circuitry, memory are erased at circuit and data Reason circuit.Storage Unit Management circuit, memory write circuit, memory reading circuitry, memory are smeared Except circuit and data processing circuit are electrically connected to microcontroller.Wherein, Storage Unit Management circuit is used Unit is wiped with the physics for managing reproducible nonvolatile memorizer module 406；Memory write circuit It is used to assign write instruction to reproducible nonvolatile memorizer module 406 write data into can answer In writing formula non-volatile memory module 406；Memory reading circuitry is used to non-volatile to duplicative Memory module 406 is assigned reading instruction and is read with from reproducible nonvolatile memorizer module 406 Data；Memory circuit of erasing is used to assign finger of erasing to reproducible nonvolatile memorizer module 406 Order is erased with by data from reproducible nonvolatile memorizer module 406；And data processing circuit is used With process be intended to write it is to the data of reproducible nonvolatile memorizer module 406 and non-from duplicative The data read in volatile 406.
Referring again to Fig. 5, HPI 504 is electrically connected to memory management circuitry 502 and uses To be electrically connected to connecting interface unit 402, with receive and recognize instruction that host computer system 11 transmitted with Data.That is, the instruction that host computer system 11 is transmitted can be passed with data by HPI 504 Deliver to memory management circuitry 502.In this exemplary embodiment, HPI 504 is compatible with SATA Standard.However, it is necessary to be appreciated that HPI 504 can also be compatible with the invention is not restricted to this PATA standards, the standards of IEEE 1394, PCI Express standards, USB standard, UHS-I interface marks Standard, UHS-II interface standards, SD standards, MS standards, MMC standards, CF standards, IDE mark Accurate or other suitable data transmission standards.
Memory interface 506 is electrically connected to memory management circuitry 502 and is used to access to make carbon copies Formula non-volatile memory module 406.That is, being intended to write to type nonvolatile The data of module 406 can be converted to reproducible nonvolatile memorizer module by memory interface 506 The 406 receptible forms of institute.
Buffer storage 508 is electrically connected to memory management circuitry 502 and is configured to temporarily store come from The data of host computer system 11 and the number for instructing or coming from reproducible nonvolatile memorizer module 406 According to.
Electric power management circuit 510 is electrically connected to memory management circuitry 502 and is used to control storage The power supply of device storage device 10.
Error checking is electrically connected to memory management circuitry 502 and is used to hold with correcting circuit 512 Row error checking and correction program are ensuring the correctness of data.Specifically, memory management circuitry is worked as 502 from host computer system 11 when receiving write instruction, and error checking can be corresponding with correcting circuit 512 The data of this write instruction produce corresponding error checking and correcting code (Error Checking and Correcting Code, referred to as：ECC Code), and memory management circuitry 502 can will correspondence this write The data for entering instruction are write to type nonvolatile mould with corresponding error checking and correcting code In block 406.Afterwards, when memory management circuitry 502 from reproducible nonvolatile memorizer module 406 Can simultaneously read the corresponding error checking of this data and correcting code during middle reading data, and error checking with Correcting circuit 512 can perform error checking and school according to this error checking and correcting code to the data for being read Positive program.
Fig. 8 is the schematic diagram of the buffer storage according to shown by an exemplary embodiment.
Fig. 8 is refer to, in this exemplary embodiment, memorizer control circuit unit 404 (or memory pipe Reason circuit 502) mapping table area MTZ is marked off in buffer storage 508, it is configured to temporarily store from can make carbon copies Logical address-physical address mapping table loaded by formula non-volatile memory module 406.Particularly, deposit Memory control circuit unit 404 (or memory management circuitry 502) can more divide mapping table area MTZ It is first area Z1 and second area Z2, and first area Z1 and second area Z2 is respectively with continuous Multiple buffer units.Each buffer unit is configured to temporarily store a logical address-physical address mapping table, and Each buffer unit can be denoted as different conditions, for example, updated (dirty) state, do not updated (clean) State, invalid (invalid) state, storage (saving) state are loaded into (loading) state etc., It is used to represent the state of the data in buffer unit.In this exemplary embodiment, a logical address-physics The size of address mapping table is 512B, therefore, the size of each buffer unit is 512B.And the firstth area The big I of domain Z1 and second area Z2 is a particular value, such as 64MB or 128MB.However, must Palpus Liao solutions, in other exemplary embodiments, the big I of buffer unit is according to actual logical address-thing Depending on reason address mapping table, and first area Z1 and second area Z2 size also visual actually used need Ask and set, the present invention is not any limitation as.
As shown in figure 8, first area Z1 has buffer unit 810 (1-0)~810 (1-n), second area Z2 has buffer unit 810 (2-0)~810 (2-n).In this exemplary embodiment, memorizer control circuit list First 404 (or memory management circuitries 502) can in advance from reproducible nonvolatile memorizer module 406 The middle mapping table area being loaded into multiple logical address-physical address mapping tables in buffer storage 508 MTZ, and this little logical address-physical address mapping table is distinctly kept in first area Z1 and the secondth area In the buffer unit of domain Z2.
Fig. 9 A~9F is the schematic diagram of the buffer storage supervisory method according to shown by an exemplary embodiment.
Fig. 9 A are refer to, the buffer unit 810 (1-0)~810 (1-n) in the Z1 of first area is kept in patrol respectively Collect address-physical address mapping table MT (0)~MT (n), the buffer unit in second area Z2 810 (2-0)~810 (2-n) difference register logic address-physical address mapping table MT (n+1)~MT (2n).It is side Just illustrate, this exemplary embodiment is not for the buffer unit of first area Z1 and second area Z2 More new state starts explanation.When write instruction is received from host computer system 11, this write instruction indicates to write Enter data to write to logical address, memorizer control circuit unit 404 (or memory management circuitry 502) Logical address-physical address mapping table belonging to this logical address can be kept in the of mapping table area MTZ One region Z1 is being safeguarded.In more detail, (or the memory pipe of memorizer control circuit unit 404 Reason circuit 502) can first judge that the logical address-physical address mapping table belonging to the logical address to be write is It is no to be temporarily stored in the buffer unit of first area Z1 or second area Z2.
In this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) Update area can be set, the logical address-physical address mapping table being updated is configured to temporarily store.In this example reality In applying example, when the just upper electricity of memory storage apparatus 10, memorizer control circuit unit 404 (or storage Device manages circuit 502) it is that update area is set as first area Z1.And in another exemplary embodiment, Memorizer control circuit unit 404 (or memory management circuitry 502) initially can also set update area It is set to second area Z2.
Write data into belonging to logical address-physical address mapping table when instruction is received from host computer system During the write instruction of the logical address of MT (n+2), memorizer control circuit unit 404 (or memory management Circuit 502) can decision logic address-physical address mapping table MT (n+2) it is loaded to buffer storage 508 In mapping table area MTZ, and be temporarily stored in the buffer unit 810 (2-1) of second area Z2.Therefore, Memorizer control circuit unit 404 (or memory management circuitry 502) can be write data into duplicative The physics programming unit that logical address is mapped described in non-volatile memory module 406, and update temporary There is the logical address-physical address mapping table MT (n+2) of buffer unit 810 (2-1).Then, memory Control circuit unit 404 (or memory management circuitry 502) can be by updated logical address-physically Moved to being set to more at present from the buffer unit 810 (2-1) of second area Z2 location mapping table MT (n+2) In the first area Z1 of new region.
In this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) The one of buffer unit during the first index P1 points to first area Z1 can be also set, and this is pointed at Buffer unit be not more new state.Specifically, memorizer control circuit unit 404 (or storage Device manages circuit 502) can multiple buffer units in the Z1 of first area tandem, by going to Sequentially judge whether afterwards not for more new state.As shown in Figure 9 A, due in now first area Z1 All buffer units are not more new state.Therefore, memorizer control circuit unit 404 (or storage Device manage circuit 502) setting the first index P1 point to first area Z1 in first buffer unit 810(1-0).Afterwards, memorizer control circuit unit 404 (or memory management circuitry 502) can basis First index P1 stores updated logical address-physical address mapping table.For example, memory is controlled Circuit unit 404 (or memory management circuitry 502) can be according to the first index P1 by updated logic Address-physical address mapping table MT (n+2) is moved to first from the buffer unit 810 (2-1) of second area Z2 In the buffer unit 810 (1-0) of region Z1.
Fig. 9 B are refer to, updated logical address-physical address mapping table MT (n+2) is moved to After in the buffer unit 810 (1-0) of one region Z1, memorizer control circuit unit 404 (or memory Management circuit 502) buffer unit 810 (1-0) can be denoted as more new state.Additionally, memory is controlled Circuit unit 404 (or memory management circuitry 502) can set the first index P1 and point to first area Z1 In the latter of buffer unit 810 (1-0) be the buffer unit of more new state.Implement in this example In example, latter buffer unit 810 (1-1) of buffer unit 810 (1-0) is not for more new state.Therefore, Memorizer control circuit unit 404 (or memory management circuitry 502) can set the first index P1 sensings Buffer unit 810 (1-1).In this exemplary embodiment, memorizer control circuit unit 404 (or memory Management circuit 502) script can be more temporarily stored in the logic in the buffer unit 810 (1-0) of first area Z1 Address-physical address mapping table MT (0) is moved into the buffer unit 810 (2-1) of second area Z2.And In another exemplary embodiment, can not also move and directly override logical address-physical address mapping table MT(0)。
Now, write data into belonging to logical address-physical address if receiving instruction from host computer system During another write instruction of the logical address of mapping table MT (n), memorizer control circuit unit 404 (or deposit Reservoir manages circuit 502) can decision logic address-physical address mapping table MT (n) be loaded deposits to buffering Mapping table area MTZ in reservoir 508, and it is temporarily stored in the buffer unit 810 (1-n) of first area Z1 In.As shown in Figure 9 C, memorizer control circuit unit 404 (or memory management circuitry 502) can be by Data write the physics mapped to logical address described in reproducible nonvolatile memorizer module 406 Programming unit, renewal is temporarily stored in the logical address-physical address mapping table in buffer unit 810 (1-n) MT (n), and buffer unit 810 (1-n) is denoted as more new state.
Now, write data into belonging to logical address-physical address if receiving instruction from host computer system During the another write instruction of the logical address of mapping table MT (k), memorizer control circuit unit 404 (or deposit Reservoir manages circuit 502) can decision logic address-physical address mapping table MT (k) be not yet loaded on it is slow The mapping table area MTZ rushed in memory 508.Therefore, memorizer control circuit unit 404 (or storage Device manages circuit 502) can be from reproducible nonvolatile memorizer module 406 by logical address-physics Address mapping table MT (k) is loaded into mapping table area MTZ, and with the firstth area pointed by the first index P1 Buffer unit 810 (1-1) in the Z1 of domain carrys out register logic address-physical address mapping table MT (k).As schemed Shown in 9D, logical address-physical address mapping table MT (k) is temporarily stored in the caching list in the Z1 of first area In 810 (1-1) of unit, and memorizer control circuit unit 404 (or memory management circuitry 502) is by data In write-in to reproducible nonvolatile memorizer module 406.Additionally, memorizer control circuit unit 404 (or memory management circuitry 502) and can more new logical addresses-physical address mapping table MT (k), and will Buffer unit 810 (1-1) is denoted as more new state.Further, memorizer control circuit unit 404 (or memory management circuitry 502) can choose latter of buffer unit 810 (1-1) in the Z1 of first area For the buffer unit 810 (1-2) of more new state is configured to temporarily store next updated logical address-physics Address mapping table, and set the first index P1 sensings buffer unit 810 (1-2).
In this exemplary embodiment, if all buffer units 810 (1-0)~810 (1-n) in the Z1 of first area All it is denoted as more new state, memorizer control circuit unit 404 (or memory management circuitry 502) Copy-back operation can be started, all buffer units 810 (1-0)~810 (1-n) of first area Z1 will be temporarily stored in In logical address-physical address mapping table restore to reproducible nonvolatile memorizer module 406. It is understood, however, that, memorizer control circuit unit 404 (or memory management circuitry 502) also can Start copy-back operation in other times point.For example, data merging or refuse collection (Garbage are being performed ) etc. collection before background operation or memory storage apparatus are de-energized or through not receiving after a while When to the write instruction for coming from host computer system 11, memorizer control circuit unit 404 (or deposit Reservoir manages circuit 502) can also start copy-back operation, the logical address-physical address mapping table that will be updated Restore to reproducible nonvolatile memorizer module 406.
In this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) The one of buffer unit during the second index P2 points to second area Z2 can also be set.Specifically, Memorizer control circuit unit 404 (or memory management circuitry 502) can be according in second area Z2 The tandem of multiple buffer units, determines the second index P2 buffer units to be pointed to back to front. As shown in fig. 9e, can be set since last buffer unit 810 (2-n) in second area Z2 Second index P2 points to buffer unit 810 (2-n).
Now, if receiving instruction reading from host computer system belongs to logical address-physical address mapping table When the reading of the data of the logical address of MT (s) is instructed, memorizer control circuit unit 404 (or memory Management circuit 502) can decision logic address-physical address mapping table MT (s) be not yet loaded on buffering and deposit Mapping table area MTZ in reservoir 508.Therefore, (or the memory pipe of memorizer control circuit unit 404 Reason circuit 502) can be from reproducible nonvolatile memorizer module 406 by logical address-physical address Mapping table MT (s) is loaded into mapping table area MTZ, and with the buffer unit pointed by the second index P2 810 (2-n) carry out register logic address-physical address mapping table MT (s).As shown in fig. 9f, logical address- After physical address mapping table MT (s) is temporarily stored in the buffer unit 810 (2-n) in second area Z2, Memorizer control circuit unit 404 (or memory management circuitry 502) just can be according to logical address-physics Address mapping table MT (s) reads data of the storage in reproducible nonvolatile memorizer module.Additionally, Memorizer control circuit unit 404 (or memory management circuitry 502) simultaneously can set the second index P2 and refer to To the previous buffer unit of buffer unit 810 (2-n) in second area Z2, i.e. buffer unit 810(2-(n-1)).In this exemplary embodiment, if the second index P2 has pointed to the of second area Z2 During one buffer unit 810 (2-0), memorizer control circuit unit 404 (or memory management circuitry 502) Last buffer unit 810 (2-n) that second area Z2 can be chosen will as next second index P2 The buffer unit of sensing.
Now, if receiving instruction reading from host computer system belongs to logical address-physical address mapping table When another reading of the data of the logical address of MT (n+1) is instructed, memorizer control circuit unit 404 (or Memory management circuitry 502) can decision logic address-physical address mapping table MT (n+1) be loaded on Mapping table area MTZ in buffer storage 508, and it is temporarily stored in the buffer unit of second area Z2 In 810 (2-0).As shown in fig. 9f, memorizer control circuit unit 404 (or memory management circuitry 502) Directly reflected according to the logical address-physical address being temporarily stored in the buffer unit 810 (2-0) of second area Z2 Firing table MT (n+1) reads the data in reproducible nonvolatile memorizer module 406.
Figure 10 A~10D is showing for the buffer storage supervisory method according to shown by another exemplary embodiment It is intended to.Figure 10 A~10D is related to be received during copy-back operation is performed to first area Z1 and write Enter buffer storage supervisory method when instructing.
Figure 10 A are refer to, in this exemplary embodiment, if being set to the first area of update area When all buffer units 810 (1-0)~810 (1-n) are all denoted as more new state in Z1, memory control Circuit unit 404 (or memory management circuitry 502) can start copy-back operation, will be temporarily stored in the firstth area Logical address-physical address mapping table in the Z1 of domain is restored in reproducible nonvolatile memorizer module. However, memorizer control circuit unit 404 (or memory management circuitry 502) also can be in other times point Start copy-back operation, and in foregoing teachings for example, will not be repeated here.Additionally, starting Copy-back operation is restored to and can answered with the logical address-physical address mapping table that will be temporarily stored in the Z1 of first area When writing formula non-volatile memory module, memorizer control circuit unit 404 (or memory management circuitry 502) update area can be reset for second area Z2.Therefore, write when being received from host computer system 11 Enter instruction, memorizer control circuit unit 404 (or memory management circuitry 502) can be according to being received Logical address-physical address mapping table that write instruction need to will update is kept in the second of mapping table area MTZ Region Z2 (i.e. update area) is being safeguarded.In this exemplary embodiment, memorizer control circuit list First 404 (or memory management circuitries 502) can be pointed in second area Z2 wherein the first index P1 One buffer unit, and this buffer unit for being pointed at is not more new state.As shown in Figure 10 A, by All buffer units in now second area Z2 are not more new state, therefore, memory control Circuit unit 404 (or memory management circuitry 502) can set the first index P1 and point to second area Z2 In first buffer unit 810 (2-0).
During copy-back operation, if from host computer system 11 receive instruction by data (below referring also to for First data) write-in is to belonging to logical address-physical address mapping table MT (k) (below referring also to being first Logical address-physical address mapping table) logical address write instruction (below referring also to be first write-in Instruction) when, memorizer control circuit unit 404 (or memory management circuitry 502) can decision logic ground The loaded mapping table area MTZ into buffer storage 508 of location-physical address mapping table MT (k), and quilt It is temporarily stored in the buffer unit 810 (1-1) of first area Z1 (below referring also to be the first buffer unit). Now, memorizer control circuit unit 404 (or memory management circuitry 502) can be write data into can The physics programming unit that logical address is mapped described in manifolding formula non-volatile memory module 406, and Logical address-physical address mapping table MT (k) is copied into second area Z2, and is temporarily stored in the first index In buffer unit 810 (2-0) (below referring also to be the second buffer unit) pointed by P1.Memory control Circuit unit processed 404 (or memory management circuitry 502) is by logical address-physical address mapping table MT (k) Logical address-physical address mapping table MT (k) ' is copied as, and as shown in Figure 10 B, by logical address-thing Reason address mapping table MT (k) ' is temporarily stored in the buffer unit 810 (2-0) of second area Z2.Also, storage Device control circuit unit 404 (or memory management circuitry 502) can update and be temporarily stored in second area Z2 Buffer unit 810 (2-0) in logical address-physical address mapping table MT (k) ', and by buffer unit 810 (2-0) are denoted as more new state.Additionally, memorizer control circuit unit 404 (or memory management Circuit 502) the first index P1 can be set point to the latter of buffer unit 810 (2-0) in second area Z2 Individual is not the buffer unit of more new state.In this exemplary embodiment, after buffer unit 810 (2-0) One buffer unit 810 (2-1) is not for more new state.Therefore, memorizer control circuit unit 404 (or memory management circuitry 502) can set the first index P1 and point to buffer unit 810 (2-1).
Now, data (below referring also to be the second data) are write if receiving instruction from host computer system Enter to belong to logical address-physical address mapping table MT (n+3) (below referring also to for the second logical address- Physical address mapping table) logical address another write instruction (below referring also to be the second write instruction) When, memorizer control circuit unit 404 (or memory management circuitry 502) can decision logic address-thing Reason address mapping table MT (n+3) loaded mapping table area MTZ into buffer storage 508, and it is temporary In there is the buffer unit 810 (2-2) (below referring also to be the 3rd buffer unit) of second area Z2.Such as Shown in Figure 10 C, memorizer control circuit unit 404 (or memory management circuitry 502) can write data Enter the physics mapped to logical address described in reproducible nonvolatile memorizer module 406 and program list Unit, and more new logical addresses-physical address mapping table MT (n+3), and buffer unit 810 (2-2) is indicated For more new state.
Now, data (below referring also to be the 3rd data) are write if receiving instruction from host computer system Enter to belonging to logical address-physical address mapping table MT (x) (below referring also to being three logical addresses-physics Address mapping table) logical address another write instruction (below referring also to be the 3rd write instruction) when, Memorizer control circuit unit 404 (or memory management circuitry 502) decision logic address-physical address Mapping table MT (x) is not yet loaded on the mapping table area MTZ in buffer storage 508.Therefore, store Device controls circuit unit 404 (or memory management circuitry 502) meeting from type nonvolatile Logical address-physical address mapping table MT (x) is loaded into mapping table area MTZ in module 406, and with Buffer unit 810 (2-1) in second area Z2 pointed by one index P1 carrys out register logic address-physics Address mapping table MT (x).As shown in Figure 10 D, logical address-physical address mapping table MT (x) is kept in In buffer unit 810 (2-1) (below referring also to be the 4th buffer unit) in second area Z2, and Memorizer control circuit unit 404 (or memory management circuitry 502) can be write data into duplicative Non-volatile memory module 406.Memorizer control circuit unit 404 (or memory management circuitry 502) And can more new logical addresses-physical address mapping table MT (x), and buffer unit 810 (2-1) is denoted as More new state.
Further, memorizer control circuit unit 404 (or memory management circuitry 502) can be chosen Latter of buffer unit 810 (2-1) is not the buffer unit of more new state to set in second area Z2 First index P1.In this exemplary embodiment, memorizer control circuit unit 404 (or memory management Circuit 502) can sequentially judge that latter buffer unit 810 (2-2) of buffer unit 810 (2-1) has been labeled For more new state.Therefore, memorizer control circuit unit 404 (or memory management circuitry 502) meeting Sequentially finds backward be not the buffer unit of more new state.Then, memorizer control circuit unit 404 (or memory management circuitry 502) can judge latter buffer unit 810 (2-3) of buffer unit 810 (2-2) It is not more new state, and sets the first index P1 to point to buffer unit 810 (2-3).
In this exemplary embodiment, after the copy-back operation on first area Z1 is completed, i.e. memory Control circuit unit 404 (or memory management circuitry 502) is by all caching lists of first area Z1 Logical address-physical address mapping table in first 810 (1-0)~810 (1-n) writes non-volatile to the duplicative Property memory module in, memorizer control circuit unit 404 (or memory management circuitry 502) can be by the All buffer units 810 (1-0)~810 (1-n) of one region Z1 are denoted as not more new state.Consequently, it is possible to When all buffer units 810 (2-0)~810 (2-n) of second area Z2 are all denoted as more new state, Memorizer control circuit unit 404 (or memory management circuitry 502) can start copy-back operation, will be temporary There is the logical address-physical address in all buffer units 810 (2-0)~810 (2-n) of second area Z2 Mapping table is restored in reproducible nonvolatile memorizer module 406, while resetting update area It is first area Z1, write-in behaviour is performed with the data of lasting write instruction of the reception from host computer system Make.In addition, in another exemplary embodiment, memorizer control circuit unit 404 (or memory Management circuit 502) subdivided in buffer storage 508 can also go out there is continuous multiple buffer unit Another region carry out register logic address-physical address mapping table, the present invention is not any limitation as.
Figure 11 A and 11B are the flows of the buffer storage supervisory method according to shown by an exemplary embodiment Figure.
Figure 11 A are refer to, in step S1101, memorizer control circuit unit 404 (or memory Management circuit 502) mapping table area can be marked off in buffer storage 508.
In step S1103, memorizer control circuit unit 404 (or memory management circuitry 502) meeting Mapping table zoning is divided into the first area and second area respectively with continuous multiple buffer unit.
In step S1105, memorizer control circuit unit 404 (or memory management circuitry 502) from Multiple logical address-physical address mapping tables to first are loaded into reproducible nonvolatile memorizer module Region and second area.As described above, each logical address-physical address mapping table being written into be by One of buffer unit in temporary one of buffer unit or second area in the first region.
In step S1107, memorizer control circuit unit 404 (or memory management circuitry 502) will Update area is set as first area.
In step S1109, memorizer control circuit unit 404 (or memory management circuitry 502) is more One of logical address-physical address mapping table of new the multiple logical address-physical address mapping table, This one of logical address-physical address mapping table is kept in the buffer unit of first area One of buffer unit, and this one of buffer unit in first area is denoted as having updated State.Specifically, memorizer control circuit unit 404 (or memory management circuitry 502) can basis The write instruction received from host computer system 11 comes more new logical addresses-physical address mapping table, correlation behaviour Make mode to be illustrated in foregoing exemplary embodiment, will not be repeated here.
In step S1111, if all buffer units of first area are all denoted as more new state When, memorizer control circuit unit 404 (or memory management circuitry 502) will be temporarily stored in first area Logical address-physical address mapping table in all buffer units restores to duplicative non-volatile memories In device module.However, memorizer control circuit unit 404 (or memory management circuitry 502) also can be Other times point starts copy-back operation, and in foregoing teachings for example, will not be repeated here.
If logical address-the physical address map in all buffer units that will be temporarily stored in first area Between table restores to reproducible nonvolatile memorizer module mid-term, receive write-in from host computer system 11 and refer to Order, will in addition perform the flow of Figure 11 B.
Figure 11 B are refer to, in step S1113, memorizer control circuit unit 404 (or memory Management circuit 502) receive instruction from host computer system and write data into belonging to a logical address-physically The write instruction of one logical address of location mapping table.
In step S1115, memorizer control circuit unit 404 (or memory management circuitry 502) will Update area is changed to second area.
In step S1117, memorizer control circuit unit 404 (or memory management circuitry 502) is sentenced Break this logical address belonging to logical address-physical address mapping table whether be temporarily stored in first area or In second area.
In step S1119, if logical address-physical address mapping table belonging to this logical address by It is temporarily stored in the buffer unit of first area (below referring also to be the first buffer unit), memory control Circuit unit 404 (or memory management circuitry 502) is write data into duplicative non-volatile memories Device module, and the logical address in the first buffer unit in first area-physical address mapping table is replicated In buffer unit (below referring also to be the second buffer unit) in second area.
In step S1121, memorizer control circuit unit 404 (or memory management circuitry 502) is more Logical address-physical address mapping table in new temporary the second buffer unit in the second area, and by the Two buffer units are denoted as more new state.
In step S1123, if logical address-physical address mapping table belonging to this logical address by It is temporarily stored in the buffer unit of second area (below referring also to be the 3rd buffer unit), memory control Circuit unit 404 (or memory management circuitry 502) is write data into duplicative non-volatile memories Device module, updates the logical address-physical address map in temporary the 3rd buffer unit in the second area Table, and the 3rd buffer unit is denoted as more new state.
In step S1125, if the logical address-physical address mapping table belonging to this logical address is not yet It is temporarily stored in first area or second area, memorizer control circuit unit 404 (or memory management electricity Road 502) logical address-thing belonging to this logical address is loaded into from reproducible nonvolatile memorizer module Reason address mapping table is simultaneously temporarily stored in the buffer unit (below referring also to be the 4th buffer unit) of second area In.
In step S1127, memorizer control circuit unit 404 (or memory management circuitry 502) will Data are write to reproducible nonvolatile memorizer module, update temporary the 4th delaying in the second area Logical address-physical address mapping table in memory cell, and the 4th buffer unit is denoted as having updated shape State.
In step S1129, if all buffer units of second area are all denoted as more new state When, memorizer control circuit unit 404 (or memory management circuitry 502) will be temporarily stored in second area Logical address-physical address mapping table in all buffer units restores to duplicative non-volatile memories In device module.However, memorizer control circuit unit 404 (or memory management circuitry 502) also can be Other times point starts copy-back operation, and in foregoing teachings for example, will not be repeated here.
In sum, buffer storage supervisory method provided by the present invention, memorizer control circuit unit It is that the specific region with continuous buffer unit is marked off in buffer storage with memory storage apparatus, And update area is set as specific region, the logical address that will be updated-physical address mapping table is concentrated It is temporarily stored in update area.Consequently, it is possible to work as the updated logical address-thing in buffer storage When reason address mapping table restores to reproducible nonvolatile memorizer module, just can be programmed according to physics single The size of unit, directly writes to thing the updated logical address-physical address mapping table in update area Reason programming unit, and need not in addition perform the operation for replicating and collecting.And set by by this specific region Be particular size, can be when copy-back operation be carried out, it is to avoid because the data volume that need to be processed is excessive and caused by system The problem of overload, and then the effectively processing speed of lifting copy-back operation.Additionally, being updated by changing The mode in region so that returned by the updated logical address-physical address mapping table in buffer storage It is sustainable to receive write instruction from host computer system during depositing to reproducible nonvolatile memorizer module Data, and perform write operation, it is to avoid cause the situation that write-in fails because the stand-by period is long, carry The stability of the system of liter.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than right Its limitation；Although being described in detail to the present invention with reference to foregoing embodiments, this area it is common Technical staff should be understood：It can still modify to the technical scheme described in foregoing embodiments, Or equivalent is carried out to which part or all technical characteristic；And these modifications or replacement, and The scope of the essence disengaging various embodiments of the present invention technical scheme of appropriate technical solution is not made.

Claims (18)

1. a kind of buffer storage supervisory method, for a buffer storage of memory storage apparatus, its It is characterised by, the memory storage apparatus have reproducible nonvolatile memorizer module, described slow Rushing storage management method includes：
Mark off first area and second area in said buffer memory, wherein the first area with The second area respectively has a continuous multiple buffer units, and the first area and described the At least a portion buffer unit in those buffer units in two regions has kept in multiple logical address-things Reason address mapping table；
Those buffer units to the first area perform copy-back operation to will be stored in the first area Those logical address-physical address mapping tables restore to the reproducible nonvolatile memorizer module In；
The first write instruction is received from host computer system, wherein first write instruction is indicated the first data Write to the first logical address, and the first logical address-physical address belonging to first logical address Mapping table has been temporarily stored in the first buffer unit among the buffer unit of the first area；
First data are write to the reproducible nonvolatile memorizer module, and by described first First logical address-physical address mapping table in region copies to the caching in the second area In the second buffer unit among unit；And
Renewal is temporarily stored in first logical address in second buffer unit in the second area - physical address mapping table.
2. buffer storage supervisory method according to claim 1, it is characterised in that update temporary First logical address-the physical address in second buffer unit in the second area reflects The step of firing table, also include：
Second buffer unit is denoted as more new state, and the second area is set as to update Region, wherein the update area is configured to temporarily store multiple logical address-physical address mapping tables being updated.
3. buffer storage supervisory method according to claim 2, it is characterised in that also include：
When all buffer units of the second area are all for the more new state, by secondth area Those logical address-physical address mapping tables in all buffer units in domain restore to the duplicative In non-volatile memory module.
4. buffer storage supervisory method according to claim 2, it is characterised in that also include：
The order of the buffer unit in the second area, chooses first in the second area Buffer unit sets the first index sensing second buffer unit as second buffer unit； And
Described in first logical address-physical address mapping table is copied into the second area After second buffer unit, setting first index is pointed among the buffer unit of the second area Another buffer unit, wherein described another buffer unit be second buffer unit it is latter not It is the buffer unit of the more new state.
5. buffer storage supervisory method according to claim 2, it is characterised in that also include：
The second write instruction is received from the host computer system, wherein second write instruction is indicated second Data are write to the second logical address, and the second logical address-physics belonging to second logical address Address mapping table has been temporarily stored in the 3rd buffer unit among the buffer unit of the second area；With And
Second data to the reproducible nonvolatile memorizer module are write, and renewal is temporarily stored in Second logical address-the physical address map in the 3rd buffer unit in the second area Table.
6. buffer storage supervisory method according to claim 2, it is characterised in that also include：
The 3rd write instruction is received from the host computer system, wherein the 3rd write instruction is indicated the 3rd Data are write to the 3rd logical address, and the three logical addresses-physics belonging to the 3rd logical address Address mapping table is not yet loaded into the mapping table area；
The 3rd logical address-physically is loaded into from the reproducible nonvolatile memorizer module Location mapping table, and the three logical addresses-physical address mapping table is temporarily stored in the second area In the 4th buffer unit among buffer unit；And
The 3rd data to the reproducible nonvolatile memorizer module are write, and renewal is temporarily stored in Three logical addresses-the physical address map in the 4th buffer unit in the second area Table.
7. a kind of memorizer control circuit unit, for controlling reproducible nonvolatile memorizer module, Characterized in that, the memorizer control circuit unit includes：
HPI, is electrically connected to host computer system；
Memory interface, is electrically connected to the reproducible nonvolatile memorizer module；
Buffer storage, is electrically connected to the HPI and the memory interface；And
Memory management circuitry, is electrically connected to the HPI, the memory interface slow with described Memory is rushed, and to mark off first area and second area in said buffer memory, wherein The first area and the second area respectively have a continuous multiple buffer units, and described the At least a portion buffer unit in those buffer units in one region and the second area has been kept in many Individual logical address-physical address mapping table,
Wherein, the memory management circuitry is also used to perform those buffer units of the first area Copy-back operation is restored to will be stored in those logical address-physical address mapping tables of the first area In the reproducible nonvolatile memorizer module,
Wherein, the memory management circuitry is also used to receive the first write instruction from the host computer system, First write instruction indicates to write first data into the first logical address, and first logic The first logical address-physical address mapping table belonging to address has been temporarily stored in the caching of the first area In the first buffer unit among unit,
Wherein, the memory management circuitry is also used to write first data non-to the duplicative Volatile, and by the first logical address-physical address map in the first area Table is copied in the second buffer unit among the buffer unit in the second area,
Wherein, the memory management circuitry is also used to update described be temporarily stored in the second area First logical address-physical address mapping table in two buffer units.
8. memorizer control circuit unit according to claim 7, it is characterised in that the storage Device management circuit is also used to for second buffer unit to be denoted as more new state, and by secondth area Domain is set as update area, wherein the update area is configured to temporarily store multiple logical address-physics being updated Address mapping table.
9. memorizer control circuit unit according to claim 8, it is characterised in that the storage Device management circuit is also used to when all buffer units of the second area are all for the more new state, Those logical address-physical address mapping tables in all buffer units of the second area are restored to In the reproducible nonvolatile memorizer module.
10. memorizer control circuit unit according to claim 8, it is characterised in that described to deposit Reservoir management circuit chooses described second also to the order of the buffer unit in the second area First buffer unit in region is used as second buffer unit, and it is described to set the sensing of the first index Second buffer unit,
Wherein, copied to by the first logical address-physical address mapping table in the first area After in second buffer unit in the second area, the memory management circuitry is also used to set Fixed first index points to another buffer unit among the buffer unit of the second area, wherein It is not the slow of the more new state that described another buffer unit is latter of second buffer unit Memory cell.
11. memorizer control circuit units according to claim 8, it is characterised in that described to deposit Reservoir management circuit is also used to receive the second write instruction, second write instruction from the host computer system Instruction writes to the second logical address the second data, and second patrolling belonging to second logical address What volume address-physical address mapping table had been temporarily stored among the buffer unit of the second area the 3rd delays In memory cell,
Wherein, the memory management circuitry is also used to write second data non-to the duplicative Volatile, and renewal be temporarily stored in the 3rd buffer unit in the second area Second logical address-physical address mapping table.
12. memorizer control circuit units according to claim 8, it is characterised in that described to deposit Reservoir management circuit is also used to receive the 3rd write instruction, the 3rd write instruction from the host computer system Instruction writes to the 3rd logical address the 3rd data, and the 3rd patrolling belonging to the 3rd logical address Collect address-physical address mapping table and be not yet loaded into the mapping table area,
Wherein, the memory management circuitry is also used to from the reproducible nonvolatile memorizer module It is middle to be loaded into the three logical addresses-physical address mapping table, and the three logical addresses-physical address Mapping table is temporarily stored in the 4th buffer unit among the buffer unit of the second area,
Wherein, the memory management circuitry is also used to write the 3rd data non-to the duplicative Volatile, and renewal be temporarily stored in the 4th buffer unit in the second area Three logical addresses-the physical address mapping table.
A kind of 13. memory storage apparatus, it is characterised in that including：
Connecting interface unit, is electrically connected to host computer system；
Reproducible nonvolatile memorizer module；And
Memorizer control circuit unit, is electrically connected to the connecting interface unit non-with the duplicative Volatile, and including buffer storage, and to draw in said buffer memory First area and second area are separated, wherein the first area respectively has with the second area connecting In those buffer units in continuous multiple buffer units, and the first area and the second area At least a portion buffer unit kept in multiple logical address-physical address mapping tables,
Wherein, the memorizer control circuit unit is also used to those buffer units to the first area Perform copy-back operation and returned with will be stored in those logical address-physical address mapping tables of the first area Deposit into the reproducible nonvolatile memorizer module,
Wherein, the memorizer control circuit unit is also used to receive first and write from the host computer system refer to Order, first write instruction indicates to write first data into the first logical address, and described first The first logical address-physical address mapping table belonging to logical address has been temporarily stored in the first area In the first buffer unit among buffer unit,
Wherein, the memorizer control circuit unit is also used to write first data and is made carbon copies to described Formula non-volatile memory module, and by the first logical address-physical address in the first area Mapping table is copied in the second buffer unit among the buffer unit in the second area,
Wherein, the memorizer control circuit unit is also used to update the institute being temporarily stored in the second area State the first logical address-physical address mapping table in the second buffer unit.
14. memory storage apparatus according to claim 13, it is characterised in that memory is controlled Circuit unit is also used to for second buffer unit to be denoted as more new state, and by the second area It is set as update area, wherein the update area is configured to temporarily store multiple logical addresses-physically being updated Location mapping table.
15. memory storage apparatus according to claim 14, it is characterised in that the memory It is all the more new state that control circuit unit is also used in all buffer units of the second area When, those logical addresses in all buffer units of the second area-physical address mapping table is restored Into the reproducible nonvolatile memorizer module.
16. memory storage apparatus according to claim 14, it is characterised in that the memory Control circuit unit chooses described second also to the order of the buffer unit in the second area First buffer unit in region is used as second buffer unit, and it is described to set the sensing of the first index Second buffer unit,
Wherein, copied to by the first logical address-physical address mapping table in the first area After in second buffer unit in the second area, the memorizer control circuit unit is also used With another buffer unit among the buffer unit for setting the first index sensing second area, It is not the more new state that wherein described another buffer unit is latter of second buffer unit Buffer unit.
17. memory storage apparatus according to claim 14, it is characterised in that the memory Control circuit unit is also used to receive the second write instruction, second write instruction from the host computer system Instruction writes to the second logical address the second data, and second patrolling belonging to second logical address What volume address-physical address mapping table had been temporarily stored among the buffer unit of the second area the 3rd delays In memory cell,
Wherein, the memorizer control circuit unit is also used to write second data and is made carbon copies to described Formula non-volatile memory module, and update the 3rd buffer unit being temporarily stored in the second area In second logical address-physical address mapping table.
18. memory storage apparatus according to claim 14, it is characterised in that the memory Control circuit unit is also used to receive the 3rd write instruction, the 3rd write instruction from the host computer system Instruction writes to the 3rd logical address the 3rd data, and the 3rd patrolling belonging to the 3rd logical address Collect address-physical address mapping table and be not yet loaded into the mapping table area,
Wherein, the memorizer control circuit unit is also used to from the type nonvolatile Three logical addresses-the physical address mapping table, and the three logical addresses-physics are loaded into module Address mapping table is temporarily stored in the 4th buffer unit among the buffer unit of the second area,
Wherein, the memorizer control circuit unit is also used to write the 3rd data and is made carbon copies to described Formula non-volatile memory module, and update the 4th buffer unit being temporarily stored in the second area In the three logical addresses-physical address mapping table.
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