CN106776376B - Buffer storage supervisory method, memorizer control circuit unit and storage device - Google Patents

Buffer storage supervisory method, memorizer control circuit unit and storage device Download PDF

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Publication number
CN106776376B
CN106776376B CN201510820913.2A CN201510820913A CN106776376B CN 106776376 B CN106776376 B CN 106776376B CN 201510820913 A CN201510820913 A CN 201510820913A CN 106776376 B CN106776376 B CN 106776376B
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area
cache unit
mapping table
logical address
unit
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CN106776376A (en
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陈国荣
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space

Abstract

The present invention provides a kind of buffer storage supervisory method, memorizer control circuit unit and storage device.The method includes: to mark off first area and second area in buffer storage to keep in multiple logical address-physical address mapping tables, and execute copy-back operation to first area.The method also includes: to receive a write instruction, and wherein logical address-physical address mapping table belonging to the logical address of this write instruction instruction has been temporarily stored in first area.The method further include: this logical address-physical address mapping table is copied into second area, and updates this logical address-physical address mapping table in second area.The present invention can promote operational paradigm and system stability when logical address-physical address mapping table is restored to reproducible nonvolatile memorizer module from buffer storage.

Description

Buffer storage supervisory method, memorizer control circuit unit and storage device
Technical field
The invention relates to a kind of buffer storage supervisory methods, and in particular to a kind of buffer storage supervisory Method, memorizer control circuit unit and storage device.
Background technique
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, so that consumer is to storage The demand of media also rapidly increases.Since reproducible nonvolatile memorizer module (for example, flash memory) has data It is non-volatile, power saving, small in size, and without characteristics such as mechanical structures, so being very suitable to be built into above-mentioned illustrated various In portable multimedia device.
In general, use reproducible nonvolatile memorizer module as storage media memory storage apparatus In, buffer storage can be generally also configured, procedure code, data is configured to temporarily store or is executing background for memory storage apparatus (background) staging area of work hours evidence.For example, the controller of memory storage apparatus can be by logical address-physics Address mapping table is loaded into buffer storage and accesses data with benefit.And when receiving write instruction and execute write operation, it deposits The controller of reservoir storage device will be updated the logical address-physical address mapping table being temporarily stored in buffer storage.And work as When having kept in the logical address-physical address mapping table being largely updated in buffer storage, memory storage apparatus Controller can that physical address mapping table restores to duplicative be non-volatile by the logical address-being updated in buffer storage In memory module.Since the logical address-physical address mapping table being updated is possible to not be to be temporarily stored in buffer storage In in continuous cache unit, and reproducible nonvolatile memorizer module is with physical programming unit for minimum write-in list Position, therefore, it is necessary to which the logical address-physical address mapping table being updated first is copied to the working area in buffer storage Domain is equivalent to the size of a physical programming unit and can just restore to reproducible nonvolatile memorizer module to be concentrated into. However, a large amount of duplication operation will lead to, system load is overweight, and restoring overlong time declines overall performance.
In addition, being stored back by the logical address-physical address mapping table being updated in buffer storage to can make carbon copies During formula non-volatile memory module, if receiving write instruction again and the above-mentioned logic being just stored back need to be updated again Address-physical address mapping table, at this time the controller of memory storage apparatus can first suspend receive this write instruction data and The execution of write operation.Thus, it may occur however that cause the case where failure is written because the waiting time is too long.Therefore, how It is promoted when logical address-physical address mapping table is restored to reproducible nonvolatile memorizer module from buffer storage Operational paradigm and system stability, thus field technical staff subject under discussion of concern.
Summary of the invention
The present invention provides a kind of buffer storage supervisory method, memorizer control circuit unit and storage device, can mention Rise fortune when logical address-physical address mapping table is restored to reproducible nonvolatile memorizer module from buffer storage Make efficiency and system stability.
One example of the present invention embodiment proposes a kind of buffer storage supervisory method, for the slow of memory storage apparatus Rush memory.This memory storage apparatus has reproducible nonvolatile memorizer module.This buffer storage supervisory method It is included in buffer storage and marks off first area and second area, wherein first area and second area respectively has company Continuous multiple cache units, and first area and at least part cache unit in the cache unit in second area are temporary Deposit multiple logical address-physical address mapping tables.This buffer storage supervisory method also includes the cache unit to first area Copy-back operation is executed so that physical address mapping table restores to duplicative is non-volatile by the logical address-for being stored in first area In memory module.This buffer storage supervisory method further includes the first write instruction being received from host system, and first is written Instruction instruction writes first data into the first logical address, and the first logical address-physics belonging to the first logical address Address mapping table has been temporarily stored in the first cache unit among the cache unit of first area.This buffer storage supervisory side Method further includes the first data of write-in to reproducible nonvolatile memorizer module, and logically by first in first area Location-physical address mapping table copies in the second cache unit among the cache unit in second area.This buffer storage Management method further includes the first logical address-physical address map updated in temporary the second cache unit in the second area Table.
In one example of the present invention embodiment, in temporary the second cache unit in the second area of above-mentioned update the The step of one logical address-physical address mapping table further includes that the second cache unit is denoted as to more new state, and by second Region is set as update area, and update area is to be configured to temporarily store multiple logical address-physical address mapping tables being updated.
In one example of the present invention embodiment, above-mentioned buffer storage supervisory method further includes the institute in second area When having cache unit all and be more new state, by logical address-physical address map in all cache units of second area Table restores in reproducible nonvolatile memorizer module.
In one example of the present invention embodiment, above-mentioned buffer storage supervisory method further includes according in second area Cache unit sequence, choose first cache unit in second area as the second cache unit, and set first and refer to Mark is directed toward the second cache unit.Furthermore in second copied to the first logical address-physical address mapping table in second area After cache unit, the first index of setting is directed toward another cache unit among the cache unit of second area, and wherein this is another One cache unit is that the latter of the second cache unit is not the cache unit of more new state.
In one example of the present invention embodiment, above-mentioned buffer storage supervisory method further includes receiving from host system Second write instruction, and the second data are written to the second logical address, and the second logical address the instruction of the second write instruction It is single that affiliated the second logical address-physical address mapping table has been temporarily stored in the caching of the third among the cache unit of second area In member.Furthermore the second data are written to reproducible nonvolatile memorizer module, and update temporary the in the second area The second logical address-physical address mapping table in three cache units.
In one example of the present invention embodiment, above-mentioned buffer storage supervisory method further includes receiving from host system Third write instruction, third data are written to third logical address for wherein third write instruction instruction, and third is logically The logical address of third belonging to location-physical address mapping table is not yet loaded into mapping table area.Furthermore it is non-volatile from duplicative Third logical address-physical address mapping table, and third logical address-physical address mapping table quilt are loaded into memory module It is temporarily stored in the 4th cache unit among the cache unit of second area.In addition, write-in third data are non-easily to duplicative The property lost memory module, and update third logical address-physical address in temporary the 4th cache unit in the second area Mapping table.
One example of the present invention embodiment proposes a kind of memorizer control circuit unit, non-volatile for controlling duplicative Property memory module.Memorizer control circuit unit includes host interface, memory interface, buffer storage and memory management Circuit.Host interface is electrically connected to host system, and memory interface is electrically connected to type nonvolatile mould Block, buffer storage are electrically connected to host interface and memory interface, memory management circuitry be electrically connected to host interface, Memory interface and buffer storage.Memory management circuitry can mark off first area and the secondth area in buffer storage Domain, wherein first area and second area respectively have continuous multiple cache units, and first area and second area In cache unit at least part cache unit kept in multiple logical address-physical address mapping tables.Furthermore it stores Device management circuit can execute copy-back operation to the cache unit of first area will be stored in logical address-physics of first area Address mapping table restores in reproducible nonvolatile memorizer module.Also, memory management circuitry is more from host system The first write instruction is received, the instruction of this first write instruction writes first data into the first logical address, and the first logic First logical address-physical address mapping table belonging to address has been temporarily stored among the cache unit of first area first slow In memory cell.Also, the first data are more written to reproducible nonvolatile memorizer module in memory management circuitry, and by The first logical address-physical address mapping table in one region copies to the second caching among the cache unit in second area In unit.In addition, memory management circuitry updates the first logical address-in temporary the second cache unit in the second area Physical address mapping table.
In one example of the present invention embodiment, the second cache unit is also denoted as by above-mentioned memory management circuitry More new state, and second area is set as update area, and update area is configured to temporarily store multiple logical addresses-being updated Physical address mapping table.
In one example of the present invention embodiment, above-mentioned memory management circuitry is also in all caching lists of second area Member all for more new state when, logical address-physical address mapping table in all cache units of second area is restored to In reproducible nonvolatile memorizer module.
In one example of the present invention embodiment, above-mentioned memory management circuitry is also according to the caching list in second area The sequence of member chooses first cache unit in second area as the second cache unit, and sets the first index and be directed toward the Two cache units.Furthermore it is copied in second area by the first logical address-physical address mapping table in first area After in second cache unit, above-mentioned memory management circuitry more set the first index be directed toward second area cache unit it In another cache unit, and it is not the slow of more new state that this another cache unit, which is the latter of the second cache unit, Memory cell.
In one example of the present invention embodiment, above-mentioned memory management circuitry also receives the second write-in from host system The second data are written to the second logical address for instruction, the instruction of this second write instruction, and the belonging to the second logical address Two logical addresses-physical address mapping table has been temporarily stored in the third cache unit among the cache unit of second area.Again Person, above-mentioned memory management circuitry update also the second data are written to reproducible nonvolatile memorizer module The second logical address-physical address mapping table in temporary third cache unit in the second area.
In one example of the present invention embodiment, above-mentioned memory management circuitry also receives third write-in from host system Third data are written to third logical address for instruction, the instruction of this third write instruction, and the belonging to third logical address Three logical addresses-physical address mapping table is not yet loaded into mapping table area.Furthermore above-mentioned memory management circuitry is more from can answer Write loading third logical address-physical address mapping table in formula non-volatile memory module, and third logical address-physics Address mapping table is temporarily stored in the 4th cache unit among the cache unit of second area.In addition, above-mentioned memory pipe Third data also be writtens to reproducible nonvolatile memorizer module in reason circuit, and update the 4th kept in the second area Third logical address-physical address mapping table in cache unit.
One example of the present invention embodiment proposes a kind of memory storage apparatus comprising connecting interface unit can be made carbon copies Formula non-volatile memory module and above-mentioned memorizer control circuit unit.Connecting interface unit is electrically connected to host system System, memorizer control circuit unit are electrically connected to connecting interface unit and reproducible nonvolatile memorizer module, and Including buffer storage.
Based on above-mentioned, memorizer control circuit unit that exemplary embodiment of the present invention is proposed, memory storage apparatus and Its buffer storage supervisory method used can be saved effectively logical address-physical address mapping table restoring to duplicative The time of non-volatile memory module, and the write-in data from host system are persistently received during restoring, it can be promoted whole The operational paradigm and stability of system system.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is the schematic diagram of the host system according to shown by an exemplary embodiment and memory storage apparatus；
Fig. 2 is the signal of the computer according to shown by an exemplary embodiment, input/output device and memory storage apparatus Figure；
Fig. 3 is the schematic diagram of host system and memory storage apparatus shown by exemplary embodiment according to the present invention；
Fig. 4 is the schematic block diagram of the memory storage apparatus according to shown by an exemplary embodiment；
Fig. 5 is the schematic block diagram of the memorizer control circuit unit according to shown by an exemplary embodiment；
Fig. 6 and Fig. 7 is the example schematic of the management physics erasing unit according to shown by an exemplary embodiment；
Fig. 8 is the schematic diagram of the buffer storage according to shown by an exemplary embodiment；
Fig. 9 A~9F is the schematic diagram of the buffer storage supervisory method according to shown by an exemplary embodiment；
Figure 10 A~10D is the schematic diagram of the buffer storage supervisory method according to shown by another exemplary embodiment；
Figure 11 A and 11B are the flow charts of the buffer storage supervisory method according to shown by an exemplary embodiment.
Description of symbols:
10: memory storage apparatus；
11: host system；
12: computer；
13: input/output device；
122: microprocessor；
124: random access memory (RAM)；
126: system bus；
128: data transmission interface；
21: mouse；
22: keyboard；
23: display；
24: printer；
25: Portable disk；
26: memory card；
27: solid state hard disk；
31: digital camera；
32:SD card；
33:MMC card；
34: memory stick；
35:CF card；
36: embedded storage device；
402: connecting interface unit；
404: memorizer control circuit unit；
406: reproducible nonvolatile memorizer module；
410 (0)~410 (N): physics wipes unit；
502: memory management circuitry；
504: host interface；
506: memory interface；
508: buffer storage；
510: electric power management circuit；
512: error checking and correcting circuit；
602: data field；
604: idle area；
606: system area；
608: replacing area；
LBA (0)~LBA (H): logic unit；
LZ (0)~LZ (M): logic region；
810 (1-0)~810 (1-n), 810 (2-0)~810 (2-n): cache unit；
MTZ: mapping table area；
Z1: first area；
Z2: second area；
P1: the first index；
P2: the second index；
MT (0)~MT (2n), MT (k), MT (k) ', MT (s), MT (x): logical address-physical address mapping table；
S1101、S1103、S1105、S1107、S1109、S1111、S1113、S1115、S1117、S1119、S1121、 S1123, S1125, S1127, S1129: the step of buffer storage supervisory method.
Specific embodiment
In general, memory storage apparatus (also referred to as, storage system) includes duplicative non-volatile memories Device module and controller (also referred to as, control circuit unit).Be commonly stored device storage device be used together with host system so that Host system can write data into memory storage apparatus or read from memory storage apparatus data.
Fig. 1 is the schematic diagram of the host system according to shown by an exemplary embodiment and memory storage apparatus, and Fig. 2 is According to the schematic diagram of computer shown by an exemplary embodiment, input/output device and memory storage apparatus.
Fig. 1 is please referred to, host system 11 generally comprises computer 12 and input/output (input/output, referred to as: I/O) Device 13.Computer 12 includes microprocessor 122, random access memory (random access memory, referred to as: RAM) 124, system bus 126 and data transmission interface 128.Input/output device 13 includes the mouse 21 such as Fig. 2, keyboard 22, display Device 23 and printer 24.It will be appreciated that the unrestricted input/output device 13 of device shown in Fig. 2, input/output device 13 can further include other devices.
In this exemplary embodiment, memory storage apparatus 10 is by data transmission interface 128 and host system 11 Other elements are electrically connected.It can be incited somebody to action by the running of microprocessor 122, random access memory 124 and input/output device 13 Data are written to memory storage apparatus 10 or read data from memory storage apparatus 10.For example, memory storage apparatus 10 can be Portable disk 25 as shown in Figure 2, memory card 26 or solid state hard disk (Solid State Drive, referred to as: SSD) 27 Deng type nonvolatile storage device.
Fig. 3 is the schematic diagram of host system and memory storage apparatus shown by exemplary embodiment according to the present invention.
In general, host system 11 is substantially to cooperate with memory storage apparatus 10 with any system of storing data System.Although host system 11 is explained with computer system, however, in another exemplary embodiment in this exemplary embodiment Middle host system 11 can be the systems such as digital camera, video camera, communication device, audio player or video player.For example, When host system is the digital camera (video camera) 31 in Fig. 3, type nonvolatile storage device is then it Used SD card 32, mmc card 33, memory stick (memory stick) 34,36 (such as Fig. 3 of CF card 35 or embedded storage device It is shown).Embedded storage device 36 includes embedded multi-media card (Embedded MMC, referred to as: eMMC), general flash Device (Universal Flash Storage, referred to as: UFS).It is noted that embedded multi-media card or general flash memory Reservoir is directly electrically connected on the substrate of host system.
Fig. 4 is the schematic block diagram of the memory storage apparatus according to shown by an exemplary embodiment.
Referring to figure 4., memory storage apparatus 10 include connecting interface unit 402, memorizer control circuit unit 404 with Reproducible nonvolatile memorizer module 406.
In this exemplary embodiment, connecting interface unit 402 is compatible with Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, referred to as: SATA) standard.However, it is necessary to be appreciated that, the present invention is not limited to This, connecting interface unit 402 is also possible to meet parallel advanced technology annex (Parallel Advanced Technology Attachment, referred to as: PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, referred to as: IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, referred to as: PCI Express) standard, universal serial bus (Universal Serial Bus, referred to as: a USB) standard, ultrahigh speed generation (Ultra High Speed-I, referred to as: UHS-I) interface standard, super Two generations (Ultra High Speed-II, referred to as: UHS-II) interface standard, secure digital (Secure Digital, letter at a high speed Claim: SD) interface standard, memory stick (Memory Stick, referred to as: MS) interface standard, multimedia storage card (Multi Media Card, referred to as: MMC) interface standard, compact flash (Compact Flash, referred to as: CF) interface standard, integrated form driving electronics Interface (Integrated Device Electronics, referred to as: IDE) standard or other suitable standards.Implement in this example In example, connecting interface unit can be encapsulated in a chip with memorizer control circuit unit, or is laid in one and is included memory Outside the chip of control circuit unit.
Memorizer control circuit unit 404 is to execute multiple logic gates or control with hardware pattern or software pattern implementation System instruction, and writing for data is carried out in reproducible nonvolatile memorizer module 406 according to the instruction of host system 11 The running such as enter, read and erase.
Reproducible nonvolatile memorizer module 406 is electrically connected to memorizer control circuit unit 404, and uses The data being written with host system 11.There is reproducible nonvolatile memorizer module 406 physics to wipe unit 410 (0)~410 (N).For example, physics erasing unit 410 (0)~410 (N) can belong to the same memory crystal grain (die) or belong to In different memory crystal grains.Each physics erasing unit is respectively provided with multiple physical programming units, wherein belonging to the same object The physical programming unit of reason erasing unit can be written independently and simultaneously be erased.However, it is necessary to be appreciated that, the present invention Without being limited thereto, each physics erasing unit is can be by 64 physical programming units, 256 physical programming units or any other Physical programming unit is formed.
In more detail, physics erasing unit is the minimum unit erased.That is, each physics erasing unit contains minimum The storage unit of number being erased together.Physical programming unit is the minimum unit of programming.That is, physical programming unit is write-in The minimum unit of data.Each physical programming unit generally includes data bit area and redundancy ratio special zone.Data bit area includes Data of multiple physics access addresses to store user, and redundancy ratio special zone to storage system data (for example, control Information and error correcting code).It can include 8 in the data bit area of each physical programming unit in this exemplary embodiment Physics access address, and the size of a physics access address is 512 bytes (byte).However, in other exemplary embodiments, It also may include the more or fewer physics access addresses of number in data bit area, the present invention is not intended to limit physics access address Size and number.For example, it is physical blocks that physics, which wipes unit, and physical programming unit is in an exemplary embodiment Physical page or physical sector, but invention is not limited thereto.
In this exemplary embodiment, reproducible nonvolatile memorizer module 406 is multi-level cell memory (Multi Level Cell, referred to as: MLC) NAND type flash memory module be (that is, can store 2 data bits in a storage unit Flash memory module).However, the invention is not limited thereto, reproducible nonvolatile memorizer module 406 can also be single-order and deposit Storage unit (Single Level Cell, referred to as: SLC) NAND type flash memory module in a storage unit (that is, can deposit Store up the flash memory module of 1 data bit), multi-level cell memory (Trinary Level Cell, referred to as: TLC) NAND Type flash memory module (that is, flash memory module that 3 data bits can be stored in a storage unit), other quick flashings Memory module or other memory modules with the same characteristics.
Fig. 5 is the schematic block diagram of the memorizer control circuit unit according to shown by an exemplary embodiment.
Referring to figure 5., memorizer control circuit unit 404 includes memory management circuitry 502, host interface 504 and deposits Memory interface 506, buffer storage 508, electric power management circuit 510 and error checking and correcting circuit 512.
Overall operation of the memory management circuitry 502 to control memorizer control circuit unit 404.Specifically, it deposits Reservoir, which manages circuit 502, has multiple control instructions, and when memory storage apparatus 10 operates, these control instructions can quilt It executes the running such as to carry out the write-in of data, read and erase.
In this exemplary embodiment, the control instruction of memory management circuitry 502 is to carry out implementation with software pattern.For example, Memory management circuitry 502 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to Order is programmed in so far read-only memory.When memory storage apparatus 10 operates, these control instructions can be by microprocessor Unit is executed the running such as to carry out the write-in of data, read and erase.
Fig. 6 and Fig. 7 is the example schematic of the management physics erasing unit according to shown by an exemplary embodiment.
It will be appreciated that being described herein the fortune of the physics erasing unit of reproducible nonvolatile memorizer module 406 When making, carrying out operating physical erasing unit with the words such as " extraction ", " grouping ", " division ", " association " is concept in logic.Namely It says, the physical location of the physics of reproducible nonvolatile memorizer module erasing unit is not changed, but in logic to can The physics erasing unit of manifolding formula non-volatile memory module is operated.
Fig. 6 is please referred to, physics can be wiped unit by memorizer control circuit unit 404 (or memory management circuitry 502) 410 (0)~410 (N) are logically grouped into data field 602, idle area 604, system area 606 and replace area 608.
The physics erasing unit for logically belonging to data field 602 and idle area 604 is to store from host system 11 data.Specifically, the physics erasing unit of data field 602 is regarded as the physics erasing unit of storing data, and The physics erasing unit in idle area 604 is the physics erasing unit to replacement data area 602.That is, working as from host system When system 11 receives write instruction and the data to be written, memory management circuitry 502 extracts physical can be wiped from idle area 604 It except unit, and writes data into extracted physics erasing unit, unit is wiped with the physics in replacement data area 602.
The physics erasing unit for logically belonging to system area 606 is to record system data.For example, system data includes Physics about the manufacturer of reproducible nonvolatile memorizer module and model, reproducible nonvolatile memorizer module Wipe unit number, physical programming unit number of each physics erasing unit etc..
Logically belonging to replace the physics erasing unit in area 608 is to replace program for bad physics erasing unit, to take The physics of generation damage wipes unit.Specifically, still there are normal physics erasing unit and data in area 608 if replacing When the physics erasing unit damage in area 602, memory management circuitry 502 can extract normal physics erasing from replacing in area 608 Unit wipes unit to replace the physics of damage.
In particular, the quantity meeting of data field 602, idle area 604, system area 606 and the physics erasing unit for replacing area 608 It is different according to different memory specifications.Further, it is necessary to be appreciated that, in the running of memory storage apparatus 10, Physics erasing unit is associated with to data field 602, idle area 604, system area 606 and replaces the grouping relationship in area 608 can be dynamically It changes.For example, when the physics erasing unit that the physics erasing unit damage in idle area 604 is substituted area 608 replaces, then Originally idle area 604 can be associated to by replacing the physics erasing unit in area 608.
Fig. 7 is please referred to, memorizer control circuit unit 404 (or memory management circuitry 502) can configuration logic unit LBA (0)~LBA (H) with map data field 602 physics wipe unit, wherein each logic unit have multiple logical subunits with Map the physical programming unit of corresponding physics erasing unit.Also, when the logic unit to be write data to of host system 11 or When updating storage the data in logic unit, memorizer control circuit unit 404 (or memory management circuitry 502) can be from the spare time It sets and extracts a physics erasing unit in area 604 data are written, unit is wiped with the physics of alternation data field 602.In this model In example embodiment, logical subunit can be logical page (LPAGE) or logic sector.
In order to identify which physics erasing unit is the data of each logic unit be stored in, in this exemplary embodiment, Memorizer control circuit unit 404 (or memory management circuitry 502) will record between logic unit and physics erasing unit Mapping.Also, when host system 11 is intended to access data in logical subunit, memorizer control circuit unit 404 (or storage Device manages circuit 502) it can confirm logic unit belonging to this logical subunit, and wiped in this logic unit mapped physics Except accessing data in unit.For example, in this exemplary embodiment, memorizer control circuit unit 404 (or memory management electricity Road 502) logical address-physical address mapping table can be stored in reproducible nonvolatile memorizer module 406 to record often One logic unit mapped physics wipe unit, and when data to be accessed memorizer control circuit unit 404 (or storage Device manages circuit 502) logical address-physical address mapping table can be loaded into buffer storage 508 to safeguard.
Reflecting for all logic units is recorded it is noted that can not store since the capacity of buffer storage 508 is limited The mapping table of relationship is penetrated, therefore, in this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) logic unit LBA (0)~LBA (H) can be grouped into multiple logic region LZ (0)~LZ (M), and be each logic area One logical address-physical address mapping table of configuration of territory.In particular, when (or the memory management of memorizer control circuit unit 404 Circuit 502) when being intended to update the mapping of some logic unit, logical address-object of logic region belonging to this corresponding logic unit Reason address mapping table can be loaded on buffer storage 508 to be updated.
In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 502 can also be with procedure code pattern The specific region of reproducible nonvolatile memorizer module 406 is stored in (for example, being exclusively used in storage system in memory module The system area of data) in.In addition, memory management circuitry 502 has microprocessor unit (not shown), read-only memory (not Show) and random access memory (not shown).In particular, this read-only memory has driving code, and when memory controls When circuit unit 404 is enabled, microprocessor unit can first carry out this driving code section, and will to be stored in duplicative non-volatile Control instruction in memory module 406 is loaded into the random access memory of memory management circuitry 502.Later, micro- place Reason device unit such as can operate these control instructions to carry out the write-in of data, read and erase at the running.
In addition, the control instruction of memory management circuitry 502 can also be with a hardware in another exemplary embodiment of the present invention Pattern carrys out implementation.For example, memory management circuitry 502 includes microcontroller, Storage Unit Management circuit, memory write-in electricity Road, memory reading circuitry, memory are erased circuit and data processing circuit.Storage Unit Management circuit, memory write-in electricity Circuit is erased on road, memory reading circuitry, memory and data processing circuit is electrically connected to microcontroller.Wherein, it stores Single Component Management circuit wipes unit to manage the physics of reproducible nonvolatile memorizer module 406；Memory write-in electricity Road writes data into non-volatile to duplicative to assign write instruction to reproducible nonvolatile memorizer module 406 In property memory module 406；Memory reading circuitry refers to assign reading to reproducible nonvolatile memorizer module 406 It enables to read data from reproducible nonvolatile memorizer module 406；Memory erases circuit to non-to duplicative Volatile 406 assigns instruction of erasing so that data to be erased from reproducible nonvolatile memorizer module 406； And data processing circuit is intended to be written data to reproducible nonvolatile memorizer module 406 and from can make carbon copies to handle The data read in formula non-volatile memory module 406.
Referring again to Fig. 5, host interface 504 is electrically connected to memory management circuitry 502 and is for electrically connecting to To connecting interface unit 402, to receive and identify instruction and data that host system 11 is transmitted.That is, host system 11 instructions transmitted and data can be sent to memory management circuitry 502 by host interface 504.In this exemplary embodiment In, host interface 504 is compatible with SATA standard.However, it is necessary to it is appreciated that the invention is not limited thereto, host interface 504 PATA standard, 1394 standard of IEEE, PCI Express standard, USB standard, UHS-I interface standard, UHS- can be compatible with II interface standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other suitable data transmission standards.
Memory interface 506 is electrically connected to memory management circuitry 502 and non-volatile to access duplicative Property memory module 406.It can be by depositing to the data of reproducible nonvolatile memorizer module 406 that is, being intended to be written Memory interface 506 is converted to the 406 receptible format of institute of reproducible nonvolatile memorizer module.
Buffer storage 508 is electrically connected to memory management circuitry 502 and is configured to temporarily store from host system 11 data and instruction or the data from reproducible nonvolatile memorizer module 406.
Electric power management circuit 510 is electrically connected to memory management circuitry 502 and to control memory storage dress Set 10 power supply.
Error checking and correcting circuit 512 are electrically connected to memory management circuitry 502 and to execute wrong inspection It looks into and correction program is to ensure the correctness of data.Specifically, when memory management circuitry 502 is received from host system 11 When to write instruction, error checking can be the corresponding error checking of data generation of this corresponding write instruction with correcting circuit 512 With correcting code (Error Checking and Correcting Code, referred to as: ECC Code), and memory management circuitry 502 the data of this corresponding write instruction can be written with corresponding error checking and correcting code to duplicative non-volatile memories In device module 406.Later, when memory management circuitry 502 reads data from reproducible nonvolatile memorizer module 406 When can read the corresponding error checking of this data and correcting code simultaneously, and error checking and correcting circuit 512 can be according to this mistakes Erroneous detection, which is looked into, executes error checking and correction program to read data with correcting code.
Fig. 8 is the schematic diagram of the buffer storage according to shown by an exemplary embodiment.
Fig. 8 is please referred to, in this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) Mapping table area MTZ is marked off in buffer storage 508, is configured to temporarily store from 406 institute of reproducible nonvolatile memorizer module Logical address-physical address mapping table of loading.In particular, memorizer control circuit unit 404 (or memory management circuitry 502) mapping table area MTZ can be more divided into first area Z1 and second area Z2, and first area Z1 and second area Z2 points It Ju You not continuous multiple cache units.Each cache unit is configured to temporarily store a logical address-physical address mapping table, and every One cache unit can be denoted as different conditions, such as updated (dirty) state, do not updated (clean) state, is invalid (invalid) state, storage (saving) state or loading (loading) state etc., to indicate the data in cache unit State.In this exemplary embodiment, logical address-physical address mapping table size is 512B, therefore, each caching The size of unit is 512B.And the size of first area Z1 and second area Z2 can be a particular value, such as 64MB or 128MB. However, it is necessary to which Liao is solved, in other exemplary embodiments, the size of cache unit can be according to actual logical address-physically Depending on the mapping table of location, and the size of first area Z1 and second area Z2 also visually actually uses demand and sets, and the present invention is simultaneously It is without restriction.
As shown in figure 8, first area Z1 has cache unit 810 (1-0)~810 (1-n), second area Z2 has caching Unit 810 (2-0)~810 (2-n).In this exemplary embodiment, memorizer control circuit unit 404 (or memory management electricity Road 502) multiple logical addresses-physical address mapping table can be carried from reproducible nonvolatile memorizer module 406 in advance Enter the mapping table area MTZ into buffer storage 508, and these logical address-physical address mapping tables are distinctly kept in In the cache unit of one region Z1 and second area Z2.
Fig. 9 A~9F is the schematic diagram of the buffer storage supervisory method according to shown by an exemplary embodiment.
Fig. 9 A is please referred to, cache unit 810 (1-0)~810 (1-n) the difference register logic address-in the Z1 of first area Cache unit 810 (2-0)~810 (2-n) in physical address mapping table MT (0)~MT (n), second area Z2 is kept in respectively patrols Collect address-physical address mapping table MT (n+1)~MT (2n).For convenience of description, this exemplary embodiment be with first area Z1 with The cache unit of second area Z2 does not start to illustrate for more new state.When receiving write instruction from host system 11, this Write-in data are written to logical address for write instruction instruction, memorizer control circuit unit 404 (or memory management circuitry 502) logical address-physical address mapping table belonging to this logical address can be kept in the first area Z1 of mapping table area MTZ To be safeguarded.In more detail, memorizer control circuit unit 404 (or memory management circuitry 502) first judgement can be intended to write Whether logical address-physical address mapping table belonging to the logical address entered has been temporarily stored in first area Z1's or second area Z2 In cache unit.
In this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) can set update Region is configured to temporarily store the logical address-physical address mapping table being updated.In this exemplary embodiment, filled when memory stores 10 are set just when powering on, memorizer control circuit unit 404 (or memory management circuitry 502) is that update area is set as first Region Z1.And in another exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) can also be first Update area is set as second area Z2 with beginning.
It writes data into when receiving instruction from host system to belonging to logical address-physical address mapping table MT (n+2) Logical address write instruction when, memorizer control circuit unit 404 (or memory management circuitry 502) judges logically The loaded mapping table area MTZ into buffer storage 508 of location-physical address mapping table MT (n+2), and it is temporarily stored in the secondth area The cache unit 810 (2-1) of domain Z2.Therefore, memorizer control circuit unit 404 (or memory management circuitry 502) can be by number According to write-in to logical address mapped physical programming unit described in reproducible nonvolatile memorizer module 406, and more Newly it is temporarily stored in logical address-physical address mapping table MT (n+2) of cache unit 810 (2-1).Then, memorizer control circuit Unit 404 (or memory management circuitry 502) can be by updated logical address-physical address mapping table MT (n+2) from second The cache unit 810 (2-1) of region Z2 is moved into the first area Z1 for being set to update area at present.
In this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) can also set One index P1 is directed toward one of cache unit in the Z1 of first area, and this cache unit being pointed to is not to have updated shape State.Specifically, memorizer control circuit unit 404 (or memory management circuitry 502) can be according to more in the Z1 of first area The tandem of a cache unit sequentially judges whether not from front to back as more new state.As shown in Figure 9 A, due at this time All cache units in one region Z1 are not more new state.Therefore, (or the memory of memorizer control circuit unit 404 Manage circuit 502) set first cache unit 810 (1-0) that the first index P1 is directed toward in the Z1 of first area.Later, it stores Device control circuit unit 404 (or memory management circuitry 502) can store updated logical address-according to the first index P1 Physical address mapping table.For example, memorizer control circuit unit 404 (or memory management circuitry 502) can be according to the first index P1 moves updated logical address-physical address mapping table MT (n+2) from the cache unit 810 (2-1) of second area Z2 Into the cache unit 810 (1-0) of first area Z1.
Fig. 9 B is please referred to, updated logical address-physical address mapping table MT (n+2) is moved to first area Z1's After in cache unit 810 (1-0), memorizer control circuit unit 404 (or memory management circuitry 502) can be by cache unit 810 (1-0) are denoted as more new state.In addition, memorizer control circuit unit 404 (or memory management circuitry 502) can be set The latter for the cache unit 810 (1-0) that fixed first index P1 is directed toward in the Z1 of first area is not the caching list of more new state Member.In this exemplary embodiment, the latter cache unit 810 (1-1) of cache unit 810 (1-0) is not more new state. Therefore, memorizer control circuit unit 404 (or memory management circuitry 502) can set the first index P1 and be directed toward cache unit 810(1-1).In this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) more can will be former Originally the logical address being temporarily stored in the cache unit 810 (1-0) of first area Z1-physical address mapping table MT (0) is moved to In the cache unit 810 (2-1) of two region Z2.And in another exemplary embodiment, it can not also move and directly override logic Address-physical address mapping table MT (0).
If writing data at this point, receiving instruction from host system to belonging to logical address-physical address mapping table When another write instruction of the logical address of MT (n), memorizer control circuit unit 404 (or memory management circuitry 502) meeting The loaded mapping table area MTZ into buffer storage 508 of decision logic address-physical address mapping table MT (n), and kept in In the cache unit 810 (1-n) of first area Z1.As shown in Figure 9 C, (or the memory pipe of memorizer control circuit unit 404 Reason circuit 502) it can write data into logical address mapped object described in reproducible nonvolatile memorizer module 406 Programming unit is managed, updates the logical address-physical address mapping table MT (n) being temporarily stored in cache unit 810 (1-n), and will delay Memory cell 810 (1-n) is denoted as more new state.
If writing data at this point, receiving instruction from host system to belonging to logical address-physical address mapping table When the another write instruction of the logical address of MT (k), memorizer control circuit unit 404 (or memory management circuitry 502) meeting Decision logic address-physical address mapping table MT (k) is not yet loaded on the mapping table area MTZ in buffer storage 508.Cause This, memorizer control circuit unit 404 (or memory management circuitry 502) can be from reproducible nonvolatile memorizer module Logical address-physical address mapping table MT (k) is loaded into mapping table area MTZ in 406, and with pointed by the first index P1 Cache unit 810 (1-1) in one region Z1 carrys out register logic address-physical address mapping table MT (k).As shown in fig. 9d, it patrols It collects address-physical address mapping table MT (k) to be temporarily stored in the cache unit 810 (1-1) in the Z1 of first area, and memory control Circuit unit 404 (or memory management circuitry 502) processed writes data into reproducible nonvolatile memorizer module 406 In.In addition, memorizer control circuit unit 404 (or memory management circuitry 502) and will be updated logical address-physical address and reflect Firing table MT (k), and cache unit 810 (1-1) is denoted as more new state.Further, memorizer control circuit unit The latter that 404 (or memory management circuitries 502) can choose cache unit 810 (1-1) in the Z1 of first area is not to have updated The cache unit 810 (1-2) of state is configured to temporarily store next updated logical address-physical address mapping table, and sets the One index P1 is directed toward cache unit 810 (1-2).
In this exemplary embodiment, if all cache units 810 (1-0)~810 (1-n) in the Z1 of first area all by It is denoted as more new state, memorizer control circuit unit 404 (or memory management circuitry 502) will start copy-back operation, with Logical address-physical address mapping table in all cache units 810 (1-0)~810 (1-n) of first area Z1 will be temporarily stored in It restores in reproducible nonvolatile memorizer module 406.It is understood, however, that memorizer control circuit unit 404 (or memory management circuitry 502) can also start copy-back operation at other times.For example, data merging or rubbish are being executed Before the background operations such as rubbish collection (Garbage collection) or memory storage apparatus are powered down or through after a period of time It does not receive when the write instruction of host system 11, memorizer control circuit unit 404 (or memory management electricity Road 502) it also will start copy-back operation, by the logical address-of update, that physical address mapping table restores to duplicative is non-volatile Memory module 406.
In this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) can also set Two index P2 are directed toward one of cache unit in second area Z2.Specifically, memorizer control circuit unit 404 (or Memory management circuitry 502) the can be determined back to front according to the tandems of multiple cache units in second area Z2 The two index P2 cache units to be directed toward.It as shown in fig. 9e, can be from the 810 (2- of the last one cache unit in second area Z2 N) start, the second index P2 of setting is directed toward cache unit 810 (2-n).
If being patrolled at this point, receiving instruction reading from host system and belonging to logical address-physical address mapping table MT (s) When collecting the reading instruction of the data of address, memorizer control circuit unit 404 (or memory management circuitry 502) judges logic Address-physical address mapping table MT (s) is not yet loaded on the mapping table area MTZ in buffer storage 508.Therefore, memory Control circuit unit 404 (or memory management circuitry 502) can be from reproducible nonvolatile memorizer module 406 by logic Address-physical address mapping table MT (s) is loaded into mapping table area MTZ, and with cache unit 810 pointed by the second index P2 (2-n) carrys out register logic address-physical address mapping table MT (s).As shown in fig. 9f, in logical address-physical address mapping table After MT (s) is temporarily stored in the cache unit 810 (2-n) in second area Z2, memorizer control circuit unit 404 (or deposit Reservoir manages circuit 502) can be stored in duplicative according to the reading of logical address-physical address mapping table MT (s) non-volatile Data in property memory module.In addition, memorizer control circuit unit 404 (or memory management circuitry 502) and can set Second index P2 is directed toward the previous cache unit of cache unit 810 (2-n) in second area Z2, i.e. 810 (2- of cache unit (n-1)).In this exemplary embodiment, if the second index P2 has pointed to first 810 (2- of cache unit of second area Z2 0) when, memorizer control circuit unit 404 (or memory management circuitry 502) can choose the last one caching of second area Z2 Unit 810 (2-n) is as next second index P2 cache unit to be directed toward.
If belonging to logical address-physical address mapping table MT (n+1) at this point, receiving instruction from host system and reading When another reading instruction of the data of logical address, memorizer control circuit unit 404 (or memory management circuitry 502) can be sentenced Disconnected logical address-physical address mapping table MT (n+1) has been loaded on the mapping table area MTZ in buffer storage 508, and temporary There are in the cache unit 810 (2-0) of second area Z2.As shown in fig. 9f, (or the memory of memorizer control circuit unit 404 Management circuit 502) directly reflected according to the logical address-physical address being temporarily stored in the cache unit 810 (2-0) of second area Z2 Firing table MT (n+1) reads the data in reproducible nonvolatile memorizer module 406.
Figure 10 A~10D is the schematic diagram of the buffer storage supervisory method according to shown by another exemplary embodiment.Figure 10A~10D relates to buffer storage when receiving write instruction during executing copy-back operation to first area Z1 Management method.
Figure 10 A is please referred to, in this exemplary embodiment, if being set to all slow in the first area Z1 of update area When memory cell 810 (1-0)~810 (1-n) is all denoted as more new state, memorizer control circuit unit 404 (or memory Management circuit 502) it will start copy-back operation, the logical address-physical address mapping table that will be temporarily stored in the Z1 of first area is returned It deposits into reproducible nonvolatile memorizer module.However, memorizer control circuit unit 404 (or memory management circuitry 502) copy-back operation can also be started at other times, and in foregoing teachings for example, details are not described herein.In addition, In starting copy-back operation, with the logical address-that will be temporarily stored in the Z1 of first area, that physical address mapping table restores to duplicative is non- When volatile, memorizer control circuit unit 404 (or memory management circuitry 502) can reset more new district Domain is second area Z2.Therefore, when receiving write instruction from host system 11, memorizer control circuit unit 404 (or storage Device manages circuit 502) can according to received write instruction the logical address-physical address mapping table that need to be updated is kept in reflecting The second area Z2 (i.e. update area) of firing table area MTZ is to be safeguarded.In this exemplary embodiment, memorizer control circuit list First index P1 can be directed toward one of cache unit in second area Z2 by first 404 (or memory management circuitries 502), and This cache unit being pointed to is not more new state.As shown in Figure 10 A, due to all caching lists in second area Z2 at this time Member is not more new state, and therefore, memorizer control circuit unit 404 (or memory management circuitry 502) can set first Index P1 is directed toward first cache unit 810 (2-0) in second area Z2.
During copy-back operation, if receiving instruction for data (below referring also to for the first data) from host system 11 Write-in is to belonging to logical address-physical address mapping table MT (k) (below referring also to for the first logical address-physical address map Table) logical address write instruction (below referring also to for the first write instruction) when, memorizer control circuit unit 404 (or Memory management circuitry 502) to judge logical address-physical address mapping table MT (k) loaded into buffer storage 508 Mapping table area MTZ, and it is temporarily stored in the cache unit 810 (1-1) (below referring also to for the first cache unit) of first area Z1 In.At this point, memorizer control circuit unit 404 (or memory management circuitry 502) can write data into duplicative it is non-easily Logical address mapped physical programming unit described in the property lost memory module 406, and by logical address-physical address map Table MT (k) copies to second area Z2, and be temporarily stored in cache unit 810 (2-0) pointed by the first index P1 (below referring also to For the second cache unit) in.Memorizer control circuit unit 404 (or memory management circuitry 502) by logical address-physically Location mapping table MT (k) copies as logical address-physical address mapping table MT (k) ', and as shown in Figure 10 B, by logical address-object Reason address mapping table MT (k) ' it is temporarily stored in the cache unit 810 (2-0) of second area Z2.Also, memorizer control circuit list First 404 (or memory management circuitries 502) will be updated the logic in the cache unit 810 (2-0) being temporarily stored in second area Z2 Address-physical address mapping table MT (k) ', and cache unit 810 (2-0) is denoted as more new state.In addition, memory control Circuit unit 404 (or memory management circuitry 502) processed can set the cache unit that the first index P1 is directed toward in second area Z2 The latter of 810 (2-0) is not the cache unit of more new state.In this exemplary embodiment, cache unit 810 (2-0) The latter cache unit 810 (2-1) is not more new state.Therefore, (or the memory pipe of memorizer control circuit unit 404 Reason circuit 502) the first index P1 direction cache unit 810 (2-1) can be set.
If being patrolled at this point, receiving instruction from host system and data (below referring also to for the second data) being written to belonging to Volume address-physical address mapping table MT (n+3) (below referring also to for the second logical address-physical address mapping table) is logically When another write instruction (below referring also to for the second write instruction) of location, memorizer control circuit unit 404 (or memory pipe Reason circuit 502) judge logical address-loaded mapping table into buffer storage 508 of physical address mapping table MT (n+3) Area MTZ, and be temporarily stored in the cache unit 810 (2-2) (below referring also to for third cache unit) of second area Z2.Such as figure Shown in 10C, memorizer control circuit unit 404 (or memory management circuitry 502) can write data into non-easily to duplicative Logical address mapped physical programming unit described in the property lost memory module 406, and more new logical addresses-physical address reflects Firing table MT (n+3), and cache unit 810 (2-2) is denoted as more new state.
If being patrolled at this point, receiving instruction from host system and data (below referring also to for third data) being written to belonging to The logical address of volume address-physical address mapping table MT (x) (below referring also to for third logical address-physical address mapping table) Another write instruction (below referring also to for third write instruction) when, (or the memory management of memorizer control circuit unit 404 Circuit 502) decision logic address-physical address mapping table MT (x) is not yet loaded on the mapping table area in buffer storage 508 MTZ.Therefore, memorizer control circuit unit 404 (or memory management circuitry 502) can be from type nonvolatile Logical address-physical address mapping table MT (x) is loaded into mapping table area MTZ in module 406, and pointed by the first index P1 Second area Z2 in cache unit 810 (2-1) carry out register logic address-physical address mapping table MT (x).Such as Figure 10 D institute Show, logical address-physical address mapping table MT (x) is temporarily stored in the cache unit 810 (2-1) in second area Z2 (below It is referenced as the 4th cache unit) in, and memorizer control circuit unit 404 (or memory management circuitry 502) can write data Enter to reproducible nonvolatile memorizer module 406.Memorizer control circuit unit 404 (or memory management circuitry 502) And it will be updated logical address-physical address mapping table MT (x), and cache unit 810 (2-1) is denoted as more new state.
Further, memorizer control circuit unit 404 (or memory management circuitry 502) can choose second area Z2 The latter of middle cache unit 810 (2-1) is not the cache unit of more new state to set the first index P1.In this example reality It applies in example, memorizer control circuit unit 404 (or memory management circuitry 502) can sequentially judge cache unit 810 (2-1) The latter cache unit 810 (2-2) has been denoted as more new state.Therefore, memorizer control circuit unit 404 (or storage Device manages circuit 502) it can sequentially find backward not as the cache unit of more new state.Then, memorizer control circuit unit 404 (or memory management circuitries 502) judge the latter cache unit 810 (2-3) of cache unit 810 (2-2) not for More new state, and set the first index P1 and be directed toward cache unit 810 (2-3).
In this exemplary embodiment, after copy-back operation completion about first area Z1, i.e. memorizer control circuit Unit 404 (or memory management circuitry 502) will be in all cache units 810 (1-0)~810 (1-n) of first area Z1 Logical address-physical address mapping table be written into the reproducible nonvolatile memorizer module, memorizer control circuit Unit 404 (or memory management circuitry 502) can mark all cache units 810 (1-0)~810 (1-n) of first area Z1 It is shown as not more new state.In this way, which all cache units 810 (2-0)~810 (2-n) as second area Z2 are all labeled When for more new state, memorizer control circuit unit 404 (or memory management circuitry 502) will start copy-back operation, will Logical address-the physical address mapping table being temporarily stored in all cache units 810 (2-0)~810 (2-n) of second area Z2 is returned It deposits into reproducible nonvolatile memorizer module 406, while resetting update area is first area Z1, persistently to connect The data of the write instruction from host system are received to execute write operation.In addition to this, in another exemplary embodiment, storage Device control circuit unit 404 (or memory management circuitry 502) subdivided in buffer storage 508 can also have been provided continuously Register logic address-physical address mapping table is carried out in another region of multiple cache units, and the present invention is not limited thereto.
Figure 11 A and 11B are the flow charts of the buffer storage supervisory method according to shown by an exemplary embodiment.
Figure 11 A is please referred to, in step S1101, memorizer control circuit unit 404 (or memory management circuitry 502) Mapping table area can be marked off in buffer storage 508.
In step S1103, memorizer control circuit unit 404 (or memory management circuitry 502) can be by mapping table area It is divided into the first area for being respectively provided with continuous multiple cache units and second area.
In step S1105, memorizer control circuit unit 404 (or memory management circuitry 502) is non-from duplicative Multiple logical address-physical address mapping tables are loaded into volatile to first area and second area.Institute as above It states, each logical address-physical address mapping table being loaded into is the one of caching list being temporarily stored in first area One of cache unit in member or second area.
In step S1107, memorizer control circuit unit 404 (or memory management circuitry 502) sets update area It is set to first area.
In step S1109, memorizer control circuit unit 404 (or memory management circuitry 502) updates the multiple One of logical address-the physical address mapping table of logical address-physical address mapping table, by this, one of them is logically Location-physical address mapping table keeps in one of cache unit to the cache unit of first area, and by the firstth area This one of cache unit in domain is denoted as more new state.Specifically, memorizer control circuit unit 404 (or deposit Reservoir manages circuit 502) can according to from host system 11 received write instructions come more new logical addresses-physical address map Table, relevant operation mode illustrate that details are not described herein in exemplary embodiment above-mentioned.
In step S1111, if all cache units of first area are all denoted as more new state, memory Control circuit unit 404 (or memory management circuitry 502) will be temporarily stored in all cache units of first area logically Location-physical address mapping table restores in reproducible nonvolatile memorizer module.However, memorizer control circuit unit 404 (or memory management circuitries 502) can also start copy-back operation at other times, and illustrate in foregoing teachings Bright, details are not described herein.
If being restored to by logical address-physical address mapping table in all cache units for being temporarily stored in first area During in reproducible nonvolatile memorizer module, write instruction is received from host system 11, executes Figure 11 B's for other Process.
Figure 11 B is please referred to, in step S1113, memorizer control circuit unit 404 (or memory management circuitry 502) Instruction, which is received, from host system writes data into writing to the logical address for belonging to one logical address-physical address mapping table Enter instruction.
In step S1115, memorizer control circuit unit 404 (or memory management circuitry 502) by update area more It is changed to second area.
In step S1117, memorizer control circuit unit 404 (or memory management circuitry 502) judges this logically Whether logical address-physical address mapping table belonging to location has been temporarily stored in first area or second area.
In step S1119, if logical address-physical address mapping table belonging to this logical address has been temporarily stored in In the cache unit (below referring also to for the first cache unit) in one region, memorizer control circuit unit 404 (or memory pipe Reason circuit 502) it writes data into reproducible nonvolatile memorizer module, and by the first cache unit in first area In logical address-physical address mapping table copy in second area cache unit (below referring also to for the second caching it is single Member) in.
In step S1121, memorizer control circuit unit 404 (or memory management circuitry 502) update is temporarily stored in the Logical address-physical address mapping table in the second cache unit in two regions, and the second cache unit is denoted as more New state.
In step S1123, if logical address-physical address mapping table belonging to this logical address has been temporarily stored in In the cache unit (below referring also to for third cache unit) in two regions, memorizer control circuit unit 404 (or memory pipe Reason circuit 502) it writes data into reproducible nonvolatile memorizer module, it is slow to update temporary third in the second area Logical address-physical address mapping table in memory cell, and third cache unit is denoted as more new state.
In step S1125, if logical address-physical address mapping table belonging to this logical address is not yet temporarily stored in First area or second area, memorizer control circuit unit 404 (or memory management circuitry 502) are non-volatile from duplicative Property memory module is loaded into logical address-physical address mapping table belonging to this logical address and is temporarily stored in the caching of second area In unit (below referring also to for the 4th cache unit).
In step S1127, memorizer control circuit unit 404 (or memory management circuitry 502) write data into Reproducible nonvolatile memorizer module updates logical address-object in temporary the 4th cache unit in the second area Address mapping table is managed, and the 4th cache unit is denoted as more new state.
In step S1129, if all cache units of second area are all denoted as more new state, memory Control circuit unit 404 (or memory management circuitry 502) will be temporarily stored in all cache units of second area logically Location-physical address mapping table restores in reproducible nonvolatile memorizer module.However, memorizer control circuit unit 404 (or memory management circuitries 502) can also start copy-back operation at other times, and illustrate in foregoing teachings Bright, details are not described herein.
In conclusion buffer storage supervisory method provided by the present invention, memorizer control circuit unit and memory Storage device is the specific region with continuous cache unit to be marked off in buffer storage, and update area is set as The logical address being updated-physical address mapping table concentration is temporarily stored in update area by specific region.In this way, work as Updated logical address-physical address mapping table in buffer storage is restored into type nonvolatile It, can be according to the size of physical programming unit, directly by updated logical address-physical address in update area when module Mapping table is written to physical programming unit, and need not in addition execute the operation of duplication with collection.And by the way that this specific region is set It is set to particular size, can avoids causing system load overweight because the data volume that need to be handled is excessive when carrying out copy-back operation Problem, and then effectively promote the processing speed of copy-back operation.In addition, by way of changing update area, so that will buffer Updated logical address-physical address mapping table in memory restores to the phase of reproducible nonvolatile memorizer module Between, the sustainable data that write instruction is received from host system, and write operation is executed, it avoids causing because the waiting time is too long The case where write-in failure, the stability of lifting system.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.

Claims (18)

1. a kind of buffer storage supervisory method, the buffer storage for memory storage apparatus, which is characterized in that described Memory storage apparatus has reproducible nonvolatile memorizer module, and the buffer storage supervisory method includes:
First area and second area are marked off in said buffer memory, wherein the first area and the second area Respectively there are continuous multiple cache units, and in those cache units in the first area and the second area At least part cache unit kept in multiple logical address-physical address mapping tables；
The first area is set as update area, copy-back operation is executed to incite somebody to action to those cache units of the first area Those logical address-physical address mapping tables for being stored in the first area restore to the duplicative non-volatile memories In device module；
The first write instruction is received from host system, wherein first write instruction instruction writes first data into first and patrols Volume address, and the first logical address-physical address mapping table belonging to first logical address has been temporarily stored in described the In the first cache unit among the cache unit in one region；
The update area is changed to the second area, first data are written and are deposited to the duplicative is non-volatile Memory modules, and the first logical address-physical address mapping table in the first area is copied into secondth area In the second cache unit among cache unit in domain；And
The the first logical address-physical address updated in temporary second cache unit in the second region reflects Firing table.
2. buffer storage supervisory method according to claim 1, which is characterized in that update is temporarily stored in the second area In second cache unit in the first logical address-physical address mapping table the step of, further includes:
Second cache unit is denoted as more new state, wherein the update area be configured to temporarily store it is multiple be updated patrol Collect address-physical address mapping table.
3. buffer storage supervisory method according to claim 2, which is characterized in that further include:
When all cache units of the second area are all the more new state, by all cachings of the second area Those logical address-physical address mapping tables in unit restore in the reproducible nonvolatile memorizer module, weight First area described in new settings is the update area.
4. buffer storage supervisory method according to claim 2, which is characterized in that further include:
According to the sequence of the cache unit in the second area, choose first in the second area for it is described more The cache unit of new state sets the first index and is directed toward second cache unit as second cache unit；And
In second cache unit copied to the first logical address-physical address mapping table in the second area Later, it sets first index and is directed toward another cache unit among the cache unit of the second area, wherein described Another cache unit is the cache unit that the latter of second cache unit is not the more new state.
5. buffer storage supervisory method according to claim 2, which is characterized in that further include:
The second write instruction is received from the host system, wherein the second data are written to for second write instruction instruction Two logical addresses, and the second logical address-physical address mapping table belonging to second logical address has been temporarily stored in institute It states in the third cache unit among the cache unit of second area；And
The update area is changed to the second area, second data are written and are deposited to the duplicative is non-volatile Memory modules, and update the second logical address-object in the temporary third cache unit in the second region Manage address mapping table.
6. buffer storage supervisory method according to claim 2, which is characterized in that further include:
Third write instruction is received from the host system, wherein third data are written to for third write instruction instruction Three logical addresses, and third logical address-physical address mapping table belonging to the third logical address is not yet loaded into and reflects Firing table area, wherein marking off the mapping table area from the buffer storage, and the mapping table zoning is divided into described first Region and the second area；
The update area is changed to the second area, institute is loaded into from the reproducible nonvolatile memorizer module State third logical address-physical address mapping table, and third logical address-physical address mapping table be temporarily stored in it is described In the 4th cache unit among the cache unit of second area；And
The third data are written to the reproducible nonvolatile memorizer module, and updates and is temporarily stored in the second area In the 4th cache unit in the third logical address-physical address mapping table.
7. a kind of memorizer control circuit unit, for controlling reproducible nonvolatile memorizer module, which is characterized in that institute Stating memorizer control circuit unit includes:
Host interface is electrically connected to host system；
Memory interface is electrically connected to the reproducible nonvolatile memorizer module；
Buffer storage is electrically connected to the host interface and the memory interface；And
Memory management circuitry is electrically connected to the host interface, the memory interface and the buffer storage, and To mark off first area and second area in said buffer memory, wherein the first area and the second area Respectively there are continuous multiple cache units, and in those cache units in the first area and the second area At least part cache unit kept in multiple logical address-physical address mapping tables,
Wherein, the memory management circuitry is also to be set as update area for the first area, to the first area Those cache units execute copy-back operation so that those logical address-physical address mapping tables of the first area will be stored in It restores in the reproducible nonvolatile memorizer module,
Wherein, the memory management circuitry is also to receive the first write instruction, first write-in from the host system Instruction instruction writes first data into the first logical address, and the first logical address-belonging to first logical address Physical address mapping table has been temporarily stored in the first cache unit among the cache unit of the first area,
Wherein, the memory management circuitry is also being changed to the second area for the update area, is written described the One data are to the reproducible nonvolatile memorizer module, and by first logical address-in the first area Physical address mapping table copies in the second cache unit among the cache unit in the second area,
Wherein, the memory management circuitry is also to update in temporary second cache unit in the second region The first logical address-physical address mapping table.
8. memorizer control circuit unit according to claim 7, which is characterized in that the memory management circuitry is also used Second cache unit is denoted as more new state, wherein the update area is configured to temporarily store multiple logics being updated Address-physical address mapping table.
9. memorizer control circuit unit according to claim 8, which is characterized in that the memory management circuitry is also used When with all cache units in the second area being all the more new state, by all caching lists of the second area Those logical address-physical address mapping tables in member restore in the reproducible nonvolatile memorizer module, again The first area is set as the update area.
10. memorizer control circuit unit according to claim 8, which is characterized in that the memory management circuitry is also To the sequence according to the cache unit in the second area, choose first in the second area for it is described more The cache unit of new state sets the first index and is directed toward second cache unit as second cache unit,
Wherein, the first logical address-physical address mapping table in the first area is being copied into secondth area After in second cache unit in domain, the memory management circuitry is also to set described in the first index direction Another cache unit among the cache unit of second area, wherein another described cache unit is that second caching is single The latter of member is not the cache unit of the more new state.
11. memorizer control circuit unit according to claim 8, which is characterized in that the memory management circuitry is also To receive the second write instruction from the host system, the second data, which are written to second, for the second write instruction instruction is patrolled Volume address, and the second logical address-physical address mapping table belonging to second logical address has been temporarily stored in described the In third cache unit among the cache unit in two regions,
Wherein, the memory management circuitry is also being changed to the second area for the update area, is written described the Two data are to the reproducible nonvolatile memorizer module, and it is slow to update the temporary third in the second region The second logical address-physical address mapping table in memory cell.
12. memorizer control circuit unit according to claim 8, which is characterized in that the memory management circuitry is also To receive third write instruction from the host system, third data, which are written to third, for the third write instruction instruction is patrolled Address is collected, and third logical address-physical address mapping table belonging to the third logical address is not yet loaded into mapping table Area, wherein marking off the mapping table area from the buffer storage, and the mapping table zoning is divided into the first area With the second area,
Wherein, the memory management circuitry is answered also the update area is changed to the second area from described It writes and is loaded into the third logical address-physical address mapping table in formula non-volatile memory module, and the third logic Address-physical address mapping table is temporarily stored in the 4th cache unit among the cache unit of the second area,
Wherein, the memory management circuitry is also to be written the third data to the type nonvolatile Module, and update the third logical address-in temporary the 4th cache unit in the second region physically Location mapping table.
13. a kind of memory storage apparatus characterized by comprising
Connecting interface unit, is electrically connected to host system；
Reproducible nonvolatile memorizer module；And
Memorizer control circuit unit is electrically connected to the connecting interface unit and the type nonvolatile Module, and including buffer storage, and to mark off first area and second area in said buffer memory, Described in first area and the second area respectively there is continuous multiple cache units, and the first area and institute It states at least part cache unit in those cache units in second area and has kept in multiple logical address-physical address and reflect Firing table,
Wherein, the memorizer control circuit unit is also to be set as update area for the first area, to described first Those cache units in region execute copy-back operation to reflect those logical address-physical address for being stored in the first area Firing table restores in the reproducible nonvolatile memorizer module,
Wherein, the memorizer control circuit unit also to from the host system receive the first write instruction, described first Write instruction instruction writes first data into the first logical address, and belonging to first logical address first logically Location-physical address mapping table has been temporarily stored in the first cache unit among the cache unit of the first area,
Wherein, institute is written also the update area is changed to the second area in the memorizer control circuit unit The first data are stated to the reproducible nonvolatile memorizer module, and logically by described first in the first area Location-physical address mapping table copies in the second cache unit among the cache unit in the second area,
Wherein, the memorizer control circuit unit is also single to update temporary second caching in the second region The first logical address-physical address mapping table in member.
14. memory storage apparatus according to claim 13, which is characterized in that memorizer control circuit unit also to Second cache unit is denoted as more new state, wherein the update area is configured to temporarily store multiple be updated logically Location-physical address mapping table.
15. memory storage apparatus according to claim 14, which is characterized in that the memorizer control circuit unit is also When to all cache units in the second area being all the more new state, by all cachings of the second area Those logical address-physical address mapping tables in unit restore in the reproducible nonvolatile memorizer module, weight First area described in new settings is the update area.
16. memory storage apparatus according to claim 14, which is characterized in that the memorizer control circuit unit is also To the sequence according to the cache unit in the second area, choose first in the second area for it is described more The cache unit of new state sets the first index and is directed toward second cache unit as second cache unit,
Wherein, the first logical address-physical address mapping table in the first area is being copied into secondth area After in second cache unit in domain, the memorizer control circuit unit is also directed toward to set first index Another cache unit among the cache unit of the second area, wherein another described cache unit is described second slow The latter of memory cell is not the cache unit of the more new state.
17. memory storage apparatus according to claim 14, which is characterized in that the memorizer control circuit unit is also To receive the second write instruction from the host system, the second data, which are written to second, for the second write instruction instruction is patrolled Volume address, and the second logical address-physical address mapping table belonging to second logical address has been temporarily stored in described the In third cache unit among the cache unit in two regions,
Wherein, institute is written also the update area is changed to the second area in the memorizer control circuit unit The second data are stated to the reproducible nonvolatile memorizer module, and update temporary described the in the second region The second logical address-physical address mapping table in three cache units.
18. memory storage apparatus according to claim 14, which is characterized in that the memorizer control circuit unit is also To receive third write instruction from the host system, third data, which are written to third, for the third write instruction instruction is patrolled Address is collected, and third logical address-physical address mapping table belonging to the third logical address is not yet loaded into mapping table Area, wherein marking off the mapping table area from the buffer storage, and the mapping table zoning is divided into the first area With the second area,
Wherein, the memorizer control circuit unit is also to be changed to the second area for the update area, from described Third logical address-the physical address mapping table, and the third are loaded into reproducible nonvolatile memorizer module Logical address-physical address mapping table is temporarily stored in the 4th cache unit among the cache unit of the second area,
Wherein, the memorizer control circuit unit is also deposited the third data are written to the duplicative is non-volatile Memory modules, and update the third logical address-object in temporary the 4th cache unit in the second region Manage address mapping table.
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