CN110390985B

CN110390985B - Memory management method, memory storage device and memory control circuit unit

Info

Publication number: CN110390985B
Application number: CN201810358395.0A
Authority: CN
Inventors: 郭哲岳; 李文晋
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2018-04-20
Filing date: 2018-04-20
Publication date: 2021-08-03
Anticipated expiration: 2038-04-20
Also published as: CN110390985A

Abstract

Example embodiments of the present invention provide a memory management method for a memory storage device including a rewritable nonvolatile memory module, a memory storage device, and a memory control circuit unit. The method comprises the following steps: corresponding to a write-in instruction from a host system, performing data integration operation on at least one physical unit of the rewritable nonvolatile memory module; and adjusting the times of executing the data merging operation according to the dispersion of a plurality of logic units corresponding to the first data stored in the first type of physical units in the rewritable nonvolatile memory module.

Description

Memory management method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a memory management mechanism, and more particularly, to a memory management method, a memory storage device and a memory control circuit unit.

Background

Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.

As the age and/or frequency of use of a memory storage device increases, the number of idle physical units in the memory storage device gradually decreases. When the number of the idle physical units is less than a preset number, the memory storage device starts to execute a garbage collection procedure. However, during the execution of the garbage collection procedure, the host system may continue to issue data write commands to the memory storage device. Therefore, during the execution of the garbage collection procedure, the data writing performance of the memory storage device may suddenly increase or decrease, thereby affecting the data writing stability of the memory storage device.

Disclosure of Invention

The invention provides a memory management method, a memory storage device and a memory control circuit unit, which can effectively improve the data writing stability of the memory storage device.

An exemplary embodiment of the present invention provides a memory management method for a memory storage device including a rewritable nonvolatile memory module, where the rewritable nonvolatile memory module includes a plurality of physical units, at least one first type of physical unit of the physical units stores first data, and the first data corresponds to a plurality of logical units. The memory management method comprises the following steps: performing at least one data union operation on at least one of the physical units corresponding to a write command from a host system; and adjusting the times of executing the data merging operation according to the dispersion of the logic unit corresponding to the first data.

In an example embodiment of the present invention, the performing the data union operation on the at least one of the physical units corresponding to the write command from the host system includes: performing at least one access event on the one of the physical units corresponding to the write command from the host system. The access event includes at least one of a data read event, a data write event, and a table read event.

In an exemplary embodiment of the invention, the step of adjusting the number of times of performing the data merging operation according to the dispersion of the logic unit corresponding to the first data includes: obtaining a first event count value according to the dispersion; and adjusting the number of access events corresponding to the write instruction execution according to the first event counter value.

In an exemplary embodiment of the present invention, the step of obtaining the first event count value according to the dispersion includes: and obtaining the first event count value according to the dispersion and the effective data storage information of the first type of physical units. The valid data storage information reflects the storage state of the valid data in the first type physical unit.

In an exemplary embodiment of the present invention, the step of obtaining the first event count value according to the dispersion and the valid data storage information of the first type physical unit includes: and obtaining the first event count value according to the dispersion, the effective data storage information of the first type of physical units and the number of at least one second type of physical unit in the physical units. The second type of physical unit does not store the valid data.

In an exemplary embodiment of the present invention, the step of obtaining the first event count value according to the dispersion includes: obtaining a second event count value according to the dispersion, wherein the second event count value corresponds to the number of at least one access event for fully writing a second type of physical unit in the physical units; and obtaining the first event count value according to the second event count value.

Another exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of physical units. At least one first type physical unit in the physical units stores first data, and the first data corresponds to a plurality of logic units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for indicating to execute at least one data union operation on at least one of the physical units corresponding to a write instruction from the host system. The memory control circuit unit is further configured to adjust the number of times of performing the data merging operation according to the dispersion of the logic unit corresponding to the first data.

In an example embodiment of the present invention, the operation of the memory control circuit unit to perform the data union operation on the at least one of the physical units in response to the write instruction from the host system includes: instructing the one of the physical units to perform at least one access event corresponding to the write command from the host system. The access event includes at least one of a data read event, a data write event, and a table read event.

In an exemplary embodiment of the invention, the operation of the memory control circuit unit adjusting the number of times of performing the data merging operation according to the dispersion of the logic unit corresponding to the first data includes: obtaining a first event count value according to the dispersion; and adjusting the number of access events corresponding to the write instruction execution according to the first event counter value.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit obtaining the first event count value according to the dispersion includes: and obtaining the first event count value according to the dispersion and the effective data storage information of the first type of physical units. The valid data storage information reflects the storage state of the valid data in the first type physical unit.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit obtaining the first event count value according to the dispersion and the valid data storage information of the first type physical unit includes: and obtaining the first event count value according to the dispersion, the effective data storage information of the first type of physical units and the number of at least one second type of physical unit in the physical units. The second type of physical unit does not store the valid data.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit obtaining the first event count value according to the dispersion includes: obtaining a second event count value according to the dispersion, wherein the second event count value corresponds to the number of at least one access event for fully writing a second type of physical unit in the physical units; and obtaining the first event count value according to the second event count value.

Another exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of physical units. At least one first type physical unit in the physical units stores first data, and the first data corresponds to a plurality of logic units. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is used for indicating to execute at least one data union operation on at least one of the physical units corresponding to a write instruction from the host system. The memory management circuit is further configured to adjust the number of times of performing the data merging operation according to the dispersion of the logic unit corresponding to the first data.

In an exemplary embodiment of the invention, the dispersion of the logic units positively correlates to the number of at least one table recorded with the logic-to-physical mapping information of the first data.

In an example embodiment of the present invention, the operation of the memory management circuit performing the data union operation on the at least one of the physical units corresponding to the write instruction from the host system includes: instructing the one of the physical units to perform at least one access event corresponding to the write command from the host system. The access event includes at least one of a data read event, a data write event, and a table read event.

In an exemplary embodiment of the invention, the operation of the memory management circuit adjusting the number of times of performing the data merging operation according to the dispersion of the logic unit corresponding to the first data includes: obtaining a first event count value according to the dispersion; and adjusting the number of access events corresponding to the write instruction execution according to the first event counter value.

In an exemplary embodiment of the present invention, the operation of the memory management circuit obtaining the first event count value according to the dispersion includes: and obtaining the first event count value according to the dispersion and the effective data storage information of the first type of physical units. The valid data storage information reflects the storage state of the valid data in the first type physical unit.

In an exemplary embodiment of the present invention, the operation of the memory management circuit obtaining the first event count value according to the dispersion and the valid data storage information of the first type of physical unit includes: and obtaining the first event count value according to the dispersion, the effective data storage information of the first type of physical units and the number of at least one second type of physical unit in the physical units. The second type of physical unit does not store the valid data.

In an exemplary embodiment of the present invention, the operation of the memory management circuit obtaining the first event count value according to the dispersion includes: obtaining a second event count value according to the dispersion, wherein the second event count value corresponds to the number of at least one access event for fully writing a second type of physical unit in the physical units; and obtaining the first event count value according to the second event count value.

Based on the above, the data union operation may be performed on at least one physical unit of the rewritable non-volatile memory module corresponding to the write command from the host system. In addition, the number of times of executing the data merging operation can be adjusted according to the dispersion of the logic unit corresponding to the first data stored in the first type of physical unit in the rewritable nonvolatile memory module. Therefore, the data writing stability of the memory storage device can be effectively improved.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention.

FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.

FIG. 3 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention.

FIG. 7 is a diagram illustrating a host write operation and a data merge operation according to an exemplary embodiment of the invention.

FIG. 8 is a diagram illustrating physical units and corresponding logical distribution status information according to an exemplary embodiment of the present invention.

FIG. 9 is a diagram illustrating logic distribution status information and corresponding second event count values according to an example embodiment of the invention.

FIG. 10 is a diagram illustrating an operation mode of a second type physical unit number and corresponding data merging operation according to an example embodiment of the present invention.

FIG. 11 is a flowchart illustrating a memory management method according to an exemplary embodiment of the invention.

Description of the reference numerals

10. 30: a memory storage device;

11. 31: a host system;

110: a system bus;

111: a processor;

112: a random access memory;

113: a read-only memory;

114: a data transmission interface;

12: input/output (I/O) devices;

20: a main board;

201: a U disk;

202: a memory card;

203: a solid state disk;

204: a wireless memory storage device;

205: a global positioning system module;

206: a network interface card;

207: a wireless transmission device;

208: a keyboard;

209: a screen;

210: a horn;

32: an SD card;

33: a CF card;

34: an embedded storage device;

341: an embedded multimedia card;

342: an embedded multi-chip package storage device;

402: a connection interface unit;

404: a memory control circuit unit;

406: a rewritable non-volatile memory module;

502: a memory management circuit;

504: a host interface;

506: a memory interface;

508: an error checking and correcting circuit;

510: a buffer memory;

512: a power management circuit;

601: a storage area;

602: an idle area;

603: a system area;

610(0) - (610C), 710(0), 721(0) - (721 (E), 731(0) - (731 (F), 810(0), 810 (1)): a physical unit;

612(0) to 612 (D): a logic unit;

701. 702, 801 to 804, 811 to 818: data;

720: a source node;

730: recovering the nodes;

821(0), 821 (1): logically distributing state information;

910: form information;

s1101: step (corresponding to a write-in command from a host system, performing data integration operation on at least one physical unit of the rewritable nonvolatile memory module);

s1102: and (adjusting the times of executing the data merging operation according to the dispersion of a plurality of logic units corresponding to first data stored in a first type of physical unit in the rewritable nonvolatile memory module).

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all connected to a system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. The host system 11 is connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be connected to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, Bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded memory device 34 includes various types of embedded memory devices such as an embedded multimedia Card (eMMC) 341 and/or an embedded Multi-Chip Package (eMCP) memory device 342, which directly connects the memory module to the substrate of the host system.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11. In the exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed Specification-I (UHS-I) interface standard, the Ultra High Speed Specification-II (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Memory (Flash) interface standard, the CF interface standard, the Device interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a solid state type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.

In the exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical programming cells, and the physical programming cells form a plurality of physical erasing cells. Specifically, the memory cells on the same word line constitute one or more physical programming cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.

In the exemplary embodiment, the physical program cell is a minimum cell to be programmed. That is, the physical programming unit is the smallest unit for writing data. For example, a physical program unit is a physical page (page) or a physical fan (sector). If the physical program units are physical pages, the physical program units usually include a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, 8, 16, or a greater or lesser number of physical fans may be included in the data bit region, and the size of each physical fan may also be greater or lesser. On the other hand, the physical erase cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, a physical erase unit is a physical block (block).

Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.

In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in a solid state form. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 502 may also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is connected to the memory management circuit 502 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transfer standard.

The memory interface 506 is connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence indicating to write data, a read instruction sequence indicating to read data, an erase instruction sequence indicating to erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

In an exemplary embodiment, the memory control circuitry 404 further includes error checking and correction circuitry 508, buffer memory 510, and power management circuitry 512.

The error checking and correcting circuit 508 is connected to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.

The buffer memory 510 is connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is connected to the memory management circuit 502 and is used to control the power of the memory storage device 10.

Referring to FIG. 6, the memory management circuit 502 logically groups the physical units 610(0) -610 (C) of the rewritable nonvolatile memory module 406 into a storage area 601, an idle (spare) area 602, and a system area 603. The physical units 610(0) to 610(a) in the storage area 601 store data. For example, physical locations 610(0) -610 (A) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610(a +1) to 610(B) in the idle region 602 are not yet used to store data (e.g., valid data). The physical units 610(B +1) to 610(C) in the system area 603 are used to store system data, such as a logical-to-physical mapping table, a bad block management table, a device model, or other types of management data.

When data is to be stored, the memory management circuit 502 selects one physical unit from the physical units 610(a +1) to 610(B) of the idle area 602 and stores data from the host system 11 or at least one physical unit in the storage area 601 into the selected physical unit. At the same time, the selected physical unit will be associated to the memory area 601. In addition, after erasing a physical unit in the storage area 601, the erased physical unit is re-associated with the idle area 602.

In the exemplary embodiment, each physical unit belonging to the memory area 601 is also referred to as a non-idle (non-spare) physical unit or a first type physical unit, and each physical unit belonging to the idle area 602 is also referred to as an idle physical unit or a second type physical unit. In the present exemplary embodiment, one physical cell refers to one physical erase cell. However, in another exemplary embodiment, one physical unit may also include a plurality of physical erase units.

The memory management circuitry 502 configures the logical units 612(0) - (612 (D) to map the physical units 610(0) - (610 (A) in the memory area 601. In the present exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logic cell may also refer to a logic program cell, a logic erase cell or be composed of a plurality of continuous or discontinuous logic addresses. In addition, each of the logical units 612(0) -612 (D) may be mapped to one or more physical units. It should be noted that the memory management circuit 502 may not configure the logical units mapped to the system area 603, so as to prevent the system data stored in the system area 603 from being modified by the user.

The memory management circuit 502 records the mapping relationship between the logical units and the physical units (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table. The logical-to-physical mapping table is stored in the physical units 610(B +1) to 610(C) of the system area 603. When the host system 11 is going to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access operations with respect to the memory storage device 10 according to the logical-to-physical mapping table.

In the exemplary embodiment, the valid data is the latest data belonging to a logical unit, and the invalid data is not the latest data belonging to any logical unit. For example, if the host system 11 stores a new data item in a logical unit to overwrite the old data originally stored in the logical unit (i.e. update the data belonging to the logical unit), the new data item stored in the storage area 601 is the latest data belonging to the logical unit and will be marked as valid, and the overwritten old data item may still be stored in the storage area 601 but marked as invalid.

In the exemplary embodiment, if the data belonging to a logical unit is updated, the mapping relationship between the logical unit and the physical unit storing the old data belonging to the logical unit is removed, and the mapping relationship between the logical unit and the physical unit storing the latest data belonging to the logical unit is established. However, in another exemplary embodiment, if the data belonging to a logical unit is updated, the mapping relationship between the logical unit and the physical unit storing the old data belonging to the logical unit can still be maintained.

When the memory storage device 10 is shipped from a factory, the total number of physical units belonging to the idle area 602 is a preset number (e.g., 30). In operation of memory storage device 10, more and more physical units are selected from idle region 602 and associated with storage region 601 to store data (e.g., user data from host system 11). Therefore, the total number of physical units belonging to the idle region 602 gradually decreases as the memory storage device 10 is used.

During operation of the memory storage device 10, the memory management circuit 502 continuously updates the total number of physical units belonging to the idle region 602. The memory management circuit 502 performs at least one data union operation according to the number of physical units in the idle region 602 (i.e., the total number of idle physical units). For example, the memory management circuit 502 can determine whether the total number of physical units belonging to the idle region 602 is less than or equal to a threshold (also referred to as a first threshold). The first threshold value is, for example, a value of 2 or more (e.g., 10), but the invention is not limited thereto. If the total number of physical units belonging to the idle region 602 is less than or equal to the first threshold, the memory management circuit 502 may perform a data union operation. In an example embodiment, the data consolidation operation is also referred to as a garbage collection (garbel collection) operation.

In a data union operation, memory management circuitry 502 may select at least one physical unit (also referred to as a source node) from memory area 601 and attempt to centrally copy valid data from the selected physical unit to another physical unit (also referred to as a recycle node). The physical unit for storing the copied valid data is selected from the idle area 602 and is associated with the storage area 601. If all valid data stored in a physical unit has been copied to the recycle node, the physical unit may be erased and associated with the idle region 602. In an exemplary embodiment, the operation of re-associating a physical unit from the memory area 601 back to the idle area 602 (or the operation of erasing a physical unit) is also referred to as releasing an idle physical unit. By performing the data union operation, one or more idle physical units are released and the total number of physical units belonging to the idle region 602 is gradually increased.

After the completion operation is started, if the physical units belonging to the idle area 602 satisfy a specific condition, the completion operation is stopped. For example, the memory management circuit 502 can determine whether the total number of physical units belonging to the idle region 602 is greater than or equal to a threshold (hereinafter also referred to as a second threshold). For example, the second threshold value may be greater than or equal to the first threshold value. If the total number of physical units belonging to the idle region 602 is greater than or equal to the second threshold, the memory management circuit 502 may stop the data rounding operation. It should be noted that stopping the data merging operation refers to ending the currently executing data merging operation. After stopping a data union operation, if the total number of physical units belonging to the idle region 602 is again less than or equal to the first threshold, a next data union operation may be performed again to attempt to release a new idle physical unit.

FIG. 7 is a diagram illustrating a host write operation and a data merge operation according to an exemplary embodiment of the invention. Referring to fig. 7, in a host write operation, the host system 11 sends at least one write command to instruct writing data 701 to a logical unit. According to the write command, data 701 is stored into physical unit 710(0) mapped to the logical unit. For example, the physical unit 710(0) may be selected from the idle region 602 of fig. 6. In an example embodiment, the physical unit 710(0) currently used to store the data 701 from the host system 11 is also referred to as an open block (open block). It should be noted that, in another exemplary embodiment, one open block may also include a plurality of physical units.

During execution of the host write operation, at least one data union operation may be performed. In a data merge operation, data 702 may be collected from physical units 721(0) -721 (E) belonging to source node 720 and written to physical units 731(0) -731 (F) belonging to recycle node 730. The data 702 is valid data. Physical units 721(0) -721 (E) belonging to the source node 720 are selected from the storage area 601 of FIG. 6, and physical units 731(0) -731 (F) belonging to the sink node 730 are selected from the free area 602 of FIG. 6. In an example embodiment, physical units 721(0) -721 (E) are the E +1 physical units that store the least significant data in memory 601 of FIG. 6. In an exemplary embodiment, the physical units 721(0) -721 (E) are selected from the memory 601 of FIG. 6 according to other rules, which are not intended to limit the present invention.

In an example embodiment, the memory management circuit 502 obtains the logical distribution status information of the first type of physical unit in the rewritable non-volatile memory module 406. For example, the memory management circuit 502 may analyze a logical unit to which data (also referred to as first data) stored in the first type of physical unit belongs to obtain logical distribution state information of the first type of physical unit. The logic distribution state information of the first type physical unit can reflect the dispersion of a plurality of logic units corresponding to the first data stored in the first type physical unit.

In an exemplary embodiment, the first data is valid data stored in at least a portion of the first type of physical unit. Therefore, the dispersion of the logical units corresponding to the first data can reflect the dispersion (i.e. dispersion) of the logical units to which at least a part of the valid data stored in the first type of physical units belongs. For example, if the plurality of logical units to which the valid data stored in the first type of physical unit belongs are more distributed (for example, most of the valid data corresponds to a plurality of discontinuous logical units), it can be determined that the dispersion of the logical units to which the first data corresponds is higher. Alternatively, if the plurality of logical units to which the valid data stored in the first type of physical unit belongs are more concentrated (for example, most of the valid data corresponds to a plurality of continuous logical units), it may be determined that the dispersion of the logical units to which the first data corresponds is lower.

In an example embodiment, the memory management circuit 502 may obtain information related to an operation efficiency of the data union operation performed on the first type of physical unit according to the dispersion of the logical unit corresponding to the first data. For example, the memory management circuit 502 can obtain an evaluation value according to the dispersion of the logic unit corresponding to the first data. This evaluation value can be regarded as the logic distribution state information of the first kind of physical unit and is used to represent the dispersion. In an exemplary embodiment, the evaluation value may reflect the number of at least one table in which the access information of the first data is recorded. For example, this evaluation value may positively correlate to the number of tables. For example, the greater the number of the at least one table in which the access information of the first data is recorded, the greater the evaluation value may be. Alternatively, from another perspective, the memory management circuit 502 can obtain the evaluation value according to at least one table recorded with the access information of the first data.

In an example embodiment, the access information of the first data includes logical-to-physical mapping information of the first data. In an exemplary embodiment, the logical-to-physical mapping table stored in the system area 603 of fig. 6 may be divided into a plurality of sub-tables, and a table recorded with access information of the first data may refer to a sub-table of the logical-to-physical mapping table. Each sub-table of the logical-to-physical mapping table may record logical-to-physical mapping information of a plurality of consecutive logical units within a logical range.

In an exemplary embodiment, the dispersion of the logical units corresponding to the first data positively correlates to the number of the at least one table recorded with the logical-to-physical mapping information of the first data. For example, if the logical-to-physical mapping information of the first data is recorded in a plurality of sub-tables of the logical-to-physical mapping table, the dispersion of the logical units corresponding to the first data may positively correlate to the total number of the sub-tables.

In an exemplary embodiment, if the logic distribution status information of the first type physical unit reflects that the dispersion of the logic units corresponding to the first data is high (i.e. the logic units of the first data are distributed or discontinuous), the logic-to-physical mapping information of the logic units of the first data may be dispersedly recorded in the plurality of sub-tables. Therefore, when performing the data union operation on the first data, it may be necessary to perform a plurality of table access operations to load the sub-tables of the logical-to-physical mapping table into the buffer memory (e.g., the buffer memory 510 of fig. 5). The sub-table loaded into the buffer memory can be used to look up the access information of the first data. In this case, since the table access operation needs to be performed a plurality of times, normally performing the data merging operation on the first data (or the first type of physical unit) may cause the data merging operation to be inefficient.

Conversely, if the logical distribution state information of the first type physical unit reflects that the dispersion of the logical units corresponding to the first data is low (i.e. the logical units to which the first data belong are more concentrated or continuous), the logical-to-physical mapping information of the logical units to which the first data belong may be more concentrated and recorded in a few sub-tables. Therefore, when the data merging operation is performed on the first data, only a few table access operations may need to be performed to query the access information of the first data, so that the operation efficiency of the data merging operation is often high. Therefore, the operation efficiency of the data merging operation and the data writing stability of the memory storage device are not easy to control without considering the logic distribution state information of the first type physical unit and/or the table access operation which may need to be executed in the data merging operation.

FIG. 8 is a diagram illustrating physical units and corresponding logical distribution status information according to an exemplary embodiment of the present invention. Referring to FIG. 8, it is assumed that data 801 to 804 are stored in the physical unit 810(0), data 811 to 818 are stored in the physical unit 810(1), and the data 801 to 804 and 811 to 818 are valid data. The logical distribution status information 821(0) is the logical distribution status information of the physical unit 810 (0). The logical distribution status information 821(1) is logical distribution status information of the physical unit 810 (1). Each of tables 001-005 and 011-018 is a sub-table of a logical to physical mapping table.

According to the logic distribution status information 821(0), the logic-to-physical mapping information of at least one logic unit to which the

data

801, 803, and 804 belong is respectively recorded in the tables 001, 004, and 005, and the logic-to-physical mapping information of at least one logic unit to which the data 802 belongs is recorded in the tables 002 and 003. According to the logic distribution status information 821(0), in the data merging operation for the physical unit 810(0), 5 tables (i.e., tables 001-005) are loaded into the buffer memory to provide access information (e.g., logic-to-physical mapping information) of the data 801-804. For example, when the data 801 is copied to a recycling node, the table 001 is loaded into the buffer memory to obtain the physical unit 810(0) currently storing the data 801 according to the logical-to-physical mapping information corresponding to the data 801. In other words, the total number of tables 5 in the logic distribution status information 821(0) can be used to obtain the evaluation value corresponding to the physical unit 810(0) and can be used to indicate that at least 5 tables 001-005 need to be read when the data 801-804 are completely shifted or copied.

Similarly, according to the logic distribution status information 821(1), the logic-to-physical mapping information of the logic units to which the data 811-818 belong is respectively set in the tables 011-018. According to the logic distribution status information 821(1), in the data merging operation for the physical unit 810(1), at least N tables (i.e., tables 011-018, where N is greater than or equal to 8) are loaded into the buffer memory to provide at least the access information (e.g., the logic-to-physical mapping information) of the data 811-818. In other words, the total number N of tables in the logic distribution status information 821(1) can be used to obtain the evaluation value corresponding to the physical unit 810(1) and can be used to indicate that at least 8 tables 011-018 need to be read to completely move or copy the data 811-818.

It should be noted that the present invention does not limit the data content and format of the logic distribution status information. For example, in another exemplary embodiment of fig. 8, the logic distribution status information 821(0) may also only record the value 5 to provide the evaluation value corresponding to the physical unit 810(0), and/or the logic distribution status information 821(1) may also only record the value N to provide the evaluation value corresponding to the physical unit 810 (1). In an exemplary embodiment, the evaluation value (e.g., 5) corresponding to the physical unit 810(0) is smaller than the evaluation value (e.g., N) corresponding to the physical unit 810(1), which indicates that the dispersion of the logical units corresponding to the data 801-804 is lower than the dispersion of the logical units corresponding to the data 811-818.

In an exemplary embodiment, in response to a write command from the host system 11, the memory management circuit 502 performs at least one data union operation on at least one physical unit in the storage area 601 and/or the idle area 602 of fig. 6. In addition, the memory management circuit 502 adjusts the number of times of performing the data merging operation according to the dispersion of the logic unit corresponding to the first data.

In an exemplary embodiment, in response to a write command from the host system 11, the memory management circuit 502 instructs at least one access event corresponding to an event count value (also referred to as a first event count value) to be executed on at least one physical unit in the memory area 601 and the idle area 602 of fig. 6. For example, assuming that the first event counter value is M, M access events may be executed according to the first event counter value corresponding to one write instruction from the host system 11. After a write command is completed, additional M access events may be performed subsequently if a next write command is received from the host system 11. The parameter M (i.e., the first event count value) may be adjusted according to the dispersion of the logic units corresponding to the first data.

It should be noted that an access event may be any data access event performed in a data merge operation. For example, an access event may be a data read event, a data write event, a table read event, or other type of data access event. The data read event is used to read valid data from the source node. The data write event is used to write the collected valid data to the recycle node. The table read event is used to load at least a portion of information of a sub-table of the logical-to-physical mapping table into the buffer memory.

In an exemplary embodiment, the logical distribution state information of the first type physical unit may reflect an average of the evaluation values of the plurality of physical units. That is, the dispersion of the logical units corresponding to the first data may be an average dispersion of the logical units corresponding to the first data stored in the plurality of first-type physical units. Taking fig. 8 as an example, if the total number of the first type physical units (i.e., the physical units 810(0) and 810(1)) as the source node is 2, the logic distribution status information of the first type physical unit may include the evaluation value (5+ N)/2. The average value may be a weighted average or a median, and the present invention is not limited thereto.

In an exemplary embodiment, the first event count is positively correlated to the dispersion of the logic cells corresponding to the first data. Taking fig. 8 as an example, if the evaluation value (5+ N)/2 is larger, the obtained first event count value M may be larger. In an exemplary embodiment, the logic distribution state information (e.g., evaluation value) of the first type physical unit may be input to an algorithm or a look-up table. The first event count value may be obtained according to the output of this algorithm or look-up table.

In an example embodiment, the memory management circuit 502 may further obtain another event count value (also referred to as a second event count value) according to the dispersion of the logic units corresponding to the first data. The second event count value may reflect that, in a data merge operation performed on at least one first type physical unit as a source node, it is generally necessary to perform P access events to fill a single second type physical unit as a sink node with collected valid data. In an example embodiment, the memory management circuit 502 may input the logic distribution state information (e.g., evaluation value) of the first type of physical unit into an algorithm or a look-up table. A second event count value may be obtained based on the output of this algorithm or look-up table.

FIG. 9 is a diagram illustrating logic distribution status information and corresponding second event count values according to an example embodiment of the invention. Referring to fig. 9, in an exemplary embodiment, after obtaining the logic distribution status information (e.g., evaluation value) of the first type physical unit as the recycling node, according to the table information 910, if the evaluation value is greater than 2000 and less than 10000, the corresponding second event count value is 600; if the evaluation value is greater than 500 and less than 2000, a corresponding second event count value of 400 is obtained; if the evaluation value is greater than 100 and less than 500, a corresponding second event count value of 200 is obtained; if the evaluation value is less than 100, the corresponding second event count value is 100. Taking the scenario that the evaluation value is greater than 100 and less than 500 as an example, the obtained second event count value 200 may indicate that, in the data merging operation performed on the first type physical unit, approximately 200 access events need to be performed to fill up a single second type physical unit as a recycle node with the collected valid data.

In the example embodiment of fig. 9, the second event count value is positively correlated to the dispersion of the logic cells corresponding to the first data. For example, if the evaluation value corresponding to the first type physical unit is larger, the obtained second event count value is also larger.

In an example embodiment, the memory management circuit 502 may obtain the first event count value according to the second event count value. For example, in an exemplary embodiment, the second event count value may be input to an algorithm or a look-up table. The first event count value may be obtained according to the output of this algorithm or look-up table.

In an example embodiment, the memory management circuitry 502 may also obtain valid data storage information for the first type of physical unit. The valid data storage information reflects the storage state of the valid data in the first type physical unit. For example, the valid data storage information may reflect how much amount of valid data is stored in each of the plurality of physical units as the source node, or how much amount of valid data is stored in average in the plurality of physical units as the source node.

In an exemplary embodiment, the memory management circuit 502 may obtain the first event count value according to the dispersion of the logical unit corresponding to the first data and the valid data storage information of the first type of physical unit. For example, the memory management circuit 502 may obtain another event count value (also referred to as a third event count value) according to the second event count value and the valid data storage information of the first type of physical unit. The third event count value may reflect that, in a data merge operation performed on at least one first type physical unit as a source node, it is generally necessary to perform Q access events to free an additional second type physical unit (i.e., an idle physical unit). Wherein the value of Q is approximately equal to the value of P multiplied by the value of R. The parameter R represents that R physical units as recycle nodes need to be filled in the data merging operation performed on at least one first type physical unit as the source node to release an additional second type physical unit.

In an example embodiment, the memory management circuit 502 may obtain the parameter R according to the valid data storage information of the first type of physical unit. For example, assuming that valid data occupies 60%, 70%, and 70% of the storage space in 3 first-type physical units as recycle nodes, respectively, after 2 second-type physical units are filled with valid data collected from the 3 first-type physical units, the 3 first-type physical units may be erased and become new second-type physical units. In addition, the full 2 second type physical units become the new first type physical units. Therefore, after the 2 second type physical units are fully written, the total number of the second type physical units is increased by 1(3-2 is equal to 1). In this exemplary embodiment, the value of R is 2, which indicates that filling 2 physical units of the second type as recycle nodes can release an additional physical unit of the second type.

In an example embodiment, the memory management circuit 502 may obtain the first event count value according to the third event count value. For example, in an exemplary embodiment, the third event count value may be input to an algorithm or a look-up table. The first event count value may be obtained according to the output of this algorithm or look-up table.

In an example embodiment, the memory management circuit 502 may further obtain the number of the second type of physical units (i.e., idle physical units) in the rewritable nonvolatile memory module 406. Taking fig. 6 as an example, the number of the second type physical units is equal to the total number of the physical units 610(a +1) to 610(B) in the idle area 602. The memory management circuit 502 may obtain the first event count value according to the dispersion of the logical units corresponding to the first data, the valid data storage information of the first type of physical units, and the number of the second type of physical units.

In an exemplary embodiment, the operation modes of the data consolidation operation include at least two operation modes of a dynamic mode (also referred to as a first operation mode), a normal mode (also referred to as a second operation mode), and an emergency mode (also referred to as a third operation mode). The memory management circuit 502 may dynamically determine or adjust the operation mode of the data consolidation operation according to the number of the second type physical units.

FIG. 10 is a diagram illustrating an operation mode of a second type physical unit number and corresponding data merging operation according to an example embodiment of the present invention. Referring to fig. 10, in an exemplary embodiment, if the number of the current second type physical units is between 0 and the value Z, the operation mode of the data merging operation may be set to the emergency mode. If the number of the second type physical units is between the value Z and the value Y, the operation mode of the data merging operation can be set to the normal mode. If the number of the second type physical units is between the value Y and the value X, the operation mode of the data merging operation can be set to the dynamic mode. If the number of the second type physical units is larger than the value X, the data merging operation is not executed.

In an exemplary embodiment, the memory management circuit 502 may obtain the first event count value according to the dispersion of the logical units corresponding to the first data, the valid data storage information of the first type of physical units, and the operation mode of the current data merging operation. For example, memory management circuitry 502 may obtain a proportion information based on the operating mode in which the current data union is operating. The ratio information is used to control the switching ratio of the open block to the idle physical unit. The swap ratio of the open blocks to the idle physical units reflects that an additional second type physical unit needs to be released corresponding to the K open blocks being filled during the host write operation.

In an exemplary embodiment, if the operation mode of the current data consolidation operation is the dynamic mode, the parameter K may be determined as S, and the ratio information may reflect that the exchange ratio of the open blocks and the second type physical units is S to 1 (i.e., an additional second type physical unit needs to be released corresponding to filling up S open blocks). In addition, if the operation mode of the current data merging operation is the normal mode, the parameter K may be determined to be 1.

In an exemplary embodiment, if the operation mode of the current data merging operation is the dynamic mode, the memory management circuit 502 may further dynamically determine or adjust the parameter S according to the valid data storage information of the first type physical unit. For example, the memory management circuit 502 may determine whether the parameter R obtained from the valid data storage information of the first type of physical unit is greater than a predetermined value. If the parameter R is greater than the predetermined value, the memory management circuit 502 may set the parameter S to a value greater than 1, for example, 2 to 4. Conversely, if the parameter R is not greater than the predetermined value, the memory management circuit 502 may set the parameter S to 1.

In an exemplary embodiment, the memory management circuit 502 may obtain the first event count value according to the dispersion of the logical units corresponding to the first data, the valid data storage information of the first type of physical units, and the ratio information. In an example embodiment, the first event count value may also be obtained or adjusted according to the type of physical unit currently being an open block (i.e., SLC NAND type, MLC NAND type, or TLC NAND type). In an exemplary embodiment, the first event count value may also be obtained or adjusted according to the write data amount of a single write command or the average write data amount of a plurality of write commands from the host system 11.

The logic distribution state information of the first type physical unit is exemplified below to include the evaluation value 400. Based on the evaluation value 400, the table information 910 of fig. 9 may be queried, for example, to obtain a second event count value of 200. The second event count value reflects that under the current logical distribution of the first type of physical units, about 200 access events need to be performed to fill a single second type of physical unit as a recycle node with valid data collected from the first type of physical unit. The parameter R may be obtained based on the available data storage information of the first type of physical unit. The parameter R, for example, is 3, which reflects that 3 second-type physical units as recycling nodes need to be filled to release an additional second-type physical unit in the current valid data storage state of the first-type physical unit. Thus, the second event count value 200 may be multiplied by a parameter R, such as 3, to obtain a third event count value 600.

According to the number of the second type physical units and the valid data storage information of the first type physical units, the parameter K may be determined to be, for example, 1, which indicates that the exchange ratio of the open block and the second type physical units is 1 to 1. That is, during the host write operation, an additional physical unit of the second type needs to be released corresponding to filling up an open block.

Assuming that the physical unit as an open block belongs to the TLC NAND type flash memory, the capacity of one open block is about 72MB, and one write command from the host system 11 is used to instruct to store 1MB of data. Thus, the data stored as indicated by the 72(72/1 ═ 72) write commands available from the host system 11 can fill an open block. Then, dividing the third event count value 600 by 72 may result in a first event count value of about 9(600/72 — 8.333).

That is, in the foregoing example, during the period of synchronously performing the host write operation and the data merging operation, 9 access events can be correspondingly performed corresponding to one write command from the host system 11, so as to achieve the effect of enabling the swap ratio of the open block to the second type physical unit to be 1 to 1 and improving the data write stability of the memory storage device.

FIG. 11 is a flowchart illustrating a memory management method according to an exemplary embodiment of the invention. Referring to fig. 11, in step S1101, a data union operation is performed on at least one physical unit of the rewritable nonvolatile memory module corresponding to a write command from the host system. In step S1102, the number of times of performing the data merging operation is adjusted according to the dispersion of the plurality of logic units corresponding to the first data stored in the first type of physical unit in the rewritable nonvolatile memory module.

However, the steps in fig. 11 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 11 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 11 can be used with the above exemplary embodiments, or can be used alone, and the invention is not limited thereto.

In summary, the data union operation may be performed on at least one physical unit of the rewritable nonvolatile memory module corresponding to the write command from the host system. In addition, the number of times of executing the data merging operation can be adjusted according to the dispersion of the logic unit corresponding to the first data stored in the first type of physical unit in the rewritable nonvolatile memory module. In an exemplary embodiment, after considering the logically distributed state information (i.e., the dispersion) of the first type physical unit as the source node of the valid data, the obtained first event count value may be adjusted according to the expected execution times of the more time-consuming operations (e.g., table access operations) in the data consolidation operation, thereby effectively improving the data writing stability of the memory storage device.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, and various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A memory management method is used for a memory storage device comprising a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of physical units, at least one first type physical unit in the physical units stores first data, and the first data corresponds to a plurality of logical units, and the memory management method comprises the following steps:

performing at least one data union operation on at least one of the plurality of physical units corresponding to a write command from a host system; and

adjusting the number of times of executing the at least one data merging operation according to the dispersion of the plurality of logic units corresponding to the first data,

wherein the write instruction indicates that second data is stored, and the first data is different from the second data.

2. The memory management method of claim 1, wherein the dispersion of the plurality of logical units positively correlates to a number of at least one table in which logical-to-physical mapping information of the first data is recorded.

3. The memory management method of claim 1, wherein the step of performing the at least one data union operation on the at least one of the plurality of physical units corresponding to the write instruction from the host system comprises:

performing at least one access event on the at least one of the plurality of physical units corresponding to the write command from the host system,

wherein the at least one access event comprises at least one of a data read event, a data write event, and a table read event.

4. The memory management method of claim 1, wherein adjusting the number of times the at least one data union operation is performed according to the dispersion of the plurality of logical units corresponding to the first data comprises:

obtaining a first event count value according to the dispersion; and

adjusting a number of the at least one access event corresponding to the write instruction execution according to the first event counter value.

5. The memory management method according to claim 4, wherein the step of obtaining the first event count value from the dispersion includes:

obtaining the first event count value according to the dispersion and the valid data storage information of the at least one first type physical unit,

wherein the valid data storage information reflects a storage state of valid data in the at least one first type physical unit.

6. The memory management method of claim 5, wherein the step of obtaining the first event count value from the dispersion and the valid data storage information of the at least one first type of physical element comprises:

obtaining the first event count value according to the dispersion, the valid data storage information of the at least one first type of physical unit, and the number of at least one second type of physical unit among the plurality of physical units,

wherein the at least one second type of physical unit does not store the valid data.

7. The memory management method according to claim 4, wherein the step of obtaining the first event count value from the dispersion includes:

obtaining a second event count value according to the dispersion, wherein the second event count value corresponds to the number of at least one access event for fully writing a second type of physical unit in the plurality of physical units; and

and obtaining the first event count value according to the second event count value.

8. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

the system comprises a rewritable nonvolatile memory module, a first storage module and a second storage module, wherein the rewritable nonvolatile memory module comprises a plurality of physical units, at least one first type of physical unit in the physical units stores first data, and the first data corresponds to a plurality of logic units; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuitry unit is configured to instruct at least one data union operation to be performed on at least one of the plurality of physical units in response to a write command from the host system,

wherein the memory control circuit unit is further configured to adjust a number of times of performing the at least one data union operation according to a dispersion of the plurality of logic units corresponding to the first data,

9. The memory storage device of claim 8, wherein the dispersion of the plurality of logical cells positively correlates to a number of at least one table in which logical-to-physical mapping information of the first data is recorded.

10. The memory storage device of claim 8, wherein the operation of the memory control circuitry unit to perform the at least one data union operation on the at least one of the plurality of physical units corresponding to the write instruction from the host system comprises:

indicating, in response to the write command from the host system, to perform at least one access event on the at least one of the plurality of physical units,

11. The memory storage device according to claim 8, wherein the operation of the memory control circuit unit adjusting the number of times of performing the at least one data union operation according to the dispersion of the plurality of logic units corresponding to the first data comprises:

obtaining a first event count value according to the dispersion; and

12. The memory storage device according to claim 11, wherein the operation of the memory control circuit unit obtaining the first event count value according to the dispersion includes:

13. The memory storage device of claim 12, wherein the operation of the memory control circuit unit to obtain the first event count value from the dispersion and the valid data storage information of the at least one first type of physical unit comprises:

14. The memory storage device according to claim 11, wherein the operation of the memory control circuit unit obtaining the first event count value according to the dispersion includes:

15. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the memory control circuit unit comprises:

a host interface for connecting to a host system;

the memory interface is used for connecting to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of physical units, at least one first type physical unit in the physical units stores first data, and the first data corresponds to a plurality of logic units; and

a memory management circuit connected to the host interface and the memory interface,

wherein the memory management circuitry is to instruct, in response to a write instruction from the host system, at least one data union operation to be performed on at least one of the plurality of physical units,

wherein the memory management circuit is further configured to adjust a number of times of performing the at least one data union operation according to a dispersion of the plurality of logic units corresponding to the first data,

16. The memory control circuit unit according to claim 15, wherein the dispersion of the plurality of logic units positively correlates with the number of at least one table in which logical-to-physical mapping information of the first data is recorded.

17. The memory control circuitry unit of claim 15, wherein the operation of the memory management circuitry to perform the at least one data union operation on the at least one of the plurality of physical units corresponding to the write instruction from the host system comprises:

18. The memory control circuit unit of claim 15, wherein the operation of the memory management circuit adjusting the number of times of performing the at least one data union operation according to the dispersion of the plurality of logic units corresponding to the first data comprises:

obtaining a first event count value according to the dispersion; and

19. The memory control circuit unit according to claim 18, wherein the operation of the memory management circuit obtaining the first event count value according to the dispersion includes:

20. The memory control circuit unit of claim 19, wherein the operation of the memory management circuit obtaining the first event count value from the dispersion and the valid data storage information of the at least one first type of physical unit comprises:

21. The memory control circuit unit according to claim 18, wherein the operation of the memory management circuit obtaining the first event count value according to the dispersion includes: