CN110879793B

CN110879793B - Memory management method, memory storage device and memory control circuit unit

Info

Publication number: CN110879793B
Application number: CN201811032033.9A
Authority: CN
Inventors: 叶志刚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2018-09-05
Filing date: 2018-09-05
Publication date: 2021-09-14
Anticipated expiration: 2038-09-05
Also published as: CN110879793A

Abstract

An exemplary embodiment of the present invention provides a memory management method, a memory storage device and a memory control circuit unit for a rewritable nonvolatile memory module, wherein the memory management method comprises: performing a host write operation to receive a write command from a host system and store first data corresponding to the write command to a first physical unit; recording first update data corresponding to the host write operation; performing data union operation to read the second data from the second physical unit and store the second data to the third physical unit; recording second updating data corresponding to the data integration operation; and reading the management information from the rewritable nonvolatile memory module to the buffer memory according to the first updating data and the second updating data and updating the management information in the buffer memory.

Description

Memory management method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a memory management technology, and more particularly, to a memory management method, a memory storage device, and a memory control circuit unit.

Background

Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.

When the number of free physical units of the memory storage device is insufficient, the stored valid data can be generally collected and freed up by the garbage collection program. When executing the garbage collection program, management information such as a logical-to-physical mapping table stored in the rewritable non-volatile memory module may be frequently accessed and modified. In addition, when a host write operation is performed to store data from the host system, management information such as a logical-to-physical mapping table stored in the rewritable nonvolatile memory module may also be frequently accessed and modified, thereby accelerating wear of the rewritable nonvolatile memory module (e.g., increasing write amplification of data).

Disclosure of Invention

The invention provides a memory management method, a memory storage device and a memory management circuit, which can effectively reduce the access times of a rewritable nonvolatile memory module.

An exemplary embodiment of the present invention provides a memory management method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units. The memory management method comprises the following steps: performing a host write operation to receive a write command from a host system and store first data corresponding to the write command to a first one of the physical units; recording first update data corresponding to the host write operation; performing a data union operation to read second data from a second one of the physical units and store the second data to a third one of the physical units; recording second updating data corresponding to the data integration operation; and reading management information from the rewritable nonvolatile memory module to a buffer memory according to the first updating data and the second updating data, and updating the management information in the buffer memory.

In an exemplary embodiment of the invention, the step of reading the management information from the rewritable non-volatile memory module to the buffer memory according to the first update data and the second update data and updating the management information in the buffer memory includes: and responding to the recorded first updating data meeting a preset condition, reading the management information from the rewritable nonvolatile memory module to the buffer memory according to the first updating data and the second updating data, and updating the management information in the buffer memory.

In an exemplary embodiment of the invention, the memory management method further includes: and in response to the data volume of the recorded first updating data not being less than a preset data volume, determining that the recorded first updating data meets the preset condition.

In an exemplary embodiment of the invention, the memory management method further includes: and continuously temporarily storing the second updating data in the buffer memory before the management information is read to the buffer memory according to the first updating data and the second updating data, and not reading the management information according to the second updating data.

In an exemplary embodiment of the invention, the step of reading the management information from the rewritable non-volatile memory module to the buffer memory according to the first update data and the second update data and updating the management information in the buffer memory includes: and updating the logical-to-physical mapping information according to the first updating data and the second updating data.

In an exemplary embodiment of the invention, the memory management method further includes: storing the updated management information to the rewritable non-volatile memory module; and clearing the first update data and the second update data in the buffer memory.

In an exemplary embodiment of the invention, the memory management method further includes: obtaining sub-update data corresponding to the same logic unit in the first update data and the second update data; and updating the management information according to the latest data in the sub-update data.

In an exemplary embodiment of the invention, the memory management method further includes: and judging whether at least one of the first updating data and the second updating data exists in the buffer memory.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is configured to perform a host write operation to receive a write command from the host system and to instruct storage of first data corresponding to the write command to a first one of the physical units. The memory control circuitry unit is also to record first update data corresponding to the host write operation. The memory control circuit unit is further configured to perform a data union operation to instruct reading of second data from a second one of the physical units and storing of the second data to a third one of the physical units. The memory control circuit unit is further used for recording second updating data corresponding to the data merging operation. The memory control circuit unit is further configured to read management information from the rewritable nonvolatile memory module to a buffer memory according to the first update data and the second update data, and update the management information in the buffer memory.

In an exemplary embodiment of the invention, the operation of the memory control circuit unit reading the management information from the rewritable non-volatile memory module to the buffer memory according to the first update data and the second update data and updating the management information in the buffer memory includes: and responding to the recorded first updating data meeting a preset condition, reading the management information from the rewritable nonvolatile memory module to the buffer memory according to the first updating data and the second updating data, and updating the management information in the buffer memory.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to determine that the recorded first update data meets the preset condition in response to that a data amount of the recorded first update data is not less than a preset data amount.

In an exemplary embodiment of the invention, before the management information is read to the buffer memory according to the first update data and the second update data, the memory control circuit unit is further configured to continuously temporarily store the second update data in the buffer memory, and not read the management information according to the second update data.

In an exemplary embodiment of the invention, the operation of the memory control circuit unit reading the management information from the rewritable non-volatile memory module to the buffer memory according to the first update data and the second update data and updating the management information in the buffer memory includes: and updating the logical-to-physical mapping information according to the first updating data and the second updating data.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to store the updated management information to the rewritable non-volatile memory module. The memory control circuit unit is further configured to clear the first update data and the second update data in the buffer memory.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to obtain sub-update data corresponding to the same logic unit in the first update data and the second update data. The memory control circuit unit is further configured to update the management information according to the latest data of the sub-update data.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to determine whether at least one of the first update data and the second update data exists in the buffer memory.

An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of physical units. The memory control circuit unit comprises a host interface, a memory interface, a buffer memory and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuit is connected to the host interface, the memory interface, and the buffer memory. The memory management circuit is configured to perform a host write operation to receive a write command from the host system and to instruct storage of first data corresponding to the write command to a first one of the physical units. The memory management circuitry is also to record first update data corresponding to the host write operation. The memory management circuit is further configured to perform a data union operation to instruct reading of second data from a second one of the physical units and storing of the second data to a third one of the physical units. The memory management circuit is further configured to record second update data corresponding to the data union operation. The memory management circuit is further used for reading management information from the rewritable nonvolatile memory module to the buffer memory according to the first updating data and the second updating data and updating the management information in the buffer memory.

In an exemplary embodiment of the invention, the operations of the memory management circuit reading the management information from the rewritable non-volatile memory module to the buffer memory according to the first update data and the second update data and updating the management information in the buffer memory include: and responding to the recorded first updating data meeting a preset condition, reading the management information from the rewritable nonvolatile memory module to the buffer memory according to the first updating data and the second updating data, and updating the management information in the buffer memory.

In an exemplary embodiment of the invention, the memory management circuit is further configured to determine that the recorded first update data meets the predetermined condition in response to a data amount of the recorded first update data not being less than a predetermined data amount.

In an exemplary embodiment of the invention, before the management information is read to the buffer memory according to the first update data and the second update data, the memory management circuit is further configured to continuously temporarily store the second update data in the buffer memory, and not read the management information according to the second update data.

In an example embodiment of the present invention, the first update data includes mapping information related to a first logical unit, the second update data includes mapping information related to a second logical unit, the first logical unit is mapped to the first physical unit, and the second logical unit is mapped to the third physical unit.

In an exemplary embodiment of the invention, the operations of the memory management circuit reading the management information from the rewritable non-volatile memory module to the buffer memory according to the first update data and the second update data and updating the management information in the buffer memory include: and updating the logical-to-physical mapping information according to the first updating data and the second updating data.

In an exemplary embodiment of the invention, the memory management circuit is further configured to store updated management information to the rewritable non-volatile memory module. The memory management circuit is also used for clearing the first updating data and the second updating data in the buffer memory.

In an exemplary embodiment of the invention, the memory management circuit is further configured to obtain sub-update data corresponding to the same logical unit in the first update data and the second update data. The memory management circuit is further configured to update the management information according to the latest data in the sub-update data.

In an exemplary embodiment of the invention, the memory management circuit is further configured to determine whether at least one of the first update data and the second update data exists in the buffer memory.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is configured to perform a first write operation, wherein the first write operation includes one of an operation of storing first data received from the host system to a first one of the physical units and an operation of writing second data stored in a second one of the physical units to a third one of the physical units. The memory control circuit unit is also used for recording first updating data corresponding to the first writing operation. The memory control circuit unit is further configured to determine whether there is second update data, the second update data being generated based on a second write operation, and the second write operation including the other of the operation of storing the first data to the first physical unit and the operation of writing the second data to the third physical unit. The memory control circuit unit is further configured to read management information from the rewritable nonvolatile memory module to a buffer memory according to the first update data and the second update data, and update the management information in the buffer memory.

Based on the above, the first update data and the second update data can be recorded corresponding to the executed host write operation and the data merge operation, respectively. After a certain time point, according to the first update data and the second update data, management information can be read from the rewritable nonvolatile memory module to a buffer memory and updated in the buffer memory. Therefore, the access times of the rewritable nonvolatile memory module can be effectively reduced, and the service life of the rewritable nonvolatile memory module is further prolonged.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention.

FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.

FIG. 3 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention.

FIG. 7 is a diagram illustrating a host write operation and a data merge operation according to an exemplary embodiment of the invention.

FIG. 8 is a diagram illustrating recording of update data according to an exemplary embodiment of the invention.

FIG. 9 is a diagram illustrating recording of update data and update management information according to an exemplary embodiment of the invention.

FIG. 10 is a flowchart illustrating a memory management method according to an exemplary embodiment of the invention.

FIG. 11 is a flowchart illustrating a memory management method according to an exemplary embodiment of the invention.

FIG. 12 is a flowchart illustrating a memory management method according to an exemplary embodiment of the invention.

Description of the reference numerals

10. 30: memory storage device

11. 31: host system

110: system bus

111: processor with a memory having a plurality of memory cells

112: random access memory

113: read-only memory

114: data transmission interface

12: input/output (I/O) device

20: main machine board

201: u disk

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network interface card

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

32: SD card

33: CF card

34: embedded memory device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

502: memory management circuit

504: host interface

506: memory interface

508: error checking and correcting circuit

510: buffer memory

512: power management circuit

601: storage area

602: idle zone

603: system area

610(0) - (610 (C), 710(0), 721(0) - (721 (E), 731(0) - (731) (F): physical unit

612(0) to 612 (D): logic unit

701. 702: data of

720: source node

730: recovery node

801. 802(1) -802 (N), 803: data of

S1001: step (executing a host write operation to receive a write command from a host system and store first data corresponding to the write command to a first physical unit)

S1002: step (recording first update data corresponding to the host write operation)

S1003: step (performing a data union operation to read the second data from the second physical unit and store the second data to the third physical unit)

S1004: step (recording second update data corresponding to the data union operation)

S1005: step (reading management information from a rewritable nonvolatile memory module to a buffer memory according to the first update data and the second update data and updating the management information in the buffer memory)

S1101: step (executing a host write operation to receive a write command from a host system and store first data corresponding to the write command to a first physical unit)

S1102: step (recording first update data corresponding to the host write operation)

S1103: step (performing a data union operation to read the second data from the second physical unit and store the second data to the third physical unit)

S1104: step (recording second update data corresponding to the data union operation)

S1105: step (judging whether the first updating data meets the preset condition)

S1106: step (reading management information from a rewritable nonvolatile memory module to a buffer memory according to the first update data and the second update data and updating the management information in the buffer memory)

S1107: storing the updated management information in a rewritable nonvolatile memory module and clearing the first update data and the second update data in the buffer memory

S1201: step (executing the first write operation)

S1202: step (recording first update data corresponding to the first write operation)

S1203: step (judging whether there is second update data)

S1204: step (reading management information from a rewritable nonvolatile memory module to a buffer memory according to the first update data and the second update data and updating the management information in the buffer memory)

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all connected to a system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. The host system 11 is connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be connected to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, Bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded memory device 34 includes various types of embedded memory devices such as an embedded multimedia Card (eMMC) 341 and/or an embedded Multi-Chip Package (eMCP) memory device 342, which directly connects the memory module to the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11. In the exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed Specification-I (UHS-I) interface standard, the Ultra High Speed Specification-II (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Memory (Flash) interface standard, the CF interface standard, the Device interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.

In the exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical programming cells, and the physical programming cells form a plurality of physical erasing cells. Specifically, the memory cells on the same word line constitute one or more physical programming cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.

In the exemplary embodiment, the physical program cell is a minimum cell to be programmed. That is, the physical programming unit is the smallest unit for writing data. For example, a physical program unit is a physical page (page) or a physical fan (sector). If the physical program units are physical pages, the physical program units usually include a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, 8, 16, or a greater or lesser number of physical fans may be included in the data bit region, and the size of each physical fan may also be greater or lesser. On the other hand, the physical erase cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, a physical erase unit is a physical block (block).

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.

In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 502 may also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is connected to the memory management circuit 502 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transfer standard.

The memory interface 506 is connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

In an exemplary embodiment, the memory control circuitry 404 further includes error checking and correction circuitry 508, buffer memory 510, and power management circuitry 512.

The error checking and correcting circuit 508 is connected to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.

The buffer memory 510 is connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is connected to the memory management circuit 502 and is used to control the power of the memory storage device 10.

In an example embodiment, the rewritable non-volatile memory module 406 of fig. 4 is also referred to as a flash (flash) memory module, the memory control circuit unit 404 is also referred to as a flash memory controller for controlling the flash memory module, and/or the memory management circuit 502 of fig. 5 is also referred to as a flash memory management circuit.

Referring to FIG. 6, the memory management circuit 502 logically groups the physical units 610(0) -610 (C) of the rewritable nonvolatile memory module 406 into a storage area 601, an idle (spare) area 602, and a system area 603. The physical units 610(0) to 610(a) in the storage area 601 store data (for example, user data from the host system 11 in fig. 1). For example, physical locations 610(0) -610 (A) in memory area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610(a +1) to 610(B) in the idle region 602 are not yet used to store data (e.g., valid data). The physical units 610(B +1) to 610(C) in the storage area 603 are used to store management information (also referred to as system data), such as a logical-to-physical mapping table, a bad block management table, a device model, or other types of management information.

When data is to be stored, the memory management circuit 502 selects one physical unit from the physical units 610(a +1) to 610(B) of the idle area 602 and stores data from the host system 11 or at least one physical unit in the storage area 601 into the selected physical unit. At the same time, the selected physical unit will be associated to the memory area 601. In addition, after erasing a physical unit in the storage area 601, the erased physical unit is re-associated with the idle area 602.

In the exemplary embodiment, each physical unit belonging to the memory area 601 is also referred to as a non-idle (non-spare) physical unit, and each physical unit belonging to the idle area 602 is also referred to as an idle physical unit. In the present exemplary embodiment, one physical cell refers to one physical erase cell. However, in another exemplary embodiment, one physical unit may also include a plurality of physical erase units.

The memory management circuitry 502 configures the logical units 612(0) - (612 (D) to map the physical units 610(0) - (610 (A) in the memory area 601. In the present exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logic cell may also refer to a logic program cell, a logic erase cell or be composed of a plurality of continuous or discontinuous logic addresses. In addition, each of the logical units 612(0) -612 (D) may be mapped to one or more physical units. It should be noted that, in an exemplary embodiment, the memory management circuit 502 may not configure the logical unit mapped to the system area 603 to prevent the management information stored in the system area 603 from being modified by the user.

The memory management circuit 502 records the mapping relationship between the logical units and the physical units (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table. The logical to physical mapping table is stored in a physical unit of the system area 603. When the host system 11 is going to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access operations with respect to the memory storage device 10 according to the logical-to-physical mapping table.

In the exemplary embodiment, the valid data is the latest data belonging to a logical unit, and the invalid data is not the latest data belonging to any logical unit. For example, if the host system 11 stores a new data item in a logical unit to overwrite the old data originally stored in the logical unit (i.e. update the data belonging to the logical unit), the new data item stored in the storage area 601 is the latest data belonging to the logical unit and will be marked as valid, and the overwritten old data item may still be stored in the storage area 601 but marked as invalid.

In the exemplary embodiment, if the data belonging to a logical unit is updated, the mapping relationship between the logical unit and the physical unit storing the old data belonging to the logical unit is removed, and the mapping relationship between the logical unit and the physical unit storing the latest data belonging to the logical unit is established. However, in another exemplary embodiment, if the data belonging to a logical unit is updated, the mapping relationship between the logical unit and the physical unit storing the old data belonging to the logical unit can still be maintained.

When the memory storage device 10 is shipped from a factory, the total number of physical units belonging to the idle area 602 is a preset number (e.g., 30). In operation of memory storage device 10, more and more physical units are selected from idle region 602 and associated with storage region 601 to store data (e.g., user data from host system 11). Therefore, the total number of physical units belonging to the idle region 602 gradually decreases as the memory storage device 10 is used.

During operation of the memory storage device 10, the memory management circuit 502 continuously updates the total number of physical units belonging to the idle region 602. The memory management circuit 502 performs the data union operation according to the number of physical units in the idle region 602 (i.e., the total number of idle physical units). For example, the memory management circuit 502 can determine whether the total number of physical units belonging to the idle region 602 is less than or equal to a threshold (also referred to as a first threshold). The first threshold value is, for example, a value of 2 or more (e.g., 10), but the invention is not limited thereto. If the total number of physical units belonging to the idle region 602 is less than or equal to the first threshold, the memory management circuit 502 may perform a data union operation. In an example embodiment, the data consolidation operation is also referred to as a garbage collection (garbel collection) operation.

In a data union operation, memory management circuitry 502 may select at least one physical unit (also referred to as a source node) from memory area 601 and attempt to copy valid data from the selected physical unit to another physical unit (also referred to as a recycle node). The physical unit for storing the copied valid data is selected from the idle area 602 and is associated with the storage area 601. If all valid data stored in a physical unit has been copied to the recycle node, the physical unit may be erased and associated with the idle region 602. In an exemplary embodiment, the operation of re-associating a physical unit from the memory area 601 back to the idle area 602 (or the operation of erasing a physical unit) is also referred to as releasing an idle physical unit. By performing the data union operation, one or more idle physical units are released and the total number of physical units belonging to the idle region 602 is gradually increased.

After the completion operation is started, if the physical units belonging to the idle area 602 satisfy a specific condition, the completion operation is stopped. For example, the memory management circuit 502 can determine whether the total number of physical units belonging to the idle region 602 is greater than or equal to a threshold (hereinafter also referred to as a second threshold). For example, the second threshold value may be greater than or equal to the first threshold value. If the total number of physical units belonging to the idle region 602 is greater than or equal to the second threshold, the memory management circuit 502 may stop the data rounding operation. It should be noted that stopping the data merging operation refers to ending the currently executing data merging operation. After stopping a data union operation, if the total number of physical units belonging to the idle region 602 is again less than or equal to the first threshold, a next data union operation may be performed again to attempt to release a new idle physical unit.

Referring to fig. 7, in a host write operation, the host system 11 sends at least one write command to instruct a logic unit (also referred to as a first logic unit) to write data 701 (also referred to as a first data). According to the write command, the data 701 is stored in the physical unit 710(0) (also referred to as the first physical unit) mapped to the first logical unit. For example, the physical unit 710(0) may be selected from the idle region 602 of fig. 6. In an example embodiment, the physical unit 710(0) currently used to store data 701 from the host system 11 is also referred to as an open block (open block) or host write block. It should be noted that, in another exemplary embodiment, an open block or a host write block may also include a plurality of physical units.

During the execution of the host write operation, a data union operation may be performed. Alternatively, the host write operation may be performed during the time that the data union operation is performed. In the data merge operation, data 702 (also referred to as second data) belonging to at least one logical unit (also referred to as second logical unit) may be collected from physical units 721(0) -721 (E) (also referred to as second physical unit) belonging to the source node 720 and written to physical units 731(0) -731 (F) (also referred to as third physical unit) belonging to the sink node 730. The data 702 includes valid data, and the second logical unit can be mapped to physical units 731(0) -731 (F). Physical units 721(0) -721 (E) belonging to the source node 720 are selected from the storage area 601 of FIG. 6, and physical units 731(0) -731 (F) belonging to the sink node 730 are selected from the free area 602 of FIG. 6. In an example embodiment, physical units 721(0) -721 (E) are the E +1 physical units that store the least significant data in memory 601 of FIG. 6. In an exemplary embodiment, the physical units 721(0) -721 (E) are selected from the memory 601 of FIG. 6 according to other rules, which are not intended to limit the present invention.

Referring to fig. 7 and 8, according to the host write operation performed, the memory management circuit 502 may record data 801 into the buffer memory 510. Data 801 includes mapping information relating to a logical unit to which data 701 belongs (i.e., a first logical unit). For example, data 801 may include physical-to-logical mapping information corresponding to data 701, which reflects a mapping of physical unit 710(0) to a first logical unit. Based on the data union operation performed, the memory management circuit 502 may record the data 802(1) and 802(2) to the buffer memory 510. Data 802(1) and 802(2) include mapping information relating to the logical unit (i.e., the second logical unit) to which data 702 belongs. For example, the data 802(1) and 802(2) may include physical-to-logical mapping information corresponding to the data 702, which reflects the mapping relationship between the physical unit 731(0) and the second logical unit.

Referring to fig. 7 to 9, according to the host write operation continuously performed in the exemplary embodiment of fig. 7, the memory management circuit 502 can continuously temporarily store the data 801 in the buffer memory 510, and the data amount of the data 801 gradually increases. In addition, according to the data merging operation continuously performed in the example embodiment of fig. 7, the memory management circuit 502 may continuously buffer the data 802(1) -802 (N) into the buffer memory 510, and the data amount of the data 802(1) -802 (N) is larger than the data amount of the data 802(1) and 802(2) in the example embodiment of fig. 8. For example, data 802(1) and 802(2) may reflect that a portion of data in data 702 is stored to physical unit 731(0), while data 802(N) may reflect that another portion of data in data 702 is stored to physical unit 731 (F).

After a certain time point (also referred to as a first time point), the memory management circuit 502 can read the data 803 from the rewritable nonvolatile memory module 406 to the buffer memory 510 according to the instructions of the data 801 and 802(1) -802 (N). For example, the data 803 may include management information stored by the system area 603 of fig. 6. Then, the memory management circuit 502 can update the data 803 in the buffer memory 510 according to the data 801 and 802(1) to 802 (N). For example, the memory management circuit 502 may update the logical-to-physical mapping information described in the logical-to-physical mapping table in the system area 603 of fig. 6 according to the physical-to-logical mapping information of the data 801 and 802(1) to 802 (N). The updated data 803 may reflect the mapping relationship between the physical unit 710(0) and the first logical unit to which the data 701 belongs and the mapping relationship between the physical units 731(0) -731 (F) and the second logical unit to which the data 702 belongs in the example embodiment of fig. 7.

The memory management circuit 502 can instruct the storage of the updated data 803 to the rewritable nonvolatile memory module 406 (e.g., the system area 603 in FIG. 6) and clear the data 801 and 802(1) -802 (N) in the buffer memory 510. After storing the updated data 803 to the rewritable nonvolatile memory module 406, the memory management circuit 502 can access the stored data (i.e., the data 701 and 702) of the physical units 710(0) and 731(0) to 731(F) according to the updated data 803 (i.e., the updated management information in the rewritable nonvolatile memory module 406).

Viewed from another perspective, in the example embodiment of fig. 8, before the first time point, the memory management circuit 502 keeps temporarily storing the data 801, 802(1), and 802(2) in the buffer memory 510, and temporarily does not read the management information (e.g., the data 803) from the rewritable nonvolatile memory module 406 according to the data 801, 802(1), and 802 (2). In the example embodiment of fig. 8, prior to the first point in time, the memory management circuitry 502 may inhibit reading of management information (e.g., the data 803) based on any of the data 801, 802(1), and 802 (2).

In the example embodiment of fig. 8, if the management information is read and updated from the rewritable nonvolatile memory module 406 only according to 802(1) and/or 802(2), each time the management information is read, the management information is worn out by the rewritable nonvolatile memory module 406 or the memory unit storing the management information. However, in the exemplary embodiment of fig. 9, after the first time point, the management information (i.e., the data 803) is read from the rewritable nonvolatile memory module 406 and updated in the buffer memory 510 according to the data 801 and 802(1) to 802(N), which can effectively reduce the number of accesses to the rewritable nonvolatile memory module 406 and further prolong the lifetime of the rewritable nonvolatile memory module 406.

In an exemplary embodiment, the memory management circuit 502 may determine whether the data 801 in the buffer memory 510 meets a predetermined condition. Taking fig. 8 as an example, if the data 801 in the buffer memory 510 does not meet the predetermined condition, the memory management circuit 502 may keep the data 801, 802(1), and 802(2) temporarily stored in the buffer memory 510 and temporarily not read the management information (e.g., the data 803) from the rewritable nonvolatile memory module 406 according to the data 801, 802(1), and 802 (2). Alternatively, taking fig. 9 as an example, if the data 801 in the buffer memory 510 meets the predetermined condition, the memory management circuit 502 may instruct the data 803 to be read from the rewritable nonvolatile memory module 406 to the buffer memory 510 at one time and update the data 803 according to the data 801 and 802(1) -802 (N). In other words, the memory management circuit 502 can read and update the data 803 in response to the data 801 in the buffer memory 510 meeting the preset condition. Further, the first time point may be any time point after the memory management circuit 502 determines that the data 801 in the buffer memory 510 meets the preset condition.

In an exemplary embodiment, the memory management circuit 502 can determine whether the data amount of the data 801 in the buffer memory 510 is not less than (i.e., equal to or greater than) a predetermined data amount. If the data size of the data 801 in the buffer memory 510 is smaller than the predetermined data size, the memory management circuit 502 may determine that the data 801 does not satisfy the predetermined condition. On the other hand, if the data amount of the data 801 in the buffer 510 is not less than the predetermined data amount, the memory management circuit 502 may determine that the data 801 meets the predetermined condition. In other words, the memory management circuit 502 may determine that the data 801 meets the predetermined condition and then read and update the data 803 in response to the data amount of the data 801 in the buffer memory 510 not being less than the predetermined data amount.

In an exemplary embodiment, the memory management circuit 502 may determine whether the data 801 and the data 802(1) -802 (N) in the buffer memory 510 describe mapping information associated with the same logical unit (also referred to as sub-update data corresponding to the same logical unit). When the data 801 and the data 802(1) to 802(N) in the buffer memory 510 describe the same mapping information on the logical unit, the memory management circuit 502 can invalidate at least part of the information in the data 802(1) to 802 (N). For example, assuming that both data 801 and data 802(1) include mapping information associated with logical unit 612(0) of FIG. 6, memory management circuitry 502 may save mapping information associated with logical unit 612(0) in data 801 and invalidate mapping information associated with logical unit 612(0) in data 802 (1). In addition, the memory management circuit 502 may delete or ignore at least some of the same information in the data 802(1) to 802 (N). This reduces the total data amount of the data 801 and the data 802(1) to 802(N) and avoids the data 803 from being repeatedly updated based on the same information.

In an exemplary embodiment, the memory management circuit 502 may obtain the mapping information between the data 801 in the buffer memory 510 and the same logical unit (i.e., the sub-update data corresponding to the same logical unit) in the data 802(1) -802 (N). Then, the memory management circuit 502 can read and update the data 803 according to the latest data among the sub update data. For example, the memory management circuit 502 may compare the data 801 in the buffer memory 510 with the data 802(1) to 802(N) or compare the data 801 in the buffer memory 510 with at least one of the data 802(1) to 802(N) to determine whether the data 801 and the data 802(1) to 802(N) in the buffer memory 510 include mapping information relating to the same logical cell. Assuming that both data 801 and data 802(1) comprise mapping information associated with logic 612(0) of FIG. 6, memory management circuitry 502 may determine that data 801 is newer or data 802(1) is newer. If the data 801 is newer, the memory management circuit 502 may update the mapping information related to the logic unit 612(0) in the data 803 according to the data 801 only. Alternatively, if the data 802(1) is newer, the memory management circuit 502 may update the mapping information related to the logic unit 612(0) in the data 803 according to the data 802(1) only.

In an example embodiment, the memory management circuit 502 may determine whether the first update data and/or the second update data exists in the buffer memory 510. The first update data includes update data generated based on one of a host write operation and a data union operation. The second update data includes update data generated based on another one of the host write operation and the data union operation. For example, the update data generated based on the host write operation includes data 801, and the update data generated based on the data union operation includes data 802(1) -802 (N).

In an exemplary embodiment, if one of the first update data and the second update data exists in the buffer memory 510 (i.e., one of the first update data and the second update data is temporarily stored in the buffer memory 510), the memory management circuit 502 may determine whether the other of the first update data and the second update data exists in the buffer memory 510. In an exemplary embodiment, if only one of the first update data and the second update data (e.g., only the data 801 or 802(1)) exists in the buffer memory 510, the buffer memory 510 may temporarily not read and update the management information according to the one of the first update data and the second update data. For example, the memory management circuit 502 may keep the one of the first update data and the second update data in the buffer memory 510. In an exemplary embodiment, if the first update data and the second update data exist in the buffer memory 510 at the same time, the memory management circuit 502 can read and update the management information (e.g., the data 803) according to the first update data and the second update data, and the operation details can be found in the exemplary embodiment of fig. 9.

Referring to fig. 10, in step S1001, a host write operation is performed to receive a write command from a host system and store first data corresponding to the write command in a first physical unit. In step S1002, first update data corresponding to the host write operation is recorded. In step S1003, a data union operation is performed to read the second data from the second physical unit and store the second data to the third physical unit. In step S1004, second update data corresponding to the data union operation is recorded. In step S1005, management information is read from the rewritable nonvolatile memory module to a buffer memory according to the first update data and the second update data, and the management information is updated in the buffer memory.

In step S1101, a host write operation is performed to receive a write instruction from a host system and store first data corresponding to the write instruction to a first physical unit. In step S1102, first update data corresponding to the host write operation is recorded. In step S1103, a data union operation is performed to read the second data from the second physical unit and store the second data to the third physical unit. In step S1104, second update data corresponding to the data union operation is recorded. In step S1105, it is determined whether the first update data meets a preset condition. If the first update data meets the predetermined condition, in step S1106, the management information is read from the rewritable nonvolatile memory module to the buffer memory according to the first update data and the second update data, and the management information is updated in the buffer memory. In step S1107, the updated management information is stored in the rewritable nonvolatile memory module and the first update data and the second update data are cleared in the buffer memory. If the determination in step S1105 is no, steps S1101 to S1104 may be repeatedly executed.

It should be noted that the present invention does not limit the execution sequence of steps S1001 to S1004 in fig. 10 and steps S1101 to S1104 in fig. 11. For example, in another exemplary embodiment of fig. 10, steps S1003 and S1004 may be performed before steps S1001 and S1002 or simultaneously with steps S1001 and S1002, and/or in another exemplary embodiment of fig. 11, steps S1103 and S1104 may be performed before steps S1101 and S1102 or simultaneously with steps S1101 and S1102.

Referring to fig. 12, in step S1201, a first write operation is performed. The first write operation includes one of an operation of storing first data received from the host system to the first physical unit (i.e., a host write operation) and an operation of writing second data stored in the second physical unit to the third physical unit (i.e., a data union operation). In step S1202, first update data corresponding to a first write operation is recorded. For example, the first update data is generated based on the first write operation and may be buffered in the buffer memory. In step S1203, it is determined whether or not second update data exists. The second update data is generated based on the second write operation and may be buffered in the buffer memory. The first write operation is different from the second write operation. For example, the second write operation includes the other of an operation of storing the first data received from the host system to the first physical unit (i.e., a host write operation) and an operation of writing the second data stored in the second physical unit to the third physical unit (i.e., a data union operation). For example, in one exemplary embodiment, the first write operation is a host write operation, and the second write operation may be a data union operation. Alternatively, in an exemplary embodiment, the first write operation is a data union operation, and the second write operation may be a host write operation.

If the second update data exists, in step S1204, the management information is read from the rewritable nonvolatile memory module to the buffer memory according to the first update data and the second update data, and the management information is updated in the buffer memory. However, if the second update data does not exist, for example, the first update data but the second update data exist in the buffer memory, the step S1201 may be returned to continue to perform the first write operation and/or the second write operation.

However, the steps in fig. 10 to 12 have been described in detail above, and are not repeated herein. It is to be noted that, the steps in fig. 10 to fig. 12 can be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the methods of fig. 10 to 12 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.

In summary, the first update data and the second update data can be recorded respectively corresponding to the host write operation and the data merge operation. After the first time point, according to the first update data and the second update data, the management information can be read from the rewritable nonvolatile memory module to the buffer memory and updated in the buffer memory. In an exemplary embodiment, the management information is read into the buffer memory for updating only when the management information needs to be updated according to the first update data (e.g., the first update data meets a predetermined condition). In an exemplary embodiment, if the buffer memory has the second update data but the first update data does not meet the predetermined condition, the management information is not read into the buffer memory for updating. In an exemplary embodiment, the management information is read into the buffer memory for updating only when the first update data and the second update data exist in the buffer memory at the same time. Therefore, the access times of the rewritable nonvolatile memory module can be effectively reduced, and the service life of the rewritable nonvolatile memory module can be further prolonged.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, and various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, the memory management method comprising:

performing a host write operation to receive a write command from a host system and store first data corresponding to the write command to a first physical unit of the plurality of physical units;

recording first update data corresponding to the host write operation;

performing a data union operation to read second data from a second physical unit of the plurality of physical units and store the second data to a third physical unit of the plurality of physical units;

recording second updating data corresponding to the data integration operation;

judging whether the first updating data and the second updating data exist in a buffer memory at the same time; and

if the first updating data and the second updating data exist in the buffer memory at the same time, reading management information from the rewritable nonvolatile memory module to the buffer memory according to the first updating data and the second updating data, and updating the management information in the buffer memory.

2. The memory management method according to claim 1, wherein the step of reading the management information from the rewritable non-volatile memory module to the buffer memory according to the first update data and the second update data and updating the management information in the buffer memory comprises:

and responding to the recorded first updating data meeting a preset condition, reading the management information from the rewritable nonvolatile memory module to the buffer memory according to the first updating data and the second updating data, and updating the management information in the buffer memory.

3. The memory management method of claim 1, further comprising:

in response to the data amount of the recorded first updating data not being less than a preset data amount, determining that the recorded first updating data meets a preset condition.

4. The memory management method of claim 1, further comprising:

and continuously temporarily storing the second updating data in the buffer memory before the management information is read to the buffer memory according to the first updating data and the second updating data, and not reading the management information according to the second updating data.

5. The memory management method of claim 1, wherein the first update data comprises mapping information relating to a first logical unit, the second update data comprises mapping information relating to a second logical unit, the first logical unit maps to the first physical unit, and the second logical unit maps to the third physical unit.

6. The memory management method according to claim 1, wherein the step of reading the management information from the rewritable non-volatile memory module to the buffer memory according to the first update data and the second update data and updating the management information in the buffer memory comprises:

and updating the logical-to-physical mapping information according to the first updating data and the second updating data.

7. The memory management method of claim 1, further comprising:

storing the updated management information to the rewritable non-volatile memory module; and

clearing the first update data and the second update data in the buffer memory.

8. The memory management method of claim 1, further comprising:

obtaining sub-update data corresponding to the same logic unit in the first update data and the second update data; and

and updating the management information according to the latest data in the sub-updating data.

9. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuitry unit is to perform a host write operation to receive a write command from the host system and to instruct storage of first data corresponding to the write command to a first physical unit of the plurality of physical units,

wherein the memory control circuitry unit is further to record first update data corresponding to the host write operation,

wherein the memory control circuit unit is further configured to perform a data union operation to instruct reading of second data from a second physical unit of the plurality of physical units and storing of the second data to a third physical unit of the plurality of physical units,

wherein the memory control circuit unit is further configured to record second update data corresponding to the data union operation,

wherein the memory control circuit unit is further configured to determine whether the first update data and the second update data exist in the buffer memory at the same time,

if the first update data and the second update data exist in the buffer memory at the same time, the memory control circuit unit is further configured to read management information from the rewritable nonvolatile memory module to the buffer memory according to the indication of the first update data and the second update data and update the management information in the buffer memory.

10. The memory storage device according to claim 9, wherein the operation of the memory control circuit unit reading the management information from the rewritable non-volatile memory module to the buffer memory according to the first update data and the second update data and updating the management information in the buffer memory includes:

11. The memory storage device according to claim 9, wherein the memory control circuit unit is further configured to determine that the recorded first update data meets a preset condition in response to a data amount of the recorded first update data not being less than a preset data amount.

12. The memory storage device according to claim 9, wherein the memory control circuit unit is further configured to keep temporarily storing the second update data in the buffer memory before reading the management information to the buffer memory according to the first update data and the second update data, and not reading the management information according to the second update data.

13. The memory storage device of claim 9, wherein the first update data comprises mapping information relating to a first logical unit, the second update data comprises mapping information relating to a second logical unit, the first logical unit maps to the first physical unit, and the second logical unit maps to the third physical unit.

14. The memory storage device according to claim 9, wherein the operation of the memory control circuit unit reading the management information from the rewritable non-volatile memory module to the buffer memory according to the first update data and the second update data and updating the management information in the buffer memory includes:

15. The memory storage device of claim 9, wherein the memory control circuitry is further to store updated management information to the rewritable non-volatile memory module,

wherein the memory control circuit unit is further configured to clear the first update data and the second update data in the buffer memory.

16. The memory storage device of claim 9, wherein the memory control circuitry unit is further to obtain sub-update data of the first update data and the second update data corresponding to a same logic cell,

wherein the memory control circuit unit is further configured to update the management information according to the latest data of the sub update data.

17. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, wherein the memory control circuit unit includes:

a host interface for connecting to a host system;

a memory interface for connecting to the rewritable nonvolatile memory module;

a buffer memory; and

a memory management circuit connected to the host interface, the memory interface, and the buffer memory,

wherein the memory management circuitry is to perform a host write operation to receive a write command from the host system and to instruct storage of first data corresponding to the write command to a first physical unit of the plurality of physical units,

wherein the memory management circuitry is also to record first update data corresponding to the host write operation,

wherein the memory management circuitry is further to perform a data union operation to instruct reading of second data from a second physical unit of the plurality of physical units and storing of the second data to a third physical unit of the plurality of physical units,

wherein the memory management circuitry is further to record second update data corresponding to the data union operation,

wherein the memory management circuit is further configured to determine whether the first update data and the second update data are present in the buffer memory at the same time,

the memory management circuit is further used for reading management information from the rewritable non-volatile memory module to the buffer memory according to the first updating data and the second updating data and updating the management information in the buffer memory.

18. The memory control circuit unit of claim 17, wherein the operation of the memory management circuit to read the management information from the rewritable non-volatile memory module to the buffer memory according to the first update data and the second update data and update the management information in the buffer memory comprises:

19. The memory control circuit unit according to claim 17, wherein the memory management circuit is further configured to determine that the recorded first update data meets a preset condition in response to a data amount of the recorded first update data not being less than a preset data amount.

20. The memory control circuit unit of claim 17, wherein the memory management circuit is further configured to keep staging the second update data in the buffer memory and not reading the management information according to the second update data before reading the management information according to the first update data and the second update data into the buffer memory.

21. The memory control circuitry unit of claim 17, wherein the first update data comprises mapping information relating to a first logical unit, the second update data comprises mapping information relating to a second logical unit, the first logical unit maps to the first physical unit, and the second logical unit maps to the third physical unit.

22. The memory control circuit unit of claim 17, wherein the operation of the memory management circuit to read the management information from the rewritable non-volatile memory module to the buffer memory according to the first update data and the second update data and update the management information in the buffer memory comprises:

23. The memory control circuit unit of claim 17, wherein the memory management circuit is further configured to store updated management information to the rewritable non-volatile memory module,

wherein the memory management circuitry is further to clear the first update data and the second update data in the buffer memory.

24. The memory control circuit unit of claim 17, wherein the memory management circuit is further to obtain sub-update data corresponding to a same logical unit of the first update data and the second update data,

wherein the memory management circuit is further configured to update the management information according to the latest data of the sub-update data.

25. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

wherein the memory control circuit unit is configured to perform a first write operation, wherein the first write operation includes one of an operation of storing first data received from the host system to a first physical unit of the plurality of physical units and an operation of writing second data stored in a second physical unit of the plurality of physical units to a third physical unit of the plurality of physical units,

wherein the memory control circuit unit is further to record first update data corresponding to the first write operation,

wherein the memory control circuit unit is further configured to determine whether the first update data and second update data coexist in a buffer memory, the second update data is generated based on a second write operation, and the second write operation includes the other of the operation of storing the first data to the first physical unit and the operation of writing the second data to the third physical unit,