TWI712886B - Memory management method, memory storage device and memory control circuit unit - Google Patents

Abstract

A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving a first write command from a host system; instructing a rewritable non-volatile memory module to perform a first write operation according to the first write command; obtaining first performance information corresponding to the first write operation; and updating threshold information according to the first performance information, wherein the threshold information is configured to determine a type of target data.

Description

Memory management method, memory storage device and memory control circuit unit

The present invention relates to a memory management technology, and particularly relates to a memory management method, a memory storage device and a memory control circuit unit.

Digital cameras, mobile phones and MP3 players have grown rapidly in the past few years, which has led to a rapid increase in consumer demand for storage media. Because rewritable non-volatile memory modules (for example, flash memory) have the characteristics of non-volatile data, power saving, small size, and no mechanical structure, they are very suitable for internal Built in the various portable multimedia devices mentioned above.

In the memory management technology, many operations are performed according to the characteristics and/or types of the stored data. For example, in the data consolidation process (or called the garbage collection process), valid data can be divided into cold data and hot data. Effective data belonging to cold data can be collected first and stored centrally, thereby improving the efficiency of the data consolidation process. Alternatively, different characteristics and/or types of data can also be managed using different data management mechanisms or data protection mechanisms to improve the data maintenance capability of the memory storage device. Therefore, how to classify specific data effectively affects the system performance of the memory storage device.

The invention provides a memory management method, a memory storage device and a memory control circuit unit, which can improve the efficiency of data classification.

An exemplary embodiment of the present invention provides a memory management method, which is used in a rewritable non-volatile memory module, and the memory management method includes: receiving a first write command from a host system; A write command instructs the rewritable non-volatile memory module to perform a first write operation; obtains first performance information corresponding to the first write operation; and updates a threshold according to the first performance information Information, where the critical information is used to determine the type of target data.

In an exemplary embodiment of the present invention, the step of updating the threshold information according to the first performance information includes: receiving a second write command from the host system; and instructing the available data according to the second write command The copy-type non-volatile memory module performs a second write operation; obtains second performance information corresponding to the second write operation; and updates the first performance information and the second performance information Critical information.

In an exemplary embodiment of the present invention, the step of updating the critical information according to the first performance information includes: obtaining a difference between the first performance information and the second performance information; and according to the difference Update the critical information.

In an exemplary embodiment of the present invention, the step of updating the threshold information according to the difference includes: if the difference meets a preset condition, increasing the value of the threshold information; and if the difference does not meet The preset condition reduces the value of the critical information.

In an exemplary embodiment of the present invention, the memory management method further includes: determining whether the target data is the first type of data or the second type of data according to the critical information, wherein the data of the first type of data The update frequency is different from the data update frequency of the second type of data.

In an exemplary embodiment of the present invention, the step of determining whether the target data is the first type of data or the second type of data according to the threshold information includes: comparing the data amount of the target data with the threshold Information; if the data amount of the target data is less than the critical information, determine that the target data is the first type of data; and if the data amount of the target data is not less than the critical information , Determining that the target data is the second type of data.

In an exemplary embodiment of the present invention, the step of determining whether the target data is the first type of data or the second type of data according to the threshold information includes: comparing the logical range of the target data with the threshold Information; if the logical range of the target data is smaller than the critical information, determine that the target data is the first type of data; and if the logical range of the target data is not smaller than the critical information , Determining that the target data is the second type of data.

In an exemplary embodiment of the present invention, the rewritable non-volatile memory module includes a plurality of physical units, the plurality of physical units includes a first physical unit and a second physical unit, and the memory The management method further includes: if the target data is the first type of data, sending a first write instruction sequence to instruct to write the target data to the first physical unit; and if the target data is of the second type Data, sending a second write instruction sequence to instruct to write the target data to the second physical unit, wherein the first physical unit is different from the second physical unit.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used for coupling to the host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used for receiving a first write command from the host system. The memory control circuit unit is further configured to instruct the rewritable non-volatile memory module to perform a first write operation according to the first write instruction. The memory control circuit unit is further used to obtain first performance information corresponding to the first write operation. The memory control circuit unit is further used for updating critical information according to the first performance information, wherein the critical information is used to determine the type of target data.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to update the critical information according to the first performance information includes: receiving a second write command from the host system; and according to the second A write command instructs the rewritable non-volatile memory module to perform a second write operation; obtains second performance information corresponding to the second write operation; and according to the first performance information and the The second performance information updates the critical information.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to update the critical information according to the first performance information includes: obtaining the difference between the first performance information and the second performance information ; And updating the critical information according to the difference.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to update the critical information according to the difference value includes: if the difference value meets a preset condition, increasing the value of the critical information; and If the difference does not meet the preset condition, reduce the value of the critical information.

In an exemplary embodiment of the present invention, the memory control circuit unit is further used to determine whether the target data is the first type of data or the second type of data according to the critical information, wherein the data of the first type of data The update frequency is different from the data update frequency of the second type of data.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to determine whether the target data is the first type of data or the second type of data according to the critical information includes: Compare the data volume of the target data with the critical information; if the data volume of the target data is less than the critical information, determine that the target data is the first type of data; and if the data of the target data If the amount is not less than the critical information, it is determined that the target data is the second type of data.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to determine whether the target data is the first type of data or the second type of data according to the critical information includes: Compare the logical range of the target data with the critical information; if the logical range of the target data is smaller than the critical information, determine that the target data is the first type of data; and if the logic of the target data The range is not less than the critical information, and the target data is determined to be the second type of data.

In an exemplary embodiment of the present invention, the rewritable non-volatile memory module includes a plurality of physical units, and the plurality of physical units includes a first physical unit and a second physical unit. If the target data is the first type of data, the memory control circuit unit is further configured to send a first write command sequence to instruct to write the target data to the first physical unit. If the target data is the second type of data, the memory control circuit unit is further used to send a second write command sequence to instruct to write the target data to the second physical unit, wherein the first The physical unit is different from the second physical unit.

Example embodiments of the present invention further provide a memory control circuit unit for controlling a rewritable non-volatile memory module, and the memory control circuit unit includes a host interface, a memory interface, and a memory management circuit . The host interface is used for coupling to a host system. The memory interface is used for coupling to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The memory management circuit is used for receiving a first write command from the host system. The memory management circuit is further configured to instruct the rewritable non-volatile memory module to perform a first write operation according to the first write instruction. The memory management circuit is further used to obtain first performance information corresponding to the first write operation. The memory management circuit is further used for updating critical information according to the first performance information, wherein the critical information is used to determine the type of target data.

In an exemplary embodiment of the present invention, the operation of the memory management circuit to update the threshold information according to the first performance information includes: receiving a second write command from the host system; and according to the second write The input command instructs the rewritable non-volatile memory module to perform a second write operation; obtains second performance information corresponding to the second write operation; and according to the first performance information and the first 2. The performance information updates the critical information.

In an exemplary embodiment of the present invention, the operation of the memory management circuit to update the critical information according to the first performance information includes: obtaining the difference between the first performance information and the second performance information; And update the critical information according to the difference.

In an exemplary embodiment of the present invention, the operation of the memory management circuit to update the critical information according to the difference includes: if the difference meets a preset condition, increasing the value of the critical information; and if If the difference does not meet the preset condition, the value of the critical information is reduced.

In an exemplary embodiment of the present invention, the first performance information includes a write amplification parameter, and the write amplification parameter reflects a write amplification ratio caused by the first write operation.

In an exemplary embodiment of the present invention, the memory management circuit is further used to determine whether the target data is the first type of data or the second type of data according to the critical information, wherein the data of the first type of data is updated The frequency is different from the data update frequency of the second type of data.

In an exemplary embodiment of the present invention, the operation of the memory management circuit to determine whether the target data is the first type of data or the second type of data according to the critical information includes: Compare the amount of data with the threshold information; if the amount of data of the target data is smaller than the threshold information, determine that the target data is the first type of data; and if the amount of data of the target data Not less than the critical information, determine that the target data is the second type of data.

In an exemplary embodiment of the present invention, the operation of the memory management circuit to determine whether the target data is the first type of data or the second type of data according to the critical information includes: Compare the logical range with the critical information; if the logical range of the target data is smaller than the critical information, determine that the target data is the first type of data; and if the logical range of the target data Not less than the critical information, determine that the target data is the second type of data.

In an exemplary embodiment of the present invention, the rewritable non-volatile memory module includes a plurality of physical units, and the plurality of physical units includes a first physical unit and a second physical unit. If the target data is the first type of data, the memory management circuit is further configured to send a first write command sequence to instruct to write the target data to the first physical unit. If the target data is the second type of data, the memory management circuit is further configured to send a second write command sequence to instruct to write the target data to the second physical unit, wherein the first physical unit The unit is different from the second physical unit.

Based on the above, after receiving the first write command from the host system, the rewritable non-volatile memory module can execute the first write operation according to the first write command and corresponds to the first write operation. The first performance information can be obtained. Then, based on the first performance information, the critical information can be updated and used to determine the type of target data. In this way, the efficiency of data classification in the memory storage device can be effectively improved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). Generally, the memory storage device is used together with the host system so that the host system can write data to the memory storage device or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the invention.

1 and FIG. 2, the host system 11 generally includes a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 are all coupled to a system bus 110.

In this exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 is coupled to the I/O device 12 through the system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I/O device 12 via the system bus 110.

In this exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 may be disposed on the main board 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be coupled to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 can be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory device. Storage devices (for example, iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be coupled to a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. Type I/O device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207.

In an exemplary embodiment, the host system mentioned is any system that can substantially cooperate with a memory storage device to store data. Although in the above exemplary embodiment, the host system is described as a computer system, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. 3, in another exemplary embodiment, the host system 31 may also be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be used for it. Various non-volatile memory storage devices such as Secure Digital (SD) card 32, Compact Flash (CF) card 33 or embedded storage device 34 are used. The embedded storage device 34 includes an embedded Multi Media Card (eMMC) 341 and/or an embedded Multi Chip Package (embedded Multi Chip Package, eMCP) storage device 342. The memory module is directly coupled to the Embedded storage device on the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable non-volatile memory module 406.

The connection interface unit 402 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 through the connection interface unit 402. In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited to this, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 Standard, high-speed peripheral component connection interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface Standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, universal flash memory (Universal Flash Storage, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 402 and the memory control circuit unit 404 can be packaged in one chip, or the connection interface unit 402 can be arranged outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used to execute a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and perform data processing in the rewritable non-volatile memory module 406 according to the instructions of the host system 11 Write, read and erase operations.

The rewritable non-volatile memory module 406 is coupled to the memory control circuit unit 404 and used for storing data written by the host system 11. The rewritable non-volatile memory module 406 can be a single-level cell (SLC) NAND flash memory module (that is, a flash memory that can store 1 bit in a memory cell). Modules), Multi Level Cell (MLC) NAND flash memory modules (that is, a flash memory module that can store 2 bits in a memory cell), and a third-level memory cell ( Triple Level Cell (TLC) NAND flash memory modules (that is, a flash memory module that can store 3 bits in a memory cell), Quad Level Cell (QLC) NAND flash memory modules Flash memory module (ie, a flash memory module that can store 4 bits in a memory cell), other flash memory modules or other memory modules with the same characteristics.

Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 406 has multiple storage states. By applying the read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In this exemplary embodiment, the memory cells of the rewritable non-volatile memory module 406 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erasing units. Specifically, the memory cells on the same character line can form one or more physical programming units. If each memory cell can store more than two bits, the physical programming unit on the same character line can be at least classified into a lower physical programming unit and an upper physical programming unit. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit is higher than that of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit. The reliability of the physical programming unit.

In this exemplary embodiment, the physical programming unit is the smallest programming unit. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area contains multiple physical sectors for storing user data, and the redundant bit area is used for storing system data (for example, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16, or more or less physical sectors, and the size of each physical sector can also be larger or smaller. On the other hand, the physical erasure unit is the smallest unit of erasure. That is, each physical erasing unit contains one of the smallest number of memory cells to be erased. For example, the physical erasing unit is a physical block.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and when the memory storage device 10 is operating, these control commands are executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 502 is equivalent to the description of the operation of the memory control circuit unit 404.

In this exemplary embodiment, the control commands of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control commands are burned into the read-only memory. When the memory storage device 10 is operating, these control commands are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control commands of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 in the form of code (for example, the memory module is dedicated to storing system data). System area). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to store it in the rewritable non-volatile memory The control commands in the volume module 406 are loaded into the random access memory of the memory management circuit 502. After that, the microprocessor unit will run these control commands to perform data writing, reading, and erasing operations.

In addition, in another exemplary embodiment, the control commands of the memory management circuit 502 can also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cell or the memory cell group of the rewritable non-volatile memory module 406. The memory write circuit is used to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406. The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406. The memory erase circuit is used to issue an erase command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding writing and reading. Take and erase operations. In an exemplary embodiment, the memory management circuit 502 can also send other types of instruction sequences to the rewritable non-volatile memory module 406 to instruct to perform corresponding operations.

The host interface 504 is coupled to the memory management circuit 502. The memory management circuit 502 can communicate with the host system 11 through the host interface 504. The host interface 504 can be used to receive and identify commands and data sent by the host system 11. For example, the commands and data sent by the host system 11 can be sent to the memory management circuit 502 through the host interface 504. In addition, the memory management circuit 502 can transmit data to the host system 11 through the host interface 504. In this exemplary embodiment, the host interface 504 is compatible with the SATA standard. However, it must be understood that the present invention is not limited to this. The host interface 504 can also be compatible with PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard. , MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 506 is coupled to the memory management circuit 502 and used to access the rewritable non-volatile memory module 406. In other words, the data to be written into the rewritable non-volatile memory module 406 is converted into a format acceptable by the rewritable non-volatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 needs to access the rewritable non-volatile memory module 406, the memory interface 506 will send a corresponding command sequence. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and various memory operations (for example, changing read Take the voltage level or perform garbage collection operation, etc.) corresponding to the instruction sequence. These command sequences are generated by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 through the memory interface 506, for example. These command sequences can include one or more signals, or data on the bus. These signals or data may include script or program code. For example, in the read command sequence, information such as the read identification code and memory address will be included.

In an exemplary embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508, a buffer memory 510, and a power management circuit 512.

The error checking and correction circuit 508 is coupled to the memory management circuit 502 and used to perform error checking and correction operations to ensure the correctness of the data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correction circuit 508 will generate a corresponding error correcting code (ECC) for the data corresponding to the write command. And/or error detecting code (EDC), and the memory management circuit 502 will write the data corresponding to the write command and the corresponding error correction code and/or error check code to the rewritable non-volatile In the memory module 406. Later, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it will also read the error correction code and/or error check code corresponding to the data, and the error check and correction circuit 508 Based on the error correction code and/or error check code, error checking and correction operations are performed on the read data.

The buffer memory 510 is coupled to the memory management circuit 502 and used to temporarily store data and commands from the host system 11 or data from the rewritable non-volatile memory module 406. The power management circuit 512 is coupled to the memory management circuit 502 and used to control the power of the memory storage device 10.

In an exemplary embodiment, the rewritable non-volatile memory module 406 of FIG. 4 is also called a flash memory module, and the memory control circuit unit 404 is also called for controlling the flash memory The flash memory controller of the physical module. In an exemplary embodiment, the memory management circuit 502 of FIG. 5 is also referred to as a flash memory management circuit.

FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Please refer to FIG. 6, the memory management circuit 502 can logically group the physical units 610(0)-610(B) of the rewritable non-volatile memory module 406 into the storage area 601 and the replacement area 602. The physical units 610(0)~610(A) in the storage area 601 are used to store data, and the physical units 610(A+1)~610(B) in the replacement area 602 are used to replace the storage area 601 Damaged physical unit. For example, if the data read from a certain physical unit contains too many errors to be corrected, this physical unit will be regarded as a damaged physical unit. It should be noted that if there is no usable physical erasing unit in the replacement area 602, the memory management circuit 502 may declare the entire memory storage device 10 as a write protect state, and no more data can be written. .

In this exemplary embodiment, each physical unit refers to a physical erasing unit. However, in another exemplary embodiment, a physical unit may also refer to a physical address, a physical programming unit, or consist of multiple continuous or discontinuous physical addresses. The memory management circuit 502 will configure the logical units 612(0)~612(C) to map the physical units 610(0)~610(A) in the storage area 601. In this exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logic unit may also refer to a logic programming unit, a logic erasing unit, or composed of multiple consecutive or discontinuous logic addresses. In addition, each of the logical units 612(0)-612(C) can be mapped to one or more physical units.

The memory management circuit 502 can record the mapping relationship between the logical unit and the physical unit (also referred to as the logical-physical address mapping relationship) in at least one logical-physical address mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform the processing of the memory storage device 10 according to the logical-physical address mapping table. Data access operations.

FIG. 7 is a schematic diagram of a data storage operation according to an exemplary embodiment of the present invention. Referring to FIG. 7, it is assumed that the memory management circuit 502 receives from the host system 11 at least one write command instructing to store data (also referred to as target data) 701. The memory management circuit 502 can temporarily store the write command and data 701 in the buffer memory 510. The memory management circuit 502 can read the critical information from the buffer memory 510. The memory management circuit 502 can determine the type of the data 701 according to the critical information.

In an exemplary embodiment, the memory management circuit 502 can determine whether the data 701 is the first type of data or the second type of data based on the critical information. If the data 701 is the first type of data, the memory management circuit 502 can send at least one write command sequence (also referred to as the first write command sequence) to instruct the rewritable non-volatile memory module 406 to buffer the memory The data 701 in 510 is stored in a physical unit (also referred to as a first physical unit) 710. Or, if the data 701 is the second type of data, the memory management circuit 502 can send at least one write command sequence (also called a second write command sequence) to instruct the rewritable non-volatile memory module 406 to The data 701 is stored in a physical unit (also referred to as a second physical unit) 720. It should be noted that the physical units 710 and 720 are two different physical units. For example, the storage area 601 in FIG. 6 may include multiple idle physical units. Each idle physical unit has not stored valid data. For example, after a certain physical unit is erased, the erased physical unit can become a new idle physical unit. The physical units 710 and 720 can be selected from these idle physical units.

In an exemplary embodiment, different types of data have different data update frequencies. For example, the data update frequency of the first type of data may be higher than the data update frequency of the second type of data. Therefore, if the data 701 belongs to the first type of data, it means that the data update frequency of the logical unit to which the data 701 belongs may be higher (for example, higher than a threshold value). Conversely, if the data 701 belongs to the second type of data, it means that the data update frequency of the logical unit to which the data 701 belongs may be low (for example, lower than a threshold). The memory management circuit 502 can store the first type of data (that is, data with a higher update frequency, also called thermal data) in the physical unit 710 and store the second type of data (that is, the data with a lower update frequency, also called The cold data) is stored centrally in the physical unit 720.

In an exemplary embodiment, the memory management circuit 502 can perform a data consolidation operation (such as a garbage collection operation) to release new idle physical units. The operation of releasing a new idle physical unit includes removing valid data from the selected physical unit (also referred to as the source node) and erasing the physical unit. In the exemplary embodiment of FIG. 7, the first type of data with a higher update frequency is stored centrally in the physical unit 710, so the data in the physical unit 710 can easily become invalid data after multiple write operations, thereby reducing The amount of valid data in the physical unit 710. Therefore, in the subsequent data merging operation, if the physical unit 710 is preferentially selected as the source node and effective data is collected from it, the release efficiency of idle physical units can be effectively improved.

In an exemplary embodiment, the memory management circuit 502 can compare the data amount of the data 701 with the critical information. If the data amount of the data 701 is less than the threshold information, the memory management circuit 502 can determine that the data 701 is the first type of data. Or, if the data amount of the data 701 is greater than (or not less than) the critical information, the memory management circuit 502 can determine that the data 701 is the second type of data.

FIG. 8 is a schematic diagram illustrating the data amount and critical information of the comparison target data according to an exemplary embodiment of the present invention. Referring to FIG. 8, in an exemplary embodiment, assuming that the data amount of the data 801 is less than the threshold information THR, the data 801 can be identified as the first type of data. Alternatively, in an exemplary embodiment, assuming that the data amount of the data 802 is not less than the threshold information THR, the data 802 can be identified as the second type of data. The value of the threshold information THR may be 4KB, 8KB, 16KB or other values, for example.

It should be noted that in another exemplary embodiment of FIG. 7, the memory management circuit 502 may also combine the logical range of the data 701 (that is, the range of the logical address of at least one logical unit to which the data 701 belongs) and the critical information Compare. If the logical range of the data 701 is smaller than the critical information, the memory management circuit 502 can determine that the data 701 belongs to the first type of data (ie, thermal data). Or, if the logical range of the data 701 is not less than the critical information, the memory management circuit 502 can determine that the data 701 belongs to the second type of data (ie, cold data).

It should be noted that, in an exemplary embodiment, the critical information used to determine the type of target data may be a fixed value. However, for memory storage devices of different models and/or different operating behaviors, the same critical information may have different accuracy in identifying the type of target data. Therefore, if the value of the threshold information can be dynamically calibrated and/or optimized during the operation of the memory storage device, then customized thresholds can be provided for memory storage devices of different models and/or different operating behaviors. Information, thereby improving the efficiency of identifying the type of target data. If the identification efficiency of the target data type is improved, the subsequent automatic management of the memory storage device can also be improved.

In an exemplary embodiment, the memory management circuit 502 can receive at least one write command (also referred to as a first write command) from the host system 11. The first write command can instruct to store a certain data (also referred to as the first data) to at least one logical unit (also referred to as the first logical unit). According to the first write command, the memory management circuit 502 can instruct the rewritable non-volatile memory module 406 to perform a certain write operation (also referred to as the first write operation). In the first write operation, the rewritable non-volatile memory module 406 can store the first data in one or more physical units mapped by the first logical unit. After the first write operation is performed, the memory management circuit 502 can obtain performance information (also referred to as first performance information) corresponding to the first write operation. The first performance information can reflect the execution performance of the first write operation. Alternatively, the memory management circuit 502 can evaluate the performance of the first write operation based on the first performance information. Then, the memory management circuit 502 can update the threshold information according to the first performance information.

In an exemplary embodiment, the first performance information includes a write amplification parameter (also referred to as the first write amplification parameter). The first write amplification parameter may reflect the write amplification ratio caused by the first write operation. For example, suppose that the data volume of the first data is 16KB, and during the first write operation, the first write operation writes a total of 48KB of data. That is, in the first data writing operation for storing the first data, the data volume of the written data is enlarged by 3 times (48/16=3). For example, the 48KB of data may include at least one data movement and/or management information update. For example, data transfer may include moving the first data from the temporary storage area in the rewritable non-volatile memory module 406 to the main storage area and/or part of the valid data in the rewritable non-volatile memory module 406 The move. The update of the management information may include the update of the logical-physical address mapping relationship, etc. In addition, the value of the first write amplification parameter may negatively correlate with the performance of the first write operation. That is, if the value of the first write amplification parameter is larger, it means that the performance of the first write operation is worse.

In an exemplary embodiment, the memory management circuit 502 can obtain the difference between the first performance information and another performance information (also referred to as second performance information). The memory management circuit 502 can update the critical information according to the difference. For example, the memory management circuit 502 can determine whether the difference meets a preset condition. If the difference meets the preset condition, the memory management circuit 502 can increase the value of the critical information. Or, if the difference does not meet the preset condition, the memory management circuit 502 can reduce the value of the critical information.

In an exemplary embodiment, the memory management circuit 502 can determine whether the difference is less than zero. If the difference is less than zero, the memory management circuit 502 can determine that the difference meets a preset condition and increase the value of the critical information. Alternatively, if the difference is not less than zero (for example, greater than zero), the memory management circuit 502 can determine that the difference does not meet the preset condition and reduce the value of the critical information.

In an exemplary embodiment, the memory management circuit 502 can receive at least one write command (also referred to as a second write command) from the host system 11. The second write command can, for example, instruct to store a certain data (also referred to as the second data) to at least one logical unit (also referred to as the second logical unit). According to the second write command, the memory management circuit 502 can instruct the rewritable non-volatile memory module 406 to perform a certain write operation (also referred to as a second write operation). In the second write operation, the rewritable non-volatile memory module 406 can store the second data in one or more physical units mapped by the second logical unit. After the second write operation is performed, the memory management circuit 502 can obtain performance information (ie, second performance information) corresponding to the second write operation. The second performance information can reflect the execution performance of the second write operation. Alternatively, the memory management circuit 502 can evaluate the performance of the second write operation based on the second performance information. Then, the memory management circuit 502 can update the threshold information according to the first performance information and the second performance information.

In an exemplary embodiment, the second performance information also includes a write amplification parameter (also referred to as a second write amplification parameter). The second write amplification parameter may reflect the write amplification ratio caused by the second write operation. For example, suppose that the data volume of the second data is 128KB, and during the second write operation, the second write operation writes a total of 1024KB of data. That is, in the second data writing operation for storing the second data, the data volume of the written data is enlarged by 8 times (1024/128=8). For example, the 1024KB data may also include at least one data movement and/or management information update, which will not be repeated here.

It should be noted that although the foregoing exemplary embodiments are all examples of writing amplification parameters as performance information, the present invention does not limit the type of performance information that reflects the performance of the writing operation. For example, in another exemplary embodiment, the performance information may also include other types of parameters to reflect the length of time required to perform a certain write operation, and so on.

FIG. 9 is a schematic diagram of obtaining performance information at different time points according to an exemplary embodiment of the present invention. 10 is a schematic diagram of a pseudo code for updating critical information according to an exemplary embodiment of the present invention.

Please refer to FIG. 9 and FIG. 10, assuming that the initial value of the threshold information THR is S. The performance information WAF(i) is obtained at time T(i), and i is between 0 and n+1. At time T(0), the threshold information THR is increased by an adjustment value ΔS. Between time points T(0) and T(1), the performance information WAF(0) can be regarded as the first performance information and the performance information WAF(1) can be regarded as the second performance information. The performance information WAF(0) can reflect the performance of the first write operation before the time point T(0). The performance information WAF(1) can reflect the performance of the second write operation between the time points T(0) and T(1). The difference F(0) between the performance information WAF(0) and WAF(1) can be obtained by subtracting WAF(0) from the performance information WAF(1). According to the difference F(0), the threshold information THR can be updated. For example, according to the virtual code 1001, if the difference F(0) is less than zero, the threshold information THR can be increased by an adjustment value ΔS. Alternatively, if the difference F(0) is greater than zero, the threshold information THR can be reduced by an adjustment value ΔS.

Then, between the time points T(1) and T(2), the performance information WAF(1) can be regarded as the first performance information and the performance information WAF(2) can be regarded as the second performance information. The performance information WAF(1) can reflect the performance of the first write operation between the time points T(0) and T(1). The performance information WAF(2) can reflect the performance of the second write operation between the time points T(1) and T(2). The difference F(1) between the performance information WAF(1) and WAF(2) can be obtained by subtracting WAF(1) from the performance information WAF(2). According to the difference F(1), the threshold information THR can be updated again. For example, according to the virtual code 1001, if the difference F(1) is less than zero, the threshold information THR can be increased by an adjustment value ΔS. Alternatively, if the difference F(1) is greater than zero, the threshold information THR can be reduced by an adjustment value ΔS. By analogy, after reaching the time point T(n+1), the critical information THR can be updated n times.

In an exemplary embodiment, if the performance information WAF(i) obtained at the time point T(i) approaches a constant value, it means that using the current threshold information THR to identify the type of target data can allow the corresponding write The performance of the entry operation tends to be stable. In this case, the current threshold information THR can be fixed and no longer updated. From another perspective, if the performance information WAF(i) obtained at the time point T(i) approaches a fixed value, it can also indicate that the current threshold information THR has been updated to the optimal value. In this case, the overall performance of the memory storage device (including data writing operations and/or data merging operations) can be maintained in a better state. In addition, when the performance information WAF(i) diverges again, the threshold information THR can also be updated again.

FIG. 11 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. Referring to FIG. 11, in step S1101, a first write command is received from the host system. In step S1102, the rewritable non-volatile memory module is instructed to perform the first write operation according to the first write command. In step S1103, first performance information corresponding to the first write operation is obtained. In step S1104, the critical information is updated according to the first performance information, where the critical information is used to determine the type of target data.

FIG. 12 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. Referring to FIG. 12, in step S1201, a first write command is received from the host system. In step S1202, the rewritable non-volatile memory module is instructed to perform the first write operation according to the first write command. In step S1203, first performance information corresponding to the first write operation is obtained. In step S1204, a second write command is received from the host system. In step S1205, the rewritable non-volatile memory module is instructed to perform a second write operation according to the second write command. In step S1206, second performance information corresponding to the second write operation is obtained. In step S1207, the critical information is updated according to the first performance information and the second performance information, where the critical information is used to determine the type of target data.

FIG. 13 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. Referring to FIG. 13, in step S1301, target data is obtained. In step S1302, the data amount of the target data is compared with the critical information. In step S1303, it is determined whether the data amount of the target data is less than the critical information. If the data amount of the target data is less than the critical information, in step S1304, it is determined that the target data is the first type of data, and in step S1305, the target data is stored in the first physical unit. However, if the data amount of the target data is not less than the critical information, in step S1306, it is determined that the target data is the second type of data, and in step S1307, the target data is stored in the second physical unit.

It should be noted that in the exemplary embodiment of FIG. 13, step S1302 can also be modified to compare the logical range of the target data with the critical information. If step S1303 determines that the logical range of the target data is smaller than the critical information, step S1304 can be entered. In addition, if it is determined in step S1303 that the logical range of the target data is not less than the critical information, step S1306 can be entered.

However, each step in FIG. 11 to FIG. 13 has been described in detail as above, and will not be repeated here. It should be noted that each step in FIG. 11 to FIG. 13 can be implemented as multiple program codes or circuits, and the present invention is not limited. In addition, the methods in FIGS. 11 to 13 can be used in conjunction with the above exemplary embodiments, or can be used alone, and the present invention is not limited.

In summary, at different time points, performance information corresponding to multiple write operations can be obtained. Based on the obtained performance information, the critical information can be updated and used to determine the type of target data. In this way, the efficiency of data classification in the memory storage device can be effectively improved and/or the overall performance of the memory storage device can be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10.30: Memory storage device 11.31: Host system 110: system bus 111: processor 112: Random Access Memory 113: read-only memory 114: Data Transmission Interface 12: Input/output (I/O) device 20: Motherboard 201: flash drive 202: Memory Card 203: Solid State Drive 204: wireless memory storage device 205: Global Positioning System Module 206: network interface card 207: wireless transmission device 208: keyboard 209: Screen 210: Horn 32: SD card 33: CF card 34: Embedded storage device 341: Embedded Multimedia Card 342: Embedded multi-chip package storage device 402: connection interface unit 404: Memory control circuit unit 406: rewritable non-volatile memory module 502: Memory Management Circuit 504: Host Interface 506: Memory Interface 508: Error checking and correction circuit 510: buffer memory 512: power management circuit 601: storage area 602: replacement area 610(0)~610(B), 710, 720: physical unit 612(0)~612(C): logic unit 701, 801, 802: data THR: critical information WAF(0)~WAF(n+1): performance information F(0)~F(n): Difference T(0)~T(n+1): time point 1001: virtual code S1101: Step (receive the first write command from the host system) S1102: Step (instruct the rewritable non-volatile memory module to execute the first write operation according to the first write command) S1103: Step (obtain first performance information corresponding to the first write operation) S1104: Step (update critical information according to the first performance information, where the critical information is used to determine the type of target data) S1201: Step (receive the first write command from the host system) S1202: Step (instruct the rewritable non-volatile memory module to perform the first write operation according to the first write command) S1203: Step (obtain first performance information corresponding to the first write operation) S1204: Step (receive the second write command from the host system) S1205: Step (instruct the rewritable non-volatile memory module to execute the second write operation according to the second write command) S1206: Step (obtain second performance information corresponding to the second write operation) S1207: Step (Update critical information based on the first performance information and the second performance information) S1301: Steps (obtain target data) S1302: Step (compare the data volume of the target data with the critical information) S1303: Step (determine whether the data volume of the target data is less than the critical information) S1304: Steps (determine that the target data is the first type of data) S1305: Step (store target data in the first physical unit) S1306: Steps (determine that the target data is the second type of data) S1307: Step (Save the target data to the second physical unit)

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the invention. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. FIG. 7 is a schematic diagram of a data storage operation according to an exemplary embodiment of the present invention. FIG. 8 is a schematic diagram illustrating the data amount and critical information of the comparison target data according to an exemplary embodiment of the present invention. FIG. 9 is a schematic diagram of obtaining performance information at different time points according to an exemplary embodiment of the present invention. 10 is a schematic diagram of a pseudo code for updating critical information according to an exemplary embodiment of the present invention. FIG. 11 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. FIG. 12 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. FIG. 13 is a flowchart of a memory management method according to an exemplary embodiment of the present invention.

S1101: Step (receive the first write command from the host system)

S1102: Step (instruct the rewritable non-volatile memory module to execute the first write operation according to the first write command)

S1103: Step (obtain first performance information corresponding to the first write operation)

S1104: Step (update critical information according to the first performance information, where the critical information is used to determine the type of target data)

Claims (27)

A memory management method for a rewritable non-volatile memory module, and the memory management method includes: receiving a first write command from a host system; and instructing the rewritable memory module according to the first write command The copy-type non-volatile memory module performs a first write operation; obtains a first performance information corresponding to the first write operation; and updates a threshold information according to the first performance information, wherein the threshold information is used To determine the type of a target data stored in the first write command. For the memory management method described in claim 1, wherein the step of updating the critical information according to the first performance information includes: receiving a second write command from the host system; according to the second write command instruction The rewritable non-volatile memory module performs a second write operation; obtains a second performance information corresponding to the second write operation; and updates the second performance information according to the first performance information and the second performance information Critical information. In the memory management method described in claim 1, wherein the step of updating the critical information according to the first performance information includes: obtaining a difference between the first performance information and a second performance information; and Update the critical information according to the difference. In the memory management method described in item 3 of the scope of patent application, the step of updating the critical information according to the difference includes: If the difference meets a preset condition, increase a value of the threshold information; and if the difference does not meet the preset condition, decrease the value of the threshold information. In the memory management method described in claim 1, wherein the first performance information includes a write amplification parameter, and the write amplification parameter reflects a write amplification ratio caused by the first write operation. For example, the memory management method described in item 1 of the scope of patent application further includes: determining whether the target data is a first type of data or a second type of data according to the critical information, wherein a data update frequency of the first type of data A data update frequency different from the second type of data. For example, in the memory management method described in item 6 of the scope of patent application, the step of determining whether the target data is the first type of data or the second type of data according to the critical information includes: a data amount of the target data and the Compare the threshold information; if the amount of the target data is less than the threshold information, determine the target data as the first type of data; and if the amount of the target data is not less than the threshold information, determine the target data as the The second type of information. For example, in the memory management method described in claim 6, wherein the step of determining whether the target data is the first type of data or the second type of data according to the critical information includes: a logical range of the target data and the Critical information; if the logical range of the target data is smaller than the critical information, determine the target data The data is the first type of data; and if the logical range of the target data is not less than the critical information, the target data is determined to be the second type of data. The memory management method according to claim 1, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the plurality of physical units includes a first physical unit and a second physical unit , And the memory management method further includes: if the target data is a first type of data, sending a first write command sequence to instruct the target data to be written to the first physical unit; and if the target data is A second type of data, sending a second write command sequence to instruct the target data to be written to the second physical unit, wherein the first physical unit is different from the second physical unit. A memory storage device includes: a connection interface unit for coupling to a host system; a rewritable non-volatile memory module; and a memory control circuit unit coupled to the connection interface unit and The rewritable non-volatile memory module, wherein the memory control circuit unit is used to receive a first write command from the host system, and the memory control circuit unit is further used to instruct according to the first write command The rewritable non-volatile memory module executes a first write operation, and the memory control circuit unit is further used to obtain a data corresponding to the first write operation A first performance information, and the memory control circuit unit is further used to update a threshold information according to the first performance information, wherein the threshold information is used to determine the type of a target data stored in the first write command. For the memory storage device described in claim 10, the operation of the memory control circuit unit to update the critical information according to the first performance information includes: receiving a second write command from the host system; The second write command instructs the rewritable non-volatile memory module to perform a second write operation; obtains a second performance information corresponding to the second write operation; and according to the first performance information and the The second performance information updates the critical information. For the memory storage device described in claim 10, wherein the operation of the memory control circuit unit to update the critical information according to the first performance information includes: obtaining a relationship between the first performance information and a second performance information And update the critical information according to the difference. For the memory storage device described in claim 12, the operation of the memory control circuit unit to update the critical information according to the difference includes: if the difference meets a preset condition, increasing a value of the critical information Value; and if the difference does not meet the preset condition, reduce the value of the critical information. The memory storage device according to claim 10, wherein the first performance information includes a write amplification parameter, and the write amplification parameter reflects a write amplification ratio caused by the first write operation. For example, the memory storage device described in claim 10, wherein the memory control circuit unit is further used for determining whether the target data is a first type data or a second type data according to the critical information, wherein the first A data update frequency of one type of data is different from a data update frequency of the second type of data. For example, in the memory storage device described in claim 15, wherein the operation of the memory control circuit unit to determine whether the target data is the first type of data or the second type of data according to the critical information includes: the target data Compare a data amount of with the threshold information; if the data amount of the target data is less than the threshold information, determine the target data as the first type of data; and if the data amount of the target data is not less than the threshold information, Determine the target data as the second type of data. For example, in the memory storage device described in claim 15, wherein the operation of the memory control circuit unit to determine whether the target data is the first type of data or the second type of data according to the critical information includes: the target data Compare a logical range of the target data with the critical information; if the logical range of the target data is smaller than the critical information, determine the target data as the first type of data; and if the logical range of the target data is not smaller than the critical information, Determine the target The data is the second type of data. The memory storage device according to claim 10, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the plurality of physical units includes a first physical unit and a second physical unit If the target data is a first type of data, the memory control circuit unit is further used to send a first write command sequence to instruct the target data to be written to the first physical unit, and if the target data is A second type of data, the memory control circuit unit is further used to send a second write command sequence to instruct to write the target data to the second physical unit, wherein the first physical unit is different from the second physical unit Entity unit. A memory control circuit unit is used to control a rewritable non-volatile memory module, and the memory control circuit unit includes: a host interface for coupling to a host system; and a memory interface for To be coupled to the rewritable non-volatile memory module; and a memory management circuit coupled to the host interface and the memory interface, wherein the memory management circuit is used to receive a second from the host system A write command, the memory management circuit is further used to instruct the rewritable non-volatile memory module to perform a first write operation according to the first write command; the memory management circuit is further used to obtain a corresponding In the first write operation A performance information, and the memory management circuit is further used for updating a threshold information according to the first performance information, wherein the threshold information is used to determine the type of a target data stored in the first write command. The memory control circuit unit according to claim 19, wherein the operation of the memory management circuit to update the critical information according to the first performance information includes: receiving a second write command from the host system; The second write command instructs the rewritable non-volatile memory module to perform a second write operation; obtains a second performance information corresponding to the second write operation; and according to the first performance information and the The second performance information updates the critical information. For the memory control circuit unit described in claim 19, wherein the operation of the memory management circuit to update the critical information according to the first performance information includes: obtaining a relationship between the first performance information and a second performance information And update the critical information according to the difference. For the memory control circuit unit described in claim 21, the operation of the memory management circuit to update the critical information according to the difference includes: if the difference meets a preset condition, increasing a value of the critical information Value; and if the difference does not meet the preset condition, reduce the value of the critical information. The memory control circuit unit described in claim 19, wherein the first performance information includes a write amplification parameter, and the write amplification parameter reflects a write amplification ratio caused by the first write operation. For example, the memory control circuit unit described in claim 19, wherein the memory management circuit is further used for determining whether the target data is a first type of data or a second type of data according to the critical information, wherein the first A data update frequency of one type of data is different from a data update frequency of the second type of data. For example, the memory control circuit unit described in claim 24, wherein the operation of the memory management circuit to determine whether the target data is the first type of data or the second type of data according to the critical information includes: the target data Compare a data amount of with the threshold information; if the data amount of the target data is less than the threshold information, determine the target data as the first type of data; and if the data amount of the target data is not less than the threshold information, Determine the target data as the second type of data. For example, in the memory storage device described in claim 24, the operation of the memory management circuit to determine whether the target data is the first type of data or the second type of data according to the critical information includes: A logical range is compared with the critical information; if the logical range of the target data is smaller than the critical information, the target data is determined to be the first type of data; and if the logical range of the target data is not smaller than the critical information, it is determined The goal The data is the second type of data. The memory control circuit unit according to claim 19, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the plurality of physical units includes a first physical unit and a second physical unit Unit, if the target data is a first type of data, the memory management circuit is further used to send a first write command sequence to instruct the target data to be written to the first physical unit, and if the target data is A second type of data, the memory management circuit is further used to send a second write command sequence to instruct the target data to be written to the second physical unit, wherein the first physical unit is different from the second physical unit unit.

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