TWI602190B - Memory control method and memory device - Google Patents

Description

Memory control method, memory device

The present invention relates to a memory control method and a memory device.

Error Correcting Codes (ECC) is a technique used to correct data errors and is widely used in communications and data storage. By attaching additional ECC data to the original data, even if the data is subject to external interference or noise during the transmission process, the receiving end can use the ECC data to correct the error data to the original correct data, thereby reducing the data error. rate.

However, it takes extra time for the system to perform ECC processing to compare and correct the data, which reduces the overall performance of the system. Therefore, there is a need to propose a new technology to solve the above problems.

The invention provides a memory control method and a memory device, which can turn on or off the error correction code (ECC) function of the memory device according to requirements, so that the system achieves a better balance between the running performance and the data correctness. . The present invention also utilizes control parameters stored in the non-volatile memory region and control parameters stored in the volatile memory region to generate ECC control parameters, thereby improving the reliability of the switch ECC function.

According to an embodiment of the present invention, a memory control method is provided, which is applicable to a memory device, including: generating an ECC control parameter according to a non-volatile control parameter and a volatile control parameter, wherein the non-volatile control parameter is stored And in a non-volatile memory area of the memory device, the volatile control parameter is stored in a volatile memory area in the memory device; and an ECC function is controlled according to the ECC control parameter, so that the access is from a memory. The data of a storage location of the cell array is processed with or without ECC functionality.

In accordance with an embodiment of the present invention, a memory device is provided that includes a memory cell array, a control circuit, an ECC correction logic, and an ECC control logic. The control circuit is coupled to the memory array for reading and writing data to a storage location in the memory cell array in response to a memory controller control command. The ECC correction logic is coupled to the memory array for performing an ECC function. The ECC control logic is coupled to the ECC correction logic for generating an ECC control parameter according to a non-volatile control parameter and a volatile control parameter, and controlling the ECC function of the ECC correction logic according to the ECC control parameter to enable access The data from the storage location is processed or not subjected to the ECC function; wherein the non-volatile control parameter is stored in a non-volatile memory region of the memory, and the volatile control parameter is stored in the memory. Memory area.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

In the present description, some embodiments of the invention are described in detail with reference to the drawings, but not all embodiments are illustrated in the drawings. In fact, these inventions may use a variety of different variations and are not limited to the embodiments herein. In contrast, the present disclosure provides these embodiments to meet the statutory requirements of the application. The same reference symbols are used in the drawings to refer to the same or similar elements.

1 is a block diagram of a memory system 100 in accordance with an embodiment of the present invention. The memory system 100 includes a memory controller 102, a first memory device 104, a second memory device 106, and an input/output (I/O) module 108. The memory controller 102 is, for example, a microcontroller (MCU) that can transmit signals through the system bus and the first memory device 104, the second memory device 106, and the input/output module 108.

The first memory device 104 is, for example, a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). The second memory device 106 is, for example, a non-volatile memory such as a flash memory. The input/output module 108 is, for example, a data transmission port.

The second memory device 106 can store data (such as firmware code or code) required by the memory controller 102 to perform functions. In one embodiment, when the memory system 100 is powered on, the memory controller 102 will initially initiate a low-performance mode and execute a hard-wired boot code to The data on the two memory devices 106 is downloaded to the first memory device 104. Next, the memory controller 102 will switch to a high performance mode and execute the data on the first memory device 104 to perform fast fetching. In yet another embodiment, the memory controller 102 can run the code directly from the second memory device 106 to perform related functions.

The memory controller 102 can access data to the first memory device 104 or the second memory device 106 during operation. During the process, the first memory device 104 or the second memory device 106 may select to perform ECC processing on the access data to ensure the correctness of the data based on the planning of the memory controller 102, or select not to perform ECC processing to improve System performance. The ECC processing (the processing based on the ECC function) can be performed based on an arbitrary ECC algorithm, such as a Hamming code algorithm, a BCH code algorithm, etc., which can generate ECC data corresponding to the original data, and after the event Correct errors in the data based on the ECC data.

In an embodiment, the memory controller 102 can plan whether the memory device needs to perform ECC processing on the access data according to the type of data to be accessed. For example, the memory controller 102 can plan the second memory device 106 to turn off the ECC function to stop ECC processing the data when the read/write error tolerance data (such as voice data) is high, thereby improving the overall system. The memory controller 102 can also schedule the second memory device 106 to perform ECC processing on the data to ensure the correctness of the data when the read/write error tolerates lower data.

FIG. 2 is a block diagram of a memory device 200 having an ECC function. The memory device 200 may be the first memory device 104 or the second memory device 106 in FIG.

The memory device 200 mainly includes a memory cell array 202, a control circuit 204, an ECC correction logic 206, and an ECC control logic 208, wherein the ECC correction logic 206 and the ECC control logic 208 can be implemented, for example, by a hardware logic circuit or a software program.

The memory device 200 further includes a transmission interface 210, for example, a data transmission port, which is mainly responsible for data transmission between the memory device 200 and external components such as the memory controller 102. The transmission interface 210 can be turned on (enabled) or turned off (disabled) in response to the control signal of the control circuit 204. When the transmission interface 210 is turned on, the transmission interface 210 will transmit data with the memory controller 102, and vice versa.

User data and ECC data are stored in the memory cell array 202. For example, if the user data to be written into the memory cell array 202 is processed by the ECC function and stored in the memory cell array 202, the user data and its corresponding ECC data will be included in the memory cell array 202.

The control circuit 204 is coupled to the memory cell array 202 and can read and write data to a storage location ADD in the memory cell array 202 in response to the control command of the memory controller 102.

The ECC correction logic 206 is coupled to the memory cell array 202 for performing an ECC function to perform ECC processing on a data to be written or read from the storage location ADD. For example, the ECC correction logic 206 can perform ECC processing on a data to be written to generate ECC data corresponding to the data to be written, and store the to-be-written data and the ECC data thereof into the memory cell array 202. .

The ECC control logic 208 can output an inhibited (or enabled) ECC control parameter based on the programming of the memory controller 102, causing the ECC correction logic 206 to turn the ECC function off (or on).

Taking a read operation as an example, the control circuit 204 first reads the user data from the storage location ADD of the memory cell array 202 in response to a read command from the memory controller 202. At this point, the user profile and its corresponding ECC profile will be sent to the ECC correction logic 206.

If the ECC function is enabled, the ECC correction logic 206 will perform ECC processing on the user data based on the ECC data to check and correct errors in the data. User data processed by the ECC function will be provided to the memory controller 102 via the transport interface 210. Conversely, if the ECC function is disabled, the ECC correction logic 206 will not perform ECC processing on the user profile, and the user profile not processed by the ECC function will be provided to the memory controller 102 directly via the transmission interface 210.

Correspondingly, in a write operation, if the ECC function is on, the ECC correction logic 206 will perform ECC processing on a to-be-written material and generate corresponding ECC data. Then, the to-be-written material and its corresponding ECC data will be written to the memory cell array 202. Conversely, if the ECC function is turned off, the ECC correction logic 206 will not perform ECC processing on the data to be written, so no ECC data corresponding to the data to be written is generated. At this time, the to-be-written data will be directly written into the memory cell array 202.

FIG. 3 is a partial schematic view of a memory device 200 in accordance with an embodiment of the present invention. In the example of FIG. 3, ECC control logic 208 can generate an ECC control parameter for the entire region of memory cell array 202. That is, when the ECC control logic 208 responds to the ECC control parameters and turns off the ECC function, all data to be written or read from the memory cell array 202 is not processed by the ECC function. Conversely, when the ECC control logic 208 responds to the ECC control parameters and turns on the ECC function, the ECC correction logic 206 will perform an ECC operation on all data to be written or read from the memory cell array 202, regardless of the storage location ADD corresponding to the data. Why?

FIG. 4 is a partial schematic view of a memory device 200 in accordance with another embodiment of the present invention. In the example of FIG. 4, the ECC control logic 208 is provided with corresponding ECC control parameters for each of the memory cells in the memory cell array 202, such that the ECC correction logic 206 can only turn the ECC function on or off for a portion of the memory cells.

The memory unit may be a block, a sector, a page, a word line, etc., depending on the actual application. For example, if the memory cell array 202 includes a first memory unit (such as a first sector) and a second memory unit (such as a second sector), the ECC control logic 208 will provide a first ECC control for the first memory unit. Parameters, and a second ECC control parameter is provided for the second memory unit. When the storage location ADD corresponding to the access data belongs to the first memory unit, the ECC control logic 208 will use the first ECC control parameter as the ECC control parameter to enable or disable the ECC function of the ECC correction logic 206; The corresponding storage location ADD belongs to the second memory unit, and the ECC control logic 208 will turn the ECC function of the ECC correction logic 206 on or off with the second ECC control parameter as the ECC control parameter.

According to an embodiment of the present invention, the ECC control logic 208 can utilize control data (hereinafter referred to as non-volatile control parameters) stored in the non-volatile memory area of the memory device 200 and control data stored in the volatile memory area (hereinafter referred to as volatilization). Sex control parameters) to generate ECC control parameters. The non-volatile memory area refers to a memory area of the memory device 200 that can retain data after power-off, and has a non-volatile memory structure, and the volatile memory area refers to a memory device. A memory area in 200 that cannot maintain data after a power failure, such as a scratchpad or other volatile memory.

The mechanism for generating ECC control parameters will be described below in conjunction with the non-limiting embodiments shown in Figures 5-7.

Figure 5 is a schematic diagram of ECC control logic in accordance with an embodiment of the present invention. The ECC control logic is, for example, but not limited to, the ECC control logic 208 shown in FIG.

In this example, ECC control logic 208 includes AND logic gate 502 for AND logic operations on non-volatile control parameters and volatile control parameters to generate ECC control parameters. The values of the non-volatile control parameters and the volatility control parameters may be planned in advance by the memory controller 102 or may be dynamically adjusted afterwards.

Since the non-volatile control parameters are stored in the non-volatile memory area, the data is not easily changed. Therefore, if the non-volatile control parameters have been planned to be disabled (such as bit "0"), even if the volatile control parameters are in operation The ECC control parameter output by the AND logic gate 502 can still be stably maintained in the same disable state as the non-volatile control parameter, so that the ECC correction logic 206 is enabled by the malfunction (such as the bit "1"). Turn off the ECC function. In other words, the ECC control logic implemented with AND logic gate 502 can be applied to situations where the ECC correction logic 206 is turned off to turn off the ECC function.

Figure 6 is a schematic diagram showing ECC control logic in accordance with another embodiment of the present invention. The ECC control logic is, for example, but not limited to, the ECC control logic 208 shown in FIG.

In this example, the ECC control logic includes an OR logic gate 602 for OR logic operations on the non-volatile control parameters and the volatility control parameters to generate ECC control parameters.

As mentioned above, since the non-volatile control parameters are stored in the non-volatile memory area, the data is less likely to be changed. Therefore, if the non-volatile control parameters have been planned to be enabled (such as bit "1"), even if volatilized The control parameters are erroneously changed into the disabled state during operation (such as bit "0"), and the ECC control parameters output by the OR logic gate 602 can be stably maintained in the enabled state, so that the ECC correction logic 206 turns on the ECC function. .

Alternatively, if the non-volatile control parameter has been previously scheduled to be off (eg, bit "0"), if the memory controller 102 needs to have the ECC correction logic 206 turn on its ECC function during operation, simply control the volatility The parameter is set to enable state (such as bit "1"). In other words, the ECC control logic implemented with OR logic gate 602 can be applied to situations where the ECC correction logic 206 is turned on to turn on the ECC function.

FIG. 7 is a schematic diagram showing ECC control logic according to another embodiment of the present invention. The ECC control logic is, for example, but not limited to, the ECC control logic 208 shown in FIG.

In this example, ECC control logic 208 includes a register 702. When the power is turned on (or other preset time point), the non-volatile control parameters are first loaded into the register 702 as a volatile control parameter. The volatility control parameters stored in the register 702 can be directly used as ECC control parameters. Thereafter, the memory controller 102 can update the value of the volatile control parameter in the register 702 through a planning command to control whether to turn the ECC function on or off.

In another embodiment, as shown in FIG. 8, the control circuit 204 responds to a detection command of the memory controller 102 to detect a valve voltage distribution of a memory cell (eg, a distribution "0" or a distribution "1"). And determine whether the valve voltage distribution falls within a valve voltage interval MR. When the valve voltage distribution falls within the valve voltage interval MR, it indicates that the margin of the memory cell is insufficient, which is easy to cause erroneous reading. At this time, the ECC control logic 208 outputs the enabled ECC control parameter to turn on the memory. The ECC function of the body device 200, thereby improving the correctness of data access. In an embodiment, the control circuit 204 detects the valve voltage distribution of each memory cell in a memory page based on the detection command, and if any of the memory cell valve voltage distribution falls within the valve voltage interval MR, the ECC control Logic 208 will output the enabled ECC control parameters to turn on the ECC function.

Conversely, when the valve voltage distribution does not fall within the valve voltage interval MR, the ECC control logic 208 will output the disabled ECC control parameters to turn off the ECC function of the memory device 200, thereby increasing system efficiency.

For example, suppose the upper and lower limits of the valve voltage interval MR are X1 and X2 volts respectively. If the valve voltage of any memory cell falls within the valve voltage range MR (X1 < memory cell voltage < X2), misinterpretation may occur. The ECC control logic 208 will output the enabled ECC control parameters to turn on the ECC function. Conversely, the valve voltage of any memory cell falls within the valve voltage interval MR (all memory cell voltages are >X1 or <X2), indicating that the read margin of the memory cell is sufficient, and the ECC control logic 208 The disabled ECC control parameters will be output to turn off the ECC function. The timing of detecting the voltage of the valve may be a detection command when the power is turned on or when the memory device is idle or connected to the memory controller 102.

FIG. 9 is a flow chart showing a memory control method according to an embodiment of the present invention.

In step 902, the memory device 200 generates an ECC control parameter according to the non-volatile control parameter and the volatile control parameter, wherein the non-volatile control parameter is stored in a non-volatile memory region in the memory device 200, and the volatile control parameter is stored. A volatile memory area in the memory device 200.

At step 904, the memory device 200 controls an ECC function in accordance with the ECC control parameters such that data accessed from the storage location ADD of the memory cell array 202 is processed or not processed by the ECC function.

In summary, the present invention provides a memory control method and a memory device, which can turn on or off the ECC function of the memory device according to requirements, so that the system achieves a better balance between operational performance and data correctness. The present invention also utilizes control parameters stored in the non-volatile memory region and control parameters stored in the volatile memory region to generate ECC control parameters, thereby improving the reliability of the switch ECC function.

While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧ memory system
102‧‧‧ memory controller
104‧‧‧First memory device
106‧‧‧Second memory device
108‧‧‧Input/Output (I/O) Module
200‧‧‧ memory device
202‧‧‧ memory cell array
204‧‧‧Control circuit
206‧‧‧ECC Correction Logic
208‧‧‧ECC Control Logic
210‧‧‧Transport interface
ADD‧‧‧ storage location
502‧‧‧AND logic gate
602‧‧‧OR logic gate
702‧‧‧ 存存器
902, 904‧‧ steps

1 is a block diagram of a memory system in accordance with an embodiment of the present invention. Figure 2 is a block diagram of a memory device having an ECC function. 3 is a partial schematic view of a memory device in accordance with an embodiment of the present invention. 4 is a partial schematic view of a memory device in accordance with another embodiment of the present invention. Figure 5 is a schematic diagram of ECC control logic in accordance with an embodiment of the present invention. Figure 6 is a schematic diagram showing ECC control logic in accordance with another embodiment of the present invention. FIG. 7 is a schematic diagram showing ECC control logic according to another embodiment of the present invention. Figure 8 is a schematic diagram showing the valve voltage distribution of the memory cell. FIG. 9 is a flow chart showing a memory control method according to an embodiment of the present invention.

902, 904‧‧ steps

Claims (16)

A memory control method, applicable to a memory device, comprising: generating an Error Correcting Codes (ECC) control parameter according to a non-volatile control parameter and a volatile control parameter, wherein the non-volatile control parameter is stored And in a non-volatile memory area of the memory device, the volatile control parameter is stored in a volatile memory area in the memory device; and an ECC function is controlled according to the ECC control parameter, so that the access is from a memory. The data of a storage location of the cell array is processed with or without the ECC function. The memory control method of claim 1, wherein controlling the ECC function further comprises: when the ECC function is turned off by using the ECC control parameter, the data accessed from the storage location of the memory cell array is not ECC function processing. The memory control method of claim 1, wherein controlling the ECC function further comprises: when the ECC function is enabled by using the ECC control parameter, accessing the data from the storage location of the memory cell array through the ECC Functional processing. The memory control method of claim 1, wherein the memory cell array comprises a first memory unit and a second memory unit, the memory control method further comprising: setting a first memory unit An ECC control parameter; a second ECC control parameter is set for the second memory unit; when the storage location corresponding to the data belongs to the first memory unit, the first ECC control parameter is used as the ECC control parameter; The storage location corresponding to the data belongs to the second memory unit, and the second ECC control parameter is used as the ECC control parameter. The memory control method of claim 1, further comprising: performing an AND logic operation on the non-volatile control parameter and the volatile control parameter through an AND gate to generate the ECC control parameter. . The memory control method of claim 1, further comprising: performing an OR logic operation on the non-volatile control parameter and the volatile control parameter through an OR logic gate to generate the ECC control parameter. . The memory control method according to claim 1, further comprising: loading the non-volatile control parameter into a register as the volatile control parameter, and storing the volatile in the register The control parameter is used as the ECC control parameter; and the value of the volatile control parameter is updated in response to a planning instruction to control whether the ECC function is turned on or off. The memory control method of claim 1, further comprising: detecting a valve voltage distribution of a memory cell; determining whether the valve voltage distribution falls within a valve voltage interval; when the valve voltage distribution falls within the The valve voltage interval is opened by the ECC control parameter; and when the valve voltage distribution does not fall within the valve voltage interval, the ECC function is turned off by the ECC control parameter. A memory device includes: a memory cell array; a control circuit coupled to the memory array for responding to a memory controller control command to read and write data to a storage location in the memory cell array; An Error Correcting Codes (ECC) correction logic coupled to the memory array for performing an ECC function; and an ECC control logic coupled to the ECC correction logic for utilizing a non-volatile control parameter And a volatility control parameter generating an ECC control parameter, and controlling the ECC function of the ECC correction logic according to the ECC control parameter, so that data accessed from the storage location of the memory cell array is processed by or without the ECC function The non-volatile control parameter is stored in a non-volatile memory area in the memory, and the volatile control parameter is stored in a volatile memory area in the memory. The memory device of claim 9, wherein when the ECC control logic returns to the ECC control parameter to turn off the ECC function, the data accessed from the storage location of the memory cell array is not processed by the ECC function. . The memory device of claim 9, wherein when the ECC control logic returns to the ECC control parameter to enable the ECC function, the data accessed from the storage location of the memory cell array is processed by the ECC function. The memory device of claim 9, wherein the memory cell array comprises a first memory unit and a second memory unit, the ECC control logic is provided with a first ECC control parameter for the first memory unit, And providing a second ECC control parameter for the second memory unit; wherein when the storage location corresponding to the data belongs to the first memory unit, the ECC control logic uses the first ECC control parameter as the ECC control parameter, when The storage location corresponding to the data belongs to the second memory unit, and the ECC control logic uses the second ECC control parameter as the ECC control parameter. The memory device of claim 9, wherein the ECC control logic includes an AND logic gate for performing an AND logic operation on the non-volatile control parameter and the volatile control parameter to generate The ECC control parameters. The memory device of claim 9, wherein the ECC control logic comprises an OR logic gate for performing an OR logic operation on the non-volatile control parameter and the volatile control parameter, This ECC control parameter is generated. The memory device of claim 9, wherein the ECC control logic comprises a register, and when the power is turned on, the non-volatile control parameter is loaded into the register as the Volatile ECC control parameter, the volatile ECC control parameter stored in the register is used as the ECC control parameter; wherein the volatile ECC control parameter stored in the register is in response to the memory controller Updated by planning instructions. The memory device of claim 9, wherein the control circuit returns a detection command of the memory controller, detects a valve voltage distribution of a memory cell, and determines whether the valve voltage distribution falls. Within a valve voltage interval; when the valve voltage distribution falls within the valve voltage interval, the ECC control logic outputs the enabled ECC control parameter to turn on the ECC function when the valve voltage distribution does not fall within the valve voltage interval The ECC control logic outputs the disabled ECC control parameter to turn off the ECC function.