CN112988076B - Flash memory control method, storage device and controller - Google Patents

Abstract

The invention provides a flash memory control method, a flash memory storage device and a flash memory controller. The method comprises the following steps: instructing the flash memory module to perform a data merging operation to copy the first data in the first physical unit to at least one second physical unit; performing a programming operation on the first physical unit after copying the first data and before erasing the first physical unit to change the data storage state of at least part of the memory cells in the first physical unit from a first state to a second state; and after programming the first entity unit, executing erasing operation on the first entity unit. Therefore, the data writing quality of the erased memory cell can be improved.

Description

Flash memory control method, storage device and controller

Technical Field

The present invention relates to a memory control technology, and more particularly, to a flash memory control method, a flash memory storage device, and a flash memory controller.

Background

Portable electronic devices such as mobile phones and notebook computers have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable electronic devices.

The memory cells in the rewritable nonvolatile memory module are used for storing data by injecting charges into the memory cells. However, the charge injected into the memory cell may be lost as the data storage time increases, the data access operation increases, and/or the temperature changes. The lost charge may be used to combat erase voltages during subsequent erasing of the memory cell, and the like, resulting in reduced erase efficiency of the memory cell. Later, when new data is required to be written into the erased memory cell, the data writing quality may be poor because the data in the memory cell is not erased cleanly.

Disclosure of Invention

The invention provides a flash memory control method, a flash memory storage device and a flash memory controller, which can improve the data writing quality after a storage unit is erased.

An exemplary embodiment of the present invention provides a flash memory control method, which includes: instructing a flash memory module in a flash memory storage device to perform a data merging operation to copy first data in a first physical unit of a plurality of physical units of the flash memory module into at least a second physical unit of the plurality of physical units; after copying the first data in the first entity unit to the at least one second entity unit and before performing an erasing operation on the first entity unit, performing a programming operation on the first entity unit again to change a data storage state of at least part of memory cells in the first entity unit from a first state to a second state; and after programming the first entity unit, executing the erasing operation on the first entity unit.

The exemplary embodiments of the present invention further provide a flash memory storage device, which includes a connection interface unit, a flash memory module, and a flash memory controller. The connection interface unit is used for being connected to a host system. The flash memory module includes a plurality of physical units. The flash memory controller is connected to the connection interface unit and the flash memory module. The flash memory controller is used for executing data merging operation so as to copy first data in a first entity unit in the plurality of entity units into at least one second entity unit in the plurality of entity units. The flash memory controller is further configured to re-perform a programming operation on the first physical unit after copying the first data in the first physical unit to the at least one second physical unit and before performing an erasing operation on the first physical unit, so as to change a data storage state of at least a portion of the memory cells in the first physical unit from a first state to a second state. The flash memory controller is further configured to perform the erase operation on the first physical unit after programming the first physical unit.

The exemplary embodiments of the present invention further provide a flash memory controller for controlling a flash memory module. The flash memory module includes a plurality of physical units. The flash memory controller includes a host interface, a memory interface, and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the flash memory module. The memory management circuit is connected to the connection interface unit and the flash memory module. The memory management circuit is used for executing data merging operation so as to copy first data in a first entity unit in the plurality of entity units into at least one second entity unit in the plurality of entity units. The memory management circuit is further configured to re-perform a programming operation on the first physical unit after copying the first data in the first physical unit to the at least one second physical unit and before performing an erasing operation on the first physical unit, so as to change a data storage state of at least part of the memory cells in the first physical unit from a first state to a second state. The memory management circuit is further configured to perform the erase operation on the first physical unit after programming the first physical unit.

In an example embodiment of the present invention, the programming operation includes: programming the first entity unit according to preset data.

In an example embodiment of the present invention, the programming operation includes: programming the first entity unit according to a preset programming mode.

In an exemplary embodiment of the present invention, the predetermined programming mode includes a single level memory cell mode.

In an example embodiment of the present invention, the programming operation includes: and converting at least one memory cell in the first physical unit from an erasing state to a programming state.

In an exemplary embodiment of the present invention, the programming operation is used to ensure that each memory cell in the first physical unit is in a programmed state before erasing the first physical unit.

Based on the above, after copying the first data from the first physical unit to the second physical unit in the flash memory module and before performing the erase operation on the first physical unit, the first physical unit may be programmed to change the data storage state of at least part of the memory cells in the first physical unit. After changing the data storage state of the memory cell, an erase operation may be performed on the first physical unit. Therefore, the data writing quality of the erased memory cells in the first physical unit can be improved.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an example embodiment of the invention;

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a data merge operation in accordance with an exemplary embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating programming a first physical unit and associating the first physical unit to an idle region according to an exemplary embodiment of the present invention;

FIG. 9A is a schematic diagram illustrating a threshold voltage distribution of memory cells in a first physical cell according to an example embodiment of the invention;

FIG. 9B is a schematic diagram illustrating the threshold voltage distribution of memory cells in a first physical unit programmed according to an example embodiment of the invention;

fig. 10 is a flowchart illustrating a flash memory control method according to an exemplary embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system such that the host system may write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be connected to a system bus 110.

In an example embodiment, host system 11 may be coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. In addition, host system 11 may be connected to I/O device 12 via system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In an exemplary embodiment, the processor 111, the ram 112, the rom 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 by a wired or wireless means through the data transfer interface 114.

In an example embodiment, the memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless fidelity (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (such as iBeacon) or the like based on a wide variety of wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention. Referring to fig. 3, in an exemplary embodiment, the host system 31 may be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. The memory storage device 30 may be a variety of nonvolatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by a host system 31. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342 that directly connect the memory module to a substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 402. In an example embodiment, the connection interface unit 402 is compatible with the serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a standard compliant with a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a High-Speed peripheral component interconnect (Peripheral Component Interconnect Express, PCI Express) standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, s) interface standard, an ehcp interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in a single chip, or the connection interface unit 402 may be disposed off-chip with the memory control circuit unit 404.

The memory control circuit unit 404 is connected to the connection interface unit 402 and the rewritable nonvolatile memory module 406. The memory control circuit unit 404 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 406 is used to store data written by the host system 11. The rewritable nonvolatile memory module 406 may include a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a second-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a fourth-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. By applying the read voltage, it can be determined which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In an example embodiment, the memory cells of the rewritable nonvolatile memory module 406 may constitute a plurality of physical program cells, and the physical program cells may constitute a plurality of physical erase cells. Specifically, memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is the subordinate entity programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is the subordinate entity programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In an exemplary embodiment, the physical programming unit is a minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and a physical sector has a size of 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to FIG. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, and an error checking and correcting circuit 508.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform writing, reading and erasing operations of data while the memory storage device 10 is operating. The operation of the memory management circuit 502 is described as follows, which is equivalent to the description of the operation of the memory control circuit unit 404.

In an example embodiment, the control instructions of memory management circuitry 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In an example embodiment, the control instructions of the memory management circuit 502 may also be stored in program code form in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit 404 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

In an example embodiment, the control instructions of the memory management circuitry 502 may also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage memory cells or groups of memory cells of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read instruction sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erase circuit is configured to issue an erase command sequence to the rewritable nonvolatile memory module 406 to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 406 to perform the corresponding write, read, erase, etc. In an example embodiment, the memory management circuitry 502 may also issue other types of sequences of instructions to the rewritable non-volatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is coupled to the memory management circuitry 502. The memory management circuitry 502 may communicate with the host system 11 through a host interface 504. The host interface 504 is used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transferred by host system 11 may be transferred to memory management circuitry 502 via host interface 504. In addition, the memory management circuitry 502 may communicate data to the host system 11 through the host interface 504. In the present exemplary embodiment, host interface 504 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with PATA standards, IEEE 1394 standards, PCI Express standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 506 is coupled to the memory management circuitry 502 and is used to access the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format acceptable to the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 is to access the rewritable nonvolatile memory module 406, the memory interface 506 will transmit the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These sequences of instructions are, for example, generated by memory management circuitry 502 and transferred to rewritable non-volatile memory module 406 through memory interface 506. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.

Error checking and correction circuitry (also referred to as decoding circuitry) 508 is coupled to the memory management circuitry 502 and is configured to perform error checking and correction operations to ensure the correctness of the data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 406. Then, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 508 performs an error check and correction operation on the read data according to the error correction code and/or the error check code.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 510 and a power management circuit 512. The buffer memory 510 is connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is coupled to the memory management circuit 502 and is used to control the power of the memory storage device 10.

In an example embodiment, the memory storage device 10 of fig. 4 is also referred to as a flash memory device, the rewritable non-volatile memory module 406 is also referred to as a flash memory module, and the memory control circuit unit 404 is also referred to as a flash memory controller for controlling the flash memory module. In an example embodiment, the memory management circuit 502 of FIG. 5 is also referred to as a flash memory management circuit.

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention. Referring to FIG. 6, the memory management circuit 502 can logically group the physical units 610 (0) -610 (C) in the rewritable nonvolatile memory module 406 into a memory area 601, a spare (spare) area 602 and a system area 603. The entity units 610 (0) to 610 (a) in the storage area 601 store data (e.g., user data from the host system 11 of fig. 1). For example, the entity units 610 (0) to 610 (a) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610 (a+1) -610 (B) in the free area 602 are not yet used to store data (e.g., valid data). The entity units 610 (b+1) -610 (C) in the storage area 603 are configured to store management information (also referred to as system data), such as a logical-to-entity mapping table, a bad block management table, a device model, or other types of management information.

When data is to be stored, the memory management circuit 502 may select one entity from the entity units 610 (a+1) to 610 (B) of the spare area 602 and store data from the host system 11 or from at least one entity in the storage area 601 into the selected entity. At the same time, the selected entity units may be associated to the storage area 601. In addition, if a certain entity in the storage area 601 does not store valid data (i.e., only stores invalid data), the entity can be re-associated to the free area 602.

In an exemplary embodiment, each physical unit belonging to the memory area 601 is also referred to as a non-idle (non-spare) physical unit, and each physical unit belonging to the idle area 602 is also referred to as an idle physical unit. In addition, a physical cell may include one or more physical erase units.

The memory management circuit 502 may configure the logic units 612 (0) -612 (D) to map the physical units 610 (0) -610 (A) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (Logical Block Address, LBAs) or other logical management units. In another exemplary embodiment, a logic cell may also correspond to a logic program cell, a logic erase cell, or be composed of a plurality of consecutive or non-consecutive logic addresses. In addition, each of logic cells 612 (0) -612 (D) may be mapped to one or more physical cells. It should be noted that in an exemplary embodiment, the memory management circuit 502 may not be configured with logic units mapped to the system area 603, so as to prevent the management information stored in the system area 603 from being modified by a user.

The memory management circuit 502 may record a mapping relationship (also referred to as logic-to-entity mapping information) between the logic units and the entity units in at least one logic-to-entity mapping table. The logical to physical mapping table is stored in the physical unit of the system area 603. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform a data access operation to the memory storage device 10 according to the logical-to-physical mapping table.

In an exemplary embodiment, valid data is the most current data belonging to a certain logical unit, and invalid data is not the most current data belonging to any logical unit. For example, if the host system 11 stores a new data to a logical unit and overwrites old data originally stored by the logical unit (i.e., updates data belonging to the logical unit), the new data stored in the storage area 601 is the latest data belonging to the logical unit and is marked as valid, and the overwrites old data may still be stored in the storage area 601 but marked as invalid.

In an exemplary embodiment, if the data pertaining to a logical unit is updated, the mapping between the logical unit and the physical unit storing the old data pertaining to the logical unit is removed, and the mapping between the logical unit and the physical unit storing the latest data pertaining to the logical unit is established. However, in another exemplary embodiment, if the data pertaining to a logical unit is updated, the mapping relationship between the logical unit and the physical unit storing the old data pertaining to the logical unit may still be maintained.

When the memory storage device 10 leaves the factory, the total number of physical units belonging to the idle area 602 is a predetermined number (e.g., 30). In operation of the memory storage device 10, more and more physical units are selected from the inactive area 602 and associated with the memory area 601 to store data (e.g., user data from the host system 11). Therefore, the total number of physical units belonging to the spare area 602 gradually decreases with the use of the memory storage device 10.

In operation of the memory storage device 10, the memory management circuit 502 can continuously update the total number of physical units belonging to the idle region 602. The memory management circuit 502 may perform a data merge operation based on the number of physical units in the free area 602 (i.e., the total number of free physical units). For example, the memory management circuit 502 may determine whether the total number of physical units belonging to the idle region 602 is less than or equal to a threshold (also referred to as a first threshold). The first threshold is, for example, 2 or greater (e.g., 10), and the present invention is not limited. If the total number of physical units belonging to the idle area 602 is less than or equal to the first threshold, the memory management circuit 502 may perform the data merging operation. In an example embodiment, the data consolidation operation is also referred to as a garbage collection (garbage collection) operation.

In a data merge operation, the memory management circuit 502 may select at least one physical unit (also referred to as a source block) from the memory area 601 and attempt to copy valid data from the selected physical unit to another physical unit (also referred to as a target block). The entity unit for storing the copied valid data is selected from the free area 602 and may be associated to the storage area 601. If the valid data stored in a particular physical cell has been copied to the target block, the physical cell may be associated with the spare area 602 and erased for the next use.

In an exemplary embodiment, the re-association of a physical unit from the memory area 601 to the spare area 602 (or the erasing of a physical unit) is also referred to as releasing a spare physical unit. By performing the data merge operation, one or more idle physical units are released and the total number of physical units belonging to the idle region 602 is gradually increased.

After the data merging operation is started, if the physical units belonging to the idle area 602 meet a specific condition, the data merging operation may be stopped. For example, the memory management circuit 502 can determine whether the total number of physical units belonging to the idle area 602 is greater than or equal to a threshold (hereinafter also referred to as a second threshold). For example, the second threshold may be greater than or equal to the first threshold. If the total number of physical units belonging to the idle region 602 is greater than or equal to the second threshold, the memory management circuit 502 may stop the data merge operation. It should be noted that, stopping the data merging operation refers to ending the currently executing data merging operation. After stopping one data merging operation, if the total number of physical units belonging to the idle area 602 is again less than or equal to the first threshold value, the next data merging operation can be performed again to try to release new idle physical units.

Fig. 7 is a schematic diagram illustrating a data merging operation according to an exemplary embodiment of the present invention. Referring to fig. 7, in the data merging operation, entity units 711 (0) to 711 (E) (also referred to as first entity units) may be selected as the source block 710, and entity units 721 (0) to 721 (F) (also referred to as second entity units) may be selected as the target block 720. For example, entity units 711 (0) through 711 (E) may be selected from the memory area 601 of FIG. 6, and entity units 721 (0) through 721 (F) may be selected from the idle area 602 of FIG. 6. The total number of the entity units 711 (0) to 711 (E) and the total number of the entity units 721 (0) to 721 (F) may be any number, and the present invention is not limited thereto.

In the data merge operation, data 701 (also referred to as first data) may be collected by the physical units 711 (0) to 711 (E) of the subordinate source block 710 and copied (e.g., written) into the physical units 721 (0) to 721 (F) of the subordinate target block 720. The copied data 701 may include valid data originally stored in the entity units 711 (0) to 711 (E).

In an example embodiment, in response to data (i.e., valid data) stored by a physical unit in the source block 710 being copied into the target block 720, the memory management circuit 502 may mark the data in the physical unit as invalid during the data merge operation. In addition, in response to all valid data stored by a physical unit in the source block 710 having been copied into the target block 720, the memory management circuit 502 may associate the physical unit with the spare area 602 of FIG. 6. The entity associated with the idle region 602 may become a new idle entity. Before writing new data into the new idle physical unit, the idle physical unit needs to be erased to clear old data.

In an example embodiment, after copying the data 701 (i.e., the first data) in the first physical unit to the second physical unit and before erasing the first physical unit, the memory management circuit 502 may perform the programming operation on the first physical unit again to overwrite at least a portion of the data in the first physical unit. For example, the overwritten data may include invalid data in the first entity unit.

In an exemplary embodiment, a program operation performed again on a first physical unit after copying data 701 (i.e., first data) in the first physical unit to a second physical unit and before erasing the first physical unit may be used to change a data storage state of at least some memory cells in the first physical unit from one state (also referred to as a first state) to another state (also referred to as a second state). For example, assuming that a memory cell in a first physical cell is in a first state (e.g., erased state) before it is erased, the programming operation may be used to change the memory cell from the first state (e.g., erased state) to a second state (e.g., non-erased state).

In an example embodiment, in the programming operation, the memory management circuit 502 may send a sequence of programming instructions (or a sequence of writing instructions) to the rewritable nonvolatile memory module 406 to instruct the rewritable nonvolatile memory module 406 to program the memory cells in the first physical cell. According to the programming instruction sequence (or the writing instruction sequence), the rewritable nonvolatile memory module 406 can apply a programming voltage (or a writing voltage) to the memory cells in the first physical unit to rewrite old data (i.e., invalid data) in the memory cells. It should be noted that in an exemplary embodiment, the old data (i.e. the invalid data) in the memory cells is rewritten before the memory cells are erased, so as to adjust the memory cells at least in the erased state to the non-erased state (also referred to as the programmed state), so as to improve the data writing quality when new data is written into the memory cells after the memory cells are erased later.

In an example embodiment, the programming operation may also be performed automatically by the rewritable nonvolatile memory module 406 without being triggered by a sequence of programming instructions (or a sequence of write instructions) from the memory management circuit 502. For example, in an example embodiment, after the rewritable nonvolatile memory module 406 receives the erase command sequence indicating to erase the first physical unit from the memory management circuit 502, the rewritable nonvolatile memory module 406 may perform the program operation on the first physical unit in response to the erase command sequence to adjust at least the memory cells in the erased state to the non-erased state before actually erasing the first physical unit. After confirming that the memory cells in the first physical cell are all in a non-erased state (i.e., after performing the programming operation), the rewritable nonvolatile memory module 406 can automatically and sequentially perform the erase operation indicated by the erase command sequence to erase the first physical cell. In other words, in an example embodiment, even if the memory management circuit 502 does not send a sequence of programming instructions (or a sequence of writing instructions) to instruct to perform the programming operation, the rewritable nonvolatile memory module 406 may automatically perform the programming operation on the first physical unit before performing the erasing operation on the first physical unit, thereby improving the data writing quality of the subsequent first physical unit.

In an example embodiment, the memory management circuit 502 may perform an erase operation on the first physical unit after performing the programming operation on the first physical unit (i.e., overwriting the invalid data in the first physical unit). For example, in this erase operation, the memory management circuit 502 may send a sequence of erase instructions to the rewritable nonvolatile memory module 406 to instruct the rewritable nonvolatile memory module 406 to apply erase voltages to the memory cells in the first physical cell to erase data in the memory cells.

FIG. 8 is a schematic diagram illustrating programming a first physical unit and associating the first physical unit to an idle region according to an exemplary embodiment of the present invention. Referring to fig. 8, in the exemplary embodiment of fig. 7, after the valid data stored in the entity units 711 (0) to 711 (E) (i.e., the first entity unit) in the source block 710 are copied to the target block 720, all the data in the entity units 711 (0) to 711 (E) are marked as invalid (i.e., become invalid data). Then, before associating the entity units 711 (0) to 711 (E) to the idle area 602, the entity units 711 (0) to 711 (E) are programmed to overwrite the data (i.e. invalid data) in the entity units 711 (0) to 711 (E). After programming the physical cells 711 (0) -711 (E), the physical cells 711 (0) -711 (E) may be associated with the inactive area 602 and subsequently erased.

It should be noted that although the example embodiment of fig. 8 is exemplified by programming the first physical unit and then associating the first physical unit to the idle zone 602. However, in another exemplary embodiment, the first entity may be associated with the idle area 602 before the first entity is programmed, or the first entity may be associated with the idle area 602 at the same time as the first entity is programmed, so long as the first entity is ensured to be programmed before being erased.

In an example embodiment, if the first physical unit is not being subjected to the programming operation, the memory management circuitry 502 may suspend (or temporarily disallow) associating the first physical unit to the idle zone 602. In an example embodiment, if the first physical unit is not performing the programming operation, the memory management circuit 502 may suspend (or temporarily disallow) performing the erase operation on the first physical unit. In an example embodiment, the memory management circuitry 502 associates only (or only allows) the first physical unit that has performed the programming operation to the idle region 602. In an example embodiment, the memory management circuit 502 performs the erase operation only (or only allows) for the first physical unit on which the program operation has been performed.

In an exemplary embodiment, if all the memory cells in the first physical unit to be erased are in a programmed state (i.e., a programmed state), the data writing quality when new data is written into the memory cells after the memory cells are erased later can be relatively better. Conversely, if all the memory cells in the first physical unit to be erased are not in the programmed state, the data writing quality when new data is written into the memory cells after the memory cells are erased later may be relatively poor.

In an exemplary embodiment, the programming operation performed prior to erasing the first physical cell may be used to transition at least one memory cell in the first physical cell from an erased state to the programmed state. Alternatively, in another aspect, the programming operation performed on the first physical unit prior to erasing the first physical unit may be used to ensure that each memory cell in the first physical unit is in the programmed state prior to erasing the first physical unit. Therefore, after the memory cells in the first physical unit are actually erased, the data writing quality when new data is written into the memory cells can be improved.

In an example embodiment, the memory management circuit 502 may instruct the rewritable nonvolatile memory module 406 to program the first physical cell according to a predetermined data during the programming operation performed before erasing the first physical cell. For example, the default data may be nonsensical data or dummy data (dummy data). For example, this default data is not user data stored by the host system (e.g., host system 11 of FIG. 1) or system data of the memory storage device 10 itself. After the first physical unit is programmed according to the preset data, the data in the first physical unit is still invalid and can wait to be erased.

In an example embodiment, the memory management circuit 502 may instruct the rewritable nonvolatile memory module 406 to program the first physical cell according to a predetermined programming mode during the programming operation performed prior to erasing the first physical cell. For example, the predetermined programming mode may include a single level memory cell (SLC) mode or other programming modes. The predetermined programming pattern may be the same as or different from the programming pattern used last time the user data (i.e. valid data) was written to the first physical unit.

FIG. 9A is a schematic diagram illustrating a threshold voltage distribution of memory cells in a first physical cell according to an example embodiment of the invention. Referring to fig. 9A, it is assumed that a certain first physical unit stores only invalid data (or does not store valid data), and the threshold voltage distribution of a plurality of memory cells in the first physical unit is shown as distribution 91. In distribution 91, the current state of a portion of the memory cells in the first physical cell is an erased state (Er) and the current state of another portion of the memory cells in the first physical cell is a programmed state (P).

FIG. 9B is a schematic diagram illustrating the threshold voltage distribution of memory cells in a first physical unit after programming according to an exemplary embodiment of the present invention. Referring to FIG. 9B, following the example embodiment of FIG. 9A, after performing the programming operation on the first physical unit, the memory cell originally having the erase state (Er) in the first physical unit may be separated from the erase state (Er). For example, a memory cell that is out of the erased state (Er) may be transitioned to have the programmed state (P).

It should be noted that fig. 9A and 9B illustrate the programming operation using a single level memory cell (SLC) mode as an example. However, in another exemplary embodiment, the programming operation performed before erasing the first physical unit may also be performed based on other programming modes, which is not limited by the present invention. For example, in an exemplary embodiment, the programming operation performed before erasing the first physical cell may be performed so long as the memory cell in the first physical cell that is in the erased state first is separated from the erased state.

Fig. 10 is a flowchart illustrating a memory control method according to an example embodiment of the present invention. Referring to fig. 10, in step S1001, a data merging operation is performed on the flash memory module to copy first data in a first physical unit of the flash memory module to at least one second physical unit of the flash memory module. After copying the first data in the first physical unit to the at least one second physical unit and before performing an erase operation on the first physical unit, in step S1002, a program operation is performed on the first physical unit to change a data storage state of at least a portion of memory cells in the first physical unit from a first state to a second state. After programming the first physical unit, in step S1003, the erase operation is performed on the first physical unit.

However, the steps in fig. 10 are described in detail above, and will not be described again here. It should be noted that each step in fig. 10 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 10 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.

In summary, after the valid data in the first physical unit is completely copied to the target block in the data merging operation, the first physical unit needs to be programmed first and then (allowed to) erased. Therefore, the data writing quality of the first entity unit when the first entity unit is extracted from the idle area to store new data can be improved.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (15)

1. A method for controlling a flash memory, comprising:

instructing a flash memory module in a flash memory storage device to perform a data merging operation to copy first data in a first physical unit of a plurality of physical units of the flash memory module into at least a second physical unit of the plurality of physical units;

After copying the first data in the first entity unit to the at least one second entity unit and before performing an erasing operation on the first entity unit, performing a programming operation on the first entity unit again to convert at least part of memory units in the first entity unit from an erasing state to a programming state; and

after programming the first physical unit, the erase operation is performed on the first physical unit.

2. The flash memory control method of claim 1, wherein the programming operation comprises:

programming the first entity unit according to preset data.

3. The flash memory control method of claim 1, wherein the programming operation comprises:

programming the first entity unit according to a preset programming mode.

4. The method of claim 3, wherein the pre-programmed pattern comprises a single level memory cell pattern.

5. The method of claim 1, wherein the programming operation is used to ensure that each memory cell of the first physical unit is in the programmed state prior to erasing the first physical unit.

6. A flash memory storage device, comprising:

a connection interface unit for connecting to a host system;

a flash memory module, wherein the flash memory module comprises a plurality of physical units; and

a flash memory controller connected to the connection interface unit and the flash memory module,

wherein the flash memory controller is used for executing data merging operation to copy first data in a first entity unit in the plurality of entity units to at least one second entity unit in the plurality of entity units,

the flash memory controller is further configured to re-perform a programming operation on the first physical unit after copying the first data in the first physical unit to the at least one second physical unit and before performing an erasing operation on the first physical unit, to convert at least part of the memory cells in the first physical unit from an erasing state to a programming state, and

the flash memory controller is further configured to perform the erase operation on the first physical unit after programming the first physical unit.

7. The flash memory storage device of claim 6, wherein the programming operation comprises:

Programming the first entity unit according to preset data.

8. The flash memory storage device of claim 6, wherein the programming operation comprises:

programming the first entity unit according to a preset programming mode.

9. The flash memory storage device of claim 8, wherein the pre-programmed pattern comprises a single level memory cell pattern.

10. The flash memory storage device of claim 6, wherein the programming operation is to ensure that each memory cell in the first physical cell is in the programmed state prior to erasing the first physical cell.

11. A flash memory controller for controlling a flash memory module, wherein the flash memory module comprises a plurality of physical units, and the flash memory controller comprises:

a host interface for connecting to a host system;

a memory interface for connecting to the flash memory module; and

a memory management circuit coupled to the host interface and the memory interface,

wherein the memory management circuit is configured to perform a data merging operation to copy first data in a first entity unit of the plurality of entity units to at least a second entity unit of the plurality of entity units,

The memory management circuit is further configured to re-perform a programming operation on the first physical unit after copying the first data in the first physical unit to the at least one second physical unit and before performing an erasing operation on the first physical unit, to convert at least part of the memory cells in the first physical unit from an erasing state to a programming state, and

the memory management circuit is further configured to perform the erase operation on the first physical unit after programming the first physical unit.

12. The flash memory controller of claim 11, wherein the programming operation comprises:

programming the first entity unit according to preset data.

13. The flash memory controller of claim 11, wherein the programming operation comprises:

programming the first entity unit according to a preset programming mode.

14. The flash memory controller of claim 13, wherein the pre-programmed pattern comprises a single level memory cell pattern.

15. The flash memory controller of claim 11, wherein the programming operation is to ensure that each memory cell in the first physical unit is in the programmed state prior to erasing the first physical unit.