CN114527941B

CN114527941B - Memory control method, memory storage device and memory control circuit unit

Info

Publication number: CN114527941B
Application number: CN202210153515.XA
Authority: CN
Inventors: 许登钧; 谢长翰
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2022-02-18
Filing date: 2022-02-18
Publication date: 2023-04-18
Anticipated expiration: 2042-02-18
Also published as: CN114527941A

Abstract

The invention provides a memory control method, a memory storage device and a memory control circuit unit. The method comprises the following steps: performing a first write operation based on a first programming pattern to successively write first data to a plurality of first chip enable regions through a plurality of channels; and after the first writing operation is performed, performing a second writing operation based on a second programming mode to continuously write second data to the first chip enable areas and the at least one second chip enable area through the channels. The total number of the plurality of first chip enable areas is greater than the total number of the at least one second chip enable area. Therefore, the access efficiency of the rewritable nonvolatile memory module can be improved.

Description

Memory control method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a memory control technology, and more particularly, to a memory control method, a memory storage device, and a memory control circuit unit.

Background

Smart phones, tablet computers, and notebook computers have grown very rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.

Most high capacity rewritable non-volatile memory modules support parallel data access to multiple memory areas using multiple channels. However, when the total number of channels does not match the total number of memory regions in the rewritable nonvolatile memory module, the rewritable nonvolatile memory module may not achieve the best access performance.

Disclosure of Invention

The invention provides a memory control method, a memory storage device and a memory control circuit unit, which can improve the access efficiency of a rewritable nonvolatile memory module.

An exemplary embodiment of the present invention provides a memory control method for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of channels and a plurality of chip enabling areas. The channels are used for accessing the chip enabling areas. The memory control method includes: performing a first write operation based on a first programming pattern to successively write first data to a plurality of first chip enable regions of the plurality of chip enable regions through the plurality of channels; and after the first write operation is performed, performing a second write operation based on a second programming mode to successively write second data to the first chip enable regions and at least a second chip enable region of the chip enable regions through the channels. The total number of the plurality of first chip enable areas is greater than the total number of the at least one second chip enable area. One memory cell programmed based on the first programming pattern in the first write operation is to store p bits. One memory cell programmed based on the second programming pattern in the second write operation is to store k bits. k is greater than p.

In an exemplary embodiment of the invention, the memory control method further includes: and executing a read operation to read the second data from the rewritable nonvolatile memory module before executing the second write operation.

In an exemplary embodiment of the present invention, the second data includes at least a portion of the first data stored in the plurality of first chip enabled areas.

In an exemplary embodiment of the present invention, one of the first chip enable regions and one of the at least one second chip enable region are connected to a same one of the channels.

In an example embodiment of the present invention, the plurality of channels includes a first channel. In the first write operation, the first channel is used to access one of the plurality of first chip enable areas. In a second write operation, the first channel is used to access the one of the plurality of first chip enable areas and one of the at least one second chip enable area.

In an exemplary embodiment of the invention, the plurality of channels further includes a second channel. In the first write operation and the second write operation, the second channel is used for accessing another one of the plurality of first chip enable areas.

In an exemplary embodiment of the present invention, the operation of writing the second data to the first chip enable areas and the at least one second chip enable area of the chip enable areas through the channels comprises: writing a first portion of the second data to the plurality of first chip enable areas; and writing a second part of the second data to the at least one second chip enable area after writing the first part of the second data to the plurality of first chip enable areas.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of channels and a plurality of chip enabling areas. The channels are used for accessing the chip enabling areas. The memory control circuit unit is used for: performing a first write operation based on a first programming pattern to successively write first data to a plurality of first chip enable regions of the plurality of chip enable regions through the plurality of channels; and after the first write operation is performed, performing a second write operation based on a second programming mode to successively write second data to the first chip enable regions and at least a second chip enable region of the chip enable regions through the channels. The total number of the plurality of first chip enable areas is greater than the total number of the at least one second chip enable area. One memory cell programmed based on the first programming pattern in the first write operation is to store p bits. One memory cell programmed based on the second programming mode in the second write operation is to store k bits. k is greater than p.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: and executing a read operation to read the second data from the rewritable nonvolatile memory module before executing the second write operation.

In an exemplary embodiment of the present invention, the operation of writing the second data to the first chip enable areas and the at least one second chip enable area of the chip enable areas sequentially through the channels comprises: writing a first portion of the second data to the plurality of first chip enable areas; and writing a second part of the second data to the at least one second chip enable area after writing the first part of the second data to the plurality of first chip enable areas.

An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of channels and a plurality of chip enabling areas. The channels are used for accessing the chip enabling areas. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuitry to: performing a first write operation based on a first programming pattern to successively write first data to a plurality of first chip enable regions of the plurality of chip enable regions through the plurality of channels; and after the first write operation is performed, performing a second write operation based on a second programming mode to successively write second data to the first chip enable areas and at least one second chip enable area of the chip enable areas through the channels. Wherein a total number of the plurality of first chip enable areas is greater than a total number of the at least one second chip enable area. One memory cell programmed based on the first programming pattern in the first write operation is to store p bits. One memory cell programmed based on the second programming pattern in the second write operation is to store k bits. k is greater than p.

In an exemplary embodiment of the invention, the memory management circuit is further configured to: and executing a read operation to read the second data from the rewritable nonvolatile memory module before executing the second write operation.

Based on the above, the first write operation may be performed based on the first programming mode to successively write the first data to the plurality of first chip enable regions through the plurality of channels. Thereafter, a second write operation may be performed based on a second programming mode to successively write second data to the plurality of first chip enable regions and at least one second chip enable region through the plurality of channels. In particular, the total number of the plurality of first chip enable areas is greater than the total number of the at least one second chip enable area. Therefore, the access efficiency of the rewritable nonvolatile memory module under the specific configuration condition can be improved.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;

FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the invention;

FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention;

FIG. 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;

FIG. 7 is a diagram illustrating a memory management circuit accessing a rewritable nonvolatile memory module through multiple channels according to an exemplary embodiment of the present invention;

FIG. 8 is a diagram illustrating a memory management circuit accessing a rewritable nonvolatile memory module through multiple channels according to an exemplary embodiment of the present invention;

FIG. 9 is a schematic diagram illustrating a first write operation according to an exemplary embodiment of the present invention;

FIGS. 10A and 10B are schematic diagrams illustrating a second write operation according to an exemplary embodiment of the invention;

FIG. 11 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be connected to a system bus (system bus) 110.

In an example embodiment, the host system 11 may be connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. In addition, the host system 11 may be connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 over the system bus 110.

In an exemplary embodiment, the processor 111, the RAM 112, the ROM 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 by wire or wirelessly through the data transmission interface 114.

In an example embodiment, the memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, near Field Communication (NFC) memory storage, wireless fidelity (WiFi) memory storage, bluetooth (Bluetooth) memory storage, or Bluetooth low energy memory storage (e.g., iBeacon) based memory storage based on various wireless Communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an example embodiment, the host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.

FIG. 3 is a diagram illustrating a host system and a memory storage device according to an example embodiment of the invention. Referring to FIG. 3, the memory storage device 30 can be used with a host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded memory device 34 includes various types of embedded memory devices such as an embedded multimedia Card (eMMC) 341 and/or an embedded Multi-Chip Package (eMCP) memory device 342, which directly connects the memory module to the substrate of the host system.

FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the PCI Express (Peripheral Component Interconnect Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may also be compliant with Serial Advanced Technology Attachment (SATA) standard, parallel Advanced Technology Attachment (PATA) standard, institute of Electrical and Electronic Engineers (IEEE) 1394 standard, universal Serial Bus (USB) standard, SD interface standard, ultra High Speed-I (UHS-I) interface standard, ultra High Speed-II (UHS-II) interface standard, memory Stick (Memory Stick, MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, universal Flash Memory (Flash) interface standard, CF interface standard, device interface standard, or other suitable Integrated Electronics standard. The connection interface unit 41 may be packaged with the memory control circuit unit 42 in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.

The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to commands of the host system 11.

The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a two-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. Each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states as the threshold voltage changes. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, memory cells on the same word line may constitute one or more physical programming cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.

In an exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).

FIG. 5 is a diagram illustrating a memory control circuit unit according to an exemplary embodiment of the invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52 and a memory interface 53.

The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 51 is explained below, it is equivalent to the operation of the memory control circuit unit 42.

In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the RAM of the memory management circuit 51. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The cell management circuit is used to manage the cells or cell groups of the rewritable nonvolatile memory module 43. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory reading circuit is used for issuing a reading instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 43 so as to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may issue other types of command sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.

The host interface 52 is connected to the memory management circuit 51. The memory management circuitry 51 may communicate with the host system 11 through a host interface 52. The host interface 52 is used for receiving and recognizing commands and data transmitted by the host system 11. For example, commands and data transmitted by the host system 11 may be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 may transmit data to the host system 11 through the host interface 52. In the exemplary embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standard.

The memory interface 53 is connected to the memory management circuit 51 and is used for accessing the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format accepted by the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits a corresponding command sequence. For example, the command sequences may include a write command sequence for writing data, a read command sequence for reading data, an erase command sequence for erasing data, and corresponding command sequences for instructing various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes the read identification code, the memory address, and other information.

In an exemplary embodiment, the memory control circuitry unit 42 further includes error checking and correction circuitry 54, buffer memory 55, and power management circuitry 56.

The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates an Error Correction Code (ECC) and/or an Error Detection Code (EDC) for data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 43. Thereafter, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 54 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.

The buffer memory 55 is connected to the memory management circuit 51 and is used for buffering data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10.

In an example embodiment, the rewritable nonvolatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of FIG. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of FIG. 5 may include a flash memory management circuit.

FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Referring to fig. 6, the memory management circuit 51 can logically group the physical units 610 (0) -610 (B) in the rewritable nonvolatile memory module 43 into a storage area 601 and an idle (spare) area 602.

In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of a plurality of consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also refer to a Virtual Block (VB). A virtual block may include a plurality of physical addresses or a plurality of physical programming units.

The physical units 610 (0) -610 (a) in the storage area 601 are used to store user data (e.g., user data from the host system 11 in fig. 1). For example, the entity units 610 (0) -610 (a) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610 (a + 1) to 610 (B) in the idle region 602 store no data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle region 602. In addition, the physical cells in the idle region 602 (or the physical cells not storing valid data) can be erased. When new data is written, one or more physical units may be fetched from the idle region 602 to store the new data. In an exemplary embodiment, the idle zone 602 is also referred to as a free pool.

The memory management circuit 51 may configure the logic units 612 (0) to 612 (C) to map the physical units 610 (0) to 610 (a) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a Logical Address may include one or more Logical Block Addresses (LBAs) or other Logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic program unit or be composed of a plurality of continuous or discontinuous logic addresses.

It is noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is mapped by a certain logic unit, it indicates that the data currently stored in the entity unit includes valid data. Otherwise, if a certain entity unit is not currently mapped by any logic unit, it indicates that the data currently stored in the entity unit is invalid.

The memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing mapping relationships between the logical units and the physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.

FIG. 7 is a diagram illustrating a memory management circuit accessing a rewritable nonvolatile memory module through multiple channels according to an exemplary embodiment of the present invention. Referring to fig. 7, the rewritable nonvolatile memory module 43 includes channels 701 (1) to 701 (n), and chip enable regions 702 (1) to 702 (n) and 703 (1) to 703 (m). The memory management circuit 51 can access the chip enable regions 702 (1) to 702 (n) and 703 (1) to 703 (m) through the channels 701 (1) to 701 (n). n and m are both positive integers greater than 1.

In an exemplary embodiment, n is equal to m. Thus, each of channels 701 (i) may connect to chip enable region 702 (i) labeled CE (0) and chip enable region 703 (i) labeled CE (1). The memory management circuit 502 may access the chip enable regions 702 (i) and 703 (i) through the channel 701 (i). When writing data to the rewritable nonvolatile memory module 43, the memory management circuit 51 may perform interleaved (interleaved) writing. For example, the memory management circuit 51 may write a part of the data to all the chip enable areas 702 (1) to 702 (n) marked as CE (0) in the rewritable nonvolatile memory module 43 successively through the channels 701 (1) to 701 (n), and then write another part of the data to all the chip enable areas 703 (1) to 703 (m) marked as CE (1) in the rewritable nonvolatile memory module 43 successively through the channels 701 (1) to 701 (n). By alternately accessing the n chip enable regions labeled CE (0) and CE (1), data write performance for n channels can be achieved.

Note that, the state where n is equal to m can be regarded as a configuration state where the total number of channels in the rewritable nonvolatile memory module 43 and the total number of chip enable areas match each other (i.e., one channel corresponds to two chip enable areas). However, in a state where n is not equal to m (e.g., m is less than n), the total number of channels in the rewritable non-volatile memory module 43 and the total number of chip enable areas do not match each other (e.g., channel 701 (i) corresponds to two chip enable areas, and channel 701 (j) corresponds to only one chip enable area). In the state where n is not equal to m, if the interleaving writing is continuously performed, the data writing performance of the rewritable nonvolatile memory module 43 may not reach the expected level (i.e., the data writing performance of n channels).

FIG. 8 is a diagram illustrating a memory management circuit accessing a rewritable nonvolatile memory module through multiple channels according to an exemplary embodiment of the present invention. Referring to FIG. 8, in an exemplary embodiment, the rewritable nonvolatile memory module 43 includes channels 801 to 804 and chip enable areas 811 to 816. The channel 801 is connected to chip enable

areas

811 and 815. Channel 802 is connected to chip enable

regions

812 and 816. The channel 803 is connected to a chip enable region 813. The channel 804 is connected to a chip enable area 814. Chip enable areas 811-814 belong to CE (0), and chip enable

areas

815 and 816 belong to CE (1). The memory management circuit 51 can access the chip enable areas 811-816 through the channels 801-804. For example, channel 801 may be used to access chip enable

areas

811 and 815, channel 802 may be used to access chip enable

areas

812 and 816, channel 803 may be used to access chip enable area 813, and channel 804 may be used to access chip enable area 814.

It is noted that, in the exemplary embodiment of FIG. 8, the total number (4) of channels 801-804 in the rewritable non-volatile memory module 43 and the total number (6) of chip enable areas 811-816 do not match each other. When data is to be stored from the host system 11 of FIG. 1, if writing is performed according to the interleaving, the memory management circuit 51 can first write a portion of the data to the chip enable areas 811-814 labeled CE (0) successively through the channels 801-804. At this time, the data write performance can be maintained at the data write performance of 4 channels. However, when another part of the data is subsequently written to the chip enable

areas

815 and 816 labeled CE (1), the writing performance of the data is reduced to 2 channels (i.e. the writing performance is reduced by half). In this situation, the host system 11 (or a user of the host system 11) may consider the data writing performance of the memory storage device 10 to be degraded or unstable.

In an exemplary embodiment, by adopting different programming modes with customized data writing behavior, the data writing performance of the same or close to 4 channels can be maintained under the condition that the total number of channels and the total number of chip enabling areas are not matched with each other as shown in fig. 8. It should be noted that the total number of channels and the total number of chip enable areas in fig. 8 are exemplary and not intended to limit the present invention.

In an example embodiment, the memory management circuit 51 may perform a write operation (also referred to as a first write operation) based on a certain programming mode (also referred to as a first programming mode) to sequentially write data (also referred to as first data) to a plurality of chip enable regions (also referred to as a first chip enable region) through a plurality of channels. After performing the first write operation, the memory management circuit 51 may perform another write operation (also referred to as a second write operation) based on another programming mode (also referred to as a second programming mode) to sequentially write another data (also referred to as a second data) to the plurality of first chip enable regions and at least one remaining chip enable region (also referred to as a second chip enable region) through the plurality of channels. In particular, the total number of the plurality of first chip enable areas is greater than the total number of the at least one second chip enable area. Taking fig. 8 as an example, the first chip enable area may include chip enable areas 811-814 labeled CE (0), and the second chip enable area may include chip enable

areas

815 and 816 labeled CE (1). The total number of chip enable areas 811-814 (i.e., 4) is greater than the total number of chip enable areas 815 and 816 (i.e., 2).

In an example embodiment, a memory cell programmed based on a first programming pattern in a first write operation is used to store p bits. One memory cell programmed based on the second programming mode in the second write operation is used for storing k bits, and k is greater than p.

In an exemplary embodiment, the first programming mode is one of an SLC programming mode, a virtual (pseudo) SLC programming mode, a lower physical programming (lower physical programming) mode, a hybrid programming (mixture programming) mode, and a less layer memory cell (less layer memory cell) mode. In the SLC programming mode and the virtual SLC programming mode, only one bit of data is stored in one memory cell. In the bottom-entity programming mode, only the bottom-entity programming unit is programmed, and the top-entity programming unit corresponding to the bottom-entity programming unit can not be programmed. In the hybrid programming mode, valid data (or real data) is programmed in the lower physical program unit, and dummy data (dummy data) is programmed in the upper physical program unit corresponding to the lower physical program unit storing the valid data. In the few-layer memory cell mode, one memory cell stores a first number of bits of data. For example, this first number may be set to 1.

In an exemplary embodiment, the second programming mode is an MLC programming mode, a TLC programming mode, a QLC programming mode, or the like. In the second programming mode, a memory cell can store a second number of bits of data, wherein the second number is equal to or greater than 2. For example, this second number may be set to 2, 3, or 4. In another exemplary embodiment, the first number (i.e., p) in the first programming mode and the second number (i.e., k) in the second programming mode may be other numbers as long as the second number is greater than the first number.

Fig. 9 is a schematic diagram illustrating a first write operation according to an exemplary embodiment of the present invention. Referring to fig. 9, the memory management circuit 51 can obtain data (i.e. first data) 901. The data 901 may be data that is indicated to be stored by the host system 11 of fig. 1. For example, the memory management circuit 51 may receive a write command from the host system 11. This write instruction may indicate to store data 901.

The memory management circuit 51 can perform a first write operation based on the first programming mode to store the data 901 to the rewritable nonvolatile memory module 406. For example, in a first write operation, the memory management circuit 51 may instruct the rewritable non-volatile memory module 406 to successively write data 901 to the chip enable areas 811 to 814 (i.e., the first chip enable area) labeled CE (0) through the channels 801 to 804. The data writing order of the data 901 in the chip enable areas 811 to 814 can be represented by the numbers 0 to 7 for the physical units in fig. 9. For example, the plurality of data segments in the data 901 can be sequentially written into the physical cell numbered 0 in the chip enable region 811, the physical cell numbered 1 in the chip enable region 812, the physical cell numbered 2 in the chip enable region 813, the physical cell numbered 3 in the chip enable region 814, the physical cell numbered 4 in the chip enable region 811, the physical cell numbered 5 in the chip enable region 812, the physical cell numbered 6 in the chip enable region 813, the physical cell numbered 7 in the chip enable region 814, and so on, based on the first programming pattern.

That is, in the first write operation, only the chip enable areas 811-814 labeled CE (0) (i.e., the first chip enable area) are used alternately to store the data 901, while the chip enable

areas

815 and 816 labeled CE (1) (i.e., the second chip enable area) can be skipped or ignored (i.e., not used). Thus, the data writing performance of the memory storage device 10 can be expected (i.e., maintain the data writing performance at the same or close to 4 channels) for the host system 11 of fig. 1. In addition, in the first write operation, the data write speed can also be increased by storing data in the first program mode.

After performing the first write operation, the memory management circuit 51 may obtain the second data. For example, after performing the first write operation, the memory management circuit 51 may perform a read operation to read the second data from the rewritable non-volatile memory module 43. For example, the second data may include at least part of the first data stored in the first chip enable region in the first write operation. Then, the memory management circuit 51 can perform a second write operation based on the second programming mode to restore the second data back to the rewritable nonvolatile memory module 43. Thereby, the memory space utilization rate of the rewritable nonvolatile memory module 43 can be increased.

FIGS. 10A and 10B are schematic diagrams illustrating a second write operation according to an exemplary embodiment of the invention. It is noted that FIG. 10A shows the first stage write in the second write operation, and FIG. 10B shows the second stage write in the second write operation. The first phase write and the second phase write may be performed alternately.

Referring to fig. 10A, after the first write operation is performed, the memory management circuit 51 may obtain data (i.e., second data) 1001. For example, the data 1001 may include at least part of the data 901 stored in the chip enable areas 811-814 in the first write operation of fig. 9. The memory management circuit 51 may read data 1001 from at least one of the chip enable areas 811 to 814. After obtaining the data 1001, the memory management circuit 51 may perform a second write operation to restore the data 1001 to the rewritable nonvolatile memory module 406 based on a second programming mode.

In the first stage writing of the second writing operation, the memory management circuit 51 may instruct the rewritable non-volatile memory module 406 to write a portion of the data 1001 (also referred to as a first portion of data) to the chip enable areas 811 to 814 (i.e., the first chip enable area) successively through the channels 801 to 804. The data write sequence of the data 1001 in the chip enable areas 811 to 814 can be represented by the numbers 0 to 3 for the physical units in fig. 10A. For example, the data segments of the data 1001 may be sequentially written into the physical cell numbered 0 in the chip enable region 811, the physical cell numbered 1 in the chip enable region 812, the physical cell numbered 2 in the chip enable region 813, and the physical cell numbered 3 in the chip enable region 814 based on the second programming pattern. Then, the memory management circuit 51 may perform the second stage write of the second write operation.

Referring to fig. 10B, in the second phase write of the second write operation, the memory management circuit 51 may instruct the rewritable nonvolatile memory module 406 to continuously write another portion of data (also referred to as a second portion of data) of the data 1001 to the chip enable areas 815 and 816 (i.e., the second chip enable area) through the

channels

801 and 802. The data writing sequence of the data 1001 in the chip enable

regions

815 and 816 can be represented by the

numbers

4 and 5 of the physical units in fig. 10B. For example, the data segments of the data 1001 may be sequentially written into the physical unit numbered 4 in the chip enable region 815 and the physical unit numbered 5 in the chip enable region 816 based on the second programming mode.

By alternately performing the two-stage writing shown in FIG. 10A and FIG. 10B, in the second writing operation, the data originally stored only in the chip enable areas 811-814 labeled CE (0) can be stored again in all the chip enable areas 811-816, so as to effectively utilize the storage space of the rewritable nonvolatile memory module 406. In addition, in the second write operation, the storage space utilization rate of the rewritable nonvolatile memory module 43 can also be increased by storing data in the second programming mode.

In an exemplary embodiment,

channels

801 and 802 of FIG. 8 are also referred to as first channels. In the first write operation,

channels

801 and 802 can be used to access chip enable

areas

811 and 812 belonging to CE (0), respectively, as shown in FIG. 9. In a second write operation, channel 801 may be used to access chip enable

regions

811 and 815 and channel 802 may be used to access chip enable

regions

812 and 816, as shown in FIGS. 10A and 10B.

In an exemplary embodiment, the

channels

803 and 804 of fig. 8 are also referred to as second channels. In the first and second write operations, the

channels

803 and 804 can only be used to access the chip enable

areas

813 and 814 belonging to CE (0), respectively.

Channels

803 and 804 cannot be used to access any chip enable region belonging to CE (1).

In an example embodiment, the first write operation is used to store data from the host system 11 of FIG. 1 that is written to the rewritable nonvolatile memory module 43 for the first time. Thus, the high-speed write provided by the first write operation may effectively improve the data write performance experienced or measured by the host system 11. On the other hand, the second write operation is to restore part of the data stored in the rewritable non-volatile memory module 43 in the background to increase the data storage amount per memory unit or physical unit. By matching the customized first write operation and the customized second write operation with different programming modes, the data write performance of the memory storage device 10 can be effectively improved under the condition that the total number of channels and the total number of chip enable areas are not matched with each other as shown in fig. 8.

In an example embodiment, a read operation for reading the second data from the rewritable non-volatile memory module 43 and a second write operation for storing the second data may be included in the data union operation. This data consolidation operation is also known as a Garbage Collection (GC) operation. The merging operation can be used to collect valid data from a specific physical unit (also referred to as a source unit) in the rewritable nonvolatile memory module 43 and store the collected valid data back to a specific physical unit (also referred to as a target unit) in the rewritable nonvolatile memory module 43. In particular, if valid data in a source unit is completely backed up (i.e., stored in the target unit), the source unit can be divided into the idle region 602 of fig. 6 and erased, thereby increasing the total number of physical units (also referred to as idle physical units) in the idle region 602.

It should be noted that, in the foregoing exemplary embodiment, each chip enable area is labeled as CE (0) or CE (1) for management, but the invention is not limited thereto. In an exemplary embodiment, the mark of each chip enable area can be adjusted or removed, and the invention is not limited thereto.

FIG. 11 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention. Referring to fig. 11, in step S1101, a first write operation is performed based on a first programming pattern to continuously write first data to a plurality of first chip enable regions through a plurality of channels. After the first write operation is performed, in step S1102, a second write operation is performed based on a second programming mode to sequentially write second data to the plurality of first chip enable areas and at least one second chip enable area through the plurality of channels. In particular, the total number of the plurality of first chip enable areas is greater than the total number of the at least one second chip enable area. In addition, one memory cell programmed based on the first programming pattern in the first writing operation is used for storing p bits, one memory cell programmed based on the second programming pattern in the second writing operation is used for storing k bits, and k is larger than p.

However, the steps in fig. 11 have been described in detail above, and are not repeated herein. It is to be noted that, the steps in fig. 11 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 11 can be used with the above exemplary embodiments, or can be used alone, and the invention is not limited thereto.

In summary, the exemplary embodiments of the invention provide a method for using different programming modes with customized data writing behavior, which can effectively maintain or even improve the data access performance of the memory storage device under the condition that the total number of channels in the rewritable non-volatile memory module and the total number of chip enable areas are not matched with each other.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory control method for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of channels and a plurality of chip enable areas, the plurality of channels are used for accessing the plurality of chip enable areas, and the memory control method comprises:

performing a first write operation based on a first programming pattern to successively write first data to a plurality of first chip enable regions of the plurality of chip enable regions through the plurality of channels; and

performing a second write operation based on a second programming mode to successively write second data to the plurality of first chip enable regions and at least a second chip enable region of the plurality of chip enable regions through the plurality of channels after performing the first write operation,

wherein a total number of the plurality of first chip enable areas is greater than a total number of the at least one second chip enable area,

one memory cell programmed based on the first programming pattern in the first write operation is to store p bits, one memory cell programmed based on the second programming pattern in the second write operation is to store k bits, and k is greater than p.

2. The memory control method of claim 1, further comprising:

and executing a read operation to read the second data from the rewritable nonvolatile memory module before executing the second write operation.

3. The memory control method according to claim 2, wherein the second data includes at least a part of the first data stored in the plurality of first chip enable regions.

4. The memory control method of claim 1, wherein one of the plurality of first chip enable regions and one of the at least one second chip enable region are connected to a same one of the plurality of channels.

5. The memory control method of claim 1, wherein the plurality of channels includes a first channel,

in the first write operation, the first channel is used to access one of the plurality of first chip enable areas, and

in a second write operation, the first channel is used to access the one of the plurality of first chip enable areas and the one of the at least one second chip enable area.

6. The memory control method of claim 5, wherein the plurality of channels further comprises a second channel, and

in the first write operation and the second write operation, the second channel is used for accessing another one of the plurality of first chip enable areas.

7. The memory control method of claim 1, wherein the operation of writing the second data to the plurality of first chip enable regions and the at least one second chip enable region of the plurality of chip enable regions in succession through the plurality of channels comprises:

writing a first portion of the second data to the plurality of first chip enable areas; and

writing a second portion of the second data to the at least one second chip enable area after writing the first portion of the second data to the plurality of first chip enable areas.

8. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable non-volatile memory module; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the rewritable nonvolatile memory module includes a plurality of channels and a plurality of chip enable areas, the plurality of channels are used for accessing the plurality of chip enable areas, and the memory control circuit unit is used for:

performing a first write operation based on a first programming mode to successively write first data to a plurality of first chip enable regions among the plurality of chip enable regions through the plurality of channels; and

9. The memory storage device of claim 8, wherein the memory control circuitry unit is further to:

10. The memory storage device of claim 9, wherein the second data comprises at least a portion of the first data stored in the plurality of first chip enable regions.

11. The memory storage device of claim 8, wherein one of the plurality of first chip enable regions and one of the at least one second chip enable region are connected to a same one of the plurality of channels.

12. The memory storage device of claim 8, wherein the plurality of channels comprises a first channel,

13. The memory storage device of claim 12, wherein the plurality of channels further comprises a second channel, and

14. The memory storage device of claim 8, wherein the operation of writing the second data to the first and second of the plurality of chip enable regions in succession through the plurality of channels comprises:

15. A memory control circuit unit, configured to control a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of channels and a plurality of chip enable areas, the plurality of channels are used to access the plurality of chip enable areas, and the memory control circuit unit includes:

a host interface for connecting to a host system;

a memory interface for connecting to the rewritable nonvolatile memory module; and

a memory management circuit connected to the host interface and the memory interface,

wherein the memory management circuitry is to:

performing a second write operation based on a second programming pattern to successively write second data to the plurality of first chip enable regions and at least one second chip enable region of the plurality of chip enable regions through the plurality of channels after performing the first write operation,

16. The memory control circuitry unit of claim 15, wherein the memory management circuitry is further to:

17. The memory control circuit unit of claim 16, wherein the second data comprises at least a portion of the first data stored in the plurality of first chip enable regions.

18. The memory control circuit unit of claim 15, wherein one of the plurality of first chip enable regions and one of the at least one second chip enable region are connected to a same one of the plurality of channels.

19. The memory control circuit unit of claim 15, wherein the plurality of channels includes a first channel,

20. The memory control circuit unit of claim 19, wherein the plurality of channels further comprises a second channel, and

21. The memory control circuit unit of claim 15, wherein the operation of writing the second data to the plurality of first chip enable regions and the at least a second chip enable region of the plurality of chip enable regions in succession through the plurality of channels comprises: