CN115599305A

CN115599305A - Data storage method, memory storage device and memory control circuit unit

Info

Publication number: CN115599305A
Application number: CN202211372667.5A
Authority: CN
Inventors: 叶志刚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2022-11-03
Filing date: 2022-11-03
Publication date: 2023-01-13

Abstract

The invention provides a data storage method, a memory storage device and a memory control circuit unit. The method comprises the following steps: receiving first data from a host system; encoding first data based on a first code rate to generate first parity data; storing the first data and the first parity data in a plurality of first entity management units; collecting second data from the rewritable non-volatile memory module; encoding the second data based on a second code rate to generate second parity data, wherein the first code rate is different from the second code rate; and storing the second data and the second parity data in a plurality of second entity management units. Thus, the data encoding and storage mechanism under different data writing situations can be optimized.

Description

Data storage method, memory storage device and memory control circuit unit

Technical Field

The invention relates to a data storage method, a memory storage device and a memory control circuit unit.

Background

Mobile phones, tablet computers and notebook computers have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small size, and no mechanical structure, it is very suitable for being built in various portable multimedia devices as described above.

Some types of rewritable non-volatile memory modules may support data encoding and decoding across physical units (e.g., across physical pages), e.g., encoding data in K physical pages across physical pages to generate parity data in 1 physical page. Thereafter, the data in the K physical pages and the parity data in the 1 physical page may be used to collectively protect the data in the K physical pages through a data protection technique across the physical pages. The data protection technique across physical pages can further improve the protection capability (and error correction capability) for data compared to the data protection technique of a single physical page. However, for a single rewritable nonvolatile memory module, the value of K is usually fixed, which results in waste of system resources (such as data transmission bandwidth and storage space) under different operation scenarios.

Disclosure of Invention

The invention provides a data storage method, a memory storage device and a memory control circuit unit, which can optimize data coding and storage mechanisms under different data writing situations.

Exemplary embodiments of the present invention provide a data storage method for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity management units. The data storage method comprises the following steps: receiving first data from a host system; encoding the first data based on a first code rate to generate first parity data; storing the first data and the first parity data in a plurality of first entity management units of the plurality of entity management units; collecting second data from the rewritable non-volatile memory module; encoding the second data based on a second code rate to generate second parity data, wherein the first code rate is different from the second code rate; and storing the second data and the second parity data in a plurality of second entity management units of the plurality of entity management units.

In an exemplary embodiment of the invention, the first data and the second data are respectively stored in the first entity management units and the second entity management units through the same programming mode.

In an example embodiment of the present invention, a protection capability of the first parity data for the first data is higher than a protection capability of the second parity data for the second data.

In an exemplary embodiment of the invention, a total number of the first entity management units is less than a total number of the second entity management units.

In an exemplary embodiment of the invention, each entity management unit of the plurality of entity management units corresponds to a die, a chip enable area or a plane in the rewritable nonvolatile memory module.

In an exemplary embodiment of the present invention, the first code rate reflects a ratio between a data amount of the first data and a data amount of the first parity data, the second code rate reflects a ratio between a data amount of the second data and a data amount of the second parity data, and the first code rate is lower than the second code rate.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity management units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for: receiving first data from the host system; encoding the first data based on a first code rate to generate first parity data; sending a first write command sequence that indicates that the first data and the first parity data are stored in a plurality of first entity management units of the plurality of entity management units; collecting second data from the rewritable non-volatile memory module; encoding the second data based on a second code rate to generate second parity data, wherein the first code rate is different from the second code rate; and sending a second write command sequence that indicates that the second data and the second parity data are stored in a plurality of second entity management units of the plurality of entity management units.

An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity management units. The memory control circuit unit comprises a host interface, a memory interface, an error checking and correcting circuit and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuitry is coupled to the host interface, the memory interface, and the error checking and correcting circuitry. The memory management circuit is to receive first data from a host system. The error checking and correcting circuit is configured to encode the first data based on a first code rate to generate first parity data. The memory management circuit is further configured to send a first write command sequence that indicates that the first data and the first parity data are stored in a first plurality of entity management units of the plurality of entity management units. The memory management circuit is further configured to collect second data from the rewritable non-volatile memory module. The error checking and correcting circuit is further configured to encode the second data based on a second code rate to generate second parity data, wherein the first code rate is different from the second code rate. The memory management circuit is further configured to send a second write command sequence that indicates that the second data and the second parity data are stored in a plurality of second entity management units of the plurality of entity management units.

Based on the above, after receiving the first data from the host system, the first data may be encoded based on the first code rate to generate first parity data, and the first data and the first parity data may be stored in a plurality of first entity management units in the rewritable non-volatile memory module. In addition, after collecting the second data from the rewritable non-volatile memory module, the second data may be encoded based on a second code rate to generate second parity data, and the second data and the second parity data may be stored in a plurality of second entity management units in the rewritable non-volatile memory module. In particular, the first code rate is different from the second code rate. By encoding the data stored in the plurality of entity management units with different code rates in different data writing situations, the data encoding and storage mechanism in different data writing situations can be effectively optimized.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;

FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the invention;

FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention;

FIG. 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;

FIG. 7 is a system architecture diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating a host write operation in accordance with an exemplary embodiment of the present invention;

FIG. 9 is a diagram illustrating a data merging operation according to an exemplary embodiment of the present invention;

FIG. 10 is a diagram illustrating encoding of first data in a host write operation according to an example embodiment of the invention;

FIG. 11 is a diagram illustrating encoding of second data in a data merge operation according to an example embodiment of the present invention;

fig. 12 is a flowchart illustrating a data storage method according to an exemplary embodiment of the present invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 may be connected to a system bus (system bus) 110.

In an example embodiment, the host system 11 may be connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. In addition, the host system 11 may be connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 over the system bus 110.

In an exemplary embodiment, the processor 111, the RAM 112, the ROM 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 by wire or wirelessly through the data transmission interface 114.

In an example embodiment, the memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, near Field Communication (NFC) memory storage, wireless facsimile (WiFi) memory storage, bluetooth (Bluetooth) memory storage, or Bluetooth low energy memory storage (e.g., iBeacon) based memory storage based on various wireless Communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an example embodiment, the host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.

FIG. 3 is a diagram illustrating a host system and a memory storage device according to an example embodiment of the invention.

Referring to FIG. 3, the memory storage device 30 can be used with a host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded memory device 34 includes various types of embedded memory devices such as an embedded multimedia Card (eMMC) 341 and/or an embedded Multi-Chip Package (eMCP) memory device 342, which directly connects the memory module to the substrate of the host system.

FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect local bus (PCI Express) standard. In an example embodiment, the connection interface unit 41 may also be compliant with Serial Advanced Technology Attachment (SATA) standard, parallel Advanced Technology Attachment (PATA) standard, institute of Electrical and Electronic Engineers (IEEE) 1394 standard, universal Serial Bus (USB) standard, SD interface standard, ultra High Speed-I (UHS-I) interface standard, second generation (Ultra High Speed-II, UHS-II) interface standard, memory Stick (Memory Stick, MS) interface standard, MCP interface standard, MMC interface standard, eMMC Universal Flash Memory (UFS) interface standard, eMCP interface standard, CF interface standard, integrated Drive Electronics (IDE) interface standard, or other suitable standards for Integrated Electronics. The connection interface unit 41 may be packaged with the memory control circuit unit 42 in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.

The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to commands of the host system 11.

The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a two-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. Each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states as the threshold voltage changes. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, memory cells on the same word line may constitute one or more physically programmed cells. If a memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.

In an example embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, a physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area stores system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).

FIG. 5 is a diagram illustrating a memory control circuit unit according to an exemplary embodiment of the invention.

Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52 and a memory interface 53. The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 51 is explained below, the operation of the memory control circuit unit 42 is equivalently explained.

In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the RAM of the memory management circuit 51. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The cell management circuit is used to manage the cells or cell groups of the rewritable nonvolatile memory module 43. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory reading circuit is used for issuing a reading instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erasing circuit is used for sending an erasing command sequence to the rewritable nonvolatile memory module 43 to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may issue other types of command sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.

The host interface 52 is connected to the memory management circuit 51. The memory management circuitry 51 may communicate with the host system 11 through a host interface 52. The host interface 52 is used for receiving and recognizing commands and data transmitted by the host system 11. For example, commands and data transmitted by the host system 11 may be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 may transmit data to the host system 11 through the host interface 52. In the exemplary embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standard.

The memory interface 53 is connected to the memory management circuit 51 and is used for accessing the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format accepted by the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits a corresponding command sequence. For example, the command sequences may include a write command sequence for writing data, a read command sequence for reading data, an erase command sequence for erasing data, and corresponding command sequences for instructing various memory operations (e.g., changing read voltage levels or performing Garbage Collection (GC) operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes information such as the read identification code, the memory address, etc.

In an exemplary embodiment, the memory control circuitry unit 42 further includes error checking and correction circuitry 54, buffer memory 55, and power management circuitry 56.

The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 43. Thereafter, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 54 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.

The buffer memory 55 is connected to the memory management circuit 51 and is used for temporarily storing data. The power management circuit 56 is a power supply connected to the memory management circuit 51 and used to control the memory storage device 10.

In an example embodiment, the rewritable nonvolatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of FIG. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of FIG. 5 may include a flash memory management circuit.

FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention.

Referring to fig. 6, the memory management circuit 51 can logically group the physical units 610 (0) -610 (B) in the rewritable nonvolatile memory module 43 into a storage area 601 and an idle (spare) area 602. In an exemplary embodiment, a physical cell refers to a physical programming cell. However, in another exemplary embodiment, one physical unit may include a plurality of physical programming units.

The physical units 610 (0) -610 (a) in the storage area 601 are used to store user data (e.g., user data from the host system 11 of fig. 1). For example, entity units 610 (0) -610 (a) in the storage area 601 may store valid (valid) data and/or invalid (invalid) data. The physical units 610 (a + 1) to 610 (B) in the idle region 602 store no data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle region 602. In addition, the physical cells in the idle region 602 (or the physical cells not storing valid data) can be erased. When new data is written, one or more physical units may be fetched from the idle region 602 to store the new data. In an exemplary embodiment, the idle region 602 is also referred to as a free pool.

The memory management circuit 51 may configure the logic units 612 (0) to 612 (C) to map the physical units 610 (0) to 610 (a) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a Logical Address may include one or more Logical Block Addresses (LBAs) or other Logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic program unit or be composed of a plurality of continuous or discontinuous logic addresses. A. B and C are positive integers and can be adjusted according to practical requirements, and the invention is not limited.

It is noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is mapped by a certain logic unit currently, it indicates that the data currently stored in the entity unit includes valid data. Otherwise, if a certain entity unit is not currently mapped by any logic unit, it indicates that the data currently stored in the entity unit is invalid.

The memory management circuit 51 records management data (also referred to as logic-to-entity mapping information) describing mapping relationships between logical units and physical units in at least one logic-to-entity mapping table. When host system 11 is to read data from memory storage device 10 or write data to memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.

FIG. 7 is a system architecture diagram of a memory storage device according to an exemplary embodiment of the invention.

Referring to fig. 7, the rewritable nonvolatile memory module 43 may include a plurality of Chip Enabled (CE) areas CE (0) to CE (E). For example, the rewritable non-volatile memory module 43 may include one or more dies (die). The crystal grains are obtained from a Wafer (Wafer) by laser dicing. Each die may be divided into one or more chip enable regions. Each of the chip enable regions CE (0) -CE (E) may include one or more planes (also referred to as memory planes, labeled as planes (0) -plane (P) in fig. 7). Each plane may contain a plurality of physical units.

It should be noted that whether a chip enable region can be accessed or not can be controlled by a chip enable signal corresponding to the chip enable region. For example, when a chip enable signal corresponding to the chip enable area CE (i) is pulled up, the rewritable nonvolatile memory module 43 may read or store data from or into the chip enable area CE (i). However, if the chip enable signal corresponding to the chip enable area CE (i) is not pulled up, the rewritable nonvolatile memory module 43 cannot read data from or store data in the chip enable area CE (i).

It should be noted that, in the exemplary embodiment, each of the chip enable areas CE (0) to CE (E) includes the same number of planes as an example. For example, chip enable region CE (0) includes planes 701 (0) -701 (P), and chip enable region CE (E) includes planes 702 (0) -702 (P), and so on. However, the total number of planes (i.e., E) in different chip enable regions may also be different, and the invention is not limited thereto. In addition, in an exemplary embodiment, the plane (i) may also include a plurality of planes.

The memory management circuit 51 can access the rewritable nonvolatile memory module 43 through channels (also referred to as memory channels) 71 (0) to 71 (D). In particular, each of the channels 71 (0) -71 (D) may be used to access a particular chip enable region. For example, the channel 71 (i) may be used to access the chip enable region (i). In addition, the values of D, E and P can be adjusted according to practical requirements, and the invention is not limited thereto.

FIG. 8 is a diagram illustrating a host write operation according to an example embodiment of the present invention.

Referring to FIG. 8, the memory management circuit 51 can perform a host write operation to store data 801 from the host system 11. For example, in a host write operation, the memory management circuit 51 may receive a write instruction from the host system 11. This write instruction may indicate to store data 801. The memory management circuit 51 can store the data 801 into the start-up unit (also referred to as a start-up unit) 81 according to the write command. For example, the enabling unit 81 may include physical units 810 (0) to 810 (F). The physical elements 810 (0) -810 (F) may be selected from the idle region 602 of fig. 6.

Fig. 9 is a diagram illustrating a data merging operation according to an exemplary embodiment of the present invention.

Referring to fig. 9, the memory management circuit 51 may also perform data union operation to release new idle physical units. For example, a new idle physical unit may be associated or added to idle region 602. For example, in a data merge operation, the memory management circuit 51 may collect data 901 from a source unit (also referred to as a source block or a source node) 91. For example, source unit 91 may include physical units 911 (0) -911 (G). The entity units 911 (0) to 911 (G) can be selected from the memory area 601 of fig. 6. The collected data 901 includes valid data. Then, the memory management circuit 51 may collectively store the data 901 to the target unit (also referred to as a target block or a target node) 92. For example, the target cell 92 may include entity cells 921 (0) to 921 (H). The physical units 921 (0) -921 (H) can be selected from the idle region 602 of fig. 6. In addition, in a data merge operation, if all valid data stored in the source unit 91 has been collected and stored to the destination unit 92, the source unit 91 may be erased and associated or added as a new idle physical unit to the idle region 602. In an example embodiment, the data consolidation operation may include a garbage collection operation.

In an exemplary embodiment, the memory management circuit 51 may manage physical units in the rewritable nonvolatile memory module 43 through a plurality of physical management units. For example, one entity management unit includes a plurality of entity units, and one entity management unit may correspond to one die, one chip enable area, or one plane in the rewritable nonvolatile memory module 43. Further, the memory management circuit 51 may store data into the rewritable nonvolatile memory module 43 or read data from the rewritable nonvolatile memory module 43 with the entity management unit as an access unit.

It should be noted that, in the host write operation and the data merging operation, before or after the data (also referred to as the target data) is stored in the rewritable nonvolatile memory module 43, the target data may be encoded to facilitate the correction of errors in the read data when the target data is subsequently read. For example, memory management circuitry 51 may instruct error checking and correction circuitry 54 to encode the target data to generate parity data corresponding to the target data. This parity data may be used to protect the target data. Thereafter, when reading the target data from the rewritable nonvolatile memory module 43, the parity data can be read together. The error checking and correcting circuit 54 decodes the target data according to the parity data to correct errors in the target data.

It should be noted that the aforementioned encoding of the target data by the error checking and correcting circuit 54 means that the target data is encoded in a multi-entity unit by the error checking and correcting circuit 54. For example, the error checking and correcting circuit 54 may use an exclusive OR (XOR) OR Reed-Solomon (RS) encoding algorithm to encode the target data in multiple physical units. In addition, the present invention does not limit the encoding/decoding algorithm employed by the error checking and correcting circuit 54.

In an exemplary embodiment, the encoding of multiple physical units is also referred to as cross-physical unit encoding. For example, error checking and correction circuit 54 may perform multi-physical-unit encoding on the target data to generate the parity data, assuming that the data may be stored continuously or dispersedly to a plurality of physical units. Thereafter, when reading at least a portion of the target data from the rewritable non-volatile memory module 43, if an error in the data read from a particular physical unit cannot be corrected based on the error correction code and/or the error check code in a single physical unit, the memory management circuit 51 may further read the parity data from the rewritable non-volatile memory module 43. The error checking and correcting circuit 54 may then perform multi-physical unit decoding on the target data according to the parity data to attempt to correct the error through a coding protection mechanism between the plurality of physical units. In an exemplary embodiment, decoding of multiple physical units is also referred to as cross-physical unit decoding. In an example embodiment, the encoding and decoding across entity units may include encoding and decoding across entity management units.

In an example embodiment, the memory management circuit 51 may receive data (also referred to as first data) from the host system 11. For example, the first data is entrained in one or more write commands. For example, the first data may include data 801 in fig. 8. In a host write operation, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to store the first data.

In particular, in a host write operation, memory management circuit 51 may instruct error checking and correction circuit 54 to encode the first data based on a particular code rate (also referred to as a first code rate) to generate parity data (also referred to as first parity data). The first parity data may be used to protect the first data. Then, the memory management circuit 51 can send one or more write command sequences (also referred to as a first write command sequence) to the rewritable nonvolatile memory module 43. The first write command sequence may instruct the rewritable non-volatile memory module 43 to store the first data and the first parity data in a part of the plurality of entity management units (also referred to as a first entity management unit).

FIG. 10 is a diagram illustrating encoding of first data in a host write operation according to an example embodiment of the invention.

Referring to fig. 10, in a host write operation, the memory management circuit 51 may instruct the error checking and correcting circuit 54 to encode (i.e., encode the multi-entity unit) the data 1001 (0) -1001 (I-1) (i.e., the first data) based on the first code rate to generate the parity data 1002 (i.e., the first parity data). The memory management circuit 51 may send a first write command sequence to instruct the rewritable nonvolatile memory module 43 to store the data 1001 (0) to 1001 (I-1) in the entity management units 1010 (0) to 1010 (I-1) continuously or dispersedly and store the parity data 1002 in the entity management unit 1020. It should be noted that the entity management units 1010 (0) -1010 (I-1) and 1020 are located on different dies, chip enabled areas or planes respectively. The entity management units 1010 (0) to 1010 (I-1) and 1020 belong to the first entity management unit. Thereafter, when reading at least a portion of the data 1001 (0) -1001 (I-1), the error checking and correcting circuit 54 may perform decoding of the multi-entity unit through the parity data 1002 and the data of the other portion of the data 1001 (0) -1001 (I-1) to attempt to correct errors in the read data through a data protection mechanism across the entity units.

On the other hand, the memory management circuit 51 may collect data (also referred to as second data) from the rewritable nonvolatile memory module 43. For example, the second data comprises data collected from the source unit by a data union operation. For example, the second data may include data 901 in fig. 9. In the data consolidation operation, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to store the second data.

In particular, in the data union operation, the memory management circuit 51 may instruct the error checking and correcting circuit 54 to encode the second data based on another code rate (also referred to as a second code rate) to generate parity data (also referred to as second parity data). The second parity data may be used to protect the second data. Then, the memory management circuit 51 can send one or more write command sequences (also referred to as a second write command sequence) to the rewritable nonvolatile memory module 43. The second write command sequence may instruct the rewritable non-volatile memory module 43 to store the second data and the second parity data in a part of the plurality of entity management units (also referred to as a second entity management unit).

Fig. 11 is a diagram illustrating encoding of second data in a data union operation according to an exemplary embodiment of the present invention.

Referring to fig. 11, in the data merge operation, the memory management circuit 51 may instruct the error checking and correcting circuit 54 to encode (i.e., encode the multi-entity unit) the data 1101 (0) -1101 (J-1) (i.e., the second data) based on the second code rate to generate the parity data 1102 (i.e., the second parity data). The memory management circuit 51 may send a second write command sequence to instruct the rewritable non-volatile memory module 43 to store the data 1101 (0) -1101 (J-1) continuously or dispersedly in the entity management units 1110 (0) -1110 (J-1) and store the parity data 1102 in the entity management unit 1120. It should be noted that the entity management units 1110 (0) -1110 (J-1) and 1120 are located on different dies, chip enabled areas or planes, respectively. The second entity management units 1110 (0) to 1110 (J-1) and 1120 belong to the entity management unit. Thereafter, when reading at least a portion of the data 1101 (0) -1101 (J-1), the error checking and correcting circuit 54 may perform decoding of the multi-entity unit with the parity data 1102 and the data of the other portion of the data 1101 (0) -1101 (J-1) to attempt to correct errors in the read data by a data protection mechanism across the entity units.

It is noted that in the exemplary embodiments of fig. 10 and 11, I is less than J. For example, I and J may be 16 and 32, respectively. In addition, the values of I and J can be adjusted according to practical requirements as long as the limitation that I is smaller than J is met.

In an example embodiment, the total number of the first entity management units may be less than the total number of the second entity management units and/or the data length of the first data may be shorter than the data length of the second data. Taking fig. 10 and 11 as an example, I is smaller than J, so the total number of entity managing units 1010 (0) -1010 (I-1) and 1020 (i.e., I + 1) is smaller than the total number of entity managing units 1110 (0) -1110 (J-1) and 1120 (i.e., J + 1), and/or the total data length of data 1001 (0) -1001 (I-1) is shorter than the total data length of data 1101 (0) -1101 (J-1).

In an exemplary embodiment, in the case of generating the first parity data and the second parity data having the same data length, the protection capability of the first parity data for the first data is higher than that of the second parity data for the second data. Taking fig. 10 and 11 as an example, I is smaller than J, so that in the case of generating

parity data

1002 and 1102 having the same data length, the protection capability of parity data 1002 for data 1001 (0) to 1001 (I-1) can be higher than that of parity data 1102 for data 1101 (0) to 1101 (J-1). For example, assuming that data 1001 (0) -1001 (I-1) and 1101 (0) -1101 (J-1) all contain N error bits, the probability that N error bits in data 1001 (0) -1001 (I-1) are corrected according to parity data 1002 may be higher than the probability that N error bits in data 1101 (0) -1101 (J-1) are corrected according to parity data 1102.

In an example embodiment, the first code rate may reflect a ratio between a data amount of the first data and a data amount of the first parity data, and the second code rate may reflect a ratio between a data amount of the second data and a data amount of the second parity data, and the first code rate may be lower than the second code rate. For example, the first code rate and the second code rate may be calculated according to the following procedures (1) and (2), respectively.

The first code rate = equation order of data amount of the first data/(data amount of the first data + data amount of the first parity data) (1)

The second code rate = equation order of data amount of the second data/(data amount of the second data + data amount of the second parity data) (2)

Taking fig. 10 and 11 as an example, the first code rate may reflect a ratio (i.e., I: 1) between the data amount of data 1001 (0) to 1001 (I-1) and the data amount of parity data 1002, and the second code rate may reflect a ratio (i.e., J: 1) between the data amount of data 1101 (0) to 1101 (J-1) and the data amount of parity data 1102. For example, assuming that I and J are 16 and 32, respectively, the first code rate and the second code rate can be 16/17 and 32/33, respectively, and the first code rate is smaller than the second code rate. In an exemplary embodiment, the first code rate is less than the second code rate, which also reflects that the protection capability of the first data by the first parity data is higher than the protection capability of the second data by the second parity data. It should be noted that, in another exemplary embodiment, the first bitrate can be adjusted to be higher than or equal to the second bitrate in different application management depending on the practical requirements.

In an exemplary embodiment, the first data and the second data are stored in the first entity management unit and the second entity management unit respectively through the same programming mode. For example, the programming modes may include SLC, MLC, TLC, QLC, or other programming modes. Taking the example that the first data and the second data are both stored in the first entity management unit and the second entity management unit through the TLC programming mode, after the first data and the first parity data are stored in the first entity management unit, a single memory cell in the first entity management unit storing the first data (and the first parity data) can store 3 bits; similarly, after the second data and the second parity data are stored in the second PM, a single cell in the second PM storing the second data (and the second parity data) may also store 3 bits. Alternatively, for example, after the first data and the first parity data are stored in the first entity management unit, a single memory cell in the first entity management unit storing the first data (and the first parity data) may store 1 bit, in which case the first data and the second data are both stored in the first entity management unit and the second entity management unit through the SLC programming mode; similarly, after the second data and the second parity data are stored in the second PM, a single cell in the second PM storing the second data (and the second parity data) may also store 1 bit.

In an example embodiment, before storing the data, the memory management circuit 51 may determine that the write operation to be performed is a host write operation or a data union operation. If (in response to) the write operation to be performed is a host write operation, memory management circuitry 51 may instruct error checking and correction circuitry 54 to encode the data to be stored (i.e., the first data) based on the first code rate to generate corresponding parity data (i.e., the first parity data). Then, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to store the first data and the first parity data into the first entity management unit. Taking fig. 10 as an example, the first bmt may include I +1 bmts, wherein the first data is stored in the I bmts and the first parity data is stored in the 1 bmt.

Alternatively, if (in response to) the write operation to be performed is a data union operation, the memory management circuit 51 may instruct the error checking and correcting circuit 54 to encode the data to be stored (i.e., the second data) based on the second code rate to generate corresponding parity data (i.e., the second parity data). Then, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to store the second data and the second parity data into the second entity management unit. For example, in fig. 11, the second ems may include J +1 ems, wherein the second data is stored in the J ems, the second parity data is stored in the 1 ems, and I is smaller than J.

Referring to fig. 12, in step S1210, it is determined that the write operation to be performed is a host write operation or a data merge operation. If (in response to) the write operation to be performed is a host write operation, in step S1211, first data is received from the host system. In step S1212, the first data is encoded based on the first code rate to generate first parity data. In step S1213, the first data and the first parity data are stored in the plurality of first entity management units. Alternatively, if (in response to) the write operation to be performed is a data union operation, in step S1221, second data is collected from the rewritable non-volatile memory module. In step S1222, second data is encoded based on the second code rate to generate second parity data. In step S1223, the second data and the second parity data are stored in a plurality of second entity management units. In particular, the protection capability of the first parity data for the first data is higher than the protection capability of the second parity data for the second data, the total number of first entity management units is less than the total number of second entity management units, and/or the first code rate is lower than the second code rate. It should be noted that, in the exemplary embodiment of fig. 12, the step S1210 can also be executed after the step S1211 and/or the step S1221, and the invention is not limited thereto.

However, the steps in fig. 12 have been described in detail above, and are not repeated herein. It is to be noted that, the steps in fig. 12 can be implemented as a plurality of program codes or circuits, which is not limited in this case. In addition, the method of fig. 12 may be used with the above exemplary embodiments, or may be used alone, and the present disclosure is not limited thereto.

In summary, the data storage method, the memory storage device and the memory control circuit unit according to the exemplary embodiments of the invention can store the first data and the first parity data in the relatively small number of first entity management units with a relatively low code rate in the host write operation. Therefore, the protection capability of the first parity data to the first data across the entity units can be maintained on the premise of considering the data access efficiency. On the other hand, in the data merging operation (e.g., garbage collection operation), the second data and the second parity data can be stored in a relatively large number of second pmus by a relatively high code rate. Therefore, on the premise of not greatly influencing the data protection capability of the cross-entity unit, the storage space occupied by the second parity data can be reduced as much as possible and/or the effective utilization rate of the storage space can be improved. Therefore, the encoding and storing mechanisms of the data can be well balanced in the host writing operation or the data merging operation.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data storage method is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of entity management units, and the data storage method comprises the following steps:

receiving first data from a host system;

encoding the first data based on a first code rate to generate first parity data;

storing the first data and the first parity data in a plurality of first entity management units of the plurality of entity management units;

collecting second data from the rewritable non-volatile memory module;

encoding the second data based on a second code rate to generate second parity data, wherein the first code rate is different from the second code rate; and

storing the second data and the second parity data in a plurality of second entity management units of the plurality of entity management units.

2. The data storage method of claim 1, wherein the first data and the second data are stored in the first entity management units and the second entity management units respectively through the same programming pattern.

3. The data storage method of claim 1, wherein a protection capability of the first data by the first parity data is higher than a protection capability of the second data by the second parity data.

4. The data storage method of claim 1, wherein a total number of the plurality of first entity management units is less than a total number of the plurality of second entity management units.

5. The data storage method of claim 1, wherein each entity management unit of the plurality of entity management units corresponds to a die, a chip enable area, or a plane of the rewritable nonvolatile memory module.

6. The data storage method of claim 1, wherein the first code rate reflects a ratio between a data amount of the first data and a data amount of the first parity data, the second code rate reflects a ratio between a data amount of the second data and a data amount of the second parity data, and the first code rate is lower than the second code rate.

7. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

the rewritable nonvolatile memory module comprises a plurality of entity management units; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is to:

receiving first data from the host system;

sending a first write command sequence that indicates that the first data and the first parity data are stored in a plurality of first entity management units of the plurality of entity management units;

collecting second data from the rewritable non-volatile memory module;

sending a second write command sequence that instructs storage of the second data and the second parity data in a plurality of second ones of the plurality of entity management units.

8. The memory storage device of claim 7, wherein the first data and the second data are stored in the first entity management units and the second entity management units, respectively, by the same programming pattern.

9. The memory storage device of claim 7, wherein the first parity data has a higher protection capability for the first data than the second parity data.

10. The memory storage device of claim 7, wherein a total number of the plurality of first entity management units is less than a total number of the plurality of second entity management units.

11. The memory storage device of claim 7, wherein each entity management unit of the plurality of entity management units corresponds to a die, a chip enable area, or a plane in the rewritable non-volatile memory module.

12. The memory storage device of claim 7, wherein the first code rate reflects a ratio between an amount of data of the first data and an amount of data of the first parity data, the second code rate reflects a ratio between an amount of data of the second data and an amount of data of the second parity data, and the first code rate is lower than the second code rate.

13. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of entity management units, and the memory control circuit unit includes:

a host interface for connecting to a host system;

a memory interface for connecting to the rewritable nonvolatile memory module;

an error checking and correcting circuit; and

memory management circuitry connected to the host interface, the memory interface, and the error checking and correcting circuitry,

wherein the memory management circuitry is to receive first data from a host system,

the error checking and correcting circuit is to encode the first data based on a first code rate to generate first parity data,

the memory management circuit is further configured to send a first write command sequence instructing to store the first data and the first parity data in a first one of the plurality of PMUs,

the memory management circuit is further configured to collect second data from the rewritable non-volatile memory module,

the error checking and correcting circuit is further configured to encode the second data based on a second code rate to generate second parity data, wherein the first code rate is different from the second code rate, and

the memory management circuit is further configured to send a second write command sequence that indicates that the second data and the second parity data are stored in a plurality of second entity management units of the plurality of entity management units.

14. The memory control circuit unit of claim 13, wherein the first data and the second data are stored in the first plurality of entity management units and the second plurality of entity management units respectively through the same programming pattern.

15. The memory control circuit unit of claim 13, wherein a protection capability of the first data by the first parity data is higher than a protection capability of the second data by the second parity data.

16. The memory control circuitry unit of claim 13, wherein a total number of the plurality of first entity management units is less than a total number of the plurality of second entity management units.

17. The memory control circuit unit of claim 13, wherein each of the plurality of entity management units corresponds to a die, a chip enable region, or a plane in the rewritable non-volatile memory module.

18. The memory control circuit unit according to claim 13, wherein the first code rate reflects a ratio between a data amount of the first data and a data amount of the first parity data, the second code rate reflects a ratio between a data amount of the second data and a data amount of the second parity data, and the first code rate is lower than the second code rate.