CN110275668A - Block management method, memorizer control circuit unit and memory storage apparatus - Google Patents

Block management method, memorizer control circuit unit and memory storage apparatus Download PDF

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Publication number
CN110275668A
CN110275668A CN201810207659.2A CN201810207659A CN110275668A CN 110275668 A CN110275668 A CN 110275668A CN 201810207659 A CN201810207659 A CN 201810207659A CN 110275668 A CN110275668 A CN 110275668A
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China
Prior art keywords
block
physical blocks
data
mapping table
control circuit
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Granted
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CN201810207659.2A
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Chinese (zh)
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CN110275668B (en
Inventor
林小东
李明彦
李国荣
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

The present invention provides a kind of block management method, memorizer control circuit unit and memory storage apparatus, for managing multiple physical blocks in reproducible nonvolatile memorizer module.The method includes: reading user's data from the first instance block in multiple physical blocks, to obtain the multiple parameters for corresponding to first instance block；The multiple parameters for corresponding to first instance block are input in block identification machine learning model, first instance block is grouped to the first block group or the second block group with the output result according to block identification machine learning model；Establish the first block mapping table and the second block mapping table；The logical address of first block mapping table is mapped to the physical blocks for belonging to the first block group and the logical address of the second block mapping table is mapped to the physical blocks for belonging to the second block group.

Description

Block management method, memorizer control circuit unit and memory storage apparatus
Technical field
The present invention relates to a kind of block management method, memorizer control circuit unit and memory storage apparatus, especially relate to And a kind of block management method based on machine learning, memorizer control circuit unit and memory storage apparatus.
Background technique
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, so that consumer is to storage The demand of media also rapidly increases.Since reproducible nonvolatile memorizer module (for example, flash memory) has data It is non-volatile, power saving, small in size, and without characteristics such as mechanical structures, so being very suitable to be built into above-mentioned illustrated various In portable multimedia device.
Flash memory would generally be divided into multiple physical blocks (physical block).In general, in flash memory Physical blocks are the minimum unit erased in reservoir.That is, each physical blocks contain minimal amount be erased together deposit Storage unit.Each physical blocks would generally be divided into multiple physical pages (physical page).Physical page is usually sequencing (program) minimum unit, in other words, physical page are the minimum unit that data are written or read data.
When flash memory storage is used as the storage media of installation computer operating system, operating system can be frequent Specific data is accessed to property, for example, file configuration table (File Allocation Table, abbreviation FAT).In above-mentioned running machine The physical blocks for making lower flash memory storage can continually be erased to complete the update of data.However, entity The number of erasing of block is limited (for example, physical blocks will be damaged after erasing 10,000 times), therefore in reality of continually erasing In the case where body block, the service life of flash memory storage will substantially shorten.
In general, storing data all has a specific use pattern to operating system on the storage means.For example, certain entities The degree of wear of block is excessively high, and the degree of wear of certain physical blocks is too low.It therefore, if can be according to the mill of each physical blocks Damage degree designs different writing mechanisms, then can will effectively promote the efficiency of flash memory storage, extends quick flashing The service life of memory storage apparatus.Base this, this field technical staff need to constantly be researched and developed and can fifty-fifty be deposited using flash memory The block management method of all physical blocks in storage system, effectively to extend the service life of flash memory storage system.
Summary of the invention
The present invention provides a kind of block management method, memorizer control circuit unit and memory storage apparatus.
One example of the present invention embodiment proposes a kind of block management method, for managing duplicative non-volatile memories Multiple physical blocks in device module.This block management method includes: to read from the first instance block in multiple physical blocks User's data out, to obtain the multiple parameters for corresponding to first instance block；Multiple ginsengs of first instance block will be corresponded to Number is input in blocks identification machine learning model, with the output result according to block identification machine learning model by first instance Block is grouped to the first block group or the second block group；Establish the first block mapping table and the second block mapping table；By the firstth area The logical address of block mapping table maps to the first instance block for belonging to the first block group；And patrolling the second block mapping table Address of cache is collected to the first instance block for belonging to the second block group.
In one example of the present invention embodiment, the logical address of above-mentioned first block mapping table is arranged in the second block and reflects Before the logical address of firing table.
In one example of the present invention embodiment, the data of the above-mentioned logical address for being stored in the first block mapping table are covered It writes frequency and is greater than the overriding frequency for being stored in the data of logical address of the second block mapping table.
In one example of the present invention embodiment, above-mentioned multiple parameters include reading busy time parameter, error bit position Set at least one of parameter and storage holding force parameter.
In one example of the present invention embodiment, above-mentioned errant bit locations parameter is that basis is read from each physical blocks Out in user's data, in the distribution of multiple error bits of upper entity program unit, in the more of middle entity program unit The distribution of a error bit and the distribution of multiple error bits in lower entity program unit obtain.
In one example of the present invention embodiment, above-mentioned block management method further include: read when from first instance block User's data can not be corrected in error checking and correct operation and when being corrected after reading operation again, memory pipe Circuit is managed being grouped first instance block to the second block group.
In one example of the present invention embodiment, above-mentioned block management method further include: write-in test data to each institute State multiple physical blocks；Test data is read from each the multiple physical blocks, to obtain corresponding to each the multiple The multiple parameters of physical blocks；And as unit of each the multiple physical blocks, each the multiple entity will be corresponded to The parameter of block is input in block identification machine learning model, will with the output result according to block identification machine learning model Multiple physical blocks are at least grouped into the first block group and the second block group.
In one example of the present invention embodiment, above-mentioned block management method further include: test data is written to multiple First tests physical blocks and reads test data, to obtain the parameters of corresponding multiple first tests physical blocks；It will test Data are written to multiple second test physical blocks and read test data, to obtain corresponding multiple second test physical blocks Parameter；And multiple first test physical blocks, the parameter of corresponding multiple first test physical blocks, multiple second are tested The parameter of physical blocks and corresponding multiple second test physical blocks carries out machine learning as training data and operates with training Block identifies machine learning model.
In one example of the present invention embodiment, above-mentioned block management method further include: by patrolling for the first block mapping table Volume address of cache to before belonging to the physical blocks of the first block group, according to block identification machine learning model output as a result, Sequence belongs to the physical blocks of the first block group.
One example of the present invention embodiment proposes a kind of memory storage apparatus comprising connector, duplicative are non-easily The property lost memory module and memorizer control circuit unit.Connector is electrically connected to host system.Duplicative is non- Volatile includes multiple physical blocks.Memorizer control circuit unit is electrically connected to connector and duplicative Non-volatile memory module.Here, memorizer control circuit unit is to be written test data to each physical blocks.Storage Device control circuit unit reads user from the first instance block in multiple physical blocks to assign reading instruction sequence Data, to obtain the multiple parameters for corresponding to first instance block.In addition, memorizer control circuit unit is to establish the firstth area Block mapping table and the second block mapping table；The logical address of first block mapping table is mapped to and belongs to the first of the first block group Physical blocks；And the logical address of the second block mapping table is mapped to the first instance block for belonging to the second block group.
In one example of the present invention embodiment, above-mentioned memorizer control circuit unit is also to by the first block mapping table Logical address be arranged in front of the logical address of the second block mapping table.
In one example of the present invention embodiment, above-mentioned memorizer control circuit unit is to be stored in the first block map The overriding frequency of the data of the logical address of table is greater than memorizer control circuit unit to be stored in the second block mapping table The overriding frequency of the data of logical address.
In one example of the present invention embodiment, when the user's data read from first instance block error checking with It can not be corrected in correct operation and when being corrected after reading operation again, above-mentioned memorizer control circuit unit is to by first Physical blocks are grouped to the second block group.
In one example of the present invention embodiment, above-mentioned memorizer control circuit unit is also to assign write instruction sequence Test data is written to each the multiple physical blocks；Memorizer control circuit unit also to assign read instruction sequence from Test data is read in each the multiple physical blocks, to obtain the multiple ginsengs for corresponding to each the multiple physical blocks Number；And as unit of each the multiple physical blocks, memorizer control circuit unit is also each described will correspond to The parameter of multiple physical blocks is input in block identification machine learning model, according to the defeated of block identification machine learning model Multiple physical blocks are at least grouped into the first block group and the second block group by result out.
In one example of the present invention embodiment, above-mentioned memorizer control circuit unit also to by test data be written to Multiple first test physical blocks and read test data, will to obtain the multiple parameters of corresponding first test physical blocks Test data is written to multiple second test physical blocks and reads test data, to obtain corresponding second test physical blocks Multiple parameters.Also, memorizer control circuit unit is also to test physical blocks, corresponding first test entity area for first The parameter of the parameter of block, the second test physical blocks and corresponding second test physical blocks carries out engineering as training data Operation is practised to train block cognitron device learning model.
In one example of the present invention embodiment, belong to the firstth area mapping to the logical address of the first block mapping table Before the running of the physical blocks of block group, memorizer control circuit unit is also to according to the defeated of block identification machine learning model Out as a result, sequence belongs to the physical blocks of the first block group.
One example of the present invention embodiment proposes a kind of memorizer control circuit unit comprising host interface, memory Interface and memory management circuitry.Host interface is electrically connected to host system.Memory interface is electrically connected to Reproducible nonvolatile memorizer module, reproducible nonvolatile memorizer module include multiple physical blocks.Memory Management circuit is electrically connected to host interface and memory interface.Here, memory management circuitry is to assign reading sequence of instructions Column read user's data from the first instance block in multiple physical blocks, correspond to the more of first instance block to obtain A parameter.In addition, memory management circuitry will correspond to the multiple parameters of first instance block to assign write instruction sequence It is input in block identification machine learning model, with the output result according to block identification machine learning model by first instance area Block is grouped to the first block group or the second block group.Memory management circuitry is to establish the first block mapping table and the second block Mapping table.Memory management circuitry belongs to the first of the first block group to map to the logical address of the first block mapping table Physical blocks；And memory management circuitry belongs to the second block group to map to the logical address of the second block mapping table First instance block.
In one example of the present invention embodiment, above-mentioned memory management circuitry is also to patrolling the first block mapping table Address arrangement is collected before the logical address of the second block mapping table.
In one example of the present invention embodiment, above-mentioned memory management circuitry is to be stored in the first block mapping table The overriding frequency of the data of logical address is greater than logical address of the memory management circuitry to be stored in the second block mapping table Data overriding frequency.
In one example of the present invention embodiment, when the user's data read from first instance block error checking with It can not be corrected in correct operation and when being corrected after reading operation again, above-mentioned memory management circuitry is to by first instance Block is grouped to the second block group.
In one example of the present invention embodiment, memory management circuitry is also to assign the write-in test of write instruction sequence Data are to each the multiple physical blocks；Memory management circuitry also reads instruction sequence from each the multiple to assign Test data is read in physical blocks, to obtain the multiple parameters for corresponding to each the multiple physical blocks；And with each The multiple physical blocks are unit, parameter of the memory management circuitry also will correspond to each the multiple physical blocks It is input in block identification machine learning model, with the output result according to block identification machine learning model by multiple entity areas Block is at least grouped into the first block group and the second block group.
In one example of the present invention embodiment, above-mentioned memory management circuitry will also be surveyed to assign write instruction sequence Examination data are written to multiple first instance blocks and read test data, to obtain multiple ginsengs of corresponding first instance block Number.In addition, also test data is written to multiple second test entities to assign write instruction sequence for memory management circuitry Block and test data is read, to obtain the multiple parameters of corresponding second test physical blocks.And memory management circuitry Also to test physical blocks, the parameter of corresponding first test physical blocks, the second test physical blocks and corresponding for first The parameter of two test physical blocks carries out machine learning as training data and operates to train block cognitron device learning model.
In one example of the present invention embodiment, belong to the firstth area mapping to the logical address of the first block mapping table Before the running of the physical blocks of block group, memory management circuitry is also to the output knot according to block identification machine learning model Fruit, sequence belong to the physical blocks of the first block group.
Based on above-mentioned, block management method, memorizer control circuit unit and memory storage apparatus provided by the invention, Using block identification machine learning model judged according to the multiple parameters of physical blocks physical blocks use state and will be real Body block is grouped, and with the good physical blocks of preferential use state, is reached and is fifty-fifty used flash memory storage system In all physical blocks purpose.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is the host system according to shown by an exemplary embodiment, memory storage apparatus and input/output (I/O) The schematic diagram of device.
Fig. 2 is the host system according to shown by another exemplary embodiment, memory storage apparatus and input/output (I/ O) the schematic diagram of device.
Fig. 3 is the schematic diagram of the host system according to shown by another exemplary embodiment and memory storage apparatus.
Fig. 4 is the schematic block diagram of the host system according to shown by an exemplary embodiment and memory storage apparatus.
Fig. 5 is the schematic block diagram of the memorizer control circuit unit according to shown by an exemplary embodiment.
The mapping schematic diagram of logical address and physical blocks when Fig. 6 is the initialization according to shown by an exemplary embodiment.
Fig. 7 is that the box of the identification machine learning model progress block management of the block according to shown by an exemplary embodiment shows It is intended to.
Fig. 8 is the mapping schematic diagram of the physical blocks according to shown by an exemplary embodiment and block mapping table.
Fig. 9 is the flow chart of the block management method according to shown by an exemplary embodiment.
Figure 10 is the method flow diagram that block identification machine learning model is established according to shown by an exemplary embodiment.
Figure 11 is the method flow diagram that the physical blocks according to shown by an exemplary embodiment are grouped again.
Description of symbols
10: memory storage apparatus；
11: host system；
12: input/output (I/O) device；
110: system bus；
111: processor；
112: random access memory (RAM)；
113: read-only memory (ROM)；
114: data transmission interface；
20: motherboard；
201:U disk；
202: storage card；
203: solid state hard disk；
204: radio memory storage device；
205: GPS module；
206: network interface card；
207: radio transmitting device；
208: keyboard；
209: screen；
210: loudspeaker；
30: memory storage apparatus；
31: host system；
32:SD card；
33:CF card；
34: embedded storage device；
341: embedded multi-media card；
342: embedded type multi-core piece sealed storage device；
402: connecting interface unit；
404: memorizer control circuit unit；
406: reproducible nonvolatile memorizer module；
502: memory management circuitry；
504: host interface；
506: memory interface；
508: buffer storage；
510: electric power management circuit；
512: error checking and correcting circuit；
LBA (0)~LBA (N), LBA (M), LBA (M+1), LBA (M+2): logical address；
410 (0)~410 (N), 410 (S), 410 (M), 410 (M+1), 410 (P), 410 (N+1), 410 (N+2), 410 (N+ 3): physical blocks；
701: block identifies machine learning model；
702: training data；
1,2,703: parameter；
420: the first block groups；
430: the second block groups；
4101: the first test physical blocks；
4102: the second test physical blocks；
70:31: busy time parameter is read；
7032: errant bit locations parameter；
7033: storage keeps force parameter；
TA: the first block mapping table；
TB: the second block mapping table；
S901: the step of test data to each physical blocks are written；
S903: test data is read from each physical blocks to obtain the multiple parameters corresponding to each physical blocks Step；
S905: the parameter for corresponding to each physical blocks is input to block identification machine as unit of each physical blocks Physical blocks are at least grouped into the output result according to block identification machine learning model by the first block group in learning model Or the step of the second block group；
S907: the step of establishing the first block mapping table and the second block mapping table；
S909: the logical address of the first block mapping table is mapped to the physical blocks for belonging to the first block group and by second The logical address of block mapping table maps to the step of physical blocks for belonging to the second block group；
S1001: test data is written to multiple first test physical blocks and reads test data to obtain correspondence The step of parameter of first test physical blocks；
S1003: test data is written to multiple second test physical blocks and reads test data to obtain correspondence The step of parameter of second test physical blocks；
S1005: physical blocks, the parameter of corresponding first test physical blocks, the second test physical blocks are tested by first Machine learning is carried out as training data with the parameter of corresponding second test physical blocks to operate to train block cognitron device The step of learning model；
S1101: user's data are read from the first instance block in multiple physical blocks and correspond to first to obtain The step of multiple parameters of physical blocks；
S1103: the parameter for corresponding to first instance block is input in block identification machine learning model according to area First instance block is grouped again to the first block group or the second block by another output result of block identification machine learning model The step of group.
Specific embodiment
In general, memory storage apparatus (also referred to as, storage system) includes duplicative non-volatile memories Device module and controller (also referred to as, control circuit unit).Be commonly stored device storage device be used together with host system so that Host system can write data into memory storage apparatus or read from memory storage apparatus data.
Fig. 1 is the host system according to shown by an exemplary embodiment, memory storage apparatus and input/output (I/O) The schematic diagram of device, and Fig. 2 is the host system according to shown by another exemplary embodiment, memory storage apparatus and defeated Enter/export the schematic diagram of (I/O) device.
Fig. 1 and Fig. 2 are please referred to, host system 11 generally comprises processor 111, random access memory (random Access memory, RAM) 112, read-only memory (read only memory, ROM) 113 and data transmission interface 114.Place Reason device 111, random access memory 112, read-only memory 113 and data transmission interface 114 are all electrically connected to system bus (system bus)110。
In this exemplary embodiment, host system 11 is by 10 electricity of data transmission interface 114 and memory storage apparatus Property connection.For example, host system 11 can write data into memory storage apparatus 10 via data transmission interface 114 or from depositing Data are read in reservoir storage device 10.In addition, host system 11 is electrically connected by system bus 110 and I/O device 12. For example, output signal can be sent to I/O device 12 via system bus 110 or received from I/O device 12 defeated by host system 11 Enter signal.
In this exemplary embodiment, processor 111, random access memory 112, read-only memory 113 and data transmission Interface 114 is on the motherboard 20 for may be provided at host system 11.The number of data transmission interface 114 can be one or more. By data transmission interface 114, motherboard 20 can be electrically connected to memory storage apparatus 10 via wired or wireless way. Memory storage apparatus 10 can be for example USB flash disk 201, storage card 202, solid state hard disk (Solid State Drive, SSD) 203 or Radio memory storage device 204.Radio memory storage device 204 can be for example close range wireless communication (Near Field Communication Storage, NFC) memory storage apparatus, radio facsimile (WiFi) memory storage apparatus, bluetooth (Bluetooth) memory storage apparatus or low-power consumption bluetooth memory storage apparatus (for example, iBeacon) etc. are with various wireless Memory storage apparatus based on mechanics of communication.In addition, motherboard 20 can also be electrically connected to entirely by system bus 110 Ball positioning system (Global Positioning System, GPS) module 205, network interface card 206, radio transmitting device 207, the various I/O device such as keyboard 208, screen 209, loudspeaker 210.For example, motherboard 20 can pass through in an exemplary embodiment 207 access wireless memory storage apparatus 204 of radio transmitting device.
In an exemplary embodiment, mentioned host system is substantially to cooperate with memory storage apparatus to store The arbitrary system of data.Although host system is explained with computer system, this exposure is not in above-mentioned exemplary embodiment It is limited to this.Fig. 3 is the schematic diagram of the host system according to shown by another exemplary embodiment and memory storage apparatus.It please refers to Fig. 3, in another exemplary embodiment, host system 31 be also possible to digital camera, video camera, communication device, audio player, The systems such as video player or tablet computer, and memory storage apparatus 30 can be its used SD card 32, CF card 33 or embedding Enter the various non-volatile memory storage device such as formula storage device 34.Embedded storage device 34 includes embedded multi-media card (embedded MMC, eMMC) 341 and/or embedded type multi-core piece sealed storage device (embedded Multi Chip Package, eMCP) embedded on all types of substrates that memory module is directly electrically connected to host system such as 342 deposit Storage device.
Fig. 4 is the schematic block diagram of the host system according to shown by an exemplary embodiment and memory storage apparatus.
Referring to figure 4., memory storage apparatus 10 include connecting interface unit 402, memorizer control circuit unit 404 with Reproducible nonvolatile memorizer module 406.
In this exemplary embodiment, connecting interface unit 402 is to be compatible to secure digital (Secure Digital, SD) to connect Mouth standard.However, it is necessary to be appreciated that, the invention is not limited thereto, and connecting interface unit 402 is also possible to meet serial advanced skill Art attachment (Serial Advanced Technology Attachment, SATA) standard, parallel advanced technology annex (Parallel Advanced Technology Attachment, PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral part Connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, general serial Bus (Universal Serial Bus, USB) standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) interface mark Standard, two generation of ultrahigh speed (Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory Stick, MS) interface Standard, multi-chip package (Multi-Chip Package) interface standard, multimedia storage card (Multi Media Card, MMC) interface standard, built-in multimedia storage card (Embedded Multimedia Card, eMMC) interface standard, general fast Flash memory (Universal Flash Storage, UFS) interface standard, embedded type multi-core piece encapsulate (embedded Multi Chip Package, eMCP) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electronics Interface (Integrated Device Electronics, IDE) standard or other suitable standards.In this exemplary embodiment, Connecting interface unit 402 can be encapsulated in memorizer control circuit unit 404 in a chip or connecting interface unit 402 It is to be laid in outside a chip comprising memorizer control circuit unit.
Memorizer control circuit unit 404 is to execute multiple logic gates or control with hardware pattern or Solid form implementation System instruction, and writing for data is carried out in reproducible nonvolatile memorizer module 406 according to the instruction of host system 11 The operation such as enter, read and erase.
Reproducible nonvolatile memorizer module 406 is electrically connected to memorizer control circuit unit 404, and uses The data being written with host system 11.Reproducible nonvolatile memorizer module 406 has physical blocks (also referred to as real Body erased cell) 410 (0)~410 (P).For example, physical blocks 410 (0)~410 (P) can belong to the same memory crystal grain (die) or belong to different memory crystal grains.Each physical blocks are respectively provided with several physical page (also referred to as entity programs Unit), wherein the physical page for belonging to the same physical blocks can be written independently and simultaneously be erased.However, it is necessary to Be appreciated that, the invention is not limited thereto, each physical blocks be can by 64 physical pages, 256 physical pages or other A physical page of anticipating is formed.
In more detail, physical blocks are the minimum unit erased.That is, each physical blocks contain the one of minimal amount And the storage unit being erased.Physical page is the minimum unit of sequencing.That is, physical page is the minimum list that data are written Member.Each physical page generally includes data bit area and redundancy ratio special zone.Data bit area includes multiple entity access addresses To store the data of user, and redundancy ratio special zone to storage system data (for example, control information and error correction Code).It can include 8 entity access addresses in the data bit area of each physical page in this exemplary embodiment, and one The size of entity access address is 512 bytes (byte).However, can also be wrapped in data bit area in other exemplary embodiments Containing the more or fewer entity access addresses of number, the present invention is not intended to limit the size and number of entity access address.For example, In an exemplary embodiment, physical blocks are entity erased cell, and physical page is that entity program unit or entity are fanned Area, but invention is not limited thereto.
In this exemplary embodiment, reproducible nonvolatile memorizer module 406 is single-order storage unit (Single Level Cell, SLC) NAND type flash memory module be (that is, can store the quick flashing of 1 data bit in a storage unit Memory module).However, the invention is not limited thereto, it is single that reproducible nonvolatile memorizer module 406 can also be multistage storage First (Multi Level Cell, MLC) NAND type flash memory module is (that is, can store 2 data ratios in a storage unit Special flash memory module), Complex Order storage unit (Trinary Level Cell, TLC) NAND type flash memory mould Block (that is, flash memory module that 3 data bits can be stored in a storage unit) or other with the same characteristics deposit Memory modules.
Fig. 5 is the schematic block diagram of the memorizer control circuit unit according to shown by an exemplary embodiment.
Referring to figure 5., memorizer control circuit unit 404 includes memory management circuitry 502, host interface 504 and deposits Memory interface 506.
Overall operation of the memory management circuitry 502 to control memorizer control circuit unit 404.Specifically, it deposits Reservoir, which manages circuit 502, has multiple control instructions, and when memory storage apparatus 10 operates, these control instructions can quilt It executes the running such as to carry out the write-in of data, read and erase.
In this exemplary embodiment, the control instruction of memory management circuitry 502 is to carry out implementation with Solid form.For example, Memory management circuitry 502 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to Order is programmed in so far read-only memory.When memory storage apparatus 10 operates, these control instructions can be by microprocessor Unit is executed the running such as to carry out the write-in of data, read and erase.
In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 502 can also be with procedure code pattern The specific region of reproducible nonvolatile memorizer module 406 is stored in (for example, being exclusively used in storage system in memory module The system area of data) in.In addition, memory management circuitry 502 has microprocessor unit (not shown), read-only memory (not Show) and random access memory (not shown).In particular, this read-only memory has driving code, and when memory controls When circuit unit 404 is enabled, microprocessor unit can first carry out this driving code section, and will to be stored in duplicative non-volatile Control instruction in memory module 406 is loaded into the random access memory of memory management circuitry 502.Later, micro- place Reason device unit such as can operate these control instructions to carry out the write-in of data, read and erase at the running.
In addition, the control instruction of memory management circuitry 502 can also be with a hardware in another exemplary embodiment of the present invention Pattern carrys out implementation.For example, memory management circuitry 502 includes microcontroller, Storage Unit Management circuit, memory write-in electricity Road, memory reading circuitry, memory are erased circuit and data processing circuit.Storage Unit Management circuit, memory write-in electricity Circuit is erased on road, memory reading circuitry, memory and data processing circuit is electrically connected to microcontroller.Wherein, it stores Physical blocks of the Single Component Management circuit to manage reproducible nonvolatile memorizer module 406；Memory write circuit is used It writes data into duplicative is non-volatile and deposits to assign write instruction to reproducible nonvolatile memorizer module 406 In memory modules 406；Memory reading circuitry to reproducible nonvolatile memorizer module 406 assign reading instruction with Data are read from reproducible nonvolatile memorizer module 406；Memory erases circuit to non-volatile to duplicative Property memory module 406 assign erase instruction data to be erased from reproducible nonvolatile memorizer module 406；And it counts According to processing circuit to handle be intended to be written data to reproducible nonvolatile memorizer module 406 and from duplicative it is non- The data read in volatile 406.
Host interface 504 is electrically connected to memory management circuitry 502 and is electrically connected to connecting interface list Member 402, to receive and identify instruction and data that host system 11 is transmitted.That is, the finger that host system 11 is transmitted Order and data can be sent to memory management circuitry 502 by host interface 504.In this exemplary embodiment, host interface 504 be to be compatible to SATA standard.However, it is necessary to be appreciated that the invention is not limited thereto, host interface 504 is also possible to be compatible to PATA standard, 1394 standard of IEEE, PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other suitable data transmission standards.
Memory interface 506 is electrically connected to memory management circuitry 502 and non-volatile to access duplicative Property memory module 406.That is, the data for being intended to be written to reproducible nonvolatile memorizer module 406 can be via depositing Memory interface 506 is converted to the 406 receptible format of institute of reproducible nonvolatile memorizer module.
Buffer storage 508 is electrically connected to memory management circuitry 502 and is configured to temporarily store from host system 11 data and instruction or the data from reproducible nonvolatile memorizer module 406.
In an exemplary embodiment, memorizer control circuit unit 404 further includes buffer storage 508, power management electricity Road 510 and error checking and correcting circuit 512.
Electric power management circuit 510 is electrically connected to memory management circuitry 502 and to control memory storage dress Set 10 power supply.
Error checking and correcting circuit 512 are electrically connected to memory management circuitry 502 and to execute wrong inspection It looks into and correction program is to ensure the correctness of data.Specifically, when memory management circuitry 502 is received from host system 11 When to write instruction, error checking can be the corresponding error checking of data generation of this corresponding write instruction with correcting circuit 512 With correcting code (Error Checking and Correcting Code, ECC Code), and 502 meeting of memory management circuitry The data of this corresponding write instruction are written with corresponding error checking and correcting code to type nonvolatile mould In block 406.Later, meeting when reading data from reproducible nonvolatile memorizer module 406 when memory management circuitry 502 The corresponding error checking of this data and correcting code are read simultaneously, and error checking and correcting circuit 512 can be examined according to this mistake It looks into and error checking and correction program is executed to read data with correcting code.
In this exemplary embodiment, error checking and correcting circuit 512 are with low-density parity check code (low Density parity code, LDPC) Lai Shizuo.However, in another exemplary embodiment, error checking and correcting circuit 512 It can also be with BCH code, convolution code (convolutional code), turbine code (turbo code), bit reversal (bit ) etc. flipping coding/decodings algorithm carrys out implementation.
Specifically, memory management circuitry 202 can be according to received data and corresponding error checking and correcting code (hereinafter also referred to error-correcting code) generates error-correcting code frame (ECC Frame) and error-correcting code frame is written to can In manifolding formula non-volatile memory module 406.Later, when memory management circuitry 502 is from duplicative non-volatile memories When device module 406 reads data, error checking can be tested with correcting circuit 512 according to the error-correcting code in error-correcting code frame Demonstrate,prove the correctness of read data.
Memory management circuitry 502, host interface 504 and memory interface 506, buffer storage 508, electricity is described below Operation performed by power management circuits 510 and error checking and correcting circuit 512, see also for by memorizer control circuit list Performed by member 404.
The mapping schematic diagram of logical address and physical blocks when Fig. 6 is the initialization according to shown by an exemplary embodiment.
It will be appreciated that when being described herein the running of the physical blocks of reproducible nonvolatile memorizer module 406, Carrying out application entity block with words such as " groupings " is concept in logic.That is, reproducible nonvolatile memorizer module The physical locations of physical blocks do not change, but in logic to the physical blocks of reproducible nonvolatile memorizer module It is operated.
In general, before the factory of memory storage apparatus 10, manufacturer will use production tool (Mass Production tool, MP tool) it is operated to open card to the execution of memory storage apparatus 10, to execute initialization action.
Fig. 6 is please referred to, for example, memory management circuitry 502 can configure logical address LBA (0)~LBA (N) to map reality Body block 410 (0)~410 (N).In an exemplary embodiment, memory management circuitry 502 can extract physical blocks and patrol to store Address-physical address mapping table (logical address-physical address mapping table) is collected to patrol to record Collect the mapping relations of address LBA (0)~LBA (N) and physical blocks 410 (0)~410 (N).
Fig. 7 is that the box of the identification machine learning model progress block management of the block according to shown by an exemplary embodiment shows It is intended to.
Please refer to Fig. 7.In an exemplary embodiment, memory management circuitry 502 will be surveyed to assign write instruction sequence Examination data are respectively written into multiple first tests physical blocks 4101 and more into reproducible nonvolatile memorizer module 406 It a second test physical blocks 4102 and assigns and reads instruction sequence and read test data respectively, to obtain corresponding multiple first Test the parameter 1 of physical blocks 4101 and the parameter 2 of corresponding multiple second test physical blocks, and memory management circuitry 502 is real by multiple first test physical blocks 4101, the parameter 1 of corresponding multiple first test physical blocks, multiple second tests The parameter 2 of body block 4102 and corresponding multiple second test physical blocks carries out machine learning operation as training data 702, To train block cognitron device learning model 701.
In an exemplary embodiment, test data is written to duplicative is non-volatile and is deposited by memory management circuitry 502 Multiple physical blocks 410 (0)~410 (N) in memory modules 406 correspond to physical blocks 410 (0)~410 (N) to obtain Multiple parameters 703, as unit of each physical blocks, by correspond to each physical blocks parameter 703 be input to It, will with the output result according to block identification machine learning model 701 in block identification machine learning model 701 after stating training Physical blocks 410 (0)~410 (N) in reproducible nonvolatile memorizer module 406 are at least grouped into the first block group 420 and the second block group 430.
Parameter 703 corresponding to physical blocks 410 (0)~410 (N) is the degree of wear or other influences with physical blocks Its use state is related.In this exemplary embodiment, the multiple parameters 703 corresponding to physical blocks 410 (0)~410 (N) are for example Including reading busy time parameter 7031, errant bit locations parameter 7032, storage holding force parameter 7033.Here, mistake ratio Special location parameter 7032 is read in test data according to from physical blocks 410 (0)~410 (N), in upper entity program list Member multiple error bits distribution, middle entity program unit multiple error bits distribution and in lower entity program The distributions of more error bits of unit obtains.
Similarly, it corresponding first tests the parameter 1 of physical blocks 4101 and corresponds to the second test physical blocks 4102 Parameter 2 also includes reading busy time parameter, errant bit locations parameter and storage to keep force parameter.
Specifically, it is assumed that using 1000 physical blocks in reproducible nonvolatile memorizer module 406 as sample This, is written into 1000 physical blocks as sample and reads test data for test data, obtain correspond to this 1000 The multiple parameters of each physical blocks in a physical blocks are known using these parameters and these 1000 physical blocks as block The training data 702 of other machine learning model 701 carries out machine learning to train block cognitron device learning model 701.Especially It is that after training data 702 is input to block identification machine learning model 701, block identifies that machine learning model 701 can be to instruction Practice data 702 and carry out study analysis, extract the feature of training data 702 and finds out these parameters and these 1000 physical blocks Between rule, construct at least two groups set, thus judge physical blocks using the feature of extraction and the rule learning found out Use state, and these 1000 physical blocks are divided by least two groups block group according at least two groups set.In general, Sample size as training data is more, and block identifies that machine learning model 701 learns more, can more improve block identification The accuracy of machine learning model 701.
For example, when one of physical blocks as sample being received the instruction of read/write test data, Test data is written or from the time of physical blocks read test data as the busy time parameter of reading to physical blocks.If writing It is longer than preset time to physical blocks or from the time of physical blocks read test data to enter test data, that is to say, that entity area The busy time parameter of the reading of block time parameter more busy than preset reading is big, then this can be classified as the physical blocks of sample For the physical blocks of use state general (or poor), and it is grouped to the second block group 430.At this point, block identifies machine Learning model 701 will do it machine learning, extract feature to this busy time parameter of reading as the physical blocks of sample, point It analyses it and reads the rule between busy time parameter and the grouping of physical blocks.For example, joining later for the busy time will be read Number is same or similar to read busy time parameters or than the preset physical blocks that read busy time parameter big, block cognitron This physical blocks can be classified as the second block group 430 of use state general (or poor) by device learning model 701.
Block identification machine learning model 701 position of error bit can also occur according to the storage unit in physical blocks It sets to be judged physical blocks and be grouped.As an example it is assumed that reproducible nonvolatile memorizer module 406 is plural number Rank storage unit (Trinary Level Cell, TLC) NAND type flash memory module, in write-in test data to TLC NAND type flash memory module as sample physical blocks and from this physical blocks read test data, it is available right It should be in the errant bit locations parameter of this physical blocks.Wherein, there is the position of error bit in the storage unit of this physical blocks Distribution including multiple error bits in upper entity program unit, middle physical page multiple error bits distribution and In the distribution of the error bit of lower entity program unit.Block identification machine learning model 701 is joined according to errant bit locations Physical blocks are classified as that use state is good or the group of use state general (or poor) by number.For example, from physical blocks When reading test data, if test data can not be corrected in error checking and correct operation, and it must use and read voltage weight again New read test data could complete timing, and such physical blocks can be classified as the group of use state general (or poor) Not, it and is grouped to the second block group 430.
That is, memory management circuitry 502 using read voltage from physical blocks read test data when, if making With this read voltage can not read test data when, memory management circuitry 502 adjust again read voltage again to physical blocks It is read.If can read test number after re-reading operation to physical blocks execution using reading voltage adjusted According to, and the position of mistake occur using error checking and correct operation detection physical blocks and correct mistake, then it is such Physical blocks still can be used and its use state is general (or poor).In other words, memory management circuitry 502 is using reading When voltage is from physical blocks read test data, if test data, such entity can be corrected in error checking and correct operation Block can be classified as the good group of use state, and be grouped to the first block group 420.Similarly, block identifies machine Learning model 701 can analyze error bit position to this errant bit locations parameter extraction feature as the physical blocks of sample The rule between parameter and the grouping of physical blocks is set, and carries out machine learning.
In order to improve the accuracy of block identification machine learning model 701, block identifies that machine learning model 701 can be to work For all parameter extraction features of 1000 physical blocks of sample, to the rule between these parameters and the grouping of physical blocks Machine learning is carried out, so that establishing can be to the reality in reproducible nonvolatile memorizer module 406 after machine learning The block identification machine learning model 701 with sufficient accuracy that body block 410 (0)~410 (N) are grouped.
Fig. 8 is the mapping schematic diagram of the physical blocks according to shown by an exemplary embodiment and block mapping table.
Fig. 8 is please referred to, memory management circuitry 502 establishes the first block mapping table TA and the second block mapping table TB. There is first block mapping table TA logical address LBA (0)~LBA (M), the second block mapping table TB to have logical address LBA (M+ 1)~LBA (N).In this exemplary embodiment, logical address LBA (0)~LBA (M) of the first block mapping table TA is arranged in Before the logical address LBA (M+1) of two block mapping table TB~LBA (N).In reproducible nonvolatile memorizer module 406 Through block identification machine learning model 701 can be divided into use state good and use shape for physical blocks 410 (0)~410 (N) Two groups of state general (or poor), i.e. the first block group 420 and the second block group 430.In an exemplary embodiment, block is known The good physical blocks of use state can be divided into the first block group 420 by other machine learning model 701, and can be by use state The physical blocks of generally (or poor) are divided into the second block group 430.The logical address LBA (0) of first block mapping table TA~ LBA (M) maps to the physical blocks for belonging to the first block group 420, and the logical address LBA (M+1) of the second block mapping table TB~ LBA (N) maps to the physical blocks for belonging to the second block group 430.
For example, memory management circuitry 502 will override the high data of frequency and be stored in the firstth area in an exemplary embodiment In the logical address LBA (0) of block mapping table TA~LBA (M), and the lower data of frequency will be override it is stored in the second block and reflect In the logical address LBA (M+1) of firing table TB~LBA (N).In general, memory management circuitry 502 can select preferential use to patrol Volume preceding physical blocks of address arrangement, that is to say, that memory management circuitry 502 can select preferential use to map to belong to the The physical blocks of one block group 420.
Please refer to Fig. 8 again, memory management circuitry 502 is from the entity area of reproducible nonvolatile memorizer module 406 Searching entities block 410 (0) in block 410 (0)~410 (N), memory management circuitry 502 are assigned the write-in of write instruction sequence and are surveyed Examination data are to physical blocks 410 (0) and assign reading instruction sequence reading test data from physical blocks 410 (0), to obtain After the busy time parameter of reading, errant bit locations parameter and storage corresponding to physical blocks 410 (0) keep force parameter, Above-mentioned parameter is input to block identification machine learning model 701, block identifies machine learning model 701 according to above-mentioned parameter It practises and is grouped physical blocks 410 (0).For example, if block identifies machine learning model 701 according to physical blocks 410 (0) Rule between parameter and grouping divides physical blocks 410 (0) to the second block group of use state general (or poor) 430, then physical blocks 410 (0) can be mapped to the logical address LBA (M+1) in the second block mapping table TB.
Similarly, memory management circuitry 502 continues the physical blocks from reproducible nonvolatile memorizer module 406 Searching entities block 410 (1) in 410 (0)~410 (N), memory management circuitry 502 assign the write-in test of write instruction sequence Data are to physical blocks 410 (1) and assign reading instruction sequence reading test data from physical blocks 410 (1), corresponded to After the parameter of physical blocks 410 (1), above-mentioned parameter is input to block identification machine learning model 701.If block cognitron Device learning model 701 is preferable to use state by physical blocks 410 (1) point according to the rule learning between above-mentioned parameter and grouping The first block group 420, then physical blocks 410 (1) can be mapped to the logical address LBA (0) in the first block mapping table TA.
Memory management circuitry 502 continues the physical blocks 410 (0) from reproducible nonvolatile memorizer module 406 Searching entities block 410 (S) in~410 (N), memory management circuitry 502 assign write instruction sequence write-in test data extremely Physical blocks 410 (S) simultaneously assign reading instruction sequence reading test data, obtain the parameter for corresponding to physical blocks 410 (S) Afterwards, above-mentioned parameter is input to block identification machine learning model 701.If block identifies machine learning model 701 according to above-mentioned When rule learning between parameter and grouping divides physical blocks 410 (S) to the first block group 420 preferable to use state, then Physical blocks 410 (S) can be mapped to the logical address LBA (1) in the first block mapping table TA.
Memory management circuitry 502 continues the physical blocks 410 (0) from reproducible nonvolatile memorizer module 406 Searching entities block 410 (M) in~410 (N), memory management circuitry 502 assign write instruction sequence write-in test data extremely Physical blocks 410 (M) simultaneously assign reading instruction sequence reading test data, obtain the parameter for corresponding to physical blocks 410 (M) Afterwards, above-mentioned parameter is input to block identification machine learning model 701.If block identifies machine learning model 701 according to above-mentioned When rule learning between parameter and grouping divides physical blocks 410 (M) to the first block group 420 preferable to use state, then Physical blocks 410 (M) can be mapped to the logical address LBA (2) in the first block mapping table TA.
It further says, belongs to the first block group mapping to the logical address LBA (2) of the first block mapping table TA Before 420 physical blocks, the output according to block identification machine learning model 701 is as a result, sequence belongs to the first block group 420 Physical blocks.That is, will belong to before the logical address LBA (2) of the first block mapping table TA is mapped to 410 (M) It is ranked up in the physical blocks 410 (1) of the first block group 420 and 410 (S).
Similarly, it maps to by the logical address LBA (M+1) of the second block mapping table TB~LBA (N) and belongs to the secondth area Before the physical blocks of block group 430, the output according to block identification machine learning model 701 is as a result, sequence belongs to the second block The physical blocks of group 430.
In an exemplary embodiment, if desired by the physical blocks 410 of reproducible nonvolatile memorizer module 406 (0)~410 the physical blocks 410 (S) in (N) are grouped again, then read user's data, from physical blocks 410 (S) to obtain The multiple parameters corresponding to physical blocks 410 (S) are obtained, multiple parameters are input in block identification machine learning model 701, with Physical blocks 410 (S) are grouped again to the first block group by another output result according to block identification machine learning model 701 420 or the second block group 430.
Fig. 9 is the flow chart of the block management method according to shown by an exemplary embodiment.
Please refer to Fig. 9.In step S901, test data is written to each physical blocks in memory management circuitry 502.
In step S903, memory management circuitry 502 reads test data from each physical blocks, to obtain correspondence In the multiple parameters of each physical blocks.
In step S905, as unit of each physical blocks, memory management circuitry 502 will correspond to each entity area The parameter of block is input in block identification machine learning model, will be real with the output result according to block identification machine learning model Body block is at least grouped into the first block group or the second block group.
In step s 907, memory management circuitry 502 establishes the first block mapping table and the second block mapping table.
In step S909, memory management circuitry 502, which maps to the logical address of the first block mapping table, belongs to The physical blocks of one block group, and the logical address of the second block mapping table is mapped to the entity area for belonging to the second block group Block.
Figure 10 is the method flow diagram that block identification machine learning model is established according to shown by an exemplary embodiment.
Figure 10 is please referred to, before the step of test data to each physical blocks are written in memory management circuitry 502, also Including step S1001.In step S1001, memory management circuitry 502 assign write instruction sequence by test data be written to Multiple first test physical blocks and assign reading instruction sequence reading test data, test entity area to obtain corresponding first The parameter of block.
In the step s 1003, memory management circuitry 502 assigns write instruction sequence and test data is written to multiple Two test physical blocks and assign reading instruction sequence reading test data, to obtain the corresponding second ginseng for testing physical blocks Number.
In step S1005, memory management circuitry 502 tests physical blocks, corresponding first test entity area for first The parameter of the parameter of block, the second test physical blocks and corresponding second test physical blocks carries out engineering as training data Operation is practised to train block cognitron device learning model.
Figure 11 is the method flow diagram that the physical blocks according to shown by an exemplary embodiment are grouped again.
Figure 11 is please referred to, in step S1101, memory management circuitry 502, which is assigned, reads instruction sequence from multiple entities User's data are read in first instance block in block, to obtain the multiple parameters for corresponding to first instance block.
In step S1103, the parameter for corresponding to first instance block is input in block identification machine learning model, First instance block is grouped again to the first block group with another output result according to block identification machine learning model or Second block group.
In conclusion block identification machine learning model of the invention judges entity according to the multiple parameters of physical blocks Physical blocks are simultaneously grouped by the use state of block, and the logical address being arranged in front in block mapping table is mapped to The good physical blocks of use state reflect block in order to the high data of the overriding such as preferential write operation system data frequency The physical blocks that posterior logical address maps to use state general (or poor) are arranged in firing table, in order to which overriding is written The low data of frequency.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field Middle technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore protection of the invention Range is subject to view as defined in claim.

Claims (27)

1. a kind of block management method, for managing multiple physical blocks in reproducible nonvolatile memorizer module, It is characterized in that, the block management method includes:
User's data are read from the first instance block in the multiple physical blocks, correspond to described first in fact to obtain The multiple parameters of body block；
The multiple parameter for corresponding to the first instance block is input in block identification machine learning model, with foundation The first instance block is grouped to the first block group or the secondth area by the output result of the block identification machine learning model Block group；
Establish the first block mapping table and the second block mapping table；
The logical address of first block mapping table is mapped to the physical blocks for belonging to the first block group；And
The logical address of second block mapping table is mapped to the physical blocks for belonging to the second block group.
2. block management method according to claim 1, wherein the logical address of first block mapping table is arranged in Before the logical address of second block mapping table.
3. block management method according to claim 2, wherein being stored in the logical address of first block mapping table Data overriding frequency be greater than be stored in second block mapping table logical address data overriding frequency.
4. block management method according to claim 1, wherein the multiple parameter includes reading busy time parameter, mistake Errored bit location parameter and storage keep at least one of force parameter.
5. block management method according to claim 4, wherein the errant bit locations parameter is according to from each institute State and read in multiple physical blocks in user's data, multiple error bits of upper entity program unit distribution, Point of distribution in multiple error bits of middle entity program unit and multiple error bits in lower entity program unit Cloth obtains.
6. block management method according to claim 1, further includes:
When the user's data read from the first instance block can not be corrected in error checking with correct operation And when being corrected after reading operation again, the first instance block is grouped to the second block group.
7. block management method according to claim 1, further includes:
Test data is written to each the multiple physical blocks；
The test data is read from each the multiple physical blocks, corresponds to each the multiple physical blocks to obtain Multiple parameters；And
As unit of each the multiple physical blocks, the parameter for corresponding to each the multiple physical blocks is input to described Block identifies in machine learning model, with the output result according to block identification machine learning model by the multiple entity Block is at least grouped into the first block group and the second block group.
8. block management method according to claim 7, further includes:
The test data is written to multiple first test physical blocks and reads the test data, to obtain corresponding institute State the parameter of multiple first test physical blocks；
The test data is written to multiple second test physical blocks and reads the test data, to obtain corresponding institute State the parameter of multiple second test physical blocks；And
By the multiple first test physical blocks, the parameter of corresponding the multiple first test physical blocks, the multiple the The parameter of two test physical blocks and corresponding the multiple second test physical blocks carries out machine learning as training data Operation identifies machine learning model with the training block.
9. block management method according to claim 1, further includes:
Before the logical address of first block mapping table is mapped to the physical blocks for belonging to the first block group, foundation The output of the block identification machine learning model is as a result, sequence belongs to the physical blocks of the first block group.
10. a kind of memory storage apparatus characterized by comprising
Connector is electrically connected to host system；
Reproducible nonvolatile memorizer module, including multiple physical blocks；And
Memorizer control circuit unit is electrically connected to the connector and the reproducible nonvolatile memorizer module,
Wherein the memorizer control circuit unit reads instruction sequence from first in the multiple physical blocks to assign User's data are read in physical blocks, to obtain the multiple parameters for corresponding to the first instance block；
Wherein the memorizer control circuit unit is to be input to area for the multiple parameters for corresponding to the first instance block Block identifies in machine learning model, with the output result according to block identification machine learning model by the first instance area Block is grouped to the first block group or the second block group；
Wherein the memorizer control circuit unit is to establish the first block mapping table and the second block mapping table；
Wherein the memorizer control circuit unit belongs to institute to map to the logical address of first block mapping table The physical blocks of the first block group are stated, and
Wherein the memorizer control circuit unit belongs to institute to map to the logical address of second block mapping table State the physical blocks of the second block group.
11. memory storage apparatus according to claim 10, wherein the memorizer control circuit unit is to by institute The logical address for stating the first block mapping table is arranged in front of the logical address of second block mapping table.
12. memory storage apparatus according to claim 11, wherein the memorizer control circuit unit is to store The logical address of first block mapping table data overriding frequency be greater than the memorizer control circuit unit to It is stored in the overriding frequency of the data of the logical address of second block mapping table.
13. memory storage apparatus according to claim 10, wherein the multiple parameter includes reading busy time ginseng Number, errant bit locations parameter and storage keep at least one of force parameter.
14. memory storage apparatus according to claim 13, wherein the errant bit locations parameter is according to from every It is read in one the multiple physical blocks in user's data, in point of multiple error bits of upper entity program unit Cloth, middle entity program unit multiple error bits distribution and in multiple error bits of lower entity program unit Distribution is to obtain.
15. memory storage apparatus according to claim 10, wherein when from described in first instance block reading User's data can not be corrected in error checking and correct operation and when being corrected after reading operation again, the memory Control circuit unit is being grouped the first instance block to the second block group.
16. memory storage apparatus according to claim 10, wherein
Also test data is written to each the multiple reality to assign write instruction sequence in the memorizer control circuit unit Body block；
The memorizer control circuit unit is also read from each the multiple physical blocks to assign reading instruction sequence The test data, to obtain the multiple parameters for corresponding to each the multiple physical blocks；And
As unit of each the multiple physical blocks, the memorizer control circuit unit is also each described will correspond to The parameter of multiple physical blocks is input in the block identification machine learning model, to identify machine learning according to the block The multiple physical blocks are at least grouped into the first block group and the second block group by the output result of model.
17. memory storage apparatus according to claim 16,
Wherein the memorizer control circuit unit also to assign said write instruction sequence by the test data be written to Multiple first test physical blocks and read the test data, to obtain corresponding the multiple first test physical blocks Multiple parameters；
Wherein the memorizer control circuit unit also to assign said write instruction sequence by the test data be written to Multiple second test physical blocks and read the test data, to obtain corresponding the multiple second test physical blocks Multiple parameters；And
The memorizer control circuit unit is also to survey the multiple first test physical blocks, corresponding the multiple first Try the multiple parameters of physical blocks, the multiple second test physical blocks and corresponding the multiple second test physical blocks Multiple parameters carry out machine learning operation as training data with the training block identification machine learning model.
18. memory storage apparatus according to claim 10, wherein by first block mapping table logically Location maps to before the running for the physical blocks for belonging to the first block group, the memorizer control circuit unit also to according to According to the output of block identification machine learning model as a result, sequence belongs to the physical blocks of the first block group.
19. a kind of memorizer control circuit unit, which is characterized in that the memorizer control circuit unit includes:
Host interface is electrically connected to host system；
Memory interface is electrically connected to reproducible nonvolatile memorizer module, wherein the duplicative is non-easily The property lost memory module includes multiple physical blocks；And
Memory management circuitry is electrically connected to the host interface and the memory interface,
Wherein the memory management circuitry reads instruction sequence from the first instance in the multiple physical blocks to assign User's data are read in block, to obtain the multiple parameters for corresponding to the first instance block；
Wherein the memory management circuitry is known the multiple parameters for corresponding to the first instance block are input to block In other machine learning model, the first instance block is divided with the output result according to block identification machine learning model Group is to the first block group or the second block group；
Wherein the memory management circuitry is to establish the first block mapping table and the second block mapping table；
Wherein the memory management circuitry belongs to described to map to the logical address of first block mapping table The physical blocks of one block group；And
Wherein the memory management circuitry belongs to described to map to the logical address of second block mapping table The physical blocks of two block groups.
20. memorizer control circuit unit according to claim 19, wherein the memory management circuitry is also to incite somebody to action The logical address of first block mapping table is arranged in front of the logical address of second block mapping table.
21. memorizer control circuit unit according to claim 20, wherein the memory management circuitry is to store It is greater than the memory management circuitry to store in the overriding frequency of the data of the logical address of first block mapping table In the overriding frequency of the data of the logical address of second block mapping table.
22. memorizer control circuit unit according to claim 19, wherein the multiple parameter includes when reading busy Between parameter, errant bit locations parameter and storage keep force parameter at least one.
23. memorizer control circuit unit according to claim 22, wherein the errant bit locations parameter is basis It is read in user's data from each the multiple physical blocks, in multiple error bits of upper entity program unit Distribution, middle entity program unit multiple error bits distribution and in multiple wrong ratios of lower entity program unit Special distribution obtains.
24. memorizer control circuit unit according to claim 19, wherein when being read from the first instance block User's data can not be corrected in error checking and correct operation and when being corrected after reading operation again, described to deposit Reservoir manages circuit being grouped the first instance block to the second block group.
25. memorizer control circuit unit according to claim 19, wherein
Also test data is written to each the multiple entity area to assign write instruction sequence in the memory management circuitry Block；
The memory management circuitry is also read described in instruction sequence reads from each the multiple physical blocks to assign Test data, to obtain the multiple parameters for corresponding to each the multiple physical blocks；And
As unit of each the multiple physical blocks, the memory management circuitry is also each the multiple will correspond to The parameter of physical blocks is input in the block identification machine learning model, to identify machine learning model according to the block Output result the multiple physical blocks are at least grouped into the first block group and the second block group.
26. memorizer control circuit unit according to claim 25,
Wherein also the test data is written to multiple to assign said write instruction sequence for the memory management circuitry First instance block and the test data is read, to obtain the multiple parameters of corresponding the multiple physical blocks；
Wherein also the test data is written to multiple to assign said write instruction sequence for the memory management circuitry Second tests physical blocks and reads the test data, to obtain the multiple of corresponding the multiple second test physical blocks Parameter；And
Wherein the memory management circuitry is also to survey the multiple first test physical blocks, corresponding the multiple first Try the multiple parameters of physical blocks, the multiple second test physical blocks and corresponding the multiple second test physical blocks Multiple parameters carry out machine learning operation as training data with the training block identification machine learning model.
27. memorizer control circuit unit according to claim 19, wherein in patrolling first block mapping table Before volume address of cache to the running for the physical blocks for belonging to the first block group, the memory management circuitry also to according to According to the output of block identification machine learning model as a result, sequence belongs to the physical blocks of the first block group.
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