CN111489776B - Data reading method, storage controller and storage device - Google Patents

Data reading method, storage controller and storage device Download PDF

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Publication number
CN111489776B
CN111489776B CN201910079868.8A CN201910079868A CN111489776B CN 111489776 B CN111489776 B CN 111489776B CN 201910079868 A CN201910079868 A CN 201910079868A CN 111489776 B CN111489776 B CN 111489776B
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target
read voltage
optimization
physical pages
word line
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CN111489776A (en
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萧又华
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Shenzhen Daxin Electronic Technology Co ltd
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Shenzhen Daxin Electronic Technology Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

The invention provides a data reading method. The method comprises the steps of responding to a plurality of monitoring results of a plurality of physical pages corresponding to a target word line, judging that reading voltage optimization operation needs to be executed on a target physical page in the physical pages, and updating a target optimization count value corresponding to the target physical page; and performing a first type read voltage optimization operation, a second type read voltage optimization operation, or a third type read voltage optimization operation corresponding to the target word line according to the target optimization count value to obtain an optimized read voltage set corresponding to the target word line, wherein the target word line is read by using the optimized read voltage set.

Description

Data reading method, storage controller and storage device
Technical Field
The present invention relates to a data reading method, and more particularly, to a data reading method, a memory controller and a memory device suitable for a memory device configured with a rewritable nonvolatile memory module.
Background
Generally, when reading data from the rewritable nonvolatile memory module, if a read failure does not occur, the system reads the data using a predetermined read voltage set or a previously used optimized read voltage set. Until a read failure occurs, the system (memory system) does not use the preset read voltage set or the used optimal voltage, and adjusts the read voltage set accordingly to try to find an optimized read voltage set, so as to successfully read the correct data by using the optimized read voltage.
However, conventionally, adjusting the read voltage set to obtain an optimized read voltage set to read data is mostly to perform a read voltage optimization operation (also called word line Level (Wordline Level) read voltage optimization operation) on the read voltage set corresponding to the target word line, and perform the read voltage optimization operation on all physical pages of the target word line at the same time. That is, the reason why the read failure is ignored in the conventional method may not be from all the physical pages of the target word line, but from a specific physical page of the target word line with poor read condition (e.g., a target physical page with a large number of error bits).
Since the conventional method cannot perform the Page Level (Page Level) read voltage optimization operation only for the transition read voltage for identifying the specific physical Page with poor read condition of the target word line. Therefore, when the reading condition of a specific physical page of the plurality of physical pages of the target word line is poor, the conventional method needs to consume a large amount of resources to perform the reading voltage optimization operation of the entire target word line, so as to obtain the optimized reading voltage corresponding to the converted reading voltage of the specific physical page, thereby improving the reading condition of the specific physical page. This results in a reduction in the efficiency of reading data.
On the other hand, when a specific physical page of the target word line is determined to need to be read for the read voltage optimization due to poor reading conditions, the conventional practice does not consider or predict whether other physical pages need to be read for the read voltage optimization at this time point. That is, the conventional method requires that the read voltage is optimized for a specific physical page or a word line until the read condition of the specific physical page of the plurality of physical pages of the word line is poor. In this way, since the conventional method performs the read voltage optimization operation when the read condition of the specific physical page is found to be poor due to the data read operation, the conventional method may cause the delay of the data read operation, thereby reducing the overall efficiency of the memory device.
Therefore, it is one of the subjects studied by the skilled in the art how to determine and predict the timing for performing the word line level read voltage optimization operation and the timing for performing the page level read voltage optimization operation, and quickly and efficiently optimize the transition read voltage for identifying the storage state of a specific physical page without preparing verification data, so as to improve the defects of the conventional method, thereby improving the data reading efficiency of the rewritable nonvolatile memory module and reducing the load of the code reduction operation.
Disclosure of Invention
The invention provides a data reading method, a memory controller and a memory device, which can determine and predict the time for executing the word line level reading voltage optimization operation and the time for executing the page level reading voltage optimization operation, quickly and efficiently obtain an accurate page level optimization reading voltage set under the condition of not preparing verified data, and further can correctly read the data of a corresponding physical page through the optimization reading voltage set, thereby improving the efficiency of the data reading operation.
An embodiment of the present invention provides a data reading method for a storage device configured with a rewritable nonvolatile memory module. The rewritable non-volatile memory module has a plurality of word lines, wherein each of the plurality of word lines is coupled to a plurality of memory cells, wherein each of the plurality of memory cells comprises a plurality of physical pages, and each of the plurality of physical pages is configured to be programmed to a bit value. The method comprises the following steps: selecting one of the plurality of word lines as a target word line, and monitoring a plurality of physical pages of the selected target word line to obtain a plurality of monitoring results of the plurality of physical pages respectively corresponding to the target word line; updating a target optimization count value corresponding to a target physical page in response to determining that a read voltage optimization operation needs to be performed on the target physical page of the plurality of physical pages of the target word line according to the monitoring results; and performing a first type read voltage optimization operation, a second type read voltage optimization operation, or a third type read voltage optimization operation corresponding to the target word line according to the target optimization count value to obtain an optimized read voltage set corresponding to the target word line, wherein the target word line is read by using the optimized read voltage set.
An embodiment of the present invention provides a memory controller for controlling a memory device configured with a rewritable non-volatile memory module. The storage controller includes: the device comprises a connection interface circuit, a memory interface control circuit, a reading voltage management circuit unit and a processor. The connection interface circuit is used for being coupled to a host system. The memory interface control circuit is configured to be coupled to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of word lines, each of the plurality of word lines is coupled to a plurality of memory cells, each of the plurality of memory cells includes a plurality of physical pages, and each of the plurality of physical pages is configured to be programmed to a bit value. The processor is coupled to the connection interface circuit, the memory interface control circuit and the read voltage management circuit unit. The processor is configured to select one of the plurality of word lines as a target word line, and monitor a plurality of physical pages of the selected target word line to obtain a plurality of monitoring results of the plurality of physical pages respectively corresponding to the target word line. In response to the processor determining that a read voltage optimization operation needs to be performed on a target physical page of the physical pages of the target word line according to the monitoring results, the read voltage management circuit unit is configured to update a target optimization count value corresponding to the target physical page, wherein the read voltage management circuit unit is further configured to perform a first type read voltage optimization operation, a second type read voltage optimization operation, or a third type read voltage optimization operation corresponding to the target word line according to the target optimization count value, so as to obtain an optimized read voltage set corresponding to the target word line, and the target word line is read by using the optimized read voltage set.
An embodiment of the present invention provides a memory device. The storage device comprises a rewritable nonvolatile memory module, a memory interface control circuit and a processor. The rewritable nonvolatile memory module is provided with a plurality of word lines, wherein each word line is coupled to a plurality of memory cells, each memory cell in the memory cells comprises a plurality of physical pages, and each physical page in the physical pages is used for being programmed to be one bit value. The memory interface control circuit is used for being coupled to the rewritable nonvolatile memory module. The processor is coupled to the memory interface control circuit. The processor loads and executes a read voltage management program code module to realize a data reading method. The data reading method comprises the following steps: selecting one of the plurality of word lines as a target word line, and monitoring a plurality of physical pages of the selected target word line to obtain a plurality of monitoring results of the plurality of physical pages respectively corresponding to the target word line; updating a target optimization count value corresponding to a target physical page in response to determining that a read voltage optimization operation needs to be performed on the target physical page of the plurality of physical pages of the target word line according to the monitoring results; and performing a first type read voltage optimization operation, a second type read voltage optimization operation, or a third type read voltage optimization operation corresponding to the target word line according to the target optimization count value to obtain an optimized read voltage set corresponding to the target word line, wherein the target word line is read by using the optimized read voltage set.
Based on the above, the data reading method, the memory controller and the memory device provided in the embodiments of the present invention may update the target optimized count value corresponding to a target physical page in response to determining that a read voltage optimization operation needs to be performed on a target physical page of a plurality of physical pages of the target word line, and determine whether to perform the read voltage optimization operation on other physical pages or on the entire target word line according to the target optimized count value; and reading the target word line using the obtained optimized read voltage set corresponding to the target word line after the read voltage optimization operation is completed. In this way, the accuracy of the data read from the target word line is improved, and the overall efficiency of the data read operation of the memory device is improved.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a block diagram illustrating a host system and a storage device according to an embodiment of the invention;
FIG. 2A is a flow chart of a data reading method according to an embodiment of the invention;
FIG. 2B is a flowchart illustrating step S25 of FIG. 2A according to an embodiment of the invention;
FIG. 3A is a flowchart illustrating step S27 of FIG. 2A according to one embodiment of the invention;
FIG. 3B is a flowchart illustrating step S27 of FIG. 2A according to another embodiment of the invention;
FIG. 4A is a diagram illustrating threshold voltage distributions of a plurality of memory cells of a word line corresponding to a first read voltage pattern and corresponding memory states of a physical page according to an embodiment of the present invention;
FIG. 4B is a diagram illustrating a read voltage optimization cycle for each of a plurality of physical pages of a wordline corresponding to a first read voltage pattern according to one embodiment of the present invention;
FIG. 5A is a diagram illustrating threshold voltage distributions of a plurality of memory cells of a wordline corresponding to a second read voltage pattern and corresponding memory states of a physical page according to an embodiment of the present invention;
FIG. 5B is a diagram illustrating a read voltage optimization cycle for each of a plurality of physical pages of a wordline corresponding to a second read voltage pattern according to an embodiment of the invention.
Description of the reference numerals
10: host system
20: storage device
110. 211: processor with a memory having a plurality of memory cells
120: host memory
130: data transmission interface circuit
210: storage controller
212: data transmission management circuit
213: memory interface control circuit
214: error checking and correcting circuit
215: read voltage management circuit unit
2151: optimized counting circuit
2152: read voltage optimization circuit
216: buffer memory
217: power management circuit
220: rewritable nonvolatile memory module
230: connection interface circuit
S21, S23, S25, S27: flow steps of data reading method
S251, S253, S255, S257, S259: step of step S25
S310, S311, S312, S313, S314, S315, S316, S317: step of step S27
S320, S321, S322, S323, S324, S325, S326, S327: step of step S27
V(i)1～V(i)7: read voltage
L: bit value of lower physical page
M: bit value of medium physical page
U: bit value of upper physical page
G1-G8: kuei code
SL1, SL2, SL 3: storage state of lower physical page
SM1, SM2, SM 3: memory state of medium physical page
SU1, SU2, SU3, SU4, SU 5: memory state of upper physical page
TPL、TPM、TPU: read voltage optimization cycle
T0-T6: point in time
Detailed Description
In the embodiment, the memory device includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a memory device controller (also referred to as a memory controller or a memory control circuit). Further, the storage device is used with a host system so that the host system can write data to or read data from the storage device.
FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention.
Referring to fig. 1, a Host System (Host System)10 includes a Processor (Processor)110, a Host Memory (Host Memory)120, and a Data Transfer Interface Circuit (Data Interface Circuit) 130. In the present embodiment, the data transmission interface circuit 130 is coupled (also referred to as electrically connected) to the processor 110 and the host memory 120. In another embodiment, the processor 110, the host memory 120 and the data transmission interface circuit 130 are coupled to each other by a System Bus (System Bus).
The Memory device 20 includes a Memory Controller (Storage Controller)210, a Rewritable Non-Volatile Memory Module (Rewritable Non-Volatile Memory Module)220, and a Connection Interface Circuit (Connection Interface Circuit) 230. The Memory controller 210 includes a processor 211, a Data Management Circuit (Data Management Circuit)212, and a Memory Interface Control Circuit (Memory Interface Control Circuit) 213.
In the present embodiment, the host system 10 is coupled to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operation. For example, the host system 10 may store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.
In the present embodiment, the processor 110, the host memory 120 and the data transmission interface circuit 130 may be disposed on a motherboard of the host system 10. The number of the data transmission interface circuits 130 may be one or more. The motherboard can be coupled to the memory device 20 via a wired or wireless connection via the data transmission interface circuit 130. The storage device 20 may be, for example, a usb disk, a memory card, a Solid State Drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon), which are based on various wireless Communication technologies. In addition, the motherboard may also be coupled to various I/O devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, and the like through a System bus.
In the present embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the PCI Express (Peripheral Component Interconnect Express) standard. The data transmission interface circuit 130 and the connection interface circuit 230 transmit data by using a Non-Volatile Memory interface (NVMe) protocol.
However, it should be understood that the present invention is not limited thereto, and the data transmission interface circuit 130 and the connection interface circuit 230 may also conform to Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Serial Advanced Technology Attachment (SATA) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed (UHS-eMI) interface standard, Ultra High Speed (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, Multi-Chip Package (Multi-P Package) interface standard, multimedia Memory Card (Multi-Media) interface, Flash Memory standard (MMC) interface, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. In addition, in another embodiment, the connection interface circuit 230 may be packaged with the memory controller 210 in a chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210.
In the present embodiment, the host memory 120 is used for temporarily storing instructions or data executed by the processor 110. For example, in the present exemplary embodiment, the host Memory 120 may be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), and the like. However, it should be understood that the present invention is not limited thereto, and the host memory 120 may be other suitable memories.
The memory controller 210 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 220 according to commands of the host system 10.
More specifically, the processor 211 in the memory controller 210 is computing hardware for controlling the overall operation of the memory controller 210. Specifically, the processor 211 has a plurality of control commands, and the control commands are executed to write, read and erase data when the memory device 20 is in operation.
It should be noted that, in the embodiment, the Processor 110 and the Processor 211 are, for example, a Central Processing Unit (CPU), a Microprocessor (micro-Processor), or other Programmable Processing Unit (Microprocessor), a Digital Signal Processor (DSP), a Programmable controller, an Application Specific Integrated Circuit (ASIC), a Programmable Logic Device (PLD), or other similar circuit elements, and the invention is not limited thereto.
In one embodiment, the memory controller 210 further has a read only memory (not shown) and a random access memory (not shown). In particular, the rom has a boot code (bootstrap code), and when the memory controller 210 is enabled, the processor 211 executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 220 into the ram of the memory controller 210. Then, the processor 211 operates the control commands to perform data writing, reading, and erasing operations. In another embodiment, the control instructions of the processor 211 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 220, for example, in a physical storage unit of the rewritable nonvolatile memory module 220 dedicated for storing system data.
In the present embodiment, as described above, the memory controller 210 further includes the data management circuit 212 and the memory interface control circuit 213. It should be noted that the operations performed by the components of the storage controller 210 may also be referred to as operations performed by the storage controller 210.
The data management circuit 212 is coupled to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used for receiving an instruction from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written into the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation is performed according to a write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (the data can be read from one or more memory units of the one or more physical units), and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read command from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.
The memory interface control circuit 213 is used to receive an instruction from the processor 211, and cooperate with the data management circuit 212 to perform a writing (also called Programming) operation, a reading operation or an erasing operation on the rewritable nonvolatile memory module 220.
For example, the processor 211 can execute a write command sequence to instruct the memory interface control circuit 213 to write data into the rewritable nonvolatile memory module 220; the processor 211 can execute a read instruction sequence to instruct the memory interface control circuit 213 to read data from one or more physical units (also called target physical units) of the corresponding read instruction of the rewritable nonvolatile memory module 220; the processor 211 can execute an erase command sequence to instruct the memory interface control circuit 213 to perform an erase operation on the rewritable nonvolatile memory module 220. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 220 to perform corresponding operations of writing, reading, and erasing. In one embodiment, the processor 211 may also issue other types of instruction sequences to the memory interface control circuit 213 to perform corresponding operations on the rewritable nonvolatile memory module 220.
In addition, the data to be written into the rewritable nonvolatile memory module 220 is converted into a format accepted by the rewritable nonvolatile memory module 220 through the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable nonvolatile memory module 220, the processor 211 transmits a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, the command sequences may include a write command sequence for indicating writing data, a read command sequence for indicating reading data, an erase command sequence for indicating erasing data, and corresponding command sequences for indicating various memory operations (e.g., changing a plurality of preset read voltage values of a preset read voltage set for performing a read operation, or performing a garbage collection procedure, etc.). The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.
The rewritable nonvolatile memory module 220 is coupled to the memory controller 210 (the memory interface control circuit 213) and is used for storing data written by the host system 10. The rewritable nonvolatile memory module 220 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND flash memory module (i.e., a flash memory module capable of storing 4 bits in one memory Cell), a three-dimensional NAND flash memory module (3D NAND flash memory) or a Vertical NAND flash memory module (Vertical flash memory module) or other modules having the same characteristics A machine module. The memory cells in the rewritable nonvolatile memory module 220 are arranged in an array.
In the embodiment, the rewritable nonvolatile Memory module 220 has a plurality of word lines, wherein each of the word lines is coupled to a plurality of Memory cells (also called Memory cells). The memory cells of the same word line are grouped into one or more physical programming cells. In addition, a plurality of physical programming units can be combined into one physical unit (physical block or physical erasing unit). In the present embodiment, a Triple Level Cell (TLC) NAND flash memory module is taken as an example, that is, in the following embodiments, a memory Cell capable of storing 3 bit values is taken as a Physical programming unit (i.e., in each programming operation, a programming voltage is applied to a Physical programming unit and then a Physical programming unit to program data), wherein each memory Cell includes a Lower Physical Page (Lower Physical Page), a Middle Physical Page (Middle Physical Page), and an Upper Physical Page (Upper Physical Page) that can respectively store one bit value.
In this embodiment, the memory cell is used as the minimum unit for writing (programming) data. The physical cells are the smallest unit of erase, i.e., each physical cell contains one of the smallest number of memory cells that are erased.
The memory controller 210 configures a plurality of logic units to the rewritable nonvolatile memory module 220. The host system 10 accesses the user data stored in the plurality of physical units through the configured logical unit. Here, each logical unit may be composed of one or more logical addresses. For example, a Logical unit may be a Logical Block (Logical Block), a Logical Page (Logical Page), or a Logical Sector (Logical Sector). A logical unit may be mapped to one or more physical units, where a physical unit may be one or more physical addresses, one or more physical sectors, one or more physical programming units, or one or more physical erasing units. In this embodiment, the logic units are logic blocks, and the logic sub-units are logic pages. Each logic unit has a plurality of logic sub-units.
In addition, the memory controller 210 establishes a Logical To Physical address mapping table (Logical To Physical address mapping table) and a Physical To Logical address mapping table (Physical To Logical address mapping table) To record an address mapping relationship between a Logical unit (e.g., a Logical block, a Logical page, or a Logical sector) and a Physical unit (e.g., a Physical erase unit, a Physical program unit, a Physical sector) configured To the rewritable nonvolatile memory module 220. In other words, the memory controller 210 may look up a physical unit mapped by a logical unit through the logical-to-physical address mapping table, and the memory controller 210 may look up a logical unit mapped by a physical unit through the physical-to-logical address mapping table. However, the technical concepts related to the mapping of the logical units and the physical units are conventional in the art and are not intended to be described in the present invention, and are not described herein again.
In the present embodiment, the error checking and correcting circuit 214 is coupled to the processor 211 and is used for performing an error checking and correcting procedure to ensure the correctness of the data. Specifically, when the processor 211 receives a write command from the host system 10, the ECC and ECC circuit 214 generates an Error Correction Code (ECC) and/or an EDC (EDC) for data corresponding to the write command, and the processor 211 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 220. Thereafter, when the processor 211 reads data from the rewritable nonvolatile memory module 220, the corresponding error correction code and/or error check code is simultaneously read, and the error checking and correcting circuit 214 performs an error checking and correcting process on the read data according to the error correction code and/or error check code.
For example, when performing a data read operation on a plurality of physical pages of a word line and performing a corresponding error checking and correcting procedure, the error checking and correcting circuit 214 may obtain a plurality of syndromes corresponding to the plurality of physical pages. The error checking and correcting circuit 214 may return the plurality of syndromes respectively corresponding to the plurality of physical pages to the processor 211. In addition, after the error checking and correcting process is completed, if the read data is successfully decoded, the error checking and correcting circuit 214 can obtain a plurality of error bits respectively corresponding to the plurality of physical pages. The error checking and correcting circuit 214 may return the error bits corresponding to the physical pages to the processor 211.
In one embodiment, the memory controller 210 further includes a buffer memory 216 and a power management circuit 217. The buffer memory is coupled to the processor 211 and is used for temporarily storing data and instructions from the host system 10, data from the rewritable nonvolatile memory module 220, or other system data for managing the storage device 20, so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 216. The power management circuit 217 is coupled to the processor 211 and is used to control the power of the memory device 20.
In the present embodiment, the read voltage management circuit unit 215 includes an optimization counter circuit 2151 and a read voltage optimization circuit 2152. The read voltage management circuit unit 215 is used to manage a plurality of read voltage sets corresponding to a plurality of word lines.
It should be noted that, for convenience of illustration, the following embodiments take a three-level cell type flash memory module as an example, but the data reading method provided by the embodiments of the present invention can also be applied to other types of flash memory modules.
In this embodiment, the read voltage management circuit unit 215 may perform a Page-Level read voltage optimization operation on one or more specific physical pages of a specific word line in the third-order cell type flash memory module according to the arrangement order of the lower physical Page, the middle physical Page, and the upper physical Page, so as to obtain a plurality of optimized read voltages respectively corresponding to the one or more specific physical pages (e.g., one of the lower physical Page, the middle physical Page, and the upper physical Page). In addition, the read voltage management circuit unit 215 may also directly perform a word-line-Level (Wordline-Level) read voltage optimization operation on the specific word line, so as to directly perform the read voltage optimization operation on all physical pages of the specific word line in the three-Level memory cell type flash memory module at the same time, and further obtain an optimized read voltage set (including a plurality of optimized read voltages respectively corresponding to the plurality of physical pages) corresponding to the specific word line.
In this embodiment, if the read voltage optimization operation has been completed and the optimized set of read voltages corresponding to the target word line is obtained, the read voltage management circuit unit 215 may record the optimized set of read voltages corresponding to the target word line.
The data reading method, the memory controller and the memory device according to the embodiments of the present invention will be described in detail below with reference to the drawings, and further, details of how the read voltage management circuit unit 215 performs a first type read voltage optimization operation, a second type read voltage optimization operation or a third type read voltage optimization operation corresponding to the target word line, and the operation flow and functions of the optimization counter circuit 2151 and the read voltage optimization circuit 2152 will be further described.
Fig. 2A is a flowchart illustrating a data reading method according to an embodiment of the invention. Referring to fig. 1 and fig. 2A, in step S21, the processor 211 selects one of a plurality of word lines as a target word line, and monitors a plurality of physical pages of the selected target word line to obtain a plurality of monitoring results respectively corresponding to the plurality of physical pages.
Specifically, the processor 211 may select one of the word lines belonging to the physical units (also referred to as a target word line) and a specific physical page of the target word line (also referred to as a target physical page) of the rewritable non-volatile memory module 220 at a specific time point, and instruct the read voltage management circuit unit 215 to perform a read voltage optimization operation on the target physical page of the target word line. For example, processor 211 may be in (1) the absence of storage device 20 (i.e., storage device 20 is absent for more than a predetermined time threshold); (2) when the storage device is powered on; or (3) when the error bit number of the data read from a word line exceeds an error bit number threshold, selecting a target word line from all the word lines to perform the read voltage optimization operation. The processor 211 may select a word line with a poor physical state (e.g., a word line with a large number of erase times, a large number of read times, a long endurance time, or a large number of error bits) as a target word line. It should be noted that the memory cells and physical pages of the selected target word line have stored data (programmed data).
In one embodiment, the processor 211 may also randomly select a target wordline and select one of the physical pages of the target wordline as the target physical page according to monitoring results of the physical pages of the target wordline.
After the target word line is selected, the processor 211 may monitor a plurality of physical pages of the selected target word line to obtain a plurality of monitoring results respectively corresponding to the plurality of physical pages. The monitoring result comprises: (1) according to the error bits numbers of the physical pages corresponding to the target word line respectively returned by the error checking and correcting circuit 214; and (2) syndromes of a plurality of physical pages respectively corresponding to the target word line.
Next, in step S23, the processor 211 determines whether a read voltage optimization operation needs to be performed on a target physical page of the physical pages according to the monitoring results. According to the different monitoring results, the processor 211 uses different determination methods in step S23.
Specifically, if the monitoring results are a plurality of error bit numbers respectively corresponding to the physical pages, the processor 211 determines whether the error bit numbers are greater than a threshold error bit number. In response to determining that a target number of error bits of the plurality of numbers of error bits is greater than the threshold number of error bits, identifying a physical page corresponding to the target number of error bits as the target physical page, and determining that the read voltage optimization operation needs to be performed on the target physical page of the plurality of physical pages of the target wordline.
On the other hand, if the monitoring results of the physical pages corresponding to the target word line are syndromes corresponding to the physical pages, respectively, the processor 211 determines whether a total number of first bit values (e.g., "1") of the syndromes is greater than a syndrome threshold value. In response to determining that a target syndrome of the plurality of syndromes has a total number of the first bit values that is greater than the syndrome threshold value, identifying a physical page corresponding to the target syndrome as the target physical page, and determining that the read voltage optimization operation needs to be performed on the target physical page of the plurality of physical pages of the target wordline.
In another embodiment, if the monitoring results of the physical pages corresponding to the target word line are syndromes corresponding to the physical pages, respectively, the processor 211 determines whether a total number of second bit values (e.g., "0") of the syndromes is less than another syndrome threshold value. In response to determining that a target syndrome of the plurality of syndromes has a total number of the second bit values that is less than the other syndrome threshold value, identifying a physical page corresponding to the target syndrome as the target physical page, and determining that the read voltage optimization operation needs to be performed on the target physical page of the plurality of physical pages of the target wordline.
In response to determining that the read voltage optimization operation need not be performed for any of the plurality of physical pages of the target wordline (step S23 → NO), flow continues to step S21. That is, the processor 211 may continue to select one of the plurality of word lines as a target word line and monitor a plurality of physical pages of the selected target word line to obtain a plurality of monitoring results respectively corresponding to the plurality of physical pages. In contrast, in response to determining that a read voltage optimization operation needs to be performed on a target physical page of the plurality of physical pages of the target wordline (step S23 → Yes), the flow continues to step S25. At this time, the processor 211 instructs the read voltage management circuit unit 215 that the target physical page is to perform the read voltage optimization operation, and the read voltage management circuit unit 215 performs step S25.
In other words, after performing step S23, the processor 211 may determine whether the read voltage optimization operation needs to be performed on one of the target physical pages in the target word line, or whether the read voltage optimization operation does not need to be performed on any one of the target physical pages in the target word line.
In step S25, the read voltage management circuit unit 215 (or the optimization counting circuit 2151) is used to update the target optimization count value corresponding to the target physical page. Details of step S25 are described below with reference to fig. 2B.
Fig. 2B is a flowchart illustrating step S25 of fig. 2A according to an embodiment of the invention. Referring to fig. 2B, in step S251, the optimization counter circuit 2151 identifies a total number of the converted read voltages respectively corresponding to the physical pages.
Specifically, in the present embodiment, as described above, the target word line stores data. That is, the plurality of memory cells of each word line of the target word line are programmed to store bit values corresponding to one of a plurality of different Gray codes (Gray codes), and the total number of the Gray codes is N. N is a positive integer greater than 2, and the value of N is predetermined according to the type of the rewritable nonvolatile memory module 220. For example, if the rewritable nonvolatile memory module 220 is TLC, N is 8; if the rewritable nonvolatile memory module 220 is an MLC, N is 4; if the rewritable nonvolatile memory module 220 is SLC, N is 2; if the rewritable nonvolatile memory module 220 is QLC, N is 16.
For the sake of uniform description, the present embodiment is exemplified by a three-level flash memory module, and a plurality of memory cells of the target word line can store bit values corresponding to 8 gray codes (N ═ 8). The following description first refers to fig. 4A to describe details of the gray codes, the memory states of the corresponding physical pages, and the corresponding transition read voltages.
FIG. 4A is a diagram illustrating threshold voltage distributions of a plurality of memory cells of a word line corresponding to a first read voltage pattern and corresponding memory states of a physical page according to an embodiment of the invention. Since the exemplary embodiment is described with reference to the rewritable non-volatile memory module 220 being a three-level cell NAND flash memory module, where N is equal to 8 (i.e., 2)3). Each memory cell of the three-rank memory cell NAND type flash memory module has three Physical pages for respectively storing bit data, and each memory cell includes a Lower Physical Page (L), a Middle Physical Page (M), and an Upper Physical Page (U) that can respectively store one bit value. Assume that processor 211 reads voltages V (i) via read voltage set V (i)1～V(i)7Reading a plurality of memory cells (a plurality of target memory cells) of a target word line of a three-level cell NAND type flash memory module, and thereby identifying different bit values (respectively corresponding to the bit values of different Golay codes) stored by the plurality of memory cells. The plurality of read voltages V (i)1～V(i)7The corresponding read voltage groups V (i) are formed according to the respective voltage value sequences.
Assume the rewritable non-volatile memory module 220 is in a first read voltage state (1/2/4). The memory state of each memory cell can be determined according to a read voltage V (i) in a set of read voltages V (i) (e.g., a set of predetermined read voltages corresponding to i equal to 1)1～V(i)7The code can be divided into 8 kinds of Golay codes, such as "L: 1M: 1U: 1", "L: 1M: 1U: 0", "L: 1M: 0U: 1", "L: 0M: 08 Golay codes of U:0 "," L: 0M: 1U: 0 "and" L: 0M: 1U: 1 "(" L: "denotes the bit value of the lower physical page;" M: "denotes the bit value of the middle physical page;" U: "denotes the bit value of the upper physical page). The 8 gray codes can also be represented as "111", "110", "100", "101", "001", "000", "010" and "011", 8 bit value combinations, wherein the bit values in each bit value combination are ordered according to the sequence of the lower, middle and upper physical pages. That is, by applying the read voltages V (i) of different voltage values of the read voltage group V (i)1～V(i)7To a memory cell of the target word line, the processor 211 may determine whether the bit value (also referred to as bit data or read bit value) stored in the memory cell corresponds to one of the plurality of gray codes ("111", "110", "100", "101", "001", "000", "010", and "011") according to whether the channel of the memory cell is turned on (i.e., the read bit value is read from a memory cell of the target word line by using the read voltage group v (i)). It should be noted that the memory cells in the rewritable non-volatile memory module 220 may have a number of gray codes (in this example, 8), and the number of the read voltages in each read voltage group is equal to the number of the gray codes minus one (in this example, 7, i.e., N-1-8-1-7).
In more detail, the gray code stored in one memory unit can be sequentially combined through the storage State (SL) of the lower physical page, the storage State (SM) of the middle physical page and the storage State (SU) of the upper physical page of the memory unit (as shown by a plurality of arrows in fig. 4A).
In the present embodiment, the read voltage V (i)4To distinguish the memory states SL1 ("1") and SL2 ("0") of the lower physical page; read Voltage V (i)2And V (i)6Memory states SM1 ("1"), SM2 ("0"), and SM3 ("1") to distinguish physical pages in between; read Voltage V (i)1、V(i)3、V(i)5、V(i)7Memory states SU1 ("1"), SU2 ("0"), SU3 to distinguish an upper physical page("1"), SU4 ("0"), and SU5 ("1"). The above example can also be seen as the lower physical page having "1" Transition Read Voltage (Read Voltage), i.e., Read Voltage V (i)4(ii) a The middle physical page has "2" switching read voltages, i.e., read voltages V (i)2And V (i)6(ii) a The upper physical page has "4" converted read voltages, i.e., read voltages V (i)1、V(i)3、V(i)5、V(i)7。
That is, the total number of converted read voltages of the lower physical page is "1"; the total number of the conversion reading voltages of the middle physical page is '2'; and the total number of converted read voltages for the upper physical page is "4". The rewritable nonvolatile memory module 220 with the above-described characteristics of multiple physical pages and corresponding total number of converted read voltages can also be considered as a rewritable nonvolatile memory module 220 (three-level cell NAND-type flash memory module) with a first read voltage pattern (1/2/4). The "1/2/4" corresponds to the total number of converted read voltages that the "lower/middle/upper physical pages" have, respectively.
The processor 211 (or the read voltage management circuit unit 215) may sequentially read the word lines by using the converted read voltages corresponding to the lower physical page, the middle physical page, and the upper physical page in the preset read voltage set, so as to obtain the storage states of the lower physical page, the middle physical page, and the upper physical page of the plurality of memory cells of the word lines, and further obtain the gray codes of the plurality of memory cells. For example, assume that the processor 211 (or the read voltage management circuit unit 215) reads a word line using the read voltage v (i) to obtain a plurality of gray codes of a plurality of memory cells of the word line. The processor 211 (or the read voltage management circuit unit 215) first uses the read voltage V (i)4To identify whether the memory state of the lower physical page of all memory cells is the memory state SL1 or the memory state SL 2; next, the processor 211 (or the read voltage management circuit 215) uses the read voltage V (i)2、V(i)6To identify whether the storage state of the physical page of such storage cells is storage state SM1, storage state SM3, or storage state SM 3; followed byThe processor 211 (or the read voltage management circuit unit 215) further uses the read voltage V (i)1、V(i)3、V(i)5、V(i)7The storage state to identify the upper physical page of such storage units is storage state SU1, storage state SU2, storage state SU3, storage state SU4, or storage state SM 5. In this way, the processor 211 (or the read voltage management circuit unit 215) can identify the storage states of the lower physical page, the middle physical page and the upper physical page of all the memory cells, and further identify the gray codes stored in all the memory cells.
However, the present invention is not limited thereto. The data reading method, the memory controller and the memory device provided by the embodiment of the invention can also be suitable for rewritable nonvolatile memory modules with other reading voltage modes. For example, in one embodiment, the rewritable non-volatile memory module 220 is in the second read voltage mode (2/3/2).
FIG. 5A is a diagram illustrating threshold voltage distributions of a plurality of memory cells of a word line corresponding to a second read voltage pattern and corresponding memory states of a physical page according to an embodiment of the invention.
Referring to FIG. 5A, assume that the rewritable nonvolatile memory module 220 is in the second read voltage state (2/3/2). The memory state of each memory cell can be determined according to a read voltage V (i) in a set of read voltages V (i) (e.g., a set of predetermined read voltages corresponding to i equal to 1)1～V(i)7The 8 Gray codes are distinguished, such as 8 Gray codes of L: 1M: 1U: 1, L: 0M: 0U: 0, L: 0M: 1U: 0, L: 1M: 0U: 0 and L: 1M: 0U: 1 (L: ' indicates the bit value of the lower physical page; ' M: ' indicates the bit value of the middle physical page; ' U: ' indicates the bit value of the upper physical page). The 8 gray codes can also be represented as "111", "011", "001", "000", "010", "110", "100" and "101", 8 bit value combinations, wherein the bit values in each bit value combination are ordered according to the sequence of the lower, middle and upper physical pages. That is, by applying the sets of read voltages separatelyV (i) read voltages of different values V (i)1～V(i)7To a memory cell of the target word line, the processor 211 may determine whether the bit value (also referred to as bit data or read bit value) stored in the memory cell corresponds to one of the plurality of gray codes ("111", "011", "001", "000", "010", "110", "100", and "101") according to whether the channel of the memory cell is turned on (i.e., the read bit value is read from a memory cell of the target word line by using the read voltage group v (i)). It should be noted that the memory cells in the rewritable non-volatile memory module 220 may have a number of gray codes (in this example, 8), and the number of the read voltages in each read voltage group is equal to the number of the gray codes minus one (in this example, 7, i.e., N-1-8-1-7).
For the rewritable non-volatile memory module 220 (three-level cell NAND flash memory module) with the second read voltage pattern (2/3/2), the read voltage V (i)1And V (i)5To distinguish the memory states SL1 ("1"), SL2 ("0"), and SL3 ("1") of the lower physical page; read Voltage V (i)2、V(i)4And V (i)6Memory states SM1 ("1"), SM2 ("0"), SM3 ("1"), and SM4 ("0") to distinguish physical pages in between; read Voltage V (i)3And V (i)7The memory states SU1 ("1"), SU2 ("0"), and SU3 ("1") to distinguish the upper physical page. According to the above example, it can be seen that the lower physical page of the memory cells of the rewritable nonvolatile memory module 220 (three-level cell NAND type flash memory module) with the second read voltage pattern (2/3/2) has "2" switching read voltages, i.e. the read voltages V (i)1And V (i)5(ii) a The middle physical page has "3" switching read voltages, i.e., read voltages V (i)2、V(i)4And V (i)6(ii) a The upper physical page has "2" transition read voltages, i.e., read voltages V (i)3And V (i)7。
That is, the total number of converted read voltages of the lower physical page is "2"; the total number of the converted reading voltages of the middle physical page is '3'; and the total number of converted read voltages for the upper physical page is "2". The rewritable nonvolatile memory module 220 with the above-mentioned characteristics of multiple physical pages and the corresponding total number of converted read voltages can also be regarded as a rewritable nonvolatile memory module 220 (three-level cell NAND-type flash memory module) with a second read voltage pattern (2/3/2). The "2/3/2" corresponds to the total number of converted read voltages that the "lower/middle/upper physical pages" have, respectively.
Referring back to fig. 2B, after the transformed read voltage sums respectively corresponding to the physical pages are identified, in step S253, the optimized counter circuit 2151 calculates the least common multiple of the transformed read voltage sums.
FIG. 4B is a diagram illustrating a read voltage optimization cycle for each of a plurality of physical pages of a wordline corresponding to a first read voltage pattern according to an embodiment of the invention. Referring to FIG. 4B, in this example, it is assumed that the rewritable non-volatile memory module 220 corresponds to a first read voltage pattern (1/2/4). The optimized count circuit 2151 has identified a total number of converted read voltages for the lower physical page as "1"; the total number of the conversion reading voltages of the middle physical page is '2'; and the total number of converted read voltages for the upper physical page is "4".
First, it should be noted that, since the memory states of each physical page are distinguished/identified according to the total number of the translation read voltages, if a physical page has more translation read voltages (i.e., the total number of the translation read voltages is larger), the more memory states the physical page needs to be distinguished from each other. For example, in this embodiment (see FIG. 4A), the upper physical page has a total of "4" of translated read voltages, and also has the most memory states (5 memory states distinguished by 4 translated read voltages).
Second, when the read state of a physical page is worse (e.g., the corresponding data read operation fails or the read data fails to be decoded), it indicates that one or more transition read voltages corresponding to the physical page cannot accurately identify/distinguish the memory state of the physical page. This phenomenon may also be considered to have failed the one or more converted read voltages.
Accordingly, assuming that the probability of failure of each of the converted read voltages is equal (or the frequency at which each of the converted read voltages needs to be optimized is the same), the probability of failure of the converted read voltage of a physical page is higher for a physical page with more converted read voltages (e.g., with more differentiated memory states). In other words, for a physical page with more transition read voltages (e.g., more differentiated memory states), the probability that the data read operation corresponding to the physical page is determined to fail is higher (or the probability that the decoding operation performed on the data read from the physical page is determined to fail is higher), and the transition read voltage of the physical page needs to be optimized more frequently (i.e., the frequency of the read voltage optimization operation to be performed on the physical page is higher). That is, the execution period of the read voltage optimization operation (also called the read voltage optimization period) performed on different physical pages can be set according to the total number of the conversion voltages of the corresponding physical pages. Physical pages with larger total number of converted read voltages will have smaller read voltage optimization cycles.
Specifically, as shown in table T400, the optimization counting circuit 2151 may set the read voltage optimization period for the lower physical page to "4", the read voltage optimization period for the middle physical page to "2", and the read voltage optimization period for the upper physical page to "1", corresponding to the total number of converted read voltages for the identified lower physical page to "1", the total number of converted read voltages for the middle physical page to "2", and the total number of converted read voltages for the upper physical page to "4".
In one embodiment, the optimization counter circuit 2151 calculates the least common multiple of the total number of the converted read voltages, e.g., "4" (step S253). Next, in step S255, the optimization counter circuit 2151 may use the quotient obtained by dividing the least common multiple by the total number of the converted read voltages respectively as a plurality of read voltage optimization periods (also called optimization weight values) corresponding to the plurality of physical pages respectively. The read voltage optimization period can also be used as an optimization weight value for accumulating a plurality of optimization sub-values corresponding to the plurality of physical pages.
In one embodiment, the optimization counting circuit 2151 may calculate a plurality of read voltage optimization periods (or optimization weight values) corresponding to the physical page according to respective reciprocals of the converted read voltages.
After obtaining a plurality of read voltage optimization cycles corresponding to the plurality of physical pages, the read voltage management circuit unit 215 (or the read voltage optimization circuit 2152) can determine the execution frequency of the read voltage optimization operation required by each physical page according to the read voltage optimization cycles. In this way, the read voltage management circuit unit 215 (or the read voltage optimization circuit 2152) can further determine whether to perform the read voltage optimization on other physical pages according to the read voltage optimization cycles when the target physical page is determined to perform the read voltage optimization.
For example, referring to fig. 4B, it is assumed that the time intervals between every two adjacent time points of the time points T0-T4 are all equal, and are all a unit optimization period. In addition, assume that the read voltage optimization period TP of the current physical pageLRead voltage optimization period TP of middle physical page during optimization period of '4' unitsMOptimization period for "2" units, and optimization period TP for reading voltage of upper physical pageUThe optimization period is "1" unit.
For example, the read voltage optimization period TP due to the upper physical pageUFor the "1" unit optimization period, the read voltage optimization circuit 2152 determines that one page level read voltage optimization operation needs to be performed on the upper physical page from time T0 to time T1 (as indicated by the dark circle corresponding to time T1). At this time (time point T1), the time does not reach the middle physical pageRead voltage optimization period TPMRead voltage optimization period TP with lower physical pageLThe read voltage optimization circuit 2152 determines that the page level read voltage optimization operation need not be performed on the middle physical page and the lower physical page, i.e., only on the upper physical page.
Continuing with the above example, assume that a unit optimization period has elapsed and that time has reached time point T2. The upper physical page passes through a reading voltage optimization period TPUThe read voltage optimization circuit 2152 determines that a page level read voltage optimization operation needs to be performed on the upper physical page. In addition, from the time point T0, the middle physical page also passes through a reading voltage optimization period TPM(length of time during 2 units of optimization) and the read voltage optimization circuit 2152 determines that a page level read voltage optimization operation needs to be performed on the physical page (as indicated by the dark circles corresponding to time T2).
Continuing with the above example, assume that the time has reached time point T3 after a unit optimization period has elapsed. The time does not reach the optimum period TP of the reading voltage of the middle physical pageMRead voltage optimization period TP with lower physical pageLThe read voltage optimization circuit 2152 determines that the page level read voltage optimization operation need not be performed on the middle physical page and the lower physical page, i.e., only on the upper physical page (as indicated by the dark circles corresponding to time T3).
Continuing with the above example, assume that the time has reached time point T4 after a unit optimization period has elapsed. The upper physical page passes through a reading voltage optimization period TPUThe read voltage optimization circuit 2152 determines that a page level read voltage optimization operation needs to be performed on the upper physical page. In addition, from the time point T0, the lower physical page also passes through a read voltage optimization period TPL(length of time during 4 unit optimization), and the read voltage optimization circuit 2152 determines that a page level read needs to be performed on the physical pageA voltage optimization operation; starting from the time point T2 of the previous read voltage optimization operation performed on the middle physical page, the middle physical page also passes through a read voltage optimization period TPM(length of time for 2 unit optimization period), the read voltage optimization circuit 2152 determines that a page level read voltage optimization operation needs to be performed on the physical page (as indicated by the dark circles corresponding to time T4). That is, at the time point T4, the read voltage optimization circuit 2152 may determine that the page level read voltage optimization operation needs to be performed on all the physical pages, or that the word line level read voltage optimization operation needs to be performed on the word lines to which all the physical pages belong.
Briefly, according to the example below in FIG. 4B, the read voltage optimization period TP according to the lower physical page "1/2/4LRead voltage optimization period TP of physical pageMRead voltage optimization period TP of physical pageUThe read voltage optimization circuit 2152 determines whether the read voltage optimization operation is to be performed on another physical page according to the physical page on which the read voltage optimization operation is currently performed.
For example, for the example of fig. 4B, read voltage optimization circuit 2152 may predict that a middle physical page also performs 1 page level read voltage optimization operation every 2 page level read voltage optimization operations; whenever the upper physical page performs the page level read voltage optimization operation 4 times, the read voltage optimization circuit 2152 may predict that the middle physical page also performs the page level read voltage optimization operation 1 time, and predict that the lower physical page also performs the page level read voltage optimization operation 1 time; every physical page performs 1 page level read voltage optimization operation, and the read voltage optimization circuit 2152 predicts that the physical page also performs 1 page level read voltage optimization operation; every physical page performs 2 page level read voltage optimization operations, read voltage optimization circuit 2152 predicts that the upper physical page also performs 1 page level read voltage optimization operation, and predicts that the lower physical page also performs 1 page level read voltage optimization operation; whenever the lower physical page performs the page level read voltage optimization operation 1 time, the read voltage optimization circuit 2152 may predict that the middle physical page also performs the page level read voltage optimization operation 1 time, and predict that the upper physical page also performs the page level read voltage optimization operation 1 time.
The above description is directed to the example of the rewritable non-volatile memory module 220 corresponding to the first read voltage pattern 1/2/4. However, the above concepts may also be applied to the rewritable nonvolatile memory module 220 corresponding to the second read voltage pattern (2/3/2) or the rewritable nonvolatile memory module 220 corresponding to other read voltage patterns. Referring to FIG. 5B, the rewritable nonvolatile memory module 220 corresponding to the second read voltage pattern (2/3/2) is described.
FIG. 5B is a diagram illustrating a read voltage optimization cycle for each of a plurality of physical pages of a wordline corresponding to a second read voltage pattern according to an embodiment of the invention. Referring to FIG. 5B, in this example, it is assumed that the rewritable non-volatile memory module 220 corresponds to the second read voltage pattern (2/3/2). The optimized count circuit 2151 has identified a total number of converted read voltages for the lower physical page of "2"; the total number of the converted reading voltages of the middle physical page is '3'; and the total number of converted read voltages for the upper physical page is "2".
Specifically, as shown in table T500, optimization counter circuit 2151 has identified a total number of translated read voltages for the lower physical page of "2", a total number of translated read voltages for the middle physical page of "3", and a total number of translated read voltages for the upper physical page of "2". Next, the optimization counter circuit 2151 calculates the least common multiple of the total number of the converted read voltages, e.g., "6" (step S253). Next, the optimization counter circuit 2151 divides the least common multiple by the total number of the converted read voltages to obtain a quotient, and takes the quotient as a plurality of read voltage optimization periods (also called optimization weight values) corresponding to the physical pages, respectively (step S255). That is, the optimization counter circuit 2151 may calculate a read voltage optimization period of the lower physical page as "3", a read voltage optimization period of the middle physical page as "2", and a read voltage optimization period of the upper physical page as "3".
Referring to fig. 5B, it is assumed that the time intervals between every two adjacent time points of the time points T0-T6 are all equal and are all a unit optimization period. In addition, assume that the read voltage optimization period TP of the current physical pageLRead voltage optimization period TP of middle physical page during optimization period of 3 unitsMOptimization period for "2" units, and optimization period TP for reading voltage of upper physical pageUThe optimization period is "3" units.
For example, the read voltage optimization period TP due to the middle physical pageMFor the "2" unit optimization period, the time from time T0 to time T2, when the 2 unit optimization period has elapsed, the read voltage optimization circuit 2152 determines that a page level read voltage optimization operation needs to be performed on the middle physical page (as indicated by the dark dot corresponding to time T2). At this time (time point T2), the time does not reach the reading voltage optimization period TP of the upper physical pageURead voltage optimization period TP with lower physical pageLThe read voltage optimization circuit 2152 determines that the page level read voltage optimization operation need not be performed on the upper physical page and the lower physical page, i.e., only on the middle physical page.
Continuing with the above example, assume that a unit optimization period has elapsed and that time has reached time point T3. From time T0, the lower physical page has passed a reading voltage optimization period TPL(length of time for 3 unit optimization period), the read voltage optimization circuit 2152 determines that the page level read voltage optimization operation needs to be performed on the next physical page. In addition, from the time point T0, the upper physical page also passes through a reading voltage optimization period TPU(3 units of length of time during the optimization period), and the read voltage optimization circuit 2152 determines that a page level read needs to be performed on the upper physical pageVoltage optimization operation (as indicated by the dark circle corresponding to time point T3). That is, at time T3, the read voltage optimization circuit 2152 determines that the lower physical page and the upper physical page both need to perform the page level read voltage optimization operation.
Continuing with the above example, assume that the time has reached time point T4 after a unit optimization period has elapsed. Since the time does not reach the optimum period TP of the read voltage of the upper physical pageURead voltage optimization period TP with lower physical pageLThe read voltage optimization circuit 2152 determines that the page level read voltage optimization operation need not be performed for the upper physical page and the lower physical page. In addition, from time T2 to time T4, a reading voltage optimization period TP has elapsed compared to the reading voltage optimization operation performed previouslyM(for a "2" unit optimization period). Accordingly, the read voltage optimization circuit 2152 determines that the page level read voltage optimization operation is performed only on the middle physical page (as indicated by the dark circles corresponding to time point T3).
Continuing with the above example, assume that the time has reached time point T5 after a unit optimization period has elapsed. Due to the read voltage optimization operation performed before, the time does not reach the read voltage optimization period TP of the upper physical pageUThe read voltage optimization period TP of the middle physical pageMThe read voltage optimization period TP of the lower physical pageLThe read voltage optimization circuit 2152 determines that the page level read voltage optimization operations need not be performed on the upper, middle and lower physical pages.
Continuing with the above example, assume that the time has reached time point T6 after a unit optimization period has elapsed. The physical page has passed a read voltage optimization period TP again from the previous read voltage optimization operation (time T3)U(length of time for 3 unit optimization period), the read voltage optimization circuit 2152 determines that a page level read voltage optimization operation needs to be performed on the upper physical page. In addition, the read voltage optimization operation performed from the previous time(time T3), the next physical page passes a read voltage optimization period TPL(length of time during 3 unit optimization), and the read voltage optimization circuit 2152 determines that the page level read voltage optimization needs to be performed on the next physical page. In addition, the middle physical page has passed a reading voltage optimization period TP again from the previous reading voltage optimization operation (time point T4)M(length of time during 2 unit optimization), and the read voltage optimization circuit 2152 determines that a page level read voltage optimization operation needs to be performed on the physical page. That is, at the time point T6, the read voltage optimization circuit 2152 may determine that the page level read voltage optimization operation needs to be performed on all the physical pages, or that the word line level read voltage optimization operation needs to be performed on the word lines to which all the physical pages belong.
Briefly, according to the example below in FIG. 5B, the read voltage optimization period TP according to the lower physical page "2/3/2LRead voltage optimization period TP of physical pageMRead voltage optimization period TP of physical pageUThe read voltage optimization circuit 2152 determines whether the read voltage optimization operation is to be performed on another physical page according to the physical page on which the read voltage optimization operation is currently performed.
For example, for the example of fig. 5B, read voltage optimization circuit 2152 may predict that the lower physical page also performs 1 page level read voltage optimization operation each time the upper physical page performs 1 page level read voltage optimization operation; whenever the physical page performs the page level read voltage optimization operation 2 times, the read voltage optimization circuit 2152 may predict that the physical page also performs the page level read voltage optimization operation 1 time; the read voltage optimization circuit 2152 predicts that the upper and lower physical pages also need to perform the page level read voltage optimization operation 1 time each time the physical page performs the page level read voltage optimization operation 3 times.
It should be noted that, in the present embodiment, the page-level read voltage optimization operation performed on a single physical page of the target word line may also be referred to as a first row read voltage optimization operation; the multiple page-level read-voltage optimization operations performed on the multiple physical pages (not all physical pages) of the portion of the target word line are also referred to as second-type read-voltage optimization operations; the multiple page-level read voltage optimization operations performed on all physical pages of the target word line, respectively, may also be referred to as a third-type read voltage optimization operation. In addition, in this embodiment, the third type read voltage optimization operation can also be performed by directly performing the word line level read voltage optimization operation on the target word line.
In order to determine whether to perform the first type of reading voltage operation, the second type of reading voltage operation, or the third row of reading voltage operation, the embodiment provides an optimization counter circuit 2151 for calculating a plurality of optimization rights corresponding to a plurality of physical pages, respectively, and recording a plurality of optimization count values corresponding to the plurality of physical pages. And giving corresponding optimal weight values to the physical pages according to a plurality of reading voltage optimization cycles of the physical pages. In addition, when a read voltage optimization operation is to be performed on a target physical page, the optimization count value of the target physical page is accumulated by using the corresponding optimization weight value, so as to determine whether the read voltage optimization operation needs to be performed on other physical pages (also called standby physical pages) according to the accumulated optimization count value.
Referring back to fig. 2B, after obtaining a plurality of optimized weight values (i.e., a plurality of corresponding read voltage optimization cycles) respectively corresponding to the plurality of physical pages. Next, in step S257, the optimization counter circuit 2151 identifies an optimization weight value corresponding to the target physical page among the optimization weight values as a target optimization weight value, and identifies a plurality of optimization weight values respectively corresponding to a plurality of standby physical pages among the optimization weight values as a plurality of standby optimization weight values, where the standby physical pages are a plurality of other physical pages that are not selected among the physical pages. For example, take fig. 4B as an example. If the lower physical page is a target physical page, the target optimal weight value is 4, the upper physical page and the middle physical page are standby physical pages, and the corresponding standby optimal weight values are 1 and 2.
Next, in step S259, the optimization count circuit 2151 adds the target optimization weight value to the optimization count value corresponding to the target physical page to obtain the target optimization count value. In this way, the optimization counter circuit 2151 completes the step of updating the target optimization counter value corresponding to the target physical page. For example, take fig. 4B as an example. Assuming that the lower physical page is a target physical page, the target optimization weight value is 4, and the current optimization count value corresponding to the lower physical page is 0. The optimization counter circuit 2151 adds the optimization counter value ("0") corresponding to the target physical page to the target optimization weight value ("4") to obtain an updated target optimization counter value ("4").
After the target optimization count value corresponding to the target physical page is updated, the process continues to step S27.
Referring to fig. 2A, in step S27, the read voltage optimization circuit 2152 performs a first type, a second type, or a third type of read voltage optimization operation on the target word line according to the target optimization count value to obtain an optimized read voltage set corresponding to the target word line, wherein the target word line can be read by using the optimized read voltage set. The following describes a method for implementing step S27 according to various embodiments with reference to fig. 3A and 3B.
Fig. 3A is a flowchart illustrating step S27 of fig. 2A according to an embodiment of the invention. Referring to fig. 3A, in step S310, the read voltage optimization circuit 2152 determines whether the target optimization count value is equal to an integer multiple of one or more target standby optimization weight values of the standby optimization weight values. In response to determining that the target optimization count value is not equal to an integer multiple of any one of the optimization weight values respectively corresponding to the standby physical pages (step S310 → no), performing step S311; in response to determining that the target optimization count value is equal to an integer multiple of the one or more target standby optimization weight values of the plurality of standby optimization weight values (step S310 → yes), step S312 is performed.
For example, taking fig. 4B as an example, assume that the target physical page is an upper physical page, the standby physical pages are a middle physical page and a lower physical page, and the corresponding standby optimization weight values are 2 and 4, respectively. Further, assume that the updated optimization count value (target optimization count value) of the upper physical page is 1 (e.g., the upper physical page is at time point T1, for example). At this time, the target optimized count value (i.e., 1) of the target physical page is not an integer multiple of the standby optimized weight value (i.e., 2) of the middle physical page (one of the standby physical pages), and the target optimized count value (i.e., 1) of the target physical page is not an integer multiple of the standby optimized weight value (i.e., 4) of the lower physical page (the other one of the standby physical pages), the read voltage optimization circuit 2152 performs step S311 to perform the first type of read voltage optimization operation on all the converted read voltages possessed by the target physical page.
The first type of read voltage optimization operation includes: performing a page rank read voltage optimization operation only on the target physical page, wherein in the page rank read voltage optimization operation performed on the target physical page, a voltage value of one or more transition read voltages in a plurality of preset read voltages corresponding to a preset read voltage set of the target word line for identifying a storage state of the target physical page is adjusted to an optimal value to obtain the optimal read voltage set corresponding to the target word line.
For example, in this example, the read voltage optimization circuit 2152 would perform the first type of read voltage optimization operation only on the target physical page (upper physical page). That is, the read voltage optimization circuit 2152 may only provide all of the translated read voltages that the target physical page (upper physical page) has (e.g., the translated read voltage V (1))1、V(1)3、V(1)5、V(1)7) Performing the page level read voltage optimization operation to convert the read voltage V (1)1、V(1)3、V(1)5、V(1)7Adjusting the respective voltage values to optimal values to obtain the optimized converted read voltages (e.g., the optimized converted read voltages V (X))1、V(X)3、V(X)5、V(X)7) And converting the obtained optimized post-conversion read voltage V (X)1、V(X)3、V(X)5、V(X)7A predetermined converted read voltage V (1) of a corresponding upper physical page in the predetermined read voltage group V (1) in place of the target word line1、V(1)3、V(1)5、V(1)7And then obtaining an optimized read voltage set corresponding to the target word line.
Similarly, in another example, it is assumed that the target physical page is an upper physical page, the standby physical pages are a middle physical page and a lower physical page, and the corresponding standby optimization weight values are 2 and 4, respectively. Further, assume that the updated optimization count value (target optimization count value) of the upper physical page is 3 (e.g., the upper physical page is at time point T3, for example). Read voltage optimization circuit 2152 performs the first type of read voltage optimization operation only on the target physical page (upper physical page).
Referring back to fig. 3A, in response to determining that the target optimization count value is equal to an integer multiple of the one or more target standby optimization weight values (step S310 → yes), in step S312, the read voltage optimization circuit 2152 identifies one or more standby physical pages corresponding to the one or more target standby optimization weight values as one or more target standby physical pages.
For example, assume that the target physical page is an upper physical page, the standby physical pages are a middle physical page and a lower physical page, and the corresponding standby optimization weight values are 2 and 4, respectively. Further, assume that the updated optimization count value (target optimization count value) of the upper physical page is 2 (e.g., the upper physical page is at time point T2, for example). At this time, the target optimization count value (2) of the target physical page is an integer multiple (i.e., 1 times) of the standby optimization weight value (i.e., 2) of the middle physical page (one of the standby physical pages), but the target optimization count value of the target physical page is not an integer multiple of the standby optimization weight value (i.e., 4) of the lower physical page (the other of the standby physical pages). That is, in this example, since the integer multiple of the standby optimization weight value of the middle physical page is the target optimization count value, the standby optimization weight value of the middle physical page is regarded as the target standby optimization weight value, and the read voltage optimization circuit 2152 identifies the middle physical page (i.e., the standby physical page corresponding to the target standby optimization weight value) as the target standby physical page.
Next, in step S313, the read voltage optimization circuit 2152 determines whether the total number of the plurality of standby physical pages is equal to the total number of the one or more target standby physical pages. In short, the read voltage optimization circuit 2152 determines whether all the standby physical pages are the target standby physical page.
In response to determining that the total number of the plurality of standby physical pages is not equal to the total number of the one or more target standby physical pages (step S313 → no), performing step S314; in response to determining that the total number of the plurality of standby physical pages is equal to the total number of the one or more target standby physical pages (step S313 → yes), step S316 is performed.
In step S314, the optimization counter circuit 2151 changes the values of one or more optimization counter values corresponding to the one or more target standby physical pages to the values of the target optimization counter values. Next, in step S315, the read voltage optimization circuit 2152 performs the second type read voltage optimization operation on all the converted read voltages of the target physical page and the one or more target standby physical pages.
For example, assume that the target physical page is a middle physical page, the standby physical pages are an upper physical page and a lower physical page, and the corresponding standby optimization weight values are 1 and 4, respectively. Further, assume that the updated optimization count value (target optimization count value) of the middle physical page is 2 (e.g., the middle physical page is at the time point T2, for example).
In this example, since the integer multiple (2 times) of the standby optimization weight value (i.e., 1) of the upper physical page is the target optimization count value (i.e., 2), the standby optimization weight value of the upper physical page is regarded as the target standby optimization weight value (step S310 → yes), and the read voltage optimization circuit 2152 recognizes the upper physical page (i.e., the standby physical page corresponding to the target standby optimization weight value) as the target standby physical page (step S312). On the other hand, the target optimization count value of the target physical page is not an integral multiple of the standby optimization weight value (i.e., 4) of the lower physical page, the standby optimization weight value of the lower physical page is not regarded as the target standby optimization weight value, and the lower physical page is not recognized as the target standby physical page.
At this time, the read voltage optimization circuit 2152 determines that the total number of the plurality of standby physical pages (i.e., 2) is not equal to the total number of the one or more target standby physical pages (i.e., 1) (step S313 → no). The optimization counter circuit 2151 changes the value of the optimization counter corresponding to the upper physical page to the value of the target optimization counter, i.e., sets the optimization counter of the upper physical page to 2 (step S314). Then, the read voltage optimization circuit 2152 performs the second type of read voltage optimization operation on all the converted read voltages of the physical page (the target physical page) and the upper physical page (the target standby physical page), respectively.
Specifically, the second-type read voltage optimization operation includes: performing the page level read voltage optimization operation on the target physical page and one or more standby physical pages of the plurality of physical pages, wherein the one or more standby physical pages are one or more other physical pages of the plurality of physical pages other than the target physical page, and a total number of the target physical page and the one or more standby physical pages is less than a total number of the plurality of physical pages.
For example, the read voltage optimization circuit 2152 switches the read voltage V (1) to the physical page according to the order of the physical page2、V(1)6Performing page level read voltage optimization, and converting the read voltage V (1) to the upper physical page1、V(1)3、V(1)5、V(1)7A page level read voltage optimization operation is performed.
On the other hand, in response to determining that the total number of the plurality of standby physical pages is equal to the total number of the one or more target standby physical pages (step S313 → yes), continuing to step S316, the read voltage optimization circuit 2152 performs the third type of read voltage optimization operation on all converted read voltages that all physical pages of the target wordline each have.
For example, assume that the target physical page is a lower physical page, the standby physical pages are a middle physical page and an upper physical page, and the corresponding standby optimization weight values are 2 and 1, respectively. Further, assume that the updated optimization count value (target optimization count value) of the lower physical page is 4 (e.g., the lower physical page is at the time point T4, for example).
In this example, since the integer multiple (2 times) of the standby optimization weight value (i.e., 2) of the middle physical page is the target optimization count value (i.e., 4), the standby optimization weight value of the middle physical page is regarded as the target standby optimization weight value (step S310 → yes), and the read voltage optimization circuit 2152 identifies the middle physical page (i.e., the standby physical page corresponding to the target standby optimization weight value) as the target standby physical page (step S312). On the other hand, since the integer multiple (4 times) of the standby optimization weight value (i.e., 1) of the upper physical page is the target optimization count value (i.e., 4), the standby optimization weight value of the upper physical page is regarded as the target standby optimization weight value (step S310 → yes), and the read voltage optimization circuit 2152 recognizes that the upper physical page (i.e., the standby physical page corresponding to the target standby optimization weight value) is also the target standby physical page (step S312).
In this example, all standby physical pages are identified as target standby physical pages. The read voltage optimization circuit 2152 determines that the total number of the standby physical pages (i.e., 2) is equal to the total number of the target standby physical pages (i.e., 2) (step S313 → yes).
Then, the read voltage optimization circuit 2152 performs the third type of read voltage optimization operation on all the converted read voltages that all the physical pages of the target word line respectively have.
Specifically, the third type of read voltage optimization operation includes: performing a word line level read voltage optimization operation on the target word line, wherein in the word line level read voltage optimization operation performed on the target word line, voltage values of the plurality of preset read voltages corresponding to the preset read voltage group of the target word line are adjusted to optimal values to obtain the optimal read voltage group corresponding to the target word line; or performing the page-level read voltage optimization operation on the plurality of physical pages, respectively, in accordance with the arrangement order of the plurality of physical pages (lower physical page → middle physical page → upper physical page).
For example, the read voltage optimization circuit 2152 can directly perform a word line level read voltage optimization operation on the target word line to simultaneously apply all read voltages V (1) of a predetermined set of read voltages for the target word line1～V(1)7The voltage value of the read voltage group is adjusted to an optimal value to obtain an optimal read voltage group. Alternatively, the read voltage optimization circuit 2152 may convert the read voltage V (1) for the next physical page first according to the arrangement order of the physical pages4Performing page level read voltage optimization operation to convert read voltage V (1) to a middle physical page2、V(1)6Performing page level read voltage optimization, and converting the read voltage V (1) to the upper physical page1、V(1)3、V(1)5、V(1)7A page level read voltage optimization operation is performed. Then, the obtained optimized reading voltage V (X) corresponding to the lower physical page4Middle physical page ofOptimized read Voltage V (X)2、V(X)6Optimized read voltage of upper physical page V (X)1、V(X)3、V(X)5、V(X)7An optimized set of read voltages for the target word line is composed.
Next, in step S317, the optimization counter circuit 2151 resets the plurality of optimized count values of the plurality of physical pages respectively corresponding to the target word line to zero after the third type read voltage optimization operation is completed.
Specifically, since all the physical pages of the target word line have been subjected to the read voltage optimization operation, all the physical pages of the target word line can be considered to be accessed again from the time point T0. In this regard, the optimized count circuit 2151 may directly reset the optimized count values for the physical pages of the target word line to zero.
In one embodiment, step S317 may be omitted, but the optimization counter circuit 2151 sets (changes) the optimization counter values of all the target standby physical pages to the updated target optimization counter values of the current target physical page.
Fig. 3B is a flowchart illustrating step S27 of fig. 2A according to another embodiment of the invention. Fig. 3B mainly differs from fig. 3A in step S320. In addition, steps S326 and S327 are the same as steps S314 and S315; steps S321 and S322 are the same as steps S316 and S317; step S324 is the same as step S311; step S325 is the same as step S312.
Referring to fig. 3B, in the alternative embodiment, in step S320, the read voltage optimization circuit 2152 determines whether the target optimization count value is equal to a least common multiple of a total number of the converted read voltages respectively corresponding to the physical pages. In response to determining that the target optimized count value is equal to the least common multiple of the total number of the converted read voltages respectively corresponding to the physical pages (step S320 → Yes), step S321 is performed.
Specifically, fig. 3B utilizes the concept that "when the target optimization count value is equal to the least common multiple of the total number of the converted read voltages of the physical pages of the target word line, the target physical page and all other standby physical pages should be subjected to the read voltage optimization operation".
For example, referring to fig. 5B, assume that the target physical page is the lower physical page. At time T6, the target optimized count value is updated to 6, and the target optimized count value is equal to the least common multiple "6" of the total number of the plurality of converted read voltages. At this time, according to the example of fig. 5B, other standby physical pages should also reach one read voltage optimization cycle. For example, at the timing T6, the upper physical page has passed one reading voltage optimization period TP again since the previous reading voltage optimization operation (time T3)U(length of time during 3 unit optimization), and the read voltage optimization circuit 2152 determines that a page level read voltage optimization operation needs to be performed on the upper physical page. In addition, the middle physical page has passed a reading voltage optimization period TP again from the previous reading voltage optimization operation (time point T4)M(length of time during 2 unit optimization), and the read voltage optimization circuit 2152 determines that a page level read voltage optimization operation needs to be performed on the physical page.
That is, no matter which physical page the target physical page is. At the time point T6, as long as the updated target optimization count value is equal to the least common multiple of the total number of the plurality of converted read voltages, all the physical pages of the target word line should be subjected to the third-type read voltage optimization operation, i.e., the page-level read voltage optimization operation is performed on all the physical pages of the target word line in the order of arrangement of the physical pages, or the word-line-level read voltage optimization operation is performed on the target word line. As described above, the subsequent steps S321 and S322 are the same as the steps S316 and S317 in fig. 3A, and are not described herein again.
Further, in response to determining that the target optimized count value is not equal to the least common multiple of the total number of the converted read voltages respectively corresponding to the physical pages (step S320 → no), step S323 is performed.
Specifically, if not equal to the least common multiple, the read voltage optimization circuit 2152 may identify that it is currently possible to perform the first type read voltage optimization operation or the second type read voltage optimization operation. The read voltage optimizing circuit 2152 may assist in the determination through step S323. In step S323, the read voltage optimization circuit 2152 determines whether the target optimization count value is equal to an integer multiple of one or more of the standby optimization weight values.
If the determination result in step S323 is yes, the read voltage optimization circuit 2152 recognizes that there is a target standby physical page and a second type read voltage optimization operation should be performed. As described above, the subsequent steps S325, S326 and S327 are the same as the steps S312, S314 and S315 in fig. 3A, and are not described herein again.
If the determination result in step S323 is "no", the read voltage optimization circuit 2152 recognizes that there is no target standby physical page, and only needs to perform the page level read voltage optimization operation on the target physical page, that is, the first type read voltage optimization operation should be performed. As described above, the subsequent step S324 is the same as the step S311 in fig. 3A, and is not described herein again.
Returning to FIG. 2A, after step S27 is completed and the optimized set of read voltages for the target word line is obtained, the target word line can be read by using the optimized set of read voltages. And, the flow may return to step S21.
In this embodiment, the concept that the optimum reading voltage should be located at the boundary between two threshold voltage distributions corresponding to two gray codes is utilized, and the concept that the area change at the boundary is small is utilized to find the position of the optimum voltage. One skilled in the art can modify the read voltage optimization method/operation of the above embodiments according to this concept. However, without departing from the spirit and scope of the present invention.
In addition, the read voltage optimization method provided by the present embodiment is more capable of optimizing one or more translation read voltages for a particular target physical page without adjusting the translation read voltages of other non-designated physical pages than in the conventional method. Thus, because the present invention focuses on tuning/testing of one or more translated read voltages for a target physical page, the total number of reads performed for read voltage optimization operations can be significantly reduced (because the translated read voltages for other, non-designated physical pages need not be tuned/tested).
For example, referring to fig. 4B, compared to the conventional method, at time points T1, T2, T3 and T4, the conventional method performs the word line level read voltage optimization operation on the entire word line due to the bad read condition of the upper physical page (e.g., the read voltage optimization cycle is reached), so that all the physical pages are performed with the read voltage optimization operation, and the memory controller 210 consumes resources and time (e.g., correspondingly increases the number of reads compared to other physical pages that do not need to be performed with the read voltage optimization operation) to process other physical pages that do not need to be performed with the read voltage optimization operation (e.g., do not reach the corresponding read voltage optimization cycle). That is, the data reading method provided by the present invention can effectively avoid the waste of resources and time (reduce unnecessary reading times) by determining whether the first type, the second type or the third type of reading voltage optimization operation should be executed currently when the reading voltage of a target physical page needs to be optimized, thereby improving the data reading efficiency of the whole memory device. In particular, as shown in fig. 4B, the number of unnecessary reads can be reduced for the physical page (upper physical page) whose read condition is most likely to be poor.
In the present embodiment, the page level read voltage optimization means performing an optimization operation on all the predetermined converted read voltages of a single physical page to obtain corresponding optimal values (e.g., obtaining the predetermined converted read voltage V (1) of the next physical page)4The optimum value of). The invention is not limited to the specific details of "page level read voltage operation". For example, multiple read voltage optimization options for a target physical page may be used to attempt to find a corresponding optimum; or adjusting the voltage value of the conversion reading voltage and using the adjusted conversion reading currentAnd reading the target physical page to judge whether the voltage value of the adjusted conversion reading voltage is the optimal value according to the obtained data reading result.
In addition, the word line level read voltage optimization operation means performing an optimization operation on all the preset converted read voltages (i.e., the entire preset read voltage set) of a single word line to obtain corresponding optimal values (e.g., obtaining the optimized read voltage set of the target word line). The invention is not limited to the specific details of "word line read voltage operation". For example, multiple read voltage optimization options for each word line may be used to attempt to find the corresponding optimal value; or adjusting the converted reading voltage group and reading the target word line by using the adjusted converted reading voltage group so as to judge whether the adjusted converted reading voltage group is the optimal reading voltage group according to the obtained data reading result.
It should be noted that, in the above embodiments, the read voltage management circuit unit 215 is implemented by a hardware circuit, but the invention is not limited thereto. For example, in one embodiment, the read voltage management circuit unit 215 may be implemented in software or hardware as a read voltage management program code module having the functions of the read voltage management circuit unit 215. The read voltage management program code module may include an optimized count program code module and a read voltage optimization program code module. The optimized counting program code module is a program code module with the function of the optimized counting circuit 2151; the read voltage optimization program code module is a program code module having the function of the read voltage optimization circuit 2152. The processor 211 can access and execute the read voltage management code module (or the optimized count code module and the read voltage optimization code module) to implement the read voltage optimization method provided by the present invention.
In summary, the data reading method, the memory controller and the memory device provided in the embodiments of the present invention may update the target optimized count value corresponding to a target physical page in a plurality of physical pages of the target word line in response to determining that a read voltage optimization operation needs to be performed on the target physical page, and determine whether to perform the read voltage optimization operation on other physical pages or on the entire target word line according to the target optimized count value; and reading the target word line using the obtained optimized read voltage set corresponding to the target word line after the read voltage optimization operation is completed. In this way, the accuracy of the data read from the target word line is improved, and the overall efficiency of the data read operation of the memory device is improved.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (11)

1. A data reading method applied to a memory device configured with a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of word lines, each of the plurality of word lines is coupled to a plurality of memory cells, each of the plurality of memory cells includes a plurality of physical pages respectively corresponding thereto, and each of the plurality of physical pages is configured to be programmed to a bit value, the method comprising:
selecting one of the plurality of word lines as a target word line, and monitoring a plurality of physical pages of the selected target word line to obtain a plurality of monitoring results of the plurality of physical pages respectively corresponding to the target word line;
updating a target optimization count value corresponding to a target physical page in response to determining that read voltage optimization operation needs to be performed on the target physical page in the plurality of physical pages of the target word line according to the monitoring results; and
performing a first type read voltage optimization operation, a second type read voltage optimization operation, or a third type read voltage optimization operation corresponding to the target word line according to the target optimization count value to obtain an optimized read voltage set corresponding to the target word line, wherein the target word line is read by using the optimized read voltage set,
wherein the first-type read voltage optimization operation comprises:
performing a page-level read voltage optimization operation only on the target physical page, wherein in the page-level read voltage optimization operation performed on the target physical page, a voltage value of one or more transition read voltages among a plurality of preset read voltages corresponding to a preset read voltage set of the target word line for identifying a memory state of the target physical page is adjusted to an optimal value to obtain the optimized read voltage set corresponding to the target word line,
wherein the second type read voltage optimization operation comprises:
performing the page-level read voltage optimization operation on the target physical page and one or more standby physical pages of the plurality of physical pages, wherein the one or more standby physical pages are one or more other physical pages of the plurality of physical pages other than the target physical page, and a total number of the target physical page and the one or more standby physical pages is less than a total number of the plurality of physical pages,
wherein the third type read voltage optimization operation comprises:
performing a word line level read voltage optimization operation on the target word line, wherein in the word line level read voltage optimization operation performed on the target word line, voltage values of the plurality of preset read voltages corresponding to the preset read voltage group of the target word line are adjusted to optimal values to obtain the optimized read voltage group corresponding to the target word line; or performing the page level read voltage optimization operation on the plurality of physical pages respectively according to the arrangement sequence of the plurality of physical pages.
2. A data reading method according to claim 1, wherein the data reading method further comprises:
if the monitoring results are a plurality of syndromes respectively corresponding to the physical pages, determining whether the total number of first bit values of the syndromes is greater than a syndrome threshold value, wherein in response to determining that the total number of the first bit values of target syndromes in the syndromes is greater than the syndrome threshold value, identifying the target physical page corresponding to the target syndrome, and determining that the read voltage optimization operation needs to be performed on the target physical page; and
and if the monitoring results are a plurality of error bit numbers respectively corresponding to the physical pages, judging whether the error bit numbers are larger than a threshold value of the error bit numbers, wherein in response to judging that a target error bit number in the error bit numbers is larger than the threshold value of the error bit numbers, identifying the target physical page corresponding to the target error bit number, and judging that the read voltage optimization operation needs to be executed on the target physical page.
3. A data reading method according to claim 1, wherein the step of updating the target optimization count value corresponding to the target physical page comprises:
identifying a plurality of converted read voltage totals respectively corresponding to the plurality of physical pages;
calculating a least common multiple of the total number of the plurality of converted read voltages;
dividing the minimum common multiple by the total number of the plurality of conversion reading voltages to obtain quotient values, and taking the quotient values as a plurality of optimized weight values corresponding to the plurality of physical pages respectively;
identifying an optimization weight value corresponding to the target physical page in the plurality of optimization weight values as a target optimization weight value, and identifying a plurality of optimization weight values respectively corresponding to a plurality of standby physical pages in the plurality of optimization weight values as a plurality of standby optimization weight values, wherein the plurality of standby physical pages are a plurality of other physical pages which are not selected in the plurality of physical pages; and
and adding the target optimization weight value to the optimization count value corresponding to the target physical page to obtain the target optimization count value.
4. The data reading method of claim 3, wherein the step of performing the first type read voltage optimization operation, the second type read voltage optimization operation, or the third type read voltage optimization operation corresponding to the target word line according to the target optimization count value comprises:
determining whether the target optimization count value is equal to an integer multiple of one or more target standby optimization weight values of the plurality of standby optimization weight values,
wherein the first-type read voltage optimization operation is performed on all of the converted read voltages that the target physical page has in response to determining that the target optimization count value is not equal to an integer multiple of any of the plurality of optimization weight values respectively corresponding to a plurality of standby physical pages,
wherein in response to determining that the target optimization count value is equal to an integer multiple of the one or more target standby optimization weight values of the plurality of standby optimization weight values, identifying a standby physical page corresponding to the one or more target standby optimization weight values as one or more target standby physical pages, and
determining whether a total number of the plurality of standby physical pages is equal to a total number of the one or more target standby physical pages,
wherein in response to determining that the total number of the plurality of standby physical pages is not equal to the total number of the one or more target standby physical pages, changing the values of one or more optimized count values corresponding to the one or more target standby physical pages to the value of the target optimized count value and performing the second type of read voltage optimization operation on all converted read voltages that the target physical page and the one or more target standby physical pages each have,
wherein in response to determining that the total number of the plurality of standby physical pages is equal to the total number of the one or more target standby physical pages, performing the third-type read voltage optimization operation on all of the converted read voltages that all of the physical pages of the target wordline each have, and after the third-type read voltage optimization operation is completed, resetting a plurality of optimized count values of the plurality of physical pages respectively corresponding to the target wordline to zero.
5. The data reading method of claim 3, wherein the step of performing the first type read voltage optimization operation, the second type read voltage optimization operation, or the third type read voltage optimization operation corresponding to the target word line according to the target optimization count value comprises:
determining whether the target optimized count value is equal to a least common multiple of a total number of the plurality of converted read voltages respectively corresponding to the plurality of physical pages,
wherein in response to determining that the target optimization count value is equal to the least common multiple, the third-type read voltage optimization operation is performed on all of the converted read voltages that all of the physical pages of the target word line have, respectively, and the plurality of optimization count values of the plurality of physical pages respectively corresponding to the target word line are reset to zero after the third-type read voltage optimization operation is completed,
wherein responsive to determining that the target optimization count value is not equal to the least common multiple, determining whether the target optimization count value is equal to an integer multiple of one or more target standby optimization weight values of the plurality of standby optimization weight values,
wherein the first-type read voltage optimization operation is performed on all of the converted read voltages that the target physical page has in response to determining that the target optimization count value is not equal to an integer multiple of any of the plurality of optimization weight values respectively corresponding to a plurality of standby physical pages,
wherein in response to determining that the target optimization count value is equal to an integer multiple of the one or more of the plurality of standby optimization weight values, identifying a standby physical page to which the one or more target standby optimization weight values correspond as one or more target standby physical pages, changing the values of the one or more optimization count values corresponding to the one or more target standby physical pages to the values of the target optimization count values, and performing the second-type read voltage optimization operation on all converted read voltages that the target physical page and the one or more target standby physical pages each have.
6. A memory controller for controlling a memory device configured with a rewritable non-volatile memory module, the memory controller comprising:
a connection interface circuit for coupling to a host system;
a memory interface control circuit coupled to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of word lines, wherein each of the plurality of word lines is coupled to a plurality of memory cells, wherein each of the plurality of memory cells comprises a plurality of physical pages, and each of the plurality of physical pages is programmed to a bit value;
a read voltage management circuit unit; and
a processor coupled to the connection interface circuit, the memory interface control circuit, and the read voltage management circuit unit,
wherein the processor is configured to select one of the plurality of word lines as a target word line and monitor a plurality of physical pages of the selected target word line to obtain a plurality of monitoring results of the plurality of physical pages respectively corresponding to the target word line,
wherein the read voltage management circuit unit is configured to update a target optimized count value corresponding to a target physical page of the target word line in response to the processor determining that a read voltage optimization operation needs to be performed on the target physical page according to the monitoring results,
wherein the read voltage management circuit unit is further configured to perform a first type read voltage optimization operation, a second type read voltage optimization operation, or a third type read voltage optimization operation corresponding to the target word line according to the target optimization count value to obtain an optimized read voltage set corresponding to the target word line, wherein the target word line is read by using the optimized read voltage set,
wherein the first-type read voltage optimization operation comprises:
the read voltage management circuit unit performs a page level read voltage optimization operation only on the target physical page, wherein in the page level read voltage optimization operation performed on the target physical page, the read voltage management circuit unit adjusts a voltage value of one or more converted read voltages, which are used to identify a storage state of the target physical page, among a plurality of preset read voltages corresponding to a preset read voltage group of the target word line to an optimal value to obtain the optimized read voltage group corresponding to the target word line,
wherein the second type read voltage optimization operation comprises:
the read voltage management circuit unit performs the page level read voltage optimization operation on the target physical page and one or more standby physical pages of the plurality of physical pages, wherein the one or more standby physical pages are one or more other physical pages of the plurality of physical pages other than the target physical page, and a total number of the target physical page and the one or more standby physical pages is less than a total number of the plurality of physical pages,
wherein the third type read voltage optimization operation comprises:
the read voltage management circuit unit performs a word line level read voltage optimization operation on the target word line, wherein in the word line level read voltage optimization operation performed on the target word line, the read voltage management circuit unit adjusts voltage values of the plurality of preset read voltages of the preset read voltage group corresponding to the target word line to an optimal value to obtain the optimized read voltage group corresponding to the target word line; or
The read voltage management circuit unit performs the page level read voltage optimization operation on the plurality of physical pages, respectively, according to an arrangement order of the plurality of physical pages.
7. The storage controller of claim 6, wherein
If the monitoring results are syndromes respectively corresponding to the physical pages, the processor determines whether a total number of first bit values of the syndromes is greater than a syndrome threshold value, wherein in response to determining that a total number of the first bit values of target syndromes among the syndromes is greater than the syndrome threshold value, the processor identifies the target physical page corresponding to the target syndrome and determines that the read voltage optimization operation needs to be performed on the target physical page,
if the plurality of monitoring results are a plurality of error bit numbers respectively corresponding to the plurality of physical pages, the processor determines whether the plurality of error bit numbers are greater than a threshold value of the error bit numbers, wherein in response to determining that a target error bit number of the plurality of error bit numbers is greater than the threshold value of the error bit number, the processor identifies the target physical page corresponding to the target error bit number and determines that the read voltage optimization operation needs to be performed on the target physical page.
8. The memory controller according to claim 6, wherein in operation of the read voltage management circuit unit to said update the target optimized count value corresponding to the target physical page,
the read voltage management circuit unit identifies a plurality of converted read voltage totals respectively corresponding to the plurality of physical pages, wherein the read voltage management circuit unit calculates a least common multiple of the plurality of converted read voltage totals,
wherein the read voltage management circuit unit divides the least common multiple by the total number of the plurality of converted read voltages respectively to obtain quotient values as a plurality of optimized weight values corresponding to the plurality of physical pages respectively,
wherein the read voltage management circuit unit identifies an optimal weight value corresponding to the target physical page among the optimal weight values as a target optimal weight value, and identifies a plurality of optimal weight values respectively corresponding to a plurality of standby physical pages among the optimal weight values as a plurality of standby optimal weight values, wherein the standby physical pages are a plurality of other physical pages that are not selected among the physical pages,
the reading voltage management circuit unit adds the optimal count value corresponding to the target physical page to the target optimal weight value to obtain the target optimal count value.
9. The memory controller according to claim 8, wherein in an operation in which the read voltage management circuit unit is further configured to perform the first type of read voltage optimization operation, the second type of read voltage optimization operation, or the third type of read voltage optimization operation corresponding to the target word line according to the target optimization count value,
the read voltage management circuit unit determines whether the target optimization count value is equal to an integer multiple of one or more target standby optimization weight values of the plurality of standby optimization weight values,
wherein the read voltage management circuit unit performs the first-type read voltage optimization operation on all of the converted read voltages that the target physical page has in response to determining that the target optimization count value is not equal to an integer multiple of any one of the plurality of optimization weight values respectively corresponding to a plurality of standby physical pages,
wherein in response to determining that the target optimization count value is equal to an integer multiple of the one or more of the plurality of standby optimization weight values, the read voltage management circuit unit identifies standby physical pages corresponding to the one or more target standby optimization weight values as one or more target standby physical pages, and
the read voltage management circuit unit determines whether a total number of the plurality of standby physical pages is equal to a total number of the one or more target standby physical pages,
wherein in response to determining that the total number of the plurality of standby physical pages is not equal to the total number of the one or more target standby physical pages, the read voltage management circuit unit changes the values of one or more optimized count values corresponding to the one or more target standby physical pages to the values of the target optimized count values and performs the second type of read voltage optimization operation on all converted read voltages that the target physical page and the one or more target standby physical pages each have,
wherein in response to determining that the total number of the plurality of standby physical pages is equal to the total number of the one or more target standby physical pages, the read voltage management circuit unit performs the third-type read voltage optimization operation on all converted read voltages that all physical pages of the target wordline have, respectively, and resets a plurality of optimized count values of the plurality of physical pages respectively corresponding to the target wordline to zero after the third-type read voltage optimization operation is completed.
10. The memory controller according to claim 8, wherein in an operation in which the read voltage management circuit unit is further configured to perform the first type of read voltage optimization operation, the second type of read voltage optimization operation, or the third type of read voltage optimization operation corresponding to the target word line according to the target optimization count value,
the read voltage management circuit unit determines whether the target optimized count value is equal to a least common multiple of a total number of the plurality of converted read voltages respectively corresponding to the plurality of physical pages,
wherein in response to determining that the target optimization count value is equal to the least common multiple, the read voltage management circuit unit performs the third-type read voltage optimization operation on all of the converted read voltages that all of the physical pages of the target word line have, respectively, and resets the optimization count values of the physical pages respectively corresponding to the target word line to zero after the third-type read voltage optimization operation is completed,
wherein in response to determining that the target optimization count value is not equal to the least common multiple, the read voltage management circuit unit determines whether the target optimization count value is equal to an integer multiple of one or more target standby optimization weight values of the plurality of standby optimization weight values,
wherein the read voltage management circuit unit performs the first-type read voltage optimization operation on all of the converted read voltages that the target physical page has in response to determining that the target optimization count value is not equal to an integer multiple of any one of the plurality of optimization weight values respectively corresponding to a plurality of standby physical pages,
wherein in response to determining that the target optimization count value is equal to an integer multiple of the one or more of the plurality of standby optimization weight values, the read voltage management circuit unit identifies that the standby physical page corresponding to the one or more target standby optimization weight values is one or more target standby physical pages, changes the values of the one or more optimization count values corresponding to the one or more target standby physical pages to the values of the target optimization count value, and performs the second type read voltage optimization operation on all converted read voltages that the target physical page and the one or more target standby physical pages have, respectively.
11. A storage device, the storage device comprising:
a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of word lines, wherein each of the plurality of word lines is coupled to a plurality of memory cells, wherein each of the plurality of memory cells comprises a plurality of physical pages, and each of the plurality of physical pages is to be programmed to a bit value;
a memory interface control circuit for coupling to the rewritable nonvolatile memory module; and
a processor coupled to the memory interface control circuit, wherein the processor loads and executes a read voltage management program code module to implement a data reading method, the data reading method comprising the steps of:
selecting one of the plurality of word lines as a target word line, and monitoring a plurality of physical pages of the selected target word line to obtain a plurality of monitoring results of the plurality of physical pages respectively corresponding to the target word line;
updating a target optimization count value corresponding to a target physical page in response to determining that read voltage optimization operation needs to be performed on the target physical page in the plurality of physical pages of the target word line according to the monitoring results; and
performing a first type read voltage optimization operation, a second type read voltage optimization operation, or a third type read voltage optimization operation corresponding to the target word line according to the target optimization count value to obtain an optimized read voltage set corresponding to the target word line, wherein the target word line is read by using the optimized read voltage set,
wherein the first-type read voltage optimization operation comprises:
performing a page-level read voltage optimization operation only on the target physical page, wherein in the page-level read voltage optimization operation performed on the target physical page, a voltage value of one or more transition read voltages among a plurality of preset read voltages corresponding to a preset read voltage set of the target word line for identifying a memory state of the target physical page is adjusted to an optimal value to obtain the optimized read voltage set corresponding to the target word line,
wherein the second type read voltage optimization operation comprises:
performing the page-level read voltage optimization operation on the target physical page and one or more standby physical pages of the plurality of physical pages, wherein the one or more standby physical pages are one or more other physical pages of the plurality of physical pages other than the target physical page, and a total number of the target physical page and the one or more standby physical pages is less than a total number of the plurality of physical pages,
wherein the third type read voltage optimization operation comprises:
performing a word line level read voltage optimization operation on the target word line, wherein in the word line level read voltage optimization operation performed on the target word line, voltage values of the plurality of preset read voltages corresponding to the preset read voltage group of the target word line are adjusted to optimal values to obtain the optimized read voltage group corresponding to the target word line; or performing the page level read voltage optimization operation on the plurality of physical pages respectively according to the arrangement sequence of the plurality of physical pages.
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