CN107958687B - Memory programming method, memory control circuit unit and memory device thereof - Google Patents
Memory programming method, memory control circuit unit and memory device thereof Download PDFInfo
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- CN107958687B CN107958687B CN201610904999.1A CN201610904999A CN107958687B CN 107958687 B CN107958687 B CN 107958687B CN 201610904999 A CN201610904999 A CN 201610904999A CN 107958687 B CN107958687 B CN 107958687B
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- G11C16/00—Erasable programmable read-only memories
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- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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Abstract
The invention relates to a memory programming method, a memory control circuit unit and a storage device thereof, which are used for a physical erasing unit of a programmable rewritable nonvolatile memory. The method includes programming a first data string to a first physical program cell using a first set of programming parameters, wherein the first physical program cell is comprised of memory cells at an intersection of a first bit line string of the physical erase cells and a first word line layer of the physical erase cells. In addition, the method further includes reprogramming the first data string to all memory cells of the first physical program cell using the second program parameter set after completely programming the first data string to all memory cells of the first physical program cell.
Description
Technical Field
The present invention relates to a memory programming method, and more particularly, to a memory programming method for a rewritable nonvolatile memory module, and a memory control circuit unit and a memory storage device using the same.
Background
Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable nonvolatile memory module (e.g., flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices as exemplified above.
Generally, the control circuit stores data by applying a voltage to a word line (or a word line layer) and programming (programming) a selected memory cell in the rewritable nonvolatile memory module through a bit line. For the large-capacity storage requirement in the market, a rewritable nonvolatile memory module with a storage unit storing 3 data bits has been developed. However, as the process technology becomes more sophisticated, it is more difficult to correctly identify the threshold voltage distribution in the memory cell storing 3 bits of data. Therefore, how to ensure the reliability of the data programmed into the rewritable nonvolatile memory module is a subject to be solved by those skilled in the art.
Disclosure of Invention
The invention provides a memory programming method, a memory control circuit unit and a memory storage device, which can effectively improve the reliability of stored data.
An exemplary embodiment of the present invention provides a memory programming method for physically erasing cells of a rewritable nonvolatile memory. The physical erasing unit of the rewritable nonvolatile memory comprises a plurality of word line layers and a plurality of bit line strings, wherein each bit line string in the bit line strings is arranged along a first direction in a separated mode, each bit line string in the bit line strings comprises a plurality of bit lines, the bit lines extend along a second direction and are arranged along a third direction in a separated mode, the word line layers are stacked along the second direction and are separated from each other, a storage unit is arranged at the intersection of each word line layer and each bit line, and at least one physical programming unit is formed by any bit line string in the bit line strings and the storage unit at the intersection of any word line layer in the word line layers. The method includes programming a first data string to at least a first physical programming cell of the physical erase unit using a first programming parameter set, wherein the first physical programming cell is formed by a first bit line string of the bit line strings and a memory cell at an intersection of a first word line layer of the word line layers. The memory programming method further includes, after completely programming the first data string to all memory cells of the first physical programming unit, reprogramming the first data string to all memory cells of the first physical programming unit using the second programming parameter set.
In an exemplary embodiment of the invention, the step of reprogramming the first data string to the first physical programming unit using the second programming parameter set after completely programming the first data string to the first physical programming unit includes: immediately after the first data string is completely programmed to the first physical programming unit, the first data string is reprogrammed to the first physical programming unit using the second programming parameter set.
In an exemplary embodiment of the invention, the step of reprogramming the first data string to the first physical programming unit using the second programming parameter set after completely programming the first data string to the first physical programming unit includes: reading the first data string from the first physical program unit after the first data string is completely programmed to the first physical program unit, performing an error checking and correcting operation on the first data string read from the first physical program unit and determining whether the number of error bits occurring on the first data string read from the first physical program unit is greater than a predefined value; and performing the above-described step of reprogramming the first data string to the first physical program unit using the second program parameter group only when the number of error bits occurring on the first data string read from the first physical program unit is greater than a predefined value.
In an exemplary embodiment of the invention, the first programming parameter set includes a first write voltage set, a first write voltage pulse time and a first verify voltage set, and the second programming parameter set includes a second write voltage set, a second write voltage pulse time and a second verify voltage set, wherein the first write voltage set is different from the second write voltage set.
In an exemplary embodiment of the invention, the first programming parameter set includes a first write voltage set, a first write voltage pulse time and a first verify voltage set, and the second programming parameter set includes a second write voltage set, a second write voltage pulse time and a second verify voltage set, wherein the first verify voltage set is different from the second verify voltage set.
In an exemplary embodiment of the invention, the second programming parameter set is the same as the first programming parameter set.
In an exemplary embodiment of the present invention, after the first data string is completely programmed to all the memory cells of the first physical program cell, the memory cells of the first physical program cell can be normally read, and the data read from the memory cells of the first physical program cell is identical to the first data string.
An exemplary embodiment of the present invention provides a memory control circuit unit for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a physical erasing unit, wherein the physical erasing unit comprises a plurality of word line layers and a plurality of bit line strings, each bit line string in the bit line strings is arranged along a first direction in a separated mode, each bit line string in the bit line strings comprises a plurality of bit lines, the bit lines extend along a second direction and are arranged along a third direction in a separated mode, the word line layers are stacked along the second direction and are separated from each other, a storage unit is arranged at the intersection of each word line layer and each bit line, and at least one physical programming unit is formed by any bit line string in the bit line strings and the storage unit at the intersection of any word line layer in the word line layers. The memory control circuit unit includes: a host interface, a memory interface, and memory management circuitry. The memory management circuit is electrically connected to the host interface and the memory interface. The host interface is used for electrically connecting to a host system, and the memory interface is used for electrically connecting to the rewritable nonvolatile memory module. The memory management circuit issues a first command sequence to program a first data string to at least a first physical programming unit of the physical erase unit using a first programming parameter set, wherein the first physical programming unit is formed by a first bit line string of the bit line strings and a memory cell at an intersection of the first word line layer of the word line layers. After the first data string is completely programmed to all the memory cells of the first physical programming unit, the memory management circuit issues a second command sequence to reprogram the first data string to all the memory cells of the first physical programming unit using the second programming parameter set.
In an exemplary embodiment of the invention, the memory management circuit is operative to reprogram the first data string to the first physical programming unit using the second programming parameter set immediately after the first data string is completely programmed to the first physical programming unit.
In an exemplary embodiment of the present invention, in an operation of reprogramming the first data string to the first physical program unit using the second programming parameter set after completely programming the first data string to the first physical program unit, the memory management circuit reads the first data string from the first physical program unit, performs an error check and correction operation on the first data string read from the first physical program unit, and determines whether the number of error bits occurring on the first data string read from the first physical program unit is greater than a predefined value after completely programming the first data string to the first physical program unit. And, the memory management circuit performs the above-described operation of reprogramming the first data string to the first physical program unit using the second program parameter group only when the number of error bits occurring on the first data string read from the first physical program unit is greater than a predefined value.
An exemplary embodiment of the invention provides a memory storage device, which includes a connection interface unit electrically connected to a host system, a rewritable nonvolatile memory module, and the memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit includes: a host interface, a memory interface, and memory management circuitry. The host interface is used for being electrically connected to a host system, the memory interface is used for being electrically connected to the rewritable nonvolatile memory module, and the memory management circuit is electrically connected to the host interface and the memory interface.
Based on the above, the memory programming method, the memory control circuit unit and the memory storage device according to the exemplary embodiments of the invention can effectively improve the reliability of the stored data and avoid data loss.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to a first exemplary embodiment.
FIG. 2 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment.
FIG. 3 is a diagram illustrating a host system and a memory storage device according to another example embodiment.
FIG. 4 is a schematic block diagram of a host system and a memory storage device according to a first exemplary embodiment.
FIG. 5 is a schematic block diagram of a rewritable nonvolatile memory module according to a first exemplary embodiment.
FIG. 6 is a diagram of a memory cell array of physically erased cells according to a first exemplary embodiment.
FIG. 7 is a schematic diagram illustrating programming of a memory cell according to a first exemplary embodiment.
FIG. 8 is a diagram illustrating reading data from a memory cell according to a first exemplary embodiment.
FIGS. 9, 10, 11 and 12 are schematic diagrams illustrating exemplary managing entity-erased cells according to the first exemplary embodiment.
FIG. 13 is a schematic block diagram of a memory control circuit unit according to a first exemplary embodiment.
Fig. 14 is a flowchart illustrating a memory programming method according to a first exemplary embodiment of the invention.
Fig. 15 is a flowchart illustrating a memory programming method according to a second exemplary embodiment of the invention.
The reference numbers illustrate:
10: a memory storage device;
11: a host system;
12: input/output (I/O) devices;
110: a system bus;
111: a processor;
112: random Access Memory (RAM);
113: read Only Memory (ROM);
114: a data transmission interface;
20: a main board;
204: a wireless memory storage device;
205: a global positioning system module;
206: a network interface card;
207: a wireless transmission device;
208: a keyboard;
209: a screen;
210: a horn;
30: a memory storage device;
31: a host system;
32: an SD card;
33: a CF card;
34: an embedded storage device;
341: an embedded multimedia card;
342: an embedded multi-chip package storage device;
402: a connection interface unit;
404: a memory control circuit unit;
406: a rewritable non-volatile memory module;
410(0), 410(1), 410(F-1), 410(F +1), 410(S-1), 410(S +1), 410(R-1), 410(R +1), 410 (N): a physical erase unit;
2202: an array of memory cells;
2204: a word line control circuit;
2206: a bit line control circuit;
2208: a row decoder;
2210: a data input/output buffer;
2212: a control circuit;
702: a storage unit;
704(1), 704(2), 704(3), 704 (4): a bit line string;
704(1-1), 704(1-2), 704(1-3), 704(1-4), 704(2-1), 704(2-2), 704(2-3), 704(2-4), 704(3-1), 704(3-2), 704(3-3), 704(3-4), 704(4-1), 704(4-2), 704(4-3), 704 (4-4): a set of bit lines;
706(1), 706(2), 706(3), 706(4), 706(5), 706(6), 706(7), 706(8), 706 (9): a word line layer;
VA: a first preset read voltage;
VB: a second preset read voltage;
VC: a third preset read voltage;
VD: a fourth preset read voltage;
VE: a fifth preset read voltage;
VF: a sixth preset read voltage;
VG: a seventh preset read voltage;
502: a data area;
504: an idle area;
506: a system area;
508: a temporary storage area;
510: a substitution region;
LBA (0) to LBA (h): a logic unit;
1302: a memory management circuit;
1304: a host interface;
1306: a memory interface;
1308: an error checking and correcting circuit;
1310: a buffer memory;
1312: a power management circuit;
s1401: a step of programming a data string (hereinafter, referred to as a first data string) to at least one physically programmed cell (hereinafter, referred to as a first physically programmed cell) of the physically erased cells using a first programming parameter set;
s1402: a step of reprogramming the first data string to the first physical program cell using the second programming parameter group;
s1501: a step of programming a data string (hereinafter, referred to as a first data string) to at least one physically programmed cell (hereinafter, referred to as a first physically programmed cell) of the physically erased cells using a first programming parameter set;
s1503: reading a first data string from a first physical programming unit;
s1505: a step of judging whether the number of error bits occurring on the read first data string is larger than a predefined value;
s1507: and reprogramming the first data string to the first physical programming unit using the second programming parameter group.
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module and a controller (also referred to as a control circuit unit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
[ first exemplary embodiment ]
Fig. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to a first exemplary embodiment, and fig. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another exemplary embodiment.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.
In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.
In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 are disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through the data transmission interface 114 in a wired or wireless manner. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory Storage 204 can be a memory Storage based on various wireless Communication technologies, such as Near Field Communication (NFC) memory Storage, wireless facsimile (WiFi) memory Storage, Bluetooth (Bluetooth) memory Storage, or Bluetooth low energy (low) memory Storage (e.g., iBeacon). In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34 used therein. The embedded memory device 34 includes embedded Multi-media cards (eMMC) 341 and/or embedded Multi-Chip Package memory devices (eMCP) 342, and various types of embedded memory devices electrically connecting the memory module to the substrate of the host system.
FIG. 4 is a schematic block diagram of a host system and a memory storage device according to a first exemplary embodiment.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.
In the exemplary embodiment, the connection interface unit 402 is compatible with Secure Digital (SD) interface standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to Serial Advanced Technology Attachment (SATA) standard, Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, High-Speed Peripheral Component connection interface (PCI Express) standard, Universal Serial Bus (USB) standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, Multi-Media-Chip (Package) interface standard, Multi-Media Embedded Multi-Chip (MMC) interface standard, eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-Chip Package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. In the present exemplary embodiment, the connection interface unit 402 and the memory control circuit unit 404 may be packaged in one chip, or the connection interface unit 402 is disposed outside a chip including the memory control circuit unit.
The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented by hardware or software, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.
The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 has physical erase units 410(0) -410 (N). For example, the physical erase units 410(0) -410 (N) may belong to the same memory die (die) or to different memory dies. Each entity erasing unit is respectively provided with a plurality of entity programming units, wherein the entity programming units belonging to the same entity erasing unit can be independently written and simultaneously erased. However, it should be understood that the present invention is not limited thereto, and each of the plurality of physical erase units may be composed of 64 physical program units, 256 physical program units, or any other number of physical program units.
In more detail, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. The physical programming cell is the smallest cell programmed. That is, the physical programming cell is the smallest cell to which data is written. Each physical programming cell typically includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical access addresses for storing user data, and the redundancy bit region stores system data (e.g., control information and error correction codes). In the exemplary embodiment, each physical program unit includes 8 physical access addresses in the data bit region, and one physical access address has a size of 512 bit group (byte). However, in other exemplary embodiments, the data bit region may include a greater or lesser number of physical access addresses, and the size and number of the physical access addresses are not limited in the present invention. For example, in an exemplary embodiment, the physically erased cells are physical blocks, and the physically programmed cells are physical pages or physical sectors, but the invention is not limited thereto.
In the present exemplary embodiment, the rewritable nonvolatile memory module 406 is a Three dimensional (3D) multilevel Cell (TLC) NAND-type flash memory module (i.e., a flash memory module that can store 3 data bits in one memory Cell) or other memory modules with the same characteristics. However, the invention is not limited thereto, and the rewritable nonvolatile memory module 406 may also be a 3D Multi-Level Cell (MLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 2 bits of data in one memory Cell) or other memory modules with the same characteristics.
FIG. 5 is a schematic block diagram of a rewritable nonvolatile memory module according to a first exemplary embodiment, and FIG. 6 is a schematic diagram of a memory cell array of physically erased cells according to the first exemplary embodiment.
Referring to fig. 5 and 6, the rewritable nonvolatile memory module 406 includes a memory cell array 2202, a word line control circuit 2204, a bit line control circuit 2206, a column decoder 2208, a data input/output buffer 2210 and a control circuit 2212.
Referring to fig. 5 and 6, the memory cell array 2202 includes a plurality of memory cells 702 for storing data, a plurality of bit line strings (e.g., a first bit line string 704(1), a second bit line string 704(2), a third bit line string 704(3), and a fourth bit line string 704(4)), and a plurality of word line layers (e.g., a first word line layer 706(1), a second word line layer 706(2), a third word line layer 706(3), a fourth word line layer 706(4), a fifth word line layer 706(5), a sixth word line layer 706(6), a seventh word line layer 706(7), an eighth word line layer 706(8), and a ninth word line layer 706 (9)). The physically erased cells are formed by memory cells 702 in memory cell array 2202. Specifically, each bit line string includes a plurality of bit line groups (e.g., bit line groups 704(1-1), bit line groups 704(1-2), bit line groups 704(1-3), bit line groups 704(1-4), bit line groups 704(2-1), bit line groups 704(2-2), bit line groups 704(2-3), bit line groups 704(2-4), bit line groups 704(3-1), bit line groups 704(3-2), bit line groups 704(3-3), bit line groups 704(3-4), bit line groups 704(4-1), bit line groups 704(4-2), bit line groups 704(4-3), bit line groups 704(4-4)), and each bit line group is arranged apart from each other in the first direction. In addition, each bit line group includes a plurality of bit lines arranged apart from each other in the third direction and extending in the second direction (the tubular elements are vertically arranged through the word line layers as shown in fig. 6). The word line layers are stacked along a second direction and separated from each other. For example, the first direction is the X-axis, the second direction is the Z-axis, and the third direction is the Y-axis. The memory cells constituting the physical erase cells are located at the intersections of each word line layer and each bit line of each bit line string. In the exemplary embodiment, the rewritable non-volatile memory module 406 is a 3D TLC NAND flash memory module, and thus the memory cells at the intersections of each bit line string and each word line layer constitute 3 physical programming units. In the case where the rewritable nonvolatile memory module 406 is a 3D MLC NAND flash memory module, the memory cells at the intersections of each bit line string and each word line layer constitute 2 physical programming units. When a write command or a read command is received from the memory control circuit unit 404, the control circuit 2212 controls the word line control circuit 2204, the bit line control circuit 2206, the column decoder 2208 and the data input/output buffer 2210 to write data into the memory cell array 2202 or read data from the memory cell array 2202, wherein the word line control circuit 2204 controls the voltage applied to the word line 706, the bit line control circuit 2206 controls the voltage applied to the bit line 704, the column decoder 2208 selects the corresponding bit line according to the decoded row address in the command, and the data input/output buffer 2210 is used for temporarily storing the data. The memory cells in the rewritable nonvolatile memory module 406 represent multi-bit (bits) data with various gate voltages. Data writing (or programming) of the memory cells of the memory cell array 2202 utilizes a voltage applied to a particular terminal, such as a control gate voltage, to change the amount of electrons in a charge trapping layer in the gate, thereby changing the conduction state of the channel of the memory cell to assume different memory states.
FIG. 7 is a schematic diagram illustrating programming of a memory cell according to a first exemplary embodiment.
Referring to fig. 7, in the present exemplary embodiment, the programming of the memory cell is accomplished by a pulsed write/verify threshold voltage method. Specifically, when data is to be written into the memory cells, the memory control circuit unit 404 sets an initial write voltage and a write voltage pulse time, and instructs the control circuit 2212 of the rewritable nonvolatile memory module 406 to program the memory cells using the set initial write voltage and write voltage pulse time, so as to write the data. The memory control circuit unit 404 then verifies the memory cell with the verification voltage to determine whether the memory cell is in the correct storage state. If the memory cell is not programmed to the correct memory state, the memory control circuit unit 404 instructs the control circuit 2212 to add an Incremental-step-pulse-programming (ISPP) adjustment value to the currently applied write voltage as a new write voltage (also called a re-write voltage) and to program the memory cell again according to the new write voltage and the write voltage pulse time. Conversely, if the memory cell has been programmed to the correct memory state, it indicates that the data has been correctly written to the memory cell. For example, the initial write Voltage is set to 16 volts (V), the write Voltage pulse time is set to 18 microseconds (μ s) and the incremental step pulse program adjust value is set to 0.6V, but the invention is not limited thereto.
The read operation of a memory cell of memory cell array 2202 identifies the data stored in the memory cell by applying a read voltage to a control gate (control gate) to turn on a channel of the memory cell (a path through which the memory cell electrically connects a bit line to a source line, such as a path from a source to a drain of the memory cell).
Fig. 8 is a schematic diagram illustrating data reading from a memory cell according to the first exemplary embodiment, which is exemplified by a 3D TLC NAND type flash memory.
Referring to fig. 8, the memory states of the memory cells of the rewritable nonvolatile memory module 406 include the Least Significant Bit (LSB) of the 1 st Bit counted from the left side, the middle Significant Bit (CSB) of the 2 nd Bit counted from the left side, and the Most Significant Bit (MSB) of the 3 rd Bit counted from the left side, wherein the LSB corresponds to the lower physical program cell, the CSB corresponds to the middle physical program cell, and the MSB corresponds to the upper physical program cell. In this example, the gate voltage of each memory cell can be divided into 8 memory states (i.e., "111", "110", "100", "101", "001", "000", "010" and "011") according to the first preset read voltage VA, the second preset read voltage VB, the third preset read voltage VC, the fourth preset read voltage VD, the fifth preset read voltage VE, the sixth preset read voltage VF and the seventh preset read voltage VG. In particular, the plurality of memory cells arranged on the same word line may constitute 3 physical program cells, wherein a physical program cell constituted by the LSB of the memory cells is referred to as a lower physical program cell, a physical program cell constituted by the CSB of the memory cells is referred to as a middle physical program cell, and a physical program cell constituted by the MSB of the memory cells is referred to as an upper physical program cell.
FIGS. 9, 10, 11 and 12 are schematic diagrams illustrating exemplary managing entity-erased cells according to the first exemplary embodiment.
Referring to fig. 9, the memory control circuit unit 404 performs a write operation on the memory cells 702 of the rewritable non-volatile memory module 406 by taking the physical programming cells as units and performs an erase operation on the memory cells 702 of the rewritable non-volatile memory module 406 by taking the physical erasing cells as units. Specifically, the memory cells 702 of the rewritable nonvolatile memory module 406 constitute a plurality of physical programming units, and the physical programming units constitute a plurality of physical erasing units 410(0) -410 (N). The physical erase cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. The physical programming cell is the smallest cell programmed. That is, one physical programming cell is the smallest unit of written data. In particular, in the exemplary embodiment, the solid program cells can be programmed one or more times before a solid erase cell is erased. Each physical programming cell typically includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical access addresses for storing user data, and the redundancy bit region stores system data (e.g., control information and error correction codes). For example, taking the rewritable non-volatile memory module 406 belonging to the 3D TLC NAND flash memory as an example, the LSB of the memory cell located at the boundary between a word line layer and a bit line string constitutes a next entity programming unit; the CSB of the memory cell located at the intersection of a word line layer and a bit line string constitutes a middle entity programming unit; and the MSBs of the memory cells located at the intersection of a word line layer and a bit line string constitute one upper physical program cell. That is, the entity programming units in the entity erasing units of the rewritable nonvolatile memory module 406 can be divided into lower entity programming units, middle entity programming units and upper entity programming units (as shown in FIG. 10).
Referring to FIG. 11, in the exemplary embodiment, the memory control circuit unit 404 logically groups the physical erase units 410(0) -410 (N) into a data area 502, an idle area 504, a system area 506, a temporary area 508, and a replacement area 510.
The physically erased cells logically belonging to the data area 502 and the idle area 504 are used for storing data from the host system 11. Specifically, the physical erase units in the data area 502 are regarded as physical erase units with stored data, and the physical erase units in the idle area 504 are used to replace the physical erase units in the data area 502. That is, when receiving a write command and data to be written from the host system 11, the memory control circuit unit 404 extracts the physical erase unit from the idle region 504 and writes the data into the extracted physical erase unit to replace the physical erase unit of the data region 502.
The physical erase unit logically belonging to the system area 506 is used for recording system data. For example, the system data includes information about the manufacturer and model of the rewritable nonvolatile memory module, the number of physically erased cells of the rewritable nonvolatile memory module, the number of physically programmed cells per physically erased cell, the software code of the memory storage device 10, and so on.
The physical erase unit logically belonging to the register 508 is used to temporarily store the data written by the host system 11.
The physically erased cells logically belonging to the replacement area 510 are used in the bad-physically-erased-cell replacement procedure to replace the damaged physically erased cells. Specifically, if there are normal physically erased cells in the replacement area 510 and the physically erased cells in the data area 502 are damaged, the memory management circuit 1302 extracts the normal physically erased cells from the replacement area 510 to replace the damaged physically erased cells.
In particular, the number of physically erased cells in the data area 502, the idle area 504, the system area 506, the temporary area 508 and the replacement area 510 may vary according to different memory specifications. Moreover, it should be appreciated that during operation of the memory storage device 10, the grouping relationship of physically erased cells associated with the data area 502, the idle area 504, the system area 506, the temporary area 508 and the replacement area 510 may dynamically change. For example, when the physically erased cells in the idle area 504 are damaged and replaced by the physically erased cells in the replacement area 510, the physically erased cells in the replacement area 510 are associated with the idle area 504. For example, in the card-open procedure, no physical erase unit is allocated to the register 508, and when the write operation is performed, the memory control circuit unit 404 extracts the physical erase unit from the idle area 504 to register the data, and the physical erase unit for registering the data is regarded as belonging to the register 508.
Referring to fig. 12, the memory control circuit unit 404 configures the logic units LBA (0) -LBA (h) to map the physical erase units of the data area 502, where each logic unit has a plurality of logic sub-units to map the physical programming units of the corresponding physical erase unit. Moreover, when the host system 11 wants to write data into the logical units or update the data stored in the logical units, the memory control circuit unit 404 extracts a physical erase unit from the idle area 504 to write data, so as to replace the physical erase unit in the data area 502. In the present exemplary embodiment, the logical subunit may be a logical page or a logical sector.
In order to identify the physical erase unit in which the data of each logic unit is stored, in the present exemplary embodiment, the memory control circuit unit 404 records the mapping between the logic units and the physical erase units. Moreover, when the host system 11 intends to access data in the logical subunit, the memory control circuit unit 404 will determine the logical unit to which the logical subunit belongs, and issue a corresponding command sequence to the rewritable nonvolatile memory module 406 to access data in the physical erase unit mapped by the logical unit. For example, in the exemplary embodiment, the memory control circuit unit 404 stores a logical-to-physical address mapping table in the rewritable nonvolatile memory module 406 to record the physical erase unit mapped by each logical unit, and the memory control circuit unit 404 loads the logical-to-physical address mapping table into the buffer memory for maintenance when data is to be accessed.
FIG. 13 is a schematic block diagram of a memory control circuit unit according to a first exemplary embodiment. It should be understood that the structure of the memory control circuit unit shown in fig. 13 is only an example, and the invention is not limited thereto.
Referring to FIG. 13, the memory control circuit unit 404 includes a memory management circuit 1302, a host interface 1304, a memory interface 1306, and an error checking and correcting circuit 1308.
The memory management circuit 1302 controls the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 1302 has a plurality of control commands, and the control commands are executed to write, read and erase data during operation of the memory storage device 10. The operations and functions performed by the memory management circuit 1302 are described below and may also be considered as being performed by the memory control circuit unit 404.
In the present exemplary embodiment, the control instructions of the memory management circuit 1302 are implemented in software. For example, the memory management circuit 1302 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 1302 may also be stored in a program code type in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 1302 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a driver, and when the memory control circuit 404 is enabled, the microprocessor first executes the driver to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 1302. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 1302 may also be implemented in hardware. For example, the memory management circuit 1302 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the entity erasing unit of the rewritable nonvolatile memory module 406; the memory writing circuit is used for issuing a writing instruction to the rewritable nonvolatile memory module 406 so as to write data into the rewritable nonvolatile memory module 406; the memory reading circuit is used for sending a reading instruction to the rewritable nonvolatile memory module 406 so as to read data from the rewritable nonvolatile memory module 406; the memory erasing circuit is used for issuing an erasing instruction to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406; the data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406.
The host interface 1304 is electrically connected to the memory management circuit 1302 and is used for receiving and identifying commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 1302 through the host interface 1304. In the exemplary embodiment, host interface 1304 is compatible with the USB standard. However, it should be understood that the present invention is not limited thereto, and the host interface 1304 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the SD standard, the SATA standard, the UHS-I interface standard, the UHS-II interface standard, the MS standard, the MMC standard, the eMMC interface standard, the UFS interface standard, the CF standard, the IDE standard, or other suitable data transfer standard.
The memory interface 1306 is electrically connected to the memory management circuit 1302 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 1306.
The error checking and correcting circuit 1308 is electrically connected to the memory management circuit 1302 and is configured to perform an error correcting procedure to ensure the correctness of the data. Specifically, when the memory management circuit 1302 reads data from the rewritable nonvolatile memory module 406, the error checking and correcting circuit 1308 performs an error correcting procedure on the read data. For example, in the exemplary embodiment, the error checking and correcting circuit 1308 is a Low Density Parity Check (LDPC) circuit and stores a Log Likelihood Ratio (LLR) value lookup table. When the memory management circuit 1302 reads data from the rewritable nonvolatile memory module 406, the error checking and correcting circuit 1308 performs an error correcting process according to the read data and the corresponding LLR value in the lookup table. It is worth mentioning that in another exemplary embodiment, the error checking and correcting circuit 1308 can also be a Turbo Code (Turbo Code) circuit.
In an exemplary embodiment of the invention, the memory control circuit unit 404 further includes a buffer memory 1310 and a power management circuit 1312.
The buffer memory 1310 is electrically connected to the memory management circuit 1302 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406.
The power management circuit 1312 is electrically connected to the memory management circuit 1302 and is used for controlling the power of the memory storage device 10.
In the present exemplary embodiment, during the process of writing data into the physically erased cells, each time the memory control circuit unit 404 issues a command sequence (i.e. a programming command containing strings such as "80", "address", "10", etc.) to apply a voltage to one of the word line layers for performing a programming operation, it only instructs to select one of the bit line strings for operation, so as to program the memory cells on the boundary between the word line layer and the bit line string. In particular, in order to increase the read margin (read margin) of the voltage distribution of the programmed memory cells to increase the reliability of data, in the exemplary embodiment, the memory control circuit unit 404 performs a second programming operation on the memory cells at the boundary between a word line layer and a bit line string after completing the complete programming of the memory cells at the boundary between the word line layer and the bit line string (i.e., completing the above-mentioned pulse write/verify threshold voltage programming operation). Specifically, after the memory cells on the boundary of a word line layer and a bit line string are completely programmed, the data on the memory cells on the boundary of the word line layer and the bit line string can be correctly read (i.e., a read command can be issued to correctly read the data on the memory cells). However, in order to increase the read margin in these memory cells, the memory control circuit unit 404 issues a program command to program these memory cells by using the above-mentioned pulse write/verify threshold voltage method when the memory cells on the boundary between the word line layer and the bit line string store correct data. That is, in the exemplary embodiment, memory control circuit unit 404 continuously performs a plurality of complete programming operations on the memory cells at the boundary between a word line layer and a bit line string.
FIG. 14 is a flowchart illustrating a memory programming method according to a first exemplary embodiment.
Referring to fig. 14, in step S1401, the memory control circuit unit 404 programs a data string (hereinafter, referred to as a first data string) to at least one physical programming unit (hereinafter, referred to as a first physical programming unit) of the physical erase unit by using a first programming parameter set, wherein the first physical programming unit is formed by memory cells on the intersection of a first bit line string 704(1) and a first word line layer 706 (1). As described above, in the exemplary embodiment, the rewritable nonvolatile memory module 406 is a 3D TLC NAND flash memory module, and thus, the memory cells at the intersection of the first bit line string 704(1) and the first word line layer 706(1) form 3 physical programming units, and the 3 physical programming units are programmed at the same time.
Next, in step S1402, the memory control circuit unit 404 reprograms the first data string to the first physical programming unit using the second programming parameter group. For example, the memory control circuit unit 404 reprograms the first data string to the first physical programming unit again using the second programming parameter group immediately after completing the programming of the first data string to the first physical programming unit.
Here, the second programming parameter set is different from the first programming parameter set. For example, the memory control circuit unit 404 generates a write voltage set (hereinafter, referred to as a second write voltage set) of a second programming parameter set according to the write voltage set of a first programming parameter set (hereinafter, referred to as a first write voltage set) and a predetermined adjustment value. Alternatively, in another exemplary embodiment, the memory control circuit unit 404 generates a verification voltage set (hereinafter, referred to as a second verification voltage set) of a second program parameter set according to the verification voltage set of the first program parameter set (hereinafter, referred to as a first verification voltage set) and a predetermined adjustment value. Furthermore, in another exemplary embodiment, the memory control circuit unit 404 generates the write voltage pulse time (hereinafter referred to as the second write voltage pulse time) of the second programming parameter group according to the write voltage pulse time of the first programming parameter group (hereinafter referred to as the first write voltage pulse time) and a predetermined adjustment value.
It is worth mentioning that, although in the present exemplary embodiment, the second programming parameter set is different from the first programming parameter set. However, the present invention is not limited thereto, and in another exemplary embodiment, the second programming parameter set may be the same as the first programming parameter set.
[ second exemplary embodiment ]
The hardware structure of the memory storage device of the second exemplary embodiment is substantially the same as that of the memory storage device of the first exemplary embodiment, except that the memory storage device of the first exemplary embodiment continuously performs a complete programming operation on the same memory cells on the same word line layer and the same bit line string, and the memory storage device of the second exemplary embodiment performs a repeated programming operation after the complete programming operation is completed and the number of error bits occurring on the programmed data is found to be greater than a predefined value. The operation of the memory storage device of the second exemplary embodiment will be described in detail below using the drawings and element numbers of the memory storage device of the first exemplary embodiment.
FIG. 15 is a flowchart illustrating a memory programming method according to a second exemplary embodiment.
Referring to fig. 15, in step S1501, the memory control circuit unit 404 programs a data string (hereinafter referred to as a first data string) to at least one physical programming unit (hereinafter referred to as a first physical programming unit) of the physical erase unit using a first programming parameter set, wherein the first physical programming unit is formed by memory cells on the intersection of the first bit line string 704(1) and the first word line layer 706 (1).
In step S1503, the memory control circuit unit 404 reads the first data string from the first physical programming unit, and in step S1505, the memory control circuit unit 404 determines whether the number of error bits occurring in the read first data string is greater than a predefined value. Specifically, the error checking and correcting circuit 1308 of the memory control circuit 404 performs an error checking and correcting operation on the read first data string. For example, the number of error bits that the error checking and correcting circuit 1308 is capable of correcting is the maximum correctable number, and the predefined value may be set to be less than or equal to the maximum correctable number of the error checking and correcting circuit 1308.
In case the number of error bits occurring on the read first data string is greater than the predefined value, the memory control circuit unit 404 re-programs the first data string to the first physical programming unit using the second programming parameter group in step S1507.
If the number of error bits occurred on the read first data string is not greater than the predefined value, the process of FIG. 15 is ended.
In summary, the data programming method, the memory control circuit unit and the memory storage device according to the exemplary embodiments of the invention repeat the programming operation on the same memory cell when programming data, thereby increasing the read margin in the voltage distribution of the memory cell to improve the reliability of data.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (21)
1. A memory programming method is used for at least one entity erasing unit of a rewritable nonvolatile memory, wherein the at least one physical erase unit includes a plurality of word line layers and a plurality of bit line strings, each of the plurality of bit line strings being arranged to be separated from each other along a first direction, each of the plurality of bit line strings includes a plurality of bit lines extending in a second direction and arranged apart from each other in a third direction, the plurality of word line layers are stacked along the second direction and separated from each other, and each word line layer and each bit line have memory cells at the crossing, any bit line string in a plurality of bit line strings and memory cells at the crossing of any word line layer in a plurality of word line layers constitute at least one entity programming unit, the memory programming method comprises:
programming a first data string to at least a first physical programming unit of the physical erase units using a first programming parameter set, wherein the at least a first physical programming unit is formed by memory cells at an intersection of a first bit line string of the plurality of bit line strings and a first word line layer of the plurality of word line layers; and
after the first data string is completely programmed to all of the at least one first physical program cell, reprogramming the first data string to all of the at least one first physical program cell using a second programming parameter set,
the number of the at least one first physical programming unit is the same as the number of the bits stored in the memory unit, and the at least one first physical programming unit is programmed at the same time.
2. The memory programming method of claim 1, wherein the step of reprogramming the first data string to the at least one first physical programming unit using the second programming parameter set after completely programming the first data string to the at least one first physical programming unit comprises:
the second programming parameter set is used to program the first data string to the at least one first physical programming cell again immediately after the first data string is completely programmed to the at least one first physical programming cell.
3. The memory programming method of claim 1, wherein the step of reprogramming the first data string to the at least one first physical programming unit using the second programming parameter set after completely programming the first data string to the at least one first physical programming unit comprises:
reading the first data string from the at least one first physical programming cell after the first data string is completely programmed to the at least one first physical programming cell;
performing an error checking and correcting operation on the first data string read from the at least one first physical program unit and determining whether a number of error bits occurring on the first data string read from the at least one first physical program unit is greater than a predefined value; and
the step of reprogramming the first data string to the at least one first physical program cell using the second programming parameter set is performed only when the number of error bits occurring on the first data string read from the at least one first physical program cell is greater than the predefined value.
4. The memory programming method of claim 1, wherein the first set of programming parameters comprises a first set of write voltages, a first set of write voltage pulses, and a first set of verify voltages and the second set of programming parameters comprises a second set of write voltages, a second set of write voltage pulses, and a second set of verify voltages,
wherein the first set of write voltages is different from the second set of write voltages.
5. The memory programming method of claim 1, wherein the first set of programming parameters comprises a first set of write voltages, a first set of write voltage pulses, and a first set of verify voltages and the second set of programming parameters comprises a second set of write voltages, a second set of write voltage pulses, and a second set of verify voltages,
wherein the first set of verify voltages is different from the second set of verify voltages.
6. The memory programming method of claim 1, wherein the second set of programming parameters is the same as the first set of programming parameters.
7. The memory programming method of claim 1, wherein after the first data string is completely programmed to all the memory cells of the at least one first physical program cell, the memory cells of the at least one first physical program cell can be normally read, and data read from the memory cells of the at least one first physical program cell is identical to the first data string.
8. A memory control circuit unit for accessing a rewritable non-volatile memory module, the memory control circuit unit comprising:
a host interface for electrically connecting to a host system;
a memory interface electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has at least one physical erasing unit, the at least one physical erase unit includes a plurality of word line layers and a plurality of bit line strings, each of the plurality of bit line strings being arranged to be separated from each other along a first direction, each of the plurality of bit line strings includes a plurality of bit lines extending in a second direction and arranged apart from each other in a third direction, the plurality of word line layers are stacked along the second direction and separated from each other, the memory unit is arranged at the crossing position of each word line layer and each bit line, and the memory unit at the crossing position of any bit line string in the plurality of bit line strings and any word line layer in the plurality of word line layers forms at least one entity programming unit; and
a memory management circuit electrically connected to the host interface and the memory interface,
wherein the memory management circuit issues a first command sequence to program a first data string to at least one first physical programming unit of the physical erase unit using a first programming parameter set, wherein the at least one first physical programming unit is formed by memory cells at an intersection of a first bit line string of the plurality of bit line groups and a first word line layer of the plurality of word line layers,
wherein the memory management circuit is further configured to issue a second sequence of instructions to reprogram the first data string to all of the at least one first physical programming cell using a second set of programming parameters after completely programming the first data string to all of the at least one first physical programming cell,
the number of the at least one first physical programming unit is the same as the number of the bits stored in the memory unit, and the at least one first physical programming unit is programmed at the same time.
9. The memory control circuit unit of claim 8, wherein in operation to reprogram the first data string to the at least one first physical programming unit using the second programming parameter set after the first data string is completely programmed to the at least one first physical programming unit, the memory management circuit reprograms the first data string to the at least one first physical programming unit using the second programming parameter set immediately after the first data string is completely programmed to the at least one first physical programming unit.
10. The memory control circuit unit of claim 8, wherein in operation of reprogramming the first data string to the at least one first physical program unit using the second programming parameter set after completely programming the first data string to the at least one first physical program unit, the memory management circuit performs an error check and correction operation on the first data string read from the at least one first physical program unit and determines whether the number of error bits occurring on the first data string read from the at least one first physical program unit is greater than a predefined value after completely programming the first data string to the at least one first physical program unit,
wherein the memory management circuit performs the above-described operation of reprogramming the first data string to the at least one first physical program cell using the second programming parameter set only when the number of error bits occurring on the first data string read from the at least one first physical program cell is greater than the predefined value.
11. The memory control circuit cell of claim 8, wherein the first programming parameter set includes a first write voltage set, a first write voltage pulse time, and a first verify voltage set and the second programming parameter set includes a second write voltage set, a second write voltage pulse time, and a second verify voltage set, wherein the first write voltage set is different from the second write voltage set.
12. The memory control circuit cell of claim 8, wherein the first programming parameter set includes a first write voltage set, a first write voltage pulse time, and a first verify voltage set and the second programming parameter set includes a second write voltage set, a second write voltage pulse time, and a second verify voltage set, wherein the first verify voltage set is different from the second verify voltage set.
13. The memory control circuit unit of claim 8, wherein the second set of programming parameters is the same as the first set of programming parameters.
14. The memory control circuit unit of claim 8, wherein after the first data string is completely programmed to all the memory cells of the at least one first physical program cell, the memory cells of the at least one first physical program cell can be read normally, and the data read from the memory cells of the at least one first physical program cell is identical to the first data string.
15. A memory storage device, comprising:
the connection interface unit is used for electrically connecting to a host system;
a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has at least one solid erasing unit, the at least one physical erase unit includes a plurality of word line layers and a plurality of bit line strings, each of the plurality of bit line strings being arranged to be separated from each other along a first direction, each of the bit line strings includes a plurality of bit lines extending in a second direction and arranged apart from each other in a third direction, the plurality of word line layers are stacked along the second direction and separated from each other, the memory unit is arranged at the crossing position of each word line layer and each bit line, and the memory unit at the crossing position of any bit line string in the plurality of bit line strings and any word line layer in the plurality of word line layers forms at least one entity programming unit; and
a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is configured to issue a first command sequence to program a first data string to at least one first physical programming unit of the physical erase unit using a first programming parameter set, wherein the at least one first physical programming unit is formed by memory cells at intersections of a first bit line string of the plurality of bit line groups and a first word line layer of the plurality of word line layers,
wherein the memory control circuit unit is further configured to issue a second command sequence to reprogram the first data string to all of the at least one first physical programming unit using a second programming parameter set after completely programming the first data string to all of the at least one first physical programming unit,
the number of the at least one first physical programming unit is the same as the number of the bits stored in the memory unit, and the at least one first physical programming unit is programmed at the same time.
16. The memory storage device of claim 15, wherein in operation of reprogramming the first data string to the at least one first physical programming unit using the second programming parameter set after completely programming the first data string to the at least one first physical programming unit, the memory control circuit unit reprograms the first data string to the at least one first physical programming unit using the second programming parameter set immediately after completely programming the first data string to the at least one first physical programming unit.
17. The memory storage device of claim 15, wherein in operation to reprogram the first data string to the at least one first physical program cell using the second programming parameter set after the first data string is completely programmed to the at least one first physical program cell, the memory control circuit unit reads the first data string from the at least one first physical program cell after the first data string is completely programmed to the at least one first physical program cell, performs an error check and correction operation on the first data string read from the at least one first physical program cell and determines whether a number of error bits occurring on the first data string read from the at least one first physical program cell is greater than a predefined value,
wherein the memory control circuit unit performs the above-described operation of reprogramming the first data string to the at least one first physical program unit using the second program parameter group only when the number of error bits occurring on the first data string read from the at least one first physical program unit is greater than the predefined value.
18. The memory storage device of claim 15, wherein the first set of programming parameters comprises a first set of write voltages, a first set of write voltage pulses, and a first set of verify voltages and the second set of programming parameters comprises a second set of write voltages, a second set of write voltage pulses, and a second set of verify voltages, wherein the first set of write voltages is different than the second set of write voltages.
19. The memory storage device of claim 15, wherein the first set of programming parameters comprises a first set of write voltages, a first set of write voltage pulses, and a first set of verify voltages and the second set of programming parameters comprises a second set of write voltages, a second set of write voltage pulses, and a second set of verify voltages, wherein the first set of verify voltages is different than the second set of verify voltages.
20. The memory storage device of claim 15, wherein the second set of programming parameters is the same as the first set of programming parameters.
21. The memory storage device of claim 15, wherein after the first data string is completely programmed to all of the at least one first physical program cell, the memory cells of the at least one first physical program cell can be read normally, and the data read from the memory cells of the at least one first physical program cell is the same as the first data string.
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| CN110910938A (en) * | 2018-09-17 | 2020-03-24 | 北京兆易创新科技股份有限公司 | Data correction method and device, storage equipment and storage medium |
| US11416416B2 (en) * | 2019-01-13 | 2022-08-16 | Ememory Technology Inc. | Random code generator with non-volatile memory |
| TWI738390B (en) | 2020-06-19 | 2021-09-01 | 群聯電子股份有限公司 | Data protection method, memory storage device and memory control circuit unit |
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