CN111724851B - Data protection method, memory storage device and memory control circuit unit - Google Patents
Data protection method, memory storage device and memory control circuit unit Download PDFInfo
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- CN111724851B CN111724851B CN202010596690.7A CN202010596690A CN111724851B CN 111724851 B CN111724851 B CN 111724851B CN 202010596690 A CN202010596690 A CN 202010596690A CN 111724851 B CN111724851 B CN 111724851B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
Abstract
The invention provides a data protection method, a memory storage device and a memory control circuit unit. The method comprises the following steps: setting a plurality of disk array labels corresponding to a plurality of word lines and a plurality of memory planes, wherein the disk array label corresponding to one word line connected with one memory plane is at least partially the same as the disk array label corresponding to another word line connected with another memory plane; receiving a write command and data corresponding to the write command from a host system; and sequentially writing the data into a plurality of word lines and a plurality of memory planes corresponding to the plurality of disk array tags.
Description
Technical Field
The present invention relates to a memory management technology, and in particular, to a data protection method, a memory storage device, and a memory control circuit unit.
Background
Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.
In the field of flash memory, 3D NAND flash memory in which more memory cells are packaged by a 3D stacking technology is currently developed. However, the 3D NAND flash memory may cause problems of physical failures such as word line short circuits due to various factors (e.g., leakage of memory cells, program failure, damage, etc.). Generally, in order to ensure the correctness of data, in some encoding/decoding technologies, data stored in multiple physical pages may be encoded into the same tag. Data belonging to the same tag can be protected from each other. When a certain data cannot be corrected by its own error correction code, the data corresponding to the same tag and stored in other physical pages can be used to assist the uncorrectable data to correct. For example, the Parity information (Parity) stored in the rewritable nonvolatile memory corresponding to the data to be corrected is used to correct the data.
However, the storage space of the rewritable nonvolatile memory module is limited, and as the capacity of the memory becomes larger, the data amount corresponding to the temporary storage tag may occupy too much capacity of the buffer memory. In particular, in a 3D NAND flash memory, the above situation is more remarkable. Therefore, how to maintain the reliability of the stored data while reducing the data amount of the stored tag is a subject of attention by those skilled in the art.
Disclosure of Invention
The invention provides a data protection method, a memory storage device and a memory control circuit unit, which can achieve good data protection capability under the condition that the capacity of a buffer memory is limited.
The embodiment of the invention provides a data protection method for a memory storage device. The memory storage device comprises a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity units, each entity unit comprises a plurality of entity programming units, and each entity programming unit corresponds to one of a plurality of word lines and one of a plurality of memory planes. The data protection method comprises the following steps: setting a plurality of disk array tags corresponding to the plurality of word lines and the plurality of memory planes, wherein the plurality of disk array tags corresponding to one of the plurality of memory planes connected by one of the plurality of word lines is at least partially identical to the plurality of disk array tags corresponding to another of the plurality of memory planes connected by another of the plurality of word lines. The plurality of disk array labels are used for representing the protection relationship between the data of the entity programming unit corresponding to one of the plurality of memory planes connected by one of the plurality of word lines and the data of the entity programming unit corresponding to another of the plurality of memory planes connected by another of the plurality of word lines.
In an exemplary embodiment of the invention, the plurality of memory planes include a first plane and a second plane, and the first plane connects a first word line and a second word line among the plurality of word lines, and the second plane connects the first word line and the second word line. Wherein the first word line is connected to the first plane and corresponds to a plurality of first disk array tags, and the second word line is connected to the second plane and corresponds to a plurality of second disk array tags. Wherein the first plurality of disk array tags is at least partially identical to the second plurality of disk array tags.
In an exemplary embodiment of the invention, the plurality of disk array tags corresponding to the different word lines connecting the same plurality of memory planes are different.
In an exemplary embodiment of the invention, the plurality of disk array tags corresponding to the plurality of memory planes with the same plurality of word lines connected to different memory planes are different.
In an exemplary embodiment of the invention, the step of setting the plurality of raid tags corresponding to the plurality of word lines and the plurality of memory planes includes: setting the disk array tags to correspond to the memory planes and the physical programming units.
In an exemplary embodiment of the invention, the method further includes: and generating parity information according to the data, and setting the disk array label corresponding to the parity information.
In an exemplary embodiment of the invention, the step of setting the raid label corresponding to the parity information includes: setting the RAID tags corresponding to the parity information to correspond to the plurality of memory planes and the plurality of physical programming units, in which the data for calculating the parity information is written.
An exemplary embodiment of the present invention provides a memory storage device. The memory storage device comprises a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for being coupled to a host system. The rewritable nonvolatile memory module comprises a plurality of entity units, each entity unit comprises a plurality of entity programming units, and each entity programming unit corresponds to one of a plurality of word lines and one of a plurality of memory planes. The memory control circuit unit is coupled to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for setting a plurality of disk array tags corresponding to the plurality of word lines and the plurality of memory planes, and one of the plurality of word lines is connected with one of the plurality of memory planes, and the plurality of disk array tags corresponding to another one of the plurality of memory planes is at least partially the same as the plurality of disk array tags corresponding to another one of the plurality of word lines. The memory control circuit unit is also used for receiving a write command and data corresponding to the write command from a host system. And the memory control circuit unit is further configured to sequentially write the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.
In an exemplary embodiment of the invention, the plurality of memory planes include a first plane and a second plane, and the first plane connects a first word line and a second word line among the plurality of word lines, and the second plane connects the first word line and the second word line. The memory control circuit unit is further configured to set the first word line to be connected to the first plane and correspond to a plurality of first disk array tags, and set the second word line to be connected to the second plane and correspond to a plurality of second disk array tags. The first plurality of disk array tags is at least partially identical to the second plurality of disk array tags.
In an exemplary embodiment of the invention, the plurality of disk array tags corresponding to the same plurality of memory planes to which the different word lines are connected are different.
In an exemplary embodiment of the invention, the plurality of disk array tags corresponding to the different memory planes connected by the same word lines are different.
In an exemplary embodiment of the invention, the operation of the memory control circuit unit for setting the plurality of disk array tags corresponding to the plurality of word lines and the plurality of memory planes includes: the memory control circuit unit is further configured to set the plurality of raid tags to correspond to the plurality of memory planes and the plurality of physical programming units.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to generate parity information according to the data, and set the raid label corresponding to the parity information.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to set the raid tag corresponding to the parity information to correspond to the plurality of memory planes and the plurality of physical programming units in which the data for calculating the parity information is written.
An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a memory storage device including a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity units, each entity unit comprises a plurality of entity programming units, and each entity programming unit corresponds to one of a plurality of word lines and one of a plurality of memory planes. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is used for being coupled to a host system. The memory interface is used for being coupled to the rewritable nonvolatile memory module. Memory management circuitry is coupled to the host interface and the memory interface. The memory management circuit is configured to set a plurality of disk array tags corresponding to the plurality of word lines and the plurality of memory planes, and one of the plurality of word lines is connected to one of the plurality of memory planes and the other of the plurality of word lines is connected to the other of the plurality of memory planes. The memory management circuit is also used for receiving a write command and data corresponding to the write command from a host system. And the memory management circuit is further configured to sequentially write the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.
In an exemplary embodiment of the invention, the plurality of memory planes include a first plane and a second plane, and the first plane connects a first word line and a second word line among the plurality of word lines, and the second plane connects the first word line and the second word line. The memory management circuit is further configured to set the first word line to connect to the first plane and correspond to a plurality of first disk array tags, and set the second word line to connect to the second plane and correspond to a plurality of second disk array tags. The first plurality of disk array tags is at least partially identical to the second plurality of disk array tags.
In an exemplary embodiment of the invention, the plurality of disk array tags corresponding to the same plurality of memory planes to which the different word lines are connected are different.
In an exemplary embodiment of the invention, the plurality of disk array tags corresponding to the different memory planes connected by the same word lines are different.
In an exemplary embodiment of the invention, the operation of the memory management circuit for setting the plurality of disk array tags corresponding to the plurality of word lines and the plurality of memory planes comprises: the memory management circuit is further configured to set the plurality of raid tags to correspond to the plurality of memory planes and the plurality of physical programming units.
In an exemplary embodiment of the invention, the memory management circuit is further configured to generate parity information according to the data, and set the raid tag corresponding to the parity information.
In an exemplary embodiment of the invention, the memory management circuit is further configured to set the raid tag corresponding to the parity information to correspond to the plurality of memory planes and the plurality of physical programming units in which the data for calculating the parity information is written.
Based on the above, the data protection method, the memory storage device and the memory control circuit unit provided in the embodiments of the present invention can set a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes by interleaving the disk array tags. Therefore, the data of the memory can be protected by using less disk array labels under the condition that the capacity of the buffer memory is limited, and the maximum protection effect is achieved.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment;
FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to another example embodiment;
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention;
FIG. 6 is a schematic block diagram of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;
FIG. 7 is a schematic block diagram of a parity information buffer according to an exemplary embodiment of the present invention;
fig. 8 is a flowchart illustrating a data protection method according to an example embodiment of the present invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module and a controller (also referred to as a control circuit unit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment. And FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all coupled to a system bus (system bus) 110.
In the exemplary embodiment, host system 11 is coupled to memory storage device 10 through data transfer interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is coupled to the I/O devices 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.
In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 are disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be coupled to the memory storage device 10 via a wired or wireless manner through the data transmission interface 114. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory Storage 204 can be a memory Storage based on various wireless Communication technologies, such as Near Field Communication (NFC) memory Storage, wireless facsimile (WiFi) memory Storage, Bluetooth (Bluetooth) memory Storage, or Bluetooth low energy (low) memory Storage (e.g., iBeacon). In addition, the motherboard 20 may also be coupled to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded memory devices 34 include embedded Multi-media card (eMMC) 341 and/or embedded Multi-Chip Package (eMCP) memory devices 342, which directly couple the memory module to the embedded memory devices on the substrate of the host system.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.
The connection interface unit 402 is used for coupling the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 402. In the exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Memory (Flash) interface standard, the CP interface standard, the CF interface standard, the Device interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.
The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.
The rewritable nonvolatile memory module 406 is coupled to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, memory cells on the same word line may constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.
In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, the physical erase unit is a physical block (block).
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.
In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In another exemplary embodiment, the control commands of the memory management circuit 502 can also be stored in a code pattern in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are coupled to the microcontroller. The cell management circuit is used to manage the cells or cell groups of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may include one or more codes or command codes respectively and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 504 is coupled to the memory management circuit 502. The memory management circuitry 502 may communicate with the host system 11 through a host interface 504. The host interface 504 is used for receiving and recognizing commands and data transmitted from the host system 11. For example, commands and data transmitted by the host system 11 may be transmitted to the memory management circuit 502 through the host interface 504. In addition, the memory management circuitry 502 may transfer data to the host system 11 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.
The memory interface 506 is coupled to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence indicating to write data, a read instruction sequence indicating to read data, an erase instruction sequence indicating to erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction codes or codes. For example, the read command sequence includes read identification codes, memory addresses, and other information.
In an exemplary embodiment, the memory control circuitry 404 further includes error checking and correction circuitry 508, buffer memory 510, and power management circuitry 512.
The error checking and correcting circuit 508 is coupled to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data is simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.
The buffer memory 510 is coupled to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. In the present embodiment, the buffer 510 includes a parity buffer for temporarily storing parity information. The power management circuit 512 is coupled to the memory management circuit 502 and is used to control the power of the memory storage device 10.
In an example embodiment, the rewritable nonvolatile memory module 406 of fig. 4 is also referred to as a flash (flash) memory module, and the memory control circuit unit 404 is also referred to as a flash memory controller for controlling the flash memory module. In an example embodiment, the memory management circuit 502 of FIG. 5 is also referred to as a flash memory management circuit.
In the exemplary embodiment, the error checking and correcting circuit 508 is implemented by a low density parity check code (LDPC). However, in another exemplary embodiment, the error checking and correcting circuit 508 may also be implemented with BCH codes, convolutional codes (convolutional codes), turbo codes (turbo codes), bit flipping (bit flipping), and other encoding/decoding algorithms.
Specifically, the memory management circuit 502 generates an error correction Frame (ECC Frame) according to the received data and the corresponding error checking and correcting code (hereinafter also referred to as error correction code) and writes the ECC Frame into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error checking and correcting circuit 508 verifies the correctness of the read data according to the error correction codes in the error correction code frame.
It should be noted that operations performed by the memory management circuit 502, the host interface 504 and the memory interface 506, the error checking and correcting circuit 508, the buffer memory 510 and the power management circuit 512 are described below, and may also be referred to as being performed by the memory control circuit unit 404.
In an example embodiment, the memory storage device 10 includes a plurality of rewritable nonvolatile memory modules 406, and the rewritable nonvolatile memory modules 406 include a plurality of Word Lines (WLs) and a plurality of memory planes (planes). Also, word lines connect multiple memory planes.
The devices of the rewritable nonvolatile memory module 406 are divided according to the memory planes in the memory die (die) of the rewritable nonvolatile memory module 406. Specifically, the rewritable nonvolatile memory module 406 can have 1 or more memory dies, each memory die has 1 or more memory planes, and each memory plane has a plurality of physical programming units. At the time of shipment, a manufacturer divides 1 or more memory planes into 1 device according to its needs. Thus, the manufacturer can manage the entire rewritable nonvolatile memory module 406 by device. The present invention does not limit the number of memory planes included in each device.
In the present exemplary embodiment, the rewritable nonvolatile memory module 406 is a Three dimensional (3D) multilevel Cell (TLC) NAND-type flash memory module (i.e., a flash memory module that can store 3 data bits in one memory Cell) or other memory modules with the same characteristics. However, the invention is not limited thereto, and the rewritable nonvolatile memory module 406 may also be a 3D Multi-Level Cell (MLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 2 bits of data in one memory Cell) or other memory modules with the same characteristics.
In the present exemplary embodiment, the rewritable nonvolatile memory module 406 includes a plurality of physical units and each physical unit includes a plurality of physical programming units, and each physical programming unit corresponds to a word line and a memory plane.
In an exemplary embodiment, when the memory management circuit 502 receives a write command and corresponding data from the host system 11, the memory management circuit 502 temporarily stores the data into the buffer memory 510 and arranges the data into sub-data strings according to the size of the physical programming unit. Thereafter, the memory management circuit 502 will program the sub-strings to the physical programming units respectively and sequentially.
On the other hand, the memory management circuit 502 generates parity information for protecting the sub-data strings according to the sub-data strings. In detail, the memory management circuit 502 may determine a disk array tag corresponding to each parity information according to a predetermined look-up table or a predetermined procedure, wherein the disk array tag is used to indicate which sub-data strings are operated by the parity information buffer to obtain each parity information. Accordingly, when the sub-data strings are programmed to the physical programming unit respectively and sequentially, the memory management circuit 502 determines that the sub-data strings are in the parity information buffer to perform a logic operation with the sub-data strings belonging to the same raid label according to the predetermined look-up table or the predetermined program to generate the parity information. In one embodiment, the logic operation for generating the parity information is an XOR operation, for example. Then, after a set of operation units (e.g., a set of physical units) is calculated, the memory management circuit 502 programs the parity information into the rewritable nonvolatile memory module 406. Specifically, the raid tags set by the memory management circuit 502 may correspond to the memory planes and the physical programming units, respectively, into which the sub data strings for calculating the parity information are written. Therefore, the memory management circuit 502 can record the disk array tag and the memory plane and the physical programming unit written by the sub data string corresponding to the disk array tag and used for calculating the parity information by using one disk array tag comparison table, and can record the disk array tag and the address where the parity information corresponding to the disk array tag is stored by using another comparison table.
Specifically, the memory management circuit 502 sets a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes. And the plurality of disk array tags corresponding to one memory plane connected by one word line are at least partially the same as the plurality of disk array tags corresponding to another memory plane connected by another word line. In this regard, one of the word lines of the rewritable nonvolatile memory module 406 is connected to one of the memory planes, and the other word line is connected to the other memory plane, which are different memory planes. And the disk array label is used for representing the protection relationship between the data of the plurality of entity programming units corresponding to one memory plane connected with one word line and the data of the plurality of entity programming units corresponding to another memory plane connected with another word line.
For example, the memory planes of the memory storage device 10 include a first plane and a second plane, and the first plane connects the first word line and the second word line, and the second plane also connects the first word line and the second word line. The first plane and the second plane respectively correspond to the physical programming units, wherein a part of the physical programming units are formed by a plurality of memory cells connected by a first word line, and a part of the physical programming units are formed by a plurality of memory cells connected by a second word line. In this example embodiment, the first word line connects the first plane and corresponds to a plurality of first disk array tags, and the second word line connects the second plane and corresponds to a plurality of second disk array tags. Wherein the first plurality of disk array tags is at least partially identical to the second plurality of disk array tags.
In an exemplary embodiment, the disk array tags corresponding to different word lines connected to the same memory plane are different. In an exemplary embodiment, the disk array tags corresponding to the same word line connecting different memory planes are different.
In more detail, each word line is connected to a plurality of physical programming units, and the memory plane includes a plurality of physical programming units. Herein, the memory management circuit 502 sets a plurality of disk array tags corresponding to a plurality of physical programming units of a plurality of memory planes. The disk array tag lookup table can record the disk array tags corresponding to the physical programming units of the memory planes.
FIG. 6 is a schematic block diagram of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. For convenience of illustration, the exemplary embodiment takes the physical units 6101-6102 in fig. 6 as an example of a set of operation units. The entities 6101-6102 include 24 entities, but the number of entities is not limited in the present invention.
FIG. 7 is a block diagram illustrating an exemplary embodiment of a parity information buffer. Referring to fig. 6 and 7, the storage unit 702 logically belonging to the parity buffer temporarily stores the parity information, and the parity information can be stored in the storage sub-units 720(0) -720 (23) included in the parity buffer, respectively. When the memory management circuit 502 receives the write command and the corresponding data from the host system 11, the memory management circuit 502 sequentially writes the data corresponding to the write command into the entity programming units 6101(0) -6101 (23) and 6102(0) -6102 (23). Here, the data is written into the physical programming units in sequence according to the physical programming units 6101(0), 6102(0), 6101(1), 6102(1), and the like. In the present embodiment, the physical programming units 6101(0) -6101 (23) and the physical programming units 6102(0) -6102 (23) correspond to different memory planes.
Take data written into the entity programming units 6101(12) as an example. When data is written into the entity programming unit 6101(12), the memory management circuit 502 determines the entity programming unit 6101(12) corresponding to the storage sub-unit 720(12) of the storage unit 702 according to a predetermined look-up table or a predetermined recipe, and performs a logic operation on the written data and the parity information stored in the storage sub-unit 720 (12). In the present exemplary embodiment, the parity information stored in the memory sub-units 720(12) is determined according to a predetermined look-up table or a predetermined program, and the entity programming unit corresponding to the entity programming unit 6101(12) in the memory sub-units 720(12) includes the entity programming unit 6102 (0). Then, the memory management circuit 502 calculates the parity information according to the data stored in the entity units 6101 to 6102 (i.e., a set of operation units), sets the disk array tags 0 to 23 corresponding to the parity information stored in the storage sub-units 720(0) to 720(23), and stores the calculated parity information in the rewritable nonvolatile memory module 406. In particular, the RAID tags 0-23 configured by the memory management circuit 502 can correspond to the physical programming units 6101(0) -6101 (23), 6102(0) -6102 (23), respectively, into which data for calculating parity information is written. In the exemplary embodiment, the memory management circuit 502 records the disk array tags 0 to 23 and the memory plane and entity programming unit 6101(0) -6101 (23), 6102(0) -6102 (23), in which the data corresponding to the disk array tags 0 to 23 for calculating the parity information is written, by using the disk array tag comparison table, and records the addresses where the parity information corresponding to the disk array tags 0 to 23 and the disk array tags 0 to 23 is stored by using another comparison table. In this regard, the corresponding relationship between the disk array tags 0-23 and the memory planes and physical program units generated by the present exemplary embodiment can be referred to as the following table 1.
The correspondence between the memory plane, the physical programming unit and the disk array tag generated in the present exemplary embodiment is shown in table 1 below. Referring to fig. 6 and table 1 below, in the present example embodiment, the memory plane of the memory storage device 10 includes a first plane P0 (i.e., a first memory plane) and a second plane P1 (i.e., a second memory plane), and the first plane P0 connects the first word line WL0 and the second word line WL1, and the second plane P1 also connects the first word line WL0 and the second word line WL 1. Herein, the entity unit 6101 included in the rewritable nonvolatile memory module 406 belongs to the first plane P0, and the entity unit 6102 belongs to the second plane P1. The first plane P0 and the second plane P1 respectively include solid programming units 6101(0) -6101 (23) and solid programming units 6102(0) -6102 (23), wherein the solid programming units 6101(0) -6101 (11) and 6102(0) -6102 (11) are composed of a plurality of memory cells connected to a first word line WL0, and the solid programming units 6101(12) -6101 (23) and 6102(12) -6102 (23) are composed of a plurality of memory cells connected to a second word line WL 1. Based on the above structure, the parity buffer configured for the 48 entity programming units 6101(0) -6101 (23), 6102(0) -6102 (23) of the entity units 6101-6102 of the present exemplary embodiment includes 24 storage sub-units.
TABLE 1
In the present example embodiment, the memory management circuit 502 sets the first word line WL0 connecting the first plane P0 to a plurality of disk array tags (also referred to as a first disk array tag). And memory management circuitry 502 sets second word line WL1 connecting second plane P1 to a plurality of disk array tags (also referred to as second disk array tag). In the exemplary embodiment, the memory management circuit 502 sets the physical programming units 6101(0) -6101 (11) included in the first word line WL0 connected to the first plane P0 to respectively correspond to the first disk array tags 0-11, and sets the physical programming units 6102(12) -6102 (23) included in the second word line WL1 connected to the second plane P1 to respectively correspond to the second disk array tags 0-11. On the other hand, the memory control circuit unit 404 sets the physical programming units 6102(0) -6102 (11) included in the first word line WL0 connected to the second plane P1 to correspond to the first disk array tags 12-23, respectively, and sets the physical programming units 6101(12) -6101 (23) included in the second word line WL1 connected to the first plane P0 to correspond to the second disk array tags 12-23, respectively. That is, in the same memory plane (the first plane P0 or the second plane P1) where the first word line WL0 and the second word line WL1 are connected, the disk array tags corresponding to the physical programming units do not have the same disk array tag.
Based on the data protection method provided by the invention, even if a single word line (for example, 2P1WL) connecting different physical planes fails partially or completely, the stored data can still be recovered according to the disk array label technology provided by the invention. On the other hand, even if two consecutive word lines (e.g., 1P2WL) connected by the same physical plane are partially or totally failed, the stored data can be recovered according to the disk array tag technology provided by the invention. Compared with the conventional method for protecting the failure of only one entity, the data protection method provided by the embodiment of the invention can simultaneously protect the two conditions. In addition, taking the physical units 6101-6102 of the embodiment of the invention respectively include 24 physical program units as an example, if the conventional parity recovery technique is to protect the failure of two entities, i.e., 2P1WL and 1P2WL, at the same time, 48 raid tags corresponding to 48 physical program units in the physical units 6101-6102 and corresponding temporary storage spaces (e.g., the storage sub-units 710(0) -710 (47) included in the storage unit 701 shown in fig. 7) are required to store temporary storage data. This is because only one physical programming cell in a set of physical cells corresponding to a set of parity information buffers can fail. Compared with the prior art, the data protection method provided by the invention can simultaneously protect two physical failure conditions of 2P1WL and 1P2WL by only using half of the disk array tags and the corresponding temporary storage space, thereby saving the temporary storage space. It should be noted that, those skilled in the art should know how to recover the stored data by using the parity information, and therefore, the description thereof is omitted here.
Fig. 8 is a flowchart illustrating a data protection method according to an example embodiment of the present invention. In step S802, a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes are set. In step S804, a write command and data corresponding to the write command are received from the host system. In step S806, the data is sequentially written into the word lines and the memory planes corresponding to the disk array tags. In step S808, parity information is generated according to the data, and the raid label corresponding to the parity information is set.
It is to be noted that, the steps in fig. 8 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 8 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.
In summary, the data protection method, the memory storage device and the memory control circuit unit provided by the embodiments of the invention can set a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes. Therefore, the data of the memory can be protected by using less disk array labels under the condition that the capacity of the buffer memory is limited, and the maximum protection effect is achieved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (18)
1. A data protection method is used for a memory storage device, the memory storage device comprises a rewritable nonvolatile memory module, the rewritable nonvolatile memory module comprises a plurality of entity units, each entity unit comprises a plurality of entity programming units, each entity programming unit corresponds to one of a plurality of word lines and one of a plurality of memory planes, and the data protection method comprises the following steps:
setting a plurality of disk array tags corresponding to the plurality of word lines and the plurality of memory planes,
and wherein the plurality of disk array tags corresponding to one of the plurality of memory planes connected by one of the plurality of word lines are at least partially identical to the plurality of disk array tags corresponding to another of the plurality of memory planes connected by another of the plurality of word lines;
receiving a write command and data corresponding to the write command from a host system; and
sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags,
and generating parity information according to the data, and setting the disk array label corresponding to the parity information.
2. The data protection method of claim 1, wherein the plurality of memory planes include a first plane and a second plane, and the first plane connects a first word line and a second word line among the plurality of word lines, the second plane connects the first word line and the second word line,
wherein the first word line connects the first plane and corresponds to a plurality of first disk array tags, and the second word line connects the second plane and corresponds to a plurality of second disk array tags,
wherein the first plurality of disk array tags is at least partially identical to the second plurality of disk array tags.
3. The data protection method of claim 1, wherein the plurality of disk array tags corresponding to different ones of the plurality of word lines connecting the same one of the plurality of memory planes are different.
4. The data protection method of claim 1, wherein the plurality of disk array tags corresponding to the same plurality of word lines connecting different ones of the plurality of memory planes are different.
5. The data protection method of claim 1, wherein setting the plurality of disk array tags corresponding to the plurality of word lines and the plurality of memory planes comprises:
setting the disk array tags to correspond to the memory planes and the physical programming units.
6. The data protection method according to claim 1, wherein the step of setting the raid label corresponding to the parity information includes:
setting the RAID tags corresponding to the parity information to correspond to the plurality of memory planes and the plurality of physical programming units, in which the data for calculating the parity information is written.
7. A memory storage device, comprising:
a connection interface unit for coupling to a host system;
the rewritable nonvolatile memory module comprises a plurality of entity units, wherein each entity unit comprises a plurality of entity programming units, and each entity programming unit corresponds to one of a plurality of word lines and one of a plurality of memory planes; and
a memory control circuit unit coupled to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is used for setting a plurality of disk array tags corresponding to the plurality of word lines and the plurality of memory planes,
and wherein the plurality of disk array tags corresponding to one of the plurality of memory planes to which one of the plurality of word lines is connected are at least partially identical to the plurality of disk array tags corresponding to another of the plurality of memory planes to which another of the plurality of word lines is connected,
the memory control circuit unit is also used for receiving a write command and data corresponding to the write command from a host system, and
the memory control circuit unit is further configured to sequentially write the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags,
the memory control circuit unit is further configured to generate parity information according to the data, and set the raid label corresponding to the parity information.
8. The memory storage device of claim 7, wherein the plurality of memory planes includes a first plane and a second plane, and the first plane connects a first word line and a second word line among the plurality of word lines, the second plane connects the first word line and the second word line,
wherein the memory control circuit unit is further configured to set the first word line to connect to the first plane and correspond to a plurality of first disk array tags, and set the second word line to connect to the second plane and correspond to a plurality of second disk array tags,
wherein the first plurality of disk array tags is at least partially identical to the second plurality of disk array tags.
9. The memory storage device of claim 7, wherein the plurality of disk array tags corresponding to the same plurality of memory planes to which different ones of the plurality of word lines are connected are different.
10. The memory storage device of claim 7, wherein the plurality of disk array tags corresponding to different ones of the plurality of memory planes connected by the same one of the plurality of word lines are different.
11. The memory storage device of claim 7, wherein the operation of the memory control circuitry unit to set the plurality of disk array tags corresponding to the plurality of word lines and the plurality of memory planes comprises:
the memory control circuit unit is further configured to set the plurality of raid tags to correspond to the plurality of memory planes and the plurality of physical programming units.
12. The memory storage device of claim 7, wherein the memory control circuit unit is further configured to set the raid tag corresponding to the parity information to correspond to the plurality of memory planes and the plurality of physical program units into which the data for calculating the parity information is written.
13. A memory control circuit unit for controlling a memory storage device including a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units, each of the plurality of physical units includes a plurality of physical programming units, each of the physical programming units corresponds to one of a plurality of word lines and one of a plurality of memory planes, and the memory control circuit unit includes:
a host interface for coupling to a host system;
a memory interface to couple to the rewritable non-volatile memory module; and
memory management circuitry coupled to the host interface and the memory interface,
wherein the memory management circuitry is to set a plurality of disk array tags corresponding to the plurality of word lines and the plurality of memory planes,
and wherein the plurality of disk array tags corresponding to one of the plurality of memory planes connected by one of the plurality of word lines is at least partially identical to the plurality of disk array tags corresponding to another of the plurality of memory planes connected by another of the plurality of word lines,
the memory management circuit is further configured to receive a write command and data corresponding to the write command from a host system, and
the memory management circuitry is further configured to sequentially write the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags,
the memory management circuit is further configured to generate parity information according to the data, and set the raid label corresponding to the parity information.
14. The memory control circuit unit of claim 13, wherein the plurality of memory planes include a first plane and a second plane, and the first plane connects a first word line and a second word line among the plurality of word lines, the second plane connects the first word line and the second word line,
wherein the memory management circuitry is further to set the first word line to connect to the first plane and correspond to a first plurality of disk array tags, and to set the second word line to connect to the second plane and correspond to a second plurality of disk array tags,
wherein the first plurality of disk array tags is at least partially identical to the second plurality of disk array tags.
15. The memory control circuitry unit of claim 13, wherein the plurality of disk array tags corresponding to the same plurality of memory planes to which different ones of the plurality of word lines are connected are different.
16. The memory control circuit unit of claim 13, wherein the plurality of disk array tags corresponding to different ones of the plurality of memory planes connected to the same one of the plurality of word lines are different.
17. The memory control circuitry unit of claim 13, wherein the operation of the memory management circuitry to set the plurality of disk array tags corresponding to the plurality of word lines and the plurality of memory planes comprises:
the memory management circuit is further configured to set the plurality of raid tags to correspond to the plurality of memory planes and the plurality of physical programming units.
18. The memory control circuit unit of claim 13, wherein the memory management circuit is further configured to set the raid tag corresponding to the parity information to correspond to the plurality of memory planes and the plurality of physical program units into which the data for calculating the parity information is written.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6735765B1 (en) * | 1999-12-07 | 2004-05-11 | Storage Technology Corporation | Sharing data between operating systems |
| CN105513635A (en) * | 2014-09-23 | 2016-04-20 | 群联电子股份有限公司 | Programming method, memory storage device, and memory control circuit unit |
| CN107958687A (en) * | 2016-10-18 | 2018-04-24 | 群联电子股份有限公司 | Memory programming method, memorizer control circuit unit and its storage device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004265162A (en) * | 2003-03-03 | 2004-09-24 | Renesas Technology Corp | Storage device and address management method |
| US8291305B2 (en) * | 2008-09-05 | 2012-10-16 | Freescale Semiconductor, Inc. | Error detection schemes for a cache in a data processing system |
| US9286160B2 (en) * | 2014-02-07 | 2016-03-15 | Stmicroelectronics S.R.L. | System and method for phase change memory with erase flag cells |
| US9348695B2 (en) * | 2014-05-21 | 2016-05-24 | Sandisk Technologies Inc. | System and method of storing redundancy data |
| TWI640997B (en) * | 2017-12-27 | 2018-11-11 | 群聯電子股份有限公司 | Data protecting method, memory control circuit unit and memory storage apparatus |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6735765B1 (en) * | 1999-12-07 | 2004-05-11 | Storage Technology Corporation | Sharing data between operating systems |
| CN105513635A (en) * | 2014-09-23 | 2016-04-20 | 群联电子股份有限公司 | Programming method, memory storage device, and memory control circuit unit |
| CN107958687A (en) * | 2016-10-18 | 2018-04-24 | 群联电子股份有限公司 | Memory programming method, memorizer control circuit unit and its storage device |
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