CN113299329A

CN113299329A - Storage device, control method thereof and control circuit unit

Info

Publication number: CN113299329A
Application number: CN202110648887.5A
Authority: CN
Inventors: 不公告发明人
Original assignee: Hosin Global Electronics Co Ltd
Current assignee: Hosin Global Electronics Co Ltd
Priority date: 2021-06-10
Filing date: 2021-06-10
Publication date: 2021-08-24

Abstract

The application discloses a storage device, a control method thereof and a control circuit unit. The first storage data of the storage device comprises user data and a first disk array error correction code and/or an error check code, and the first storage data is generated by the unit error correction code string code according to the user data; the control circuit unit is also used for defining a virtual programming unit, and storing second storage data formed by the first storage data of the plurality of entity programming units, wherein the second storage data comprises entity programming data and a second disk array error correction code and/or an error check code; according to the entity programming data in the virtual programming unit, the control circuit unit generates the second disk array error correction code and/or the error check code by using the cross-cell error correction code and stores the second disk array error correction code and/or the error check code in the entity programming unit. The control unit circuit provided by the invention can improve the correction capability of the error correcting code of the storage device and improve the space utilization efficiency of the storage device.

Description

Storage device, control method thereof and control circuit unit

Technical Field

The present application relates to the field of storage technologies, and in particular, to a storage device, a control method thereof, and a control circuit unit.

Background

The NAND flash has the defect block generation in production and use, so ECC (error Correcting code) is introduced, and if a memory block generates errors and can be corrected by the ECC, the block does not count the defect block; but if the ECC is not corrected, the block can not be used any more and can only be marked as a bad block. Therefore, the error correction capability of ECC becomes an important factor for improving the utilization efficiency of the storage space of the storage device.

Disclosure of Invention

In view of this, the present application provides a memory device, a control method thereof, and a control circuit unit, which can improve the error correction capability of the memory device ECC by the control method of the memory device provided by the present application, and specifically includes:

a control circuit unit of a storage device comprises a rewritable nonvolatile storage module, wherein the rewritable nonvolatile storage module comprises a plurality of entity erasing units, the entity erasing units respectively comprise a plurality of entity programming units, first storage data are stored in the entity programming units, the first storage data comprise user data and first disk array error correction codes and/or error check codes, and the first disk array error correction codes and/or the error check codes are generated by an error correction code string code of the unit according to the user data;

the control circuit unit is further used for defining a virtual programming unit, the virtual programming unit stores second storage data formed by the first storage data of the plurality of entity programming units, and the second storage data comprises entity programming data and second disk array error correction codes and/or error check codes; according to the entity programming data in the virtual programming unit, the control circuit unit generates the second disk array error correction code and/or the error check code by using the cross-cell error correction code and stores the second disk array error correction code and/or the error check code in the entity programming unit.

Furthermore, the ECC string of this unit is an ECC string containing BCH.

Still further, the error correction code string code including the BCH includes a BCH-CRC string code.

Further, the present cell error correction code string code is an error correction code string code including LDPC.

Still further, the LDPC-containing error correction code string code includes: LDPC-BCH string codes, LDPC-CRC string codes, LDPC-BCH-BCH string codes, LDPC-BCH-CRC string codes.

Further, the cross-cell error correction code is at least one of an XOR, Reed-Solomon, BCH, CRC, convolutional code, and Turbo.

Furthermore, the cross-page error correcting code is Reed-Solomon-XOR string code, BCH-XOR string code or BCH-Reed-Solomon string code.

A method of controlling a storage device, the method comprising:

providing a storage device, wherein the storage device comprises a rewritable nonvolatile storage module, the rewritable nonvolatile storage module comprises a plurality of entity erasing units, the entity erasing units respectively comprise a plurality of entity programming units, the entity programming units store first storage data, the first storage data comprises user data and first disk array error correction codes and/or error check codes, and the first disk array error correction codes and/or error check codes are generated by a unit error correction code string code according to the user data;

defining a virtual programming unit, wherein the virtual programming unit stores second storage data formed by the first storage data of the plurality of entity programming units, and the second storage data comprises entity programming data and a second disk array error correction code and/or an error check code;

and generating the second disk array error correction code and/or the error check code according to the entity programming data in the virtual programming unit by using the cross-cell error correction code and storing the second disk array error correction code and/or the error check code in the entity programming unit.

Further, the element error correction code string code includes a BCH-CRC string code.

Further, the present cell ecc string code includes: LDPC-BCH string codes, LDPC-CRC string codes, LDPC-BCH-BCH string codes, LDPC-BCH-CRC string codes.

Further, the cross-cell error correction code is at least one of XOR, Reed-Solomon, BCH and CRC.

A memory device comprising the control circuit unit of any one of the above, or operating the control method of any one of the above.

According to the data correction method and the data correction device, different error correction code strings of the unit and cross-unit error correction codes are used for data correction of the storage device in the entity programming unit and the virtual programming unit, so that the error correction capability of the storage device can be improved, the space use efficiency of the storage device is improved, and the service life of the storage device is prolonged.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, memory storage device, and I/O device according to another embodiment of the present invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another embodiment of the invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an embodiment of the present invention;

FIG. 5 is a schematic block diagram of a memory control circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a multi-frame code shown in accordance with an embodiment of the present invention;

FIG. 7 is a first physical program cell encoding diagram according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating a second physical program cell encoding according to an embodiment of the present invention;

FIG. 9 is a diagram illustrating a third physical program cell encoding according to an embodiment of the present invention;

FIG. 10 is a diagram illustrating a fourth physical program cell encoding according to an embodiment of the present invention;

FIG. 11 is a diagram illustrating a fifth physical program cell encoding according to an embodiment of the present invention;

FIG. 12 is a diagram illustrating a sixth physical program cell encoding according to an embodiment of the present invention;

fig. 13 is a flowchart illustrating a control method of a memory device according to an embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.

Generally, a memory device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, the storage device is used with a host system so that the host system can write data to or read data from the storage device.

FIG. 1 is a diagram illustrating a host system, a storage device, and an input/output (I/O) device according to an embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a storage device and an I/O device according to another exemplary embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory device 10 through the data transmission interface 114. For example, host system 11 may store data to storage device 10 or read data from storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory device 10 via a wired or wireless connection via the data transmission interface 114. The storage device 10 may be, for example, a personal disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless storage device 204. The wireless storage device 204 may be a storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) storage device, wireless facsimile (WIFI) storage device, Bluetooth (Bluetooth) storage device, or Bluetooth low energy (iBeacon) storage device. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 can access the wireless storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system is any system that can substantially cooperate with a storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the storage device 30 may be various non-volatile storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded Multi-Media Card (eMMC) 341 and/or embedded Multi-Chip Package (eMCP) memory device 342, which electrically connects the memory module directly to the embedded memory device on the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used to electrically connect the memory device 10 to the host system 11. In the present exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed Specification-I (UHS-I) interface standard, the Ultra High Speed Specification-II (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (Flash) interface standard, the CP interface standard, the CF interface standard, the Device Electronic interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404. The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing data writing, reading and erasing operations in the rewritable nonvolatile memory module 406 according to commands of the host system 11. The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.

In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 constitute a plurality of physical programming cells, and the physical programming cells constitute a plurality of physical erasing cells. Specifically, the memory cells on the same word line constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.

In this example embodiment, the physical program cell may be a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If a physical program cell is a physical page, the physical program cell typically includes a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area stores system data, such as management data, e.g., error correction codes. In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to write, read, and erase data when the memory device 10 is in operation. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.

In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory device 10 is in operation, the control commands are executed by the microprocessor unit to perform data writing, reading, and erasing operations.

In another exemplary embodiment, the control instructions of the memory management circuit 502 may also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may include one or more program codes or command codes respectively and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is electrically connected to the memory management circuit 502 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transfer standard.

The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 510, an error checking and correcting circuit 508 and a power management circuit 512. The buffer memory 510 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory device 10. The error checking and correcting circuit 508 is electrically connected to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding error correcting code and/or error detecting code into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data is simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.

In the exemplary embodiment, the memory control circuit unit 404 may perform single-frame (single-frame) coding on data stored in the same physical program unit, or perform multi-frame (multi-frame) coding on data stored in a plurality of physical program units. Depending on the encoding algorithm used, the memory control circuitry 404 may encode the data to be protected to generate corresponding error correction codes and/or error check codes. For convenience of explanation, the error correction code and/or the error check code generated through encoding will be collectively referred to as encoded data hereinafter.

Fig. 6 is a diagram illustrating multi-frame coding according to an exemplary embodiment of the present invention.

Referring to fig. 6, taking the first storage data stored in the encoded entity programming units 810(0) to 810(E) as an example, the first storage data may include user data and a first disk array error correction code and/or an error check code, at least a portion of the data stored in each of the entity programming units 810(0) to 810(E) may be regarded as a frame, and when single-frame encoding is adopted, the error correction code string code of this unit may be used to generate the corresponding first disk array error correction code and/or error check code 801(r) by encoding the user data 801(1) to 801(r-1) of the entity programming unit 810(0), the first raid error correction code and/or the error checking code 801(r) may be stored in the physical programming unit 810(0) or other physical programming units of the rewritable nonvolatile memory module. In the multi-frame coding, data in the physical programming units 810(0) to 810(E) are coded according to the position of each bit (or byte). For example, the bits b11, b21, …, bp1 at position 801(1) are encoded as the bit bo1 in the first raid error correction code and/or ecc, and at this time, the bits b11, b21, …, bp1 and bit bo1 at position 801(1) form a virtual program unit 811; bits b12, b22, … and bp2 at position 801(2) are encoded as bit bo2 in the error correction code and/or the error check code of the first raid using the cross-cell error correction code, and at this time, bits b12, b22, …, bp2 and bit bo2 at position 801(2) form a second virtual program cell 812; by analogy, the bits b1r, b2r, …, bpr at the position 801(r) are encoded as bits bor in the first raid error correction code and/or the error check code using the cross-cell error correction code, and form the r-th virtual program unit 81 r. In each of the above virtual program units, the second storage data comprising the first storage data of the plurality of physical program units may be stored, and the second storage data may comprise the physical program data b11, b21, …, bp1 and the second disk array error correction code and/or error check code bo1 from the plurality of physical program unit locations 801 (1). It should be noted that each of the above virtual program cells may be formed by physical program cells from different memory blocks of different dies, and the formation of the virtual program cells does not limit the locations of the physical program cells.

In addition, the unit error correction code string may be an error correction code string including BCH or an error correction code string including LDPC, and the unit error correction code string is used in a cascade of a plurality of error correction codes to improve the error correction capability of the error correction codes. When the present-unit error correction code string code including the error correction code string code of BCH is employed, a BCH-CRC string code or a BCH-hamming string code may be employed. When an error correction code string code including LDPC is employed, it is possible to employ: LDPC-BCH string codes, LDPC-Hamming string codes, LDPC-CRC string codes, LDPC-BCH-BCH string codes, LDPC-BCH-CRC string codes, and the like.

Referring to fig. 7, when the error correction code string of the present embodiment adopts BCH-CRC string, the user data 801(1) -801 (r-1) of the present entity programming unit is used as the data to be encoded to determine CRC check bits, generate CRC codes, and then perform BCH encoding on the CRC codes by using BCH encoding, so as to obtain BCH codes, and obtain the first disk array error correction codes and/or error check codes. Correspondingly, in the decoding process, the BCH code is decoded to obtain BCH decoding data, then CRC decoding is carried out on the BCH decoding data to obtain CRC decoding data and a CRC checking result, the CRC checking result is used for judging whether error data exist in the BCH decoding data, whether the error amount of the data in the data to be decoded by the BCH overflows the error correction capability of the BCH code is detected and judged in time through CRC checking, and the reliability of output data is ensured. Referring to fig. 8, when the error correction code string code of the present cell adopts an LDPC-BCH string code, an LDPC check bit may be determined according to user data 801(1) to 801(r-1) of the present entity programming cell as data to be encoded, so as to generate an LDPC code, where the LDPC code includes the user data and the LDPC check bit, and then a BCH check bit is determined according to the LDPC code, so as to generate a BCH code, where the BCH code includes the LDPC code and the BCH check bit. Or referring to fig. 9, when the error correction code string code of the unit adopts the LDPC-CRC string code, the user data of the entity programming unit may be used as the data to be encoded to determine the CRC check bits, so as to generate the CRC code, where the CRC code includes the user data and the CRC check bits, and then the low-density parity check LDPC check bits are determined according to the CRC code, so as to generate the LDPC code, where the LDPC code includes the CRC code and the LDPC check bits.

As an optional implementation manner, the unit error correction code string may also adopt a triple string to improve the error correction capability of the error correction code. For example, referring to fig. 10, when an LDPC-BCH string code is used, a first BCH check bit may be determined according to user data of the present physical programming unit as data to be encoded, a first BCH code is generated, where the first BCH code includes the user data and the first BCH check bit, a second BCH check bit is then determined according to the first BCH code, a second BCH code is generated, where the second BCH code includes the first BCH code and the second BCH check bit, and a low density parity check LDPC check bit is finally determined according to the second BCH code, and an LDPC code is generated, where the LDPC code includes the second BCH code and the LDPC check bit. Referring to fig. 11, when the error correction code string code of the unit adopts an LDPC-BCH-CRC string code, an LDPC check bit may be determined according to user data of the entity programming unit as data to be encoded, so as to generate an LDPC code, where the LDPC code includes the user data and the LDPC check bit, then a cyclic redundancy check BCH check is determined according to the LDPC code, so as to generate a BCH code, where the BCH code includes the LDPC code and the BCH check bit, and finally a low density parity check CRC check is determined according to the BCH code, so as to generate a CRC code, and the CRC code includes the BCH code and a CRC check bit; alternatively, referring to fig. 12, a BCH check bit may be determined according to user data of the entity programming unit as data to be encoded, a BCH code is generated, the BCH code includes the user data and the BCH check bit, then a cyclic redundancy check CRC check bit is determined according to the BCH code, a CRC code is generated, the CRC code includes the BCH code and the CRC check bit, and finally a low density parity check LDPC check bit is determined according to the CRC code, and an LDPC code is generated, the LDPC code includes a CRC code and an LDPC check bit. By using the multiple error correcting code string code, triple coding of user data can be realized, the error correcting capability of the error correcting code is improved, and the error rate during data storage is reduced.

In this embodiment, the cross-cell error correction code may be at least one of XOR, Reed-Solomon, BCH, and CRC, or a double error correction code string code such as Reed-Solomon-XOR string code or BCH-XOR string code. When the cross-cell error correction code uses XOR coding, after the writing is completed, the cross-cell error correction codes are XOR-coded according to the entity programming data of each virtual programming cell 811, respectively, to generate XOR codes as the second disk array error correction codes. When the cross-cell error correction code uses Reed-Solomon coding, after the writing of the entity programming units 810(0) to 810(E) is finished, the cross-cell error correction code respectively carries out the Reed-Solomon coding according to the entity programming data of each virtual programming unit 811 and forms a Reed-Solomon check bit, and generates a Reed-Solomon code as a second disk array error correction code. When the cross-cell error correction code uses BCH encoding, after the writing is completed, the cross-cell error correction codes are respectively BCH encoded according to the entity programming data of each virtual programming cell 811 and form BCH check bits, and a BCH code is generated as a second disk array error correction code. When the cross-cell error correction code uses CRC coding, after the writing is completed, the cross-cell error correction code performs CRC coding according to the entity programming data of each virtual programming cell 811, and forms CRC check bits, thereby generating a CRC code as a second disk array error correction code.

As an optional implementation mode, a double error correction code string code such as a cross-cell error correction code Reed-Solomon-XOR string code, a BCH-Reed-Solomon string code or a BCH-XOR string code is used for improving the error correction capability of the error correction code. When the cross-cell error correcting code adopts a Reed-Solomon-XOR string code, the cross-cell error correcting code respectively carries out XOR coding according to the entity programming data of each virtual programming cell 811 to generate an XOR code, the XOR code comprises the data after the entity programming data is coded, then a Reed-Solomon check bit is determined according to the XOR code to generate the Reed-Solomon code, the Reed-Solomon code comprises the XOR code and the Reed-Solomon check bit, and finally the Reed-Solomon code is generated to be used as a second disk array error correcting code and/or an error checking code. Referring to fig. 11, when the cross-cell error correction code adopts a BCH-Reed-Solomon string code, the cross-cell error correction code performs BCH encoding according to the entity programming data of each virtual programming cell 811, respectively, to determine BCH check bits, generates a BCH code, the BCH code includes the entity programming data and the BCH check bits, then determines Reed-Solomon check bits according to the BCH code, generates a Reed-Solomon code, the Reed-Solomon code includes the BCH code and the Reed-Solomon check bits, and finally generates the Reed-Solomon code as a second disk array error correction code and/or an error check code. When the cross-cell error correcting code adopts a BCH-XOR string code, the cross-cell error correcting code respectively performs XOR coding according to the entity programming data of each virtual programming cell 811 to generate an XOR code, the XOR code comprises the data after the entity programming data is coded, then a BCH check bit is determined according to the XOR code to generate a BCH code, the BCH code comprises the XOR code and the BCH check bit, and finally the BCH code is generated to serve as a second disk array error correcting code and/or an error checking code.

It should be apparent that, the above unit error correction code string and the above cross-unit error correction code string may be respectively combined for use, and any one of the above unit error correction code string and any one of the above cross-unit error correction code string may be combined for use in a certain storage device, so as to achieve better error correction, which is not limited in this respect.

After encoding the data is completed, the data read from the physical programming units 810(0) -810 (E) may be decoded according to the first and second disk array error correction codes and/or error check codes (hereinafter referred to as encoded data 820) to attempt to correct errors that may be present in the read data.

In addition, in another exemplary embodiment of fig. 6, the data for generating the encoded data 820 may also include redundant bits (redundancy bits) corresponding to data bits (data bits) in the data stored in the entity programming units 810(0) -810 (E). Take the data stored in the entity programming unit 810(0) as an example, wherein the redundant bits are generated by performing single frame encoding on the data bits stored in the entity programming unit 810(0), for example. In the present exemplary embodiment, it is assumed that when reading the data in the physical programming unit 810(0), the data read from the physical programming unit 810(0) can be decoded by using the redundancy bits (e.g., the single frame coded data) in the physical programming unit 810(0) for error detection and correction. However, when the decoding using the redundancy bits in the physical programming unit 810(0) fails (e.g., the number of bits error of the data stored in the decoded physical programming unit 810(0) is greater than a threshold), a Retry-Read mechanism may be used to attempt to Read the correct data from the physical programming unit 810 (0). When the correct data cannot be Read from the physical programming units 810(0) by the Retry-Read mechanism, the encoded data 820 and the data of the physical programming units 810(1) to 810(E) can be Read, and the decoding is performed according to the encoded data 820 and the data of the physical programming units 810(1) to 810(E) to try to correct the errors in the data stored in the physical programming units 810 (0). That is, in the exemplary embodiment, when decoding using the encoded data generated by the single-frame encoding fails and reading using the re-Read (Retry-Read) mechanism fails, the encoded data generated by the multi-frame encoding is decoded instead.

An embodiment of the present invention further provides a method for controlling a storage device, and as shown in fig. 13, the method for controlling a storage device may include the following steps:

step 1401: providing a storage device, wherein the storage device comprises a rewritable nonvolatile storage module, the rewritable nonvolatile storage module comprises a plurality of entity erasing units, the entity erasing units respectively comprise a plurality of entity programming units, the entity programming units store first storage data, the storage data comprises user data and first disk array error correction codes and/or error check codes, and the first disk array error correction codes and/or error check codes are generated by the unit error correction code string codes according to the user data.

Step 1402: defining a virtual programming unit, wherein the virtual programming unit stores second storage data formed by the first storage data of the plurality of entity programming units, and the second storage data comprises entity programming data and a second disk array error correction code and/or an error check code.

Step 1403: and generating the second disk array error correction code and/or the error check code according to the entity programming data in the virtual programming unit by using the cross-cell error correction code.

Step 1404: and storing the second disk array error correction code and/or the error check code in the physical programming unit.

The control method of the storage device provided in this embodiment may be implemented by using the control circuit unit in the above embodiment, and for the specific description of the relevant steps, reference may be made to the above embodiment, which is not described herein again, but it is to be noted that the method may also be implemented by using computer software, and the like, which is not limited herein.

The present application further provides a storage device, where the storage device includes the control circuit unit in the foregoing embodiment, or the control method in the foregoing embodiment may be executed, so as to achieve improvement of error correction capability of an error correction code, and for related descriptions, reference may be made to the foregoing embodiments, which are not described herein again.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and any person skilled in the art can easily use the equivalent structure or equivalent flow transformation, such as the combination of technical features between the embodiments or the direct or indirect application to other related technical fields without departing from the spirit and scope of the present invention, and all such changes are encompassed in the present application.

Claims

1. The control circuit unit of the storage device is characterized in that the storage device comprises a rewritable nonvolatile storage module, the rewritable nonvolatile storage module comprises a plurality of entity erasing units, the entity erasing units respectively comprise a plurality of entity programming units, the entity programming units store first storage data, the first storage data comprises user data and first disk array error correction codes and/or error check codes, and the first disk array error correction codes and/or the error check codes are generated by the error correction code string code of the unit according to the user data;

2. The control circuit unit according to claim 1, wherein the local-unit error-correcting code string is an error-correcting code string including BCH.

3. The control circuit unit according to claim 2, wherein the error correction code string code including the BCH includes a BCH-CRC string code.

4. The control circuit unit according to claim 1, wherein the present-unit error correction code string code is an LDPC-containing error correction code string code.

5. The control circuit unit of the memory device according to claim 4, wherein the error correction code string code including LDPC comprises: LDPC-BCH string codes, LDPC-CRC string codes, LDPC-BCH-BCH string codes, LDPC-BCH-CRC string codes.

6. The control circuit unit of claim 1, wherein the cross-cell error correction code is at least one of an XOR, Reed-Solomon, BCH, CRC, convolutional code, and Turbo error correction code.

7. The control circuit unit of the memory device according to claim 6, wherein the page crossing error correction code is a Reed-Solomon-XOR string code, an XOR-BCH string code, a BCH-Reed-Solomon string code.

8. A method of controlling a storage device, the method comprising:

9. The control method according to claim 8, wherein the present-unit error correction code string code includes a BCH-CRC string code.

10. The control method according to claim 8, wherein the present cell error correction code string code includes: LDPC-BCH string codes, LDPC-CRC string codes, LDPC-BCH-BCH string codes, LDPC-BCH-CRC string codes.

11. The control method according to claim 8, wherein the cross-cell error correction code is at least one of an XOR, a Reed-Solomon, a BCH, and a CRC.

12. A memory device comprising the control circuit unit according to any one of claims 1 to 7, or operating the control method according to any one of claims 8 to 11.