CN114077515A - Data writing method, memory control circuit unit and memory storage device - Google Patents

Data writing method, memory control circuit unit and memory storage device Download PDF

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Publication number
CN114077515A
CN114077515A CN202010794976.6A CN202010794976A CN114077515A CN 114077515 A CN114077515 A CN 114077515A CN 202010794976 A CN202010794976 A CN 202010794976A CN 114077515 A CN114077515 A CN 114077515A
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Prior art keywords
error correction
array
data
physical
unit
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Chinese (zh)
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陈秉正
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Phison Electronics Corp
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Phison Electronics Corp
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Priority to CN202010794976.6A priority Critical patent/CN114077515A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution

Abstract

The invention provides a data writing method, a memory control circuit unit and a memory storage device. The method comprises the following steps: receiving first data and second data from a host system; generating a first array error correction code according to the first data, and generating a second array error correction code according to the second data; programming a first group including the first array of error correction codes into a first chip enable group using a first programming mode; and programming a second group including the second array of error correction codes into the second chip enable group using a second programming mode.

Description

Data writing method, memory control circuit unit and memory storage device
Technical Field
The present invention relates to a data writing method, and more particularly, to a data writing method for a rewritable nonvolatile memory module, and a memory control circuit unit and a memory storage device using the same.
Background
Digital cameras, cell phones, and MP3 have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small size, fast read/write speed, and no mechanical structure, it is very suitable for being built in various portable multimedia devices as the storage medium.
Generally, to ensure the security of data, data stored in a rewritable nonvolatile memory module is encoded to generate an error correction code. If an error occurs in the data, the error correction code can be used to modify the error. In one approach, the rewritable non-volatile memory module includes a plurality of memory chips, one of which is used to store the error correction code, and the other of which is used to store data. Therefore, when one memory chip storing data is damaged, other data and error correction codes can be used for recovering the damaged data. However, when reading data, it is not necessary to read the error correction code if the data is not damaged, so that the load of each memory chip is different when reading data, and the data reading is not efficient. Therefore, how to increase the utilization efficiency of the memory space and improve the efficiency of data reading is a concern for those skilled in the art.
Disclosure of Invention
The invention provides a data writing method, a memory control circuit unit and a memory storage device, which can improve the data reading efficiency by averagely dispersing array error correction codes.
An exemplary embodiment of the present invention provides a data writing method for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of management units, wherein the management units comprise a plurality of chip enabling groups, each chip enabling group comprises a plurality of planes, each plane comprises a plurality of physical programming units, and the chip enabling groups comprise a first chip enabling group and a second chip enabling group. The data writing method comprises the following steps: receiving first data and second data from a host system; generating a first array error correction code according to the first data, and generating a second array error correction code according to the second data; programming a first group including the first array of error correction codes into the first chip enable group using a first programming mode; and programming a second group including the second array of error correction codes into the second chip enable group using a second programming mode. The second programming mode is different from the first programming mode, and the first array error correction code and the second array error correction code are respectively used for correcting the plurality of physical programming units storing the first data and the second data.
In an exemplary embodiment of the invention, the first data has a different data size than the second data, and the first array of error correction codes and the second array of error correction codes have a different number of correctable physical program units.
In an exemplary embodiment of the present invention, the first array of error correction codes is programmed to a first super physical program cell according to a first program order in the first program mode, and the second array of error correction codes is programmed to a second super physical program cell according to a second program order in the second program mode, wherein the first program order is different from the second program order.
In an exemplary embodiment of the invention, the first super physical program unit has a plurality of physical program units, wherein the first physical program unit is a physical program unit programmed last in the first super physical program unit. The second super physical programming unit has a plurality of physical programming units, wherein the second physical programming unit is the physical programming unit programmed last in the second super physical programming unit, and the relative position of the first physical programming unit in the first super physical programming unit is different from the relative position of the second physical programming unit in the second super physical programming unit.
In an exemplary embodiment of the invention, the super-physical erase unit includes the first chip enable group and the second chip enable group, wherein the number of sets of the first array error correction codes programmed to the first chip enable group is the same as the number of sets of the second array error correction codes programmed to the second chip enable group, and the super-physical erase unit is the smallest data erase management unit.
In an exemplary embodiment of the invention, the first array error correction code includes a first partial array error correction code and a second partial array error correction code.
In an exemplary embodiment of the invention, the method further comprises: temporarily storing the first partial array error correction code in a buffer memory; and after generating the second partial array error correction code according to the first data, programming the first partial array error correction code and the second partial array error correction code into the plurality of physical programming units of different planes included in the first chip enable group respectively.
In an exemplary embodiment of the invention, the first array of error correction codes and the second array of error correction codes are parity correction codes. The first array of error correction codes is used for correcting the physical programming units which generate errors according to a parity correction algorithm when at least one of the physical programming units which store the first data generates errors. The second array error correction code is used for correcting the physical programming unit which generates the error according to the parity correction algorithm when at least one of the physical programming units which store the second data generates the error.
In an exemplary embodiment of the invention, the method further comprises: generating a redundant error correction code according to the first data, wherein the redundant error correction code is used for correcting a single physical programming unit written with at least part of the first data. Wherein the number of bits correctable by the redundant error correction codes is less than the number of bits correctable by the first array of error correction codes.
An exemplary embodiment of the present invention provides a memory control circuit unit for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of management units, wherein the management units comprise a plurality of chip enabling groups, each chip enabling group comprises a plurality of planes, each plane comprises a plurality of physical programming units, and the chip enabling groups comprise a first chip enabling group and a second chip enabling group. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is configured to couple to a host system. The memory interface is used for being coupled to the rewritable nonvolatile memory module. The memory management circuit is coupled to the host interface and the memory interface. Wherein the memory management circuitry is to receive first data and second data from the host system. The memory management circuit is further configured to generate a first array error correction code according to the first data and a second array error correction code according to the second data. The memory management circuit is further configured to program a first group including the first array of error correction codes into the first chip enable group using a first programming mode. And the memory management circuit is further configured to program a second group including the second array error correction code into the second chip enable group using a second programming mode, the second programming mode being different from the first programming mode. The first array of error correction codes and the second array of error correction codes are used for correcting the plurality of physical programming units storing the first data and the second data respectively.
In an exemplary embodiment of the invention, the first data has a different data size than the second data, and the first array of error correction codes and the second array of error correction codes have a different number of correctable physical program units.
In an exemplary embodiment of the invention, the memory management circuit is further configured to program the first array of error correction codes to a first super-physical program cell according to a first program order in the first program mode. And the memory management circuit is further configured to program the second array of error correction codes to a second super-physical programming unit according to a second programming order in the second programming mode. Wherein the first programming order is different from the second programming order.
In an exemplary embodiment of the invention, the first super physical program unit has a plurality of physical program units, wherein the first physical program unit is a physical program unit programmed last in the first super physical program unit. The second super physical programming unit has a plurality of physical programming units, wherein the second physical programming unit is the physical programming unit programmed last in the second super physical programming unit, and the relative position of the first physical programming unit in the first super physical programming unit is different from the relative position of the second physical programming unit in the second super physical programming unit.
In an exemplary embodiment of the invention, the super-physical erase unit includes the first chip enable group and the second chip enable group, wherein the number of sets of the first array error correction codes programmed to the first chip enable group is the same as the number of sets of the second array error correction codes programmed to the second chip enable group, and the super-physical erase unit is the smallest data erase management unit.
In an exemplary embodiment of the invention, the first array error correction code includes a first partial array error correction code and a second partial array error correction code.
In an exemplary embodiment of the invention, the memory management circuit is further configured to temporarily store the first partial array error correction code in a buffer memory. And the memory management circuit is further configured to program the first partial array error correction code and the second partial array error correction code into the plurality of physical programming units of different planes included in the first chip enable group, respectively, after generating the second partial array error correction code according to the first data.
In an exemplary embodiment of the invention, the first array of error correction codes and the second array of error correction codes are parity correction codes. The first array of error correction codes is used for correcting the physical programming units which generate errors according to a parity correction algorithm when at least one of the physical programming units which store the first data generates errors. The second array error correction code is used for correcting the physical programming unit which generates the error according to the parity correction algorithm when at least one of the physical programming units which store the second data generates the error.
In an exemplary embodiment of the invention, the memory management circuit is further configured to generate a redundant error correction code according to the first data, the redundant error correction code being used to correct a single physical programming unit written with at least a portion of the first data. Wherein the number of bits correctable by the redundant error correction codes is less than the number of bits correctable by the first array of error correction codes.
An exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being coupled to a host system. The rewritable nonvolatile memory module comprises a plurality of management units, wherein the management units comprise a plurality of chip enabling groups, each chip enabling group comprises a plurality of planes, each plane comprises a plurality of physical programming units, and the chip enabling groups comprise a first chip enabling group and a second chip enabling group. The memory control circuit unit is coupled to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for receiving first data and second data from the host system. The memory control circuit unit is further configured to generate a first array error correction code according to the first data and generate a second array error correction code according to the second data. The memory control circuit unit is further configured to program a first group including the first array error correction code into the first chip enable group using a first programming mode. And the memory control circuit unit is further configured to program a second group including the second array error correction code into the second chip enable group using a second programming mode, the second programming mode being different from the first programming mode. The first array of error correction codes and the second array of error correction codes are used for correcting the plurality of physical programming units storing the first data and the second data respectively.
In an exemplary embodiment of the invention, the first data has a different data size than the second data, and the first array of error correction codes and the second array of error correction codes have a different number of correctable physical program units.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to program the first array of error correction codes to a first super physical program unit according to a first program order in the first program mode. And the memory control circuit unit is further used for programming the second array error correction codes to a second ultra-physical programming unit according to a second programming sequence in the second programming mode. Wherein the first programming order is different from the second programming order.
In an exemplary embodiment of the invention, the first super physical program unit has a plurality of physical program units, wherein the first physical program unit is a physical program unit programmed last in the first super physical program unit. The second super physical programming unit has a plurality of physical programming units, wherein the second physical programming unit is the physical programming unit programmed last in the second super physical programming unit, and the relative position of the first physical programming unit in the first super physical programming unit is different from the relative position of the second physical programming unit in the second super physical programming unit.
In an exemplary embodiment of the invention, the super-physical erase unit includes the first chip enable group and the second chip enable group, wherein the number of sets of the first array error correction codes programmed to the first chip enable group is the same as the number of sets of the second array error correction codes programmed to the second chip enable group, and the super-physical erase unit is the smallest data erase management unit.
In an exemplary embodiment of the invention, the first array error correction code includes a first partial array error correction code and a second partial array error correction code.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to temporarily store the first partial array error correction code in a buffer memory. The memory control circuit unit is further configured to program the first partial array error correction code and the second partial array error correction code into the plurality of physical programming units of different planes included in the first chip enable group, respectively, after generating the second partial array error correction code according to the first data.
In an exemplary embodiment of the invention, the first array of error correction codes and the second array of error correction codes are parity correction codes. The first array of error correction codes is used for correcting the physical programming units which generate errors according to a parity correction algorithm when at least one of the physical programming units which store the first data generates errors. The second array error correction code is used for correcting the physical programming unit which generates the error according to the parity correction algorithm when at least one of the physical programming units which store the second data generates the error.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to generate a redundant error correction code according to the first data, the redundant error correction code being used to correct a single physical programming unit written with at least part of the first data. Wherein the number of bits correctable by the redundant error correction codes is less than the number of bits correctable by the first array of error correction codes.
Based on the above, the data writing method, the memory control circuit unit and the memory storage device according to the exemplary embodiments of the invention can store the array error correction codes in different chip enables, so that the memory can averagely read the data stored in each chip enable when reading the data. Accordingly, the invention improves the data reading efficiency by evenly dispersing the array error correction codes in each chip enable. In addition, the exemplary embodiment of the present invention can further reduce the chance of using a single plane to read data when the memory reads data by storing the array error correction codes in different enabled planes of the same chip, thereby further improving the data reading efficiency.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment;
FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to another example embodiment;
FIG. 4 is a schematic block diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention;
FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;
FIG. 7 is a diagram illustrating a management unit according to an exemplary embodiment of the present invention;
FIGS. 8-10 are schematic diagrams illustrating a write array error correction code according to an exemplary embodiment of the invention;
FIG. 11 is a flowchart illustrating a data writing method according to an example embodiment of the present invention;
fig. 12 is a flowchart illustrating a data writing method according to an example embodiment of the present invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module and a controller (also referred to as a control circuit unit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment. And FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all coupled to a system bus (system bus) 110.
In the present exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is coupled to the I/O devices 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.
In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 are disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be coupled to the memory storage device 10 via a wired or wireless manner through the data transmission interface 114. The memory storage device 10 may be, for example, a personal disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory Storage device 204 can be, for example, a Near Field Communication (NFC) memory Storage device, a wireless facsimile (WiFi) memory Storage device, a Bluetooth (Bluetooth) memory Storage device, or a Bluetooth low energy (iBeacon) memory Storage device based on various wireless Communication technologies. In addition, the motherboard 20 may also be coupled to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded Multi-media cards (eMMC) 341 and/or embedded Multi-Chip Package memory devices (eMCP) 342, which directly couple the memory module to the embedded memory device on the substrate of the host system.
FIG. 4 is a schematic block diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the present invention.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.
In the exemplary embodiment, the connection interface unit 402 is compatible with Secure Digital (SD) interface standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to Serial Advanced Technology Attachment (SATA) standard, Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, High-Speed Peripheral Component connection interface (PCI Express) standard, Universal Serial Bus (USB) standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, Package (Multi-Media-p) interface standard, Multi-Media Chip (Multimedia Card) interface standard, eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-Chip Package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. In the present exemplary embodiment, the connection interface unit 402 and the memory control circuit unit 404 may be packaged in one chip, or the connection interface unit 402 is disposed outside a chip including the memory control circuit unit.
The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.
The rewritable nonvolatile memory module 406 is coupled to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 has physical erasing units 410(0) -410 (N). For example, the physical erase units 410(0) -410 (N) may belong to the same memory die (die) or to different memory dies. Each physical erasing unit is respectively provided with a plurality of physical programming units, wherein the physical programming units belonging to the same physical erasing unit can be independently written and simultaneously erased. However, it should be understood that the invention is not limited thereto, and each physical erase unit may be composed of 64 physical program units, 256 physical program units, or any other physical program units.
In more detail, the physical erase unit is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. The physical programming unit is the minimum unit for programming. That is, the physical programming unit is the smallest unit for writing data. Each physical program unit generally includes a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical access addresses for storing user data, and the redundant bit area stores system data (e.g., management data such as control information and error correction codes). In the exemplary embodiment, each physical program unit includes 8 physical access addresses in the data bit area, and one physical access address has a size of 512 bytes (byte). However, in other exemplary embodiments, the data bit area may include a greater or lesser number of physical access addresses, and the size and number of the physical access addresses are not limited in the present invention. For example, in an exemplary embodiment, the physical erase unit is a physical block (block), and the physical program unit is a physical page (page) or a physical sector (sector), but the invention is not limited thereto.
In the exemplary embodiment, the rewritable nonvolatile memory module 406 is a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 data bit in one memory Cell). However, the invention is not limited thereto, and the rewritable nonvolatile memory module 406 may also be a Multi-Level Cell (MLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 2 data bits in one memory Cell), a Multi-Level Cell (TLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 3 data bits in one memory Cell), or other memory modules with the same characteristics. Specifically, the memory cells on the same word line may constitute one or more physical programming cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504 and a memory interface 506.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10.
In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In another exemplary embodiment of the invention, the control command of the memory management circuit 502 can also be stored in a code pattern in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a driver, and when the memory control circuit 404 is enabled, the microprocessor first executes the driver to load the control command stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In another exemplary embodiment of the invention, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used for managing physical erasing cells of the rewritable nonvolatile memory module 406; the memory writing circuit is used for issuing a writing instruction to the rewritable nonvolatile memory module 406 so as to write data into the rewritable nonvolatile memory module 406; the memory reading circuit is used for sending a reading instruction to the rewritable nonvolatile memory module 406 so as to read data from the rewritable nonvolatile memory module 406; the memory erasing circuit is used for issuing an erasing instruction to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406; the data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406.
The host interface 504 is coupled to the memory management circuit 502 and is used for being coupled to the connection interface unit 402 to receive and identify commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE1394 standard, the PCI Express standard, the USB standard, the UHS-I interface standard, the UHS-II interface standard, the SD standard, the MS standard, the MMC standard, the CF standard, the IDE standard, or other suitable data transmission standards.
The memory interface 506 is coupled to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506.
The buffer memory 508 is coupled to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406.
In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 508, a power management circuit 510, and an error checking and correcting circuit 512.
The power management circuit 510 is coupled to the memory management circuit 502 and is used to control the power of the memory storage device 10.
The error checking and correcting circuit 512 is coupled to the memory management circuit 502 and is used for performing an error checking and correcting process to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the Error Checking and Correcting circuit 512 generates an Error Checking and Correcting Code (ECC Code) corresponding to the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC Code into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the corresponding error checking and correcting codes are simultaneously read, and the error checking and correcting circuit 512 performs an error checking and correcting process on the read data according to the error checking and correcting codes.
Operations performed by the memory management circuit 502, the host interface 504 and the memory interface 506, the buffer memory 508, the power management circuit 510 and the error checking and correcting circuit 512 are described below and may also be referred to as being performed by the memory control circuit unit 404.
In an exemplary embodiment, the memory management circuit 502 temporarily stores the first data into the buffer 508 and generates an error checking and correcting code (herein, abbreviated as an error correcting code) according to the first data. The type of the error correction code may be parity checking code (parity checking code), channel coding (channel coding), or other types. For example, the error correction code generated by the memory management circuit 502 may be a hamming code, a low density parity check code (LDPC code), a turbo code, or a Reed-solomon code (RS code), but the invention is not limited thereto. If the length ratio of the data to the error correction code is m: n, it means that m physical programming units storing the data correspond to n physical programming units storing the error correction code, where m and n are positive integers. In general, the positive integer m is larger than the positive integer n, but the invention is not limited thereto. Also, the present invention is not limited to the values of the positive integer m and the positive integer n.
In an exemplary embodiment, the error correction code includes an array error correction code. The memory management circuit 502 temporarily stores the first data into the buffer 508 and generates the array error correction code according to the first data. The array error correction code is used for correcting a plurality of physical programming units storing first data. For example, the memory management circuit 502 performs logic operations on data programmed into different physical program cells to generate array error correction codes. Therefore, the array error correction code can correct more than two physically programmed data. The generated array error correction code is also programmed to a physical program cell. In the exemplary embodiment, the array error correction code is generated by the memory management circuit 502, however, the array error correction code may also be generated by the error checking and correcting circuit 512, and the invention is not limited thereto.
The memory management circuit 502 can manage and access the physical nodes in the rewritable non-volatile memory module 406 based on the management unit. One management unit is also called a Virtual Block (VB). A management unit may comprise a plurality of physical nodes. For example, a management unit may cover multiple physical nodes belonging to one or more planes (also referred to as memory planes) and/or one or more Chip Enables (CEs) in the rewritable nonvolatile memory module 406.
FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 6, the rewritable nonvolatile memory module 406 includes management units 61(0) -61 (n). Each of management units 61(0) -61 (n) includes chip enable (also referred to as a chip enable group) CE (0) and CE (1). The chip enable CE (0) and CE (1) each include a plurality of physical nodes. The memory management circuit 502 may enable the chip enable (chip enable) pins respectively. The memory management circuit 502 can access the management units 61(0) to 61(n) through the channels 60(0) to 60 (m). For example, the memory management circuit 502 may access the management units 61(0) and 61(1) in parallel (or alternatively referred to as interleaved) through at least two of the channels 60(0) to 60 (m). In addition, chip enable CE (0) and CE (1) may include a plurality of planes (e.g., first planes PL (1), PL (3), PL (5), PL (7) and second planes PL (2), PL (4), PL (6), PL (8) of FIG. 7), respectively).
The planes in the management units 61(0) and 61(1) may include a plurality of physical nodes. These physical nodes may be accessed in parallel (or interleaved) to improve access efficiency. In an example embodiment, a plurality of consecutive physical nodes in a plane may be referred to as a physical programming unit. Alternatively, in an exemplary embodiment, a plurality of consecutive physical nodes in a chip enable may be referred to as a physical programming unit. Alternatively, in an example embodiment, a plurality of consecutive physical nodes in a plurality of planes may be referred to as one physical programming unit.
Memory management circuitry 502 may also perform operations (e.g., data write operations, data erase operations) by combining physical erase units belonging to different memory planes into a super-physical unit (also referred to as a super-physical erase unit). A super-physical cell includes at least two available physical erased cells of all physical erased cells. In the exemplary embodiment, at least two available physical erase units included in a super-physical unit belong to different operation units (e.g., planes, interlaces, or channels). Therefore, different physical program cells among the super physical program cells included in the super physical cells can be simultaneously programmed according to the same write command.
Fig. 7 is a diagram illustrating a management unit according to an exemplary embodiment of the invention. Referring to fig. 7, taking the management units 61(0) and 61(1) as an example, the first planes PL (1), PL (3), PL (5), PL (7) and the second planes PL (2), PL (4), PL (6), PL (8) may include a plurality of physical nodes. The management unit 61(0) includes chip enable CE (0) and CE (1), and the first plane PL (1), PL (3) and the second plane PL (2), PL (4) in the chip enable CE (0) and CE (1) include physical programming units 701(0) to 701(M), 702(0) to 702(M), 703(0) to 703(M) and 704(0) to 704(M), respectively. The management unit 61(1) includes chip enable CE (0) and CE (1), and the first plane PL (5), PL (7) and the second plane PL (6), PL (8) in the chip enable CE (0) and CE (1) include physical programming units 705(0) to 705(M), 706(0) to 706(M), 707(0) to 707(M), and 708(0) to 708(M), respectively. In the exemplary embodiment, the physical programming units 701(0) -708 (0), 701(1) -708 (1), and 701(M) -708 (M) can be configured as super physical programming units, respectively.
In the exemplary embodiment, memory management circuit 502 may write data into a plurality of physical program cells according to the program sequence of planes PL (1) -PL (8). Assuming that all the physical programming units are blank, in order to write a piece of write data that can be filled with 16 physical programming units, the memory management circuit 502 will program the write data into the physical programming units according to a programming order from the first blank physical programming unit (e.g., the physical programming unit 701(0)), such as the physical programming units 701(0), 702(0), 703(0), 704(0), 705(0), 706(0), 707(0), 708(0), 701(1), 702(1), 703(1), 704(1), 705(1), 706(1), 707(1), 708(1), and so on. In another embodiment, the memory management circuit 502 can program data into a single (or more) management units, for example, data can be programmed into a plurality of physical programming units according to the programming order of the planes PL (1) -PL (4), which is not limited herein.
FIGS. 8 and 9 are schematic diagrams illustrating a write array error correction code according to an exemplary embodiment of the invention. For simplicity, the reference numbers corresponding to each physical programming unit are not directly drawn, and the reference numbers of each data and array error correction code stored physical programming unit in fig. 8 and 9 can be simultaneously compared with the reference numbers of the physical programming unit in fig. 7 and the left physical programming unit in fig. 8 and 9.
In the exemplary embodiment of FIG. 8, the ratio of the length of the data to the length of the array error correction code is 16: 1 (i.e., the positive integer m is 16 and the positive integer n is 1). It is assumed that the array error correction code is the size of a physical programming unit. The memory management circuit 502 programs a first group including a first array of error correction codes into a first chip enable group using a first programming mode. Wherein the first group includes first data and a first array of error correction codes. Referring to fig. 8, the memory management circuit 502 generates the array error correction code 811 (also called the first partial array error correction code) according to the first data 810(1) -810 (16), 820(1) -820 (16) and the first partial data 810(1) -810 (16). After generating the array error correction codes 811, the memory management circuit 502 temporarily stores the array error correction codes 811 in the buffer memory 508 of the memory control circuit unit 404. After the array error correction code 812 (also called the second partial array error correction code) is generated according to the second partial data 820(1) -820 (16), the memory management circuit 502 simultaneously programs the array error correction code 811 and the array error correction code 812 (also called the first array error correction code) sequentially and respectively into the physical programming units 701 and 702(4) of different planes. In addition, the memory management circuit 502 programs a second group including the second array error correction code into a second chip enable group using a second programming mode. Wherein the second group includes second data and a second array error correction code. Similarly, the memory management circuit 502 generates the array error correction code 821 (also called the third partial array error correction code) according to the third part of the second data 830(1) -830 (16), 840(1) -840 (16). After generating the array error correction code 821, the memory management circuit 502 temporarily stores the array error correction code 831 in the buffer memory 508 of the memory control circuit unit 404. After the array error correction codes 822 (also called as fourth portion array error correction codes) are generated according to the fourth portion data 840(1) -840 (16), the memory management circuit 502 simultaneously programs the array error correction codes 821 and the array error correction codes 822 (also called as second array error correction codes) into the physical programming units 703(8) and 704(8) of different planes, respectively, and so on. Therefore, in the second programming mode, the memory management circuit 502 programs the second array of error correction codes into a second chip enable group different from the first chip enable group. In other words, the memory management circuit 502 programs one set of the array error correction codes 811 and 812 to the first and second planes PL (1) and PL (2) of the same chip enable, programs the other set of the array error correction codes 821 and 822 to the first and second planes PL (3) and PL (4) of the other chip enable, and so on. That is, the array error correction code comprises a plurality of partial array error correction codes which can be enabled in pairs and evenly distributed on different chips. When the memory management circuit 502 is to read the data stored in the management units 61(0) and 61(1), the data stored in the chip enable CE (0) and the chip enable CE (1) in the management units 61(0) and 61(1) can be read in a multi-plane (multi-plane) manner. Therefore, the chance of reading data in a one-plane (one-plane) manner can be reduced. Since the memory management circuit 502 generally treats the array ECC code as invalid data when reading data, it does not read the physical program cells in which the array ECC code is stored. Therefore, when the plurality of partial array error correction codes included in the array error correction code are not stored in pairs in two enabled planes of the same chip, the partial array error correction codes may be stored in pairs with the valid data in the two enabled planes of the same chip, so that the memory management circuit 502 needs to read the valid data in a single-plane manner, which affects the reading performance. By the operation of dispersing the array error correction codes, the exemplary embodiment can evenly disperse the array error correction codes in the first plane and the second plane of each chip enable, and the memory management circuit 502 can evenly read the data stored in each chip enable, thereby improving the data reading efficiency.
In another embodiment, the first partial array error correction code and the second partial array error correction code may not be programmed in pairs into different planes (e.g., the first plane PL (1) and the second plane PL (2)) enabled by the first chip. Similarly, the third and fourth partial array error correction codes may be programmed into different enabled planes of the second chip without pairing. Thus, the purpose of evenly dispersing the array error correction codes in different chip enables can be achieved.
In this example embodiment, the array error correction code 811 is a parity correction code. In other embodiments, the array error correction code 811 may also be a BCH or other type of error correction code. When one of the physical program cells storing the first part of data 810(1) -810 (16) generates an error, the memory management circuit 502 corrects the physical program cell generating the error according to a parity correction algorithm. Other array error correction codes may also modify the corresponding data according to the parity correction algorithm.
In an exemplary embodiment, the first portion of data 810(1) -810 (16) is stored in the buffer memory 508 before being programmed into the physical programming units 701(0) -708 (0) and 701(1) -708 (1). Before the first portion 810(1) of data is programmed to the physical programming unit 701(0), the memory management circuit 502 generates a temporary array error correction code according to the first portion 810 (1). Then, the memory management circuit 502 programs the first portion of data 810(1) to the physical programming unit 701(0), and generates another temporary array error correction code according to the temporary array error correction code and the first portion of data 810 (2). Similarly, after writing the first portion 810(2), the other temporary ECC is generated with the first portion 810(3) and so on. In other words, the memory management circuit 502 generates the temporary array error correction code corresponding to the first portion of data every time the first portion of data is written, and the temporary array error correction code becomes the array error correction code 811 after all the first data 810(1) -810 (16) are written. The memory management circuit 502 stores the temporary array error correction code in the buffer memory 508. However, in another exemplary embodiment, the memory management circuit 502 may also generate the array error correction code 811 based on the first portion of data 810(1) - (810) (16) at one time (for example, the array error correction code 811 is generated before or after the first portion of data 810(1) - (810) (16) is written), and the invention is not limited thereto. In the present exemplary embodiment, the memory management circuit 502 can generate the array error correction code 821 according to the second part data 820(1) -820 (16) in the same manner as described above, which is not described herein again.
In an exemplary embodiment, the first portion of data 810(1) -810 (16) is received from the host system 11. However, the host system 11 may issue more than 16 physical program cells or less than 16 physical program cells at a time. In other words, the first portion of data 810(1) -810 (16) may correspond to one or more write commands. For example, the host system 11 first receives a write command, which is data to be written into 12 physical program cells. After receiving the data, the memory management circuit 502 does not generate the array error correction code 811 immediately. Next, the host system 11 issues another write command, which is data to be written into 4 physical program cells. The memory management circuit 502 obtains the first part of data 810(1) -810 (16) from the data corresponding to the two write commands. For example, the memory management circuit 502 obtains the first partial data 810(1) to 810(12) from the first write command, and obtains the first partial data 810(13) to 810(16) from the second write command. The data in the second write command that has not been written is merged with the data in the other write command. In this way, the first portions of data 810(1) -810 (16) correspond to two write commands, but the first portions of data 810(1) -810 (16) may correspond to three or more write commands, and the invention is not limited thereto. Alternatively, the first write command is to write 17 physical program cells of data, and the memory management circuit 202 obtains the first part of data 810(1) -810 (16) from the data, and the remaining 1 physical program cell of data is merged with other data (e.g., the data of 15 physical program cells in the next write data). That is, the first partial data 810(1) to 810(16) may correspond to one write command. Similarly, the second portion of data 820(1) -820 (16) may correspond to one or more write commands, but the invention is not limited thereto.
In the example embodiment of FIG. 9, the memory management circuit 502 only programs data to the physical program cells in the first program mode. In the second programming mode, the memory management circuit 502 programs the data and the array error correction code to the physical programming unit. Wherein the array error correction code is programmed into the physical programming units of different chip enable groups. Specifically, after generating the array error correction codes 811-841, the memory management circuit 502 temporarily stores the array error correction codes 811-41 in the buffer memory 508 of the memory control circuit unit 404. After the array error correction codes 842 are generated, the memory management circuit 502 simultaneously writes the array error correction codes 811-842 into the physical programming units 701(N) -708 (N) of different planes in sequence and respectively. In other exemplary embodiments, the memory management circuit 502 may temporarily store different numbers of array error correction codes in the buffer memory 508 of the memory control circuit unit 404, and sequentially and respectively write the generated array error correction codes to the first plane and the second plane of the chip enable after generating two, four, eight or other dual array error correction codes. Herein, the array error correction code comprises a plurality of partial array error correction codes which can be dispersed in pairs in different enabled planes of the chip. In other embodiments, the plurality of partial array error correction codes included in the array error correction code may also be programmed into different chip enabled planes without being paired, and the invention is not limited thereto.
FIG. 10 is a diagram illustrating a write array error correction code according to an exemplary embodiment of the invention. The embodiment is described by taking an example of generating a first array error correction code according to the first data and generating a second array error correction code according to the second data. In the present exemplary embodiment, the memory management circuit 502 programs a first group including a first array of error correction codes into a first chip enable group using a first programming mode. The memory management circuit 502 programs a second group including the second array of error correction codes into a second chip enable group using a second programming mode. The first group comprises first data and a first array of error correction codes, and the second group comprises second data and a second array of error correction codes.
Referring to FIG. 10, the physical programming units 701(0) -708 (0) are combined into a super physical unit, and so on. The memory management circuit 502 programs the first array of error correction codes into the physical program cells of the super physical program cells according to a first programming order in a first programming mode. In detail, the memory management circuit 502 generates the array error correction code 810 according to the first data 810(1) -810 (32), and programs the array error correction code 810 into the physical programming units 701(4) of the physical programming units 701(4) -708 (4) (also called the first super physical programming unit) according to the first programming order in the first programming mode. The first programming order is, for example, sequentially programmed from the first plane PL (1) to the second plane PL (8), so that the physical programming units 701(4) (also called the first physical programming unit) are the last physical programming units programmed in the physical programming units 701(4) -708 (4). The memory management circuit 502 generates the array error correction code 820 according to the second data 820(1) - (820) (32), and programs the array error correction code 820 into the physical programming units 708(7) of the physical programming units 701(8) - (708) (8) (also called second super physical programming unit) according to the second programming order in the second programming mode. The second programming order is, for example, sequentially programmed from the second plane PL (8) to the first plane PL (1), so that the physical programming units 701(8) (also called the second physical programming unit) are the physical programming units that are programmed last in the physical programming units 701(8) -708 (8). Here, the first programming order is different from the second programming order, and the relative positions of the physical programming units 701 (701) (4) in the physical programming units 701(4) -708 (4) are different from the relative positions of the physical programming units 708(8) in the physical programming units 701(8) -708 (8). The exemplary embodiment does not limit the programming sequence of the first data 810(1) -810 (32) and the second data 820(1) -820 (32). Thus, the array error correction codes 810 and 820 can be programmed into different chip enable groups according to different programming sequences.
In another exemplary embodiment, the amount of data of the first data used to generate the first array of error correction codes is different from the amount of data of the second data used to generate the second array of error correction codes. The first array of error correction codes and the second array of error correction codes can correct different numbers of physical programming units. For example, the data amount of the first data is the data amount that can be stored by 28 physical programming cells, and the data amount of the second data is the data amount that can be stored by 32 physical programming cells. The memory management circuit 502 sequentially programs the first data and the generated first array of error correction codes into the physical programming unit, and then sequentially programs the second data and the generated second array of error correction codes into the physical programming unit. Therefore, the first array error correction code and the second array error correction code can be programmed into different chip enabling groups due to different data volumes for generating the array error correction codes.
In the above embodiments, the memory management circuit 502 may generate an array error correction code including a plurality of partial array error correction codes according to the received data, which is not limited herein. Also, the memory management circuit 502 may write the generated plurality of partial array error correction codes into the super physical program cells including the consecutive physical program cells.
In the above embodiments, the super-physical erase unit is the smallest data erase management unit, and the super-physical erase unit has a plurality of physical program units. According to the data writing method provided by the exemplary embodiment, in an exemplary embodiment, the number of sets of the array error correction codes programmed to each chip enable group included in the super physical erase unit is the same. For example, referring to FIG. 7, the super physical erase unit may include a chip enable CE (0) and a chip enable CE (1), and the number of sets of array error correction codes programmed to the chip enable CE (0) is the same as the number of sets of second array error correction codes programmed to the chip enable CE (1).
The error correction code also includes redundant error correction codes as compared to the array error correction code. In an exemplary embodiment, after the memory management circuit 502 writes a first data to one or more physically erased cells, a redundant error correction code is generated based on the first data. The redundancy error correction code is used for correcting a part of bits in a single physical programming unit written with at least part of the first data. The number of bits that can be corrected by the redundant error correction code is smaller than the number of bits that can be corrected by the array error correction code. For example, the redundancy ECC is stored in the redundancy bit region, and can only correct a part of bits of data in the data bit region of a single physical programming unit. In the exemplary embodiment, the redundant error correction codes are generated by the memory management circuit 502, however, the redundant error correction codes may also be generated by the error checking and correcting circuit 512, and the invention is not limited thereto.
Fig. 11 is a flowchart illustrating a data writing method according to an example embodiment of the present invention. Referring to fig. 11, in step S1102, first data and second data are received from a host system. In step S1104, a first array of error correction codes is generated according to the first data, and a second array of error correction codes is generated according to the second data. In step S1106, a first group including the first array of error correction codes is programmed into the first chip enable group using a first programming mode. In step S1108, a second group including the second array of error correction codes is programmed into the second chip enable group using a second programming mode.
Fig. 12 is a flowchart illustrating a data writing method according to an example embodiment of the present invention. Referring to fig. 12, in step S1202, first data, second data and third data are received from a host system. In step S1204, a first partial array error correction code is generated according to the first data, a second partial array error correction code is generated according to the second data, and a third partial array error correction code is generated according to the third data. In step S1206, the first partial array error correction code, the second partial array error correction code, and the third partial array error correction code are temporarily stored in a buffer memory. In step S1208, fourth data is received from the host system, and a fourth partial array error correction code is generated according to the fourth data. In step S1210, the first partial array error correction code and the second partial array error correction code are written into the plurality of physical programming units of different planes included in the first chip enable group, respectively, and the third partial array error correction code and the fourth partial array error correction code are written into the plurality of physical programming units of different planes included in the second chip enable group, respectively.
The steps in fig. 11 and fig. 12 have been described in detail above, and are not described again here. However, the steps in fig. 11 and fig. 12 can be implemented as a plurality of codes or circuits, and the invention is not limited thereto. In addition, the methods of fig. 11 and fig. 12 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.
In particular, the data writing method according to the exemplary embodiment of the present invention may make the number of the array error correction codes included in each chip enable group as the same as possible. In another exemplary embodiment, the number of array error correction codes included in each plane may also be made as equal as possible. Accordingly, the array error correction codes can be evenly distributed among the chip enables.
In summary, the data writing method, the memory control circuit unit and the memory storage device according to the exemplary embodiments of the invention can averagely read the data stored in each chip enable when the memory reads the data by averagely dispersing the array error correction codes in different chip enables, thereby improving the data reading efficiency. In other embodiments, the array error correction codes are further stored in different planes of the same chip enable, so that the chance of reading data in a single-plane manner is reduced when the memory reads data, and the data stored in each chip enable can be read averagely, thereby improving the data reading efficiency.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (27)

1. A data writing method is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of management units, the management units comprise a plurality of chip enabling groups, each chip enabling group comprises a plurality of planes, each plane comprises a plurality of physical programming units, the chip enabling groups comprise a first chip enabling group and a second chip enabling group, and the data writing method comprises the following steps:
receiving first data and second data from a host system;
generating a first array error correction code according to the first data, and generating a second array error correction code according to the second data;
programming a first group including the first array of error correction codes into the first chip enable group using a first programming mode; and
programming a second group including the second array of error correction codes into the second chip enable group using a second programming mode, the second programming mode being different from the first programming mode,
the first array of error correction codes and the second array of error correction codes are used for correcting the plurality of physical programming units storing the first data and the second data respectively.
2. The data writing method according to claim 1, wherein the first data has a different data size than the second data, and the first and second arrays of error correction codes have different numbers of correctable physical program cells.
3. The data writing method according to claim 1, wherein the first array of error correction codes is programmed to a first super-physical program cell according to a first program order in the first program mode,
programming the second array of error correction codes to a second super-physical programming unit according to a second programming order in the second programming mode,
wherein the first programming order is different from the second programming order.
4. The data writing method according to claim 3, wherein the first super physical program cell has a plurality of physical program cells, wherein a first physical program cell is a physical program cell programmed last in the first super physical program cell,
the second super physical programming unit comprises a plurality of physical programming units, wherein the second physical programming unit is the physical programming unit programmed last in the second super physical programming unit, and the relative position of the first physical programming unit in the first super physical programming unit is different from the relative position of the second physical programming unit in the second super physical programming unit.
5. The data writing method according to claim 1, wherein the first chip enable group and the second chip enable group are included in a super-physical erase unit, wherein the number of sets of the first array error correction codes programmed to the first chip enable group is the same as the number of sets of the second array error correction codes programmed to the second chip enable group, wherein the super-physical erase unit is a minimum data erase management unit.
6. The data writing method according to claim 1, wherein the first array error correction code comprises a first partial array error correction code and a second partial array error correction code.
7. The data writing method of claim 6, the method further comprising:
temporarily storing the first partial array error correction code in a buffer memory; and
after generating the second partial array error correction code according to the first data, programming the first partial array error correction code and the second partial array error correction code into the plurality of physical programming units of different planes included in the first chip enable group, respectively.
8. The data writing method according to claim 1, wherein the first and second arrays of error correction codes are parity correction codes, the first array of error correction codes is used to correct the physical program unit in which an error occurs according to a parity correction algorithm when an error occurs in at least one of the physical program units in which the first data is stored, and the second array of error correction codes is used to correct the physical program unit in which an error occurs according to the parity correction algorithm when an error occurs in at least one of the physical program units in which the second data is stored.
9. The data writing method of claim 1, the method further comprising:
generating a redundant error correction code according to the first data, the redundant error correction code being used to correct a single physical programming unit written with at least part of the first data,
wherein the number of bits correctable by the redundant error correction codes is less than the number of bits correctable by the first array of error correction codes.
10. A memory control circuit unit is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of management units, the management units comprise a plurality of chip enabling groups, each chip enabling group comprises a plurality of planes, each plane comprises a plurality of physical programming units, the chip enabling groups comprise a first chip enabling group and a second chip enabling group, and the memory control circuit unit comprises:
a host interface for coupling to a host system;
a memory interface to couple to the rewritable non-volatile memory module; and
memory management circuitry coupled to the host interface and the memory interface,
wherein the memory management circuitry is to receive first data and second data from the host system,
the memory management circuit is further configured to generate a first array of error correction codes based on the first data and a second array of error correction codes based on the second data,
the memory management circuit is further configured to program a first group including the first array of error correction codes into the first chip enable group using a first programming mode, and
the memory management circuit is further configured to program a second group including the second array error correction code into the second chip enable group using a second programming mode, the second programming mode being different from the first programming mode,
the first array of error correction codes and the second array of error correction codes are used for correcting the plurality of physical programming units storing the first data and the second data respectively.
11. The memory control circuit unit of claim 10, wherein the first data has a different data amount than the second data, and the first array of error correction codes and the second array of error correction codes have a different number of correctable physical program cells.
12. The memory control circuit unit of claim 10, wherein the memory management circuit is further configured to program the first array of error correction codes to a first super-physical program cell according to a first program order in the first program mode, and
the memory management circuit is further configured to program the second array of error correction codes to a second super-physical programming unit according to a second programming order in the second programming mode,
wherein the first programming order is different from the second programming order.
13. The memory control circuit unit of claim 12, wherein the first super physical program unit has a plurality of physical program units, wherein a first physical program unit is a physical program unit that is programmed last in the first super physical program unit,
the second super physical programming unit comprises a plurality of physical programming units, wherein the second physical programming unit is the physical programming unit programmed last in the second super physical programming unit, and the relative position of the first physical programming unit in the first super physical programming unit is different from the relative position of the second physical programming unit in the second super physical programming unit.
14. The memory control circuit unit of claim 10, wherein the first chip enable group and the second chip enable group are included in a super-physical erase unit, wherein the number of sets of the first array of error correction codes programmed to the first chip enable group is the same as the number of sets of the second array of error correction codes programmed to the second chip enable group, wherein the super-physical erase unit is a minimum data erase management unit.
15. The memory control circuitry unit of claim 10, wherein the first array of error correction codes comprises a first partial array of error correction codes and a second partial array of error correction codes.
16. The memory control circuitry unit of claim 15, wherein the memory management circuitry is further to suspend the first partial array error correction code in a buffer memory, and
the memory management circuit is further configured to program the first partial array error correction code and the second partial array error correction code into the plurality of physical programming units of different planes included in the first chip enable group, respectively, after generating the second partial array error correction code according to the first data.
17. The memory control circuit cell of claim 10, wherein the first array of error correction codes and the second array of error correction codes are parity correction codes,
the first array of error correction codes is used for correcting the physical programming units which generate errors according to a parity correction algorithm when at least one of the physical programming units which store the first data generates errors,
the second array error correction code is used for correcting the physical programming unit which generates the error according to the parity correction algorithm when at least one of the physical programming units which store the second data generates the error.
18. The memory control circuit unit of claim 10, wherein the memory management circuit is further configured to generate a redundant error correction code based on the first data, the redundant error correction code configured to correct a single physical program cell written with at least a portion of the first data,
wherein the number of bits correctable by the redundant error correction codes is less than the number of bits correctable by the first array of error correction codes.
19. A memory storage device, comprising:
a connection interface unit for coupling to a host system;
the memory module comprises a plurality of management units, wherein each management unit comprises a plurality of chip enabling groups, each chip enabling group comprises a plurality of planes, each plane comprises a plurality of physical programming units, and the chip enabling groups comprise a first chip enabling group and a second chip enabling group; and
a memory control circuit unit coupled to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuitry unit is to receive first data and second data from the host system,
the memory control circuit unit is further used for generating a first array error correction code according to the first data and generating a second array error correction code according to the second data,
the memory control circuit unit is further configured to program a first group including the first array error correction code into the first chip enable group using a first programming mode, and
the memory control circuit unit is further configured to program a second group including the second array error correction code into the second chip enable group using a second programming mode, the second programming mode being different from the first programming mode,
the first array of error correction codes and the second array of error correction codes are used for correcting the plurality of physical programming units storing the first data and the second data respectively.
20. The memory storage device of claim 19, wherein the first data has a different data size than the second data, and the first array of error correction codes and the second array of error correction codes have a different number of correctable physical program cells.
21. The memory storage device of claim 19, wherein the memory control circuit unit is further configured to program the first array of error correction codes to a first superphysical program cell according to a first program order in the first program mode, and
the memory control circuit unit is further configured to program the second array of error correction codes to a second super physical programming unit according to a second programming order in the second programming mode,
wherein the first programming order is different from the second programming order.
22. The memory storage device of claim 21, wherein the first super physical program cell has a plurality of physical program cells, wherein a first physical program cell is a last programmed physical program cell of the first super physical program cells,
the second super physical programming unit comprises a plurality of physical programming units, wherein the second physical programming unit is the physical programming unit programmed last in the second super physical programming unit, and the relative position of the first physical programming unit in the first super physical programming unit is different from the relative position of the second physical programming unit in the second super physical programming unit.
23. The memory storage device of claim 19, wherein the first chip enable group and the second chip enable group are included in a super-physical erase unit, wherein a number of sets of the first array of error correction codes programmed to the first chip enable group is the same as a number of sets of the second array of error correction codes programmed to the second chip enable group, wherein the super-physical erase unit is a minimum data erase management unit.
24. The memory storage device of claim 19, wherein the first array of error correction codes comprises a first partial array error correction code and a second partial array error correction code.
25. The memory storage device of claim 24, wherein the memory control circuitry unit is further to temporarily store the first partial array error correction code in a buffer memory, and
the memory control circuit unit is further configured to program the first partial array error correction code and the second partial array error correction code into the plurality of physical programming units of different planes included in the first chip enable group, respectively, after generating the second partial array error correction code according to the first data.
26. The memory storage device of claim 19, wherein the first array of error correction codes and the second array of error correction codes are parity correction codes,
the first array of error correction codes is used for correcting the physical programming units which generate errors according to a parity correction algorithm when at least one of the physical programming units which store the first data generates errors,
the second array error correction code is used for correcting the physical programming unit which generates the error according to the parity correction algorithm when at least one of the physical programming units which store the second data generates the error.
27. The memory storage device of claim 19, wherein the memory control circuit unit is further configured to generate a redundant error correction code based on the first data, the redundant error correction code configured to correct a single physical program cell to which at least a portion of the first data is written,
wherein the number of bits correctable by the redundant error correction codes is less than the number of bits correctable by the first array of error correction codes.
CN202010794976.6A 2020-08-10 2020-08-10 Data writing method, memory control circuit unit and memory storage device Pending CN114077515A (en)

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