CN104679441B - Time estimating and measuring method, memory storage apparatus, memorizer control circuit unit - Google Patents

Time estimating and measuring method, memory storage apparatus, memorizer control circuit unit Download PDF

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CN104679441B
CN104679441B CN201310638312.0A CN201310638312A CN104679441B CN 104679441 B CN104679441 B CN 104679441B CN 201310638312 A CN201310638312 A CN 201310638312A CN 104679441 B CN104679441 B CN 104679441B
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data
state
those
storage units
written
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CN104679441A (en
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林纬
许佑诚
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Phison Electronics Corp
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Phison Electronics Corp
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Abstract

The present invention provides a kind of time estimating and measuring method, memory storage apparatus, memorizer control circuit unit, for including the reproducible nonvolatile memorizer module of multiple storage units.The method includes：Write first data into multiple first storage units into the storage unit；First storage unit is read according to a reading voltage, to judge that each first storage unit is to belong to first state or the second state；And the number that basis belongs to the first storage unit of first state is calculated, and the temporal information of reproducible nonvolatile memorizer module is obtained according to this number.

Description

Time estimating and measuring method, memory storage apparatus, memorizer control circuit unit
Technical field
The invention relates to a kind of time estimating and measuring method, and in particular to type nonvolatile mould Time estimating and measuring method, memory storage apparatus, the memorizer control circuit unit of block.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years so that consumer is to storage The demand of media also rapidly increases.Since reproducible nonvolatile memorizer module (for example, flash memory) has data It is non-volatile, power saving, small and without characteristics such as mechanical structures, thus be extremely suitable for use in it is above-mentioned it is illustrated it is various just It takes in formula multimedia device.
Generally, for a data in reproducible nonvolatile memorizer module, if this data can be calculated How long it is stored in reproducible nonvolatile memorizer module, then there may be some purposes, such as whether judges this data It may lose or determine how to read these data.However, obtain time letter to one clock of configuration or timer Breath, then need additional power supply.Therefore, how to estimate the temporal information of reproducible nonvolatile memorizer module, lead thus Field technique personnel subject under discussion of concern.
Invention content
The present invention provides a kind of time estimating and measuring method, memory storage apparatus and memorizer control circuit unit, can estimate Measure the temporal information of reproducible nonvolatile memorizer module.
An exemplary embodiment of the invention proposes a kind of time estimating and measuring method, for type nonvolatile mould Block.This reproducible nonvolatile memorizer module includes multiple storage units.The method includes：It writes first data into institute State multiple first storage units in storage unit；First storage unit is read according to a reading voltage, to judge each First storage unit is to belong to first state or the second state；And calculate the of the first storage unit for belonging to first state One number, and according to the first time information of first number acquirement reproducible nonvolatile memorizer module.
In an exemplary embodiment, above-mentioned write first data into the step of the first storage unit further includes：According to reading Voltage is taken to read the first storage unit, to judge that each first storage unit is to belong to first state or the second state；With And record belongs to second number of the first storage unit of first state.It is above-mentioned that first time information is obtained according to first number Step includes：First time information is obtained according to the difference between first number and second number, wherein first time information is to use With estimation the first data of write-in to the first storage unit elapsed time of reading.
In an exemplary embodiment, above-mentioned time estimating and measuring method further includes：Second data are written non-to duplicative Volatile；And record first time information, wherein first time information is to estimate the first data of write-in To the second data elapsed time of write-in.
In an exemplary embodiment, above-mentioned time estimating and measuring method further includes：The reading instruction from host system is received, It indicates to read the second data；The first storage unit is re-read according to voltage is read, to judge that the first storage unit is to belong to First state or the second state calculate the third number for the first storage unit for belonging to first state, and according to the third Number obtains the second temporal information of reproducible nonvolatile memorizer module, wherein the second temporal information is to estimate to write Enter the first data to re-reading for the first storage unit elapsed time.The method further includes：According to the second temporal information with First time information obtains third temporal information, and wherein third temporal information is to estimate the second data of write-in to reading second Data elapsed time.
In an exemplary embodiment, above-mentioned time estimating and measuring method further includes：At least one is determined according to third temporal information The number of a first voltage, and the second data are read according to first voltage.
In an exemplary embodiment, first storage unit of each above-mentioned is located on a bit line, and each compares Special line, which reacts on, reads one sensing electric current of voltage generation.This time estimating and measuring method further includes：According to produced by each bit line Sensing electric current or bit line on voltage level, it is to belong to first state or second to judge each first storage unit State.
In an exemplary embodiment, above-mentioned the step of obtaining first time information according to first number, includes：By first Number one look-up table of input, and the output of look-up table is obtained using as first time information.
An of the invention exemplary embodiment proposes a kind of memory storage apparatus, including connecting interface unit, above-mentioned answers Write formula non-volatile memory module and memorizer control circuit unit.Connecting interface unit is to be electrically connected to a host System.Memorizer control circuit unit is electrically connected to connecting interface unit and reproducible nonvolatile memorizer module, To write first data into multiple first storage units into the storage unit, and read according to a reading voltage First storage unit, to judge that each first storage unit is to belong to first state or the second state.Memory control electricity Road unit obtains duplicative to calculate first number of the first storage unit for belonging to first state according to first number The first time information of non-volatile memory module.
In an exemplary embodiment, above-mentioned memorizer control circuit unit is write first data into the first storage unit Operation further includes：Memorizer control circuit unit reads the first storage unit according to voltage is read, to judge that each first is deposited Storage unit is to belong to first state or the second state, and records second of the first storage unit for belonging to first state Number.Memorizer control circuit unit is to obtain first time information according to the difference between first number and second number.Wherein One temporal information is to estimate the first data of write-in to the first storage unit elapsed time of reading.
In an exemplary embodiment, above-mentioned memorizer control circuit unit is also being written the second data to can make carbon copies Formula non-volatile memory module, and record first time information.Wherein first time information is to estimate write-in first Data were extremely written for the second data elapsed time.
In an exemplary embodiment, above-mentioned memorizer control circuit unit is also receiving the reading from host system The second data are read in instruction, instruction.Memorizer control circuit unit also to according to read voltage re-read the first storage Unit to judge that the first storage unit is to belong to first state or the second state, calculates the first storage for belonging to first state The third number of unit, and according to the second temporal information of third number acquirement reproducible nonvolatile memorizer module. Second temporal information is to estimate the first data of write-in to re-reading for the first storage unit elapsed time.Memory control Circuit unit processed is also to according to the second temporal information and first time information acquirement third temporal information.Third temporal information is To estimate the second data of write-in to the second data elapsed time of reading.
In an exemplary embodiment, above-mentioned memorizer control circuit unit also to according to third temporal information determine to The number of a few first voltage, and the second data are read according to first voltage.
In an exemplary embodiment, first storage unit of each above-mentioned is located on a bit line, and each compares Special line, which reacts on, reads one sensing electric current of voltage generation.Each storage unit is the sensing according to caused by each bit line Voltage level on electric current or each bit line, which is judged, belongs to first state or the second state.
In an exemplary embodiment, above-mentioned memorizer control circuit unit is that first number is inputted a look-up table, and And the output of look-up table is obtained using as first time information.
An exemplary embodiment of the invention proposes a kind of memorizer control circuit unit.It is non-volatile for above-mentioned duplicative Property memory module.Memorizer control circuit unit includes host interface, memory interface and memory management circuitry.Host connects Mouth is to be electrically connected to host system.Memory interface is to be electrically connected to type nonvolatile mould Block.Memory management circuitry is electrically connected to host interface and memory interface, is deposited to write first data into described Multiple first storage units in storage unit, and the first storage unit is read according to a reading voltage, to judge each First storage unit is to belong to first state or the second state.Memory management circuitry also belongs to first state to calculate First number of the first storage unit, and according to the first time of first number acquirement reproducible nonvolatile memorizer module Information.
In an exemplary embodiment, above-mentioned memory management circuitry is write first data into the operation of the first storage unit It further includes：Memory management circuitry reads the first storage unit according to voltage is read, to judge that each first storage unit is Belong to first state or the second state, and record second number of the first storage unit for belonging to first state.Memory The operation that management circuit obtains first time information according to first number includes：Memory management circuitry is according to first number and Difference between two numbers obtains first time information, and wherein first time information is to estimate the first data of write-in to reading the One storage unit elapsed time.
In an exemplary embodiment, above-mentioned memory management circuitry is also non-to duplicative being written the second data Volatile, and record first time information.First time information is to estimate the first data of write-in to writing Entered for the second data elapsed time.
In an exemplary embodiment, above-mentioned memory management circuitry also refers to receive the reading from host system It enables, the second data are read in instruction.Memory management circuitry also to according to read voltage re-read the first storage unit, with It is to belong to first state or the second state to judge the first storage unit, calculates the of the first storage unit for belonging to first state Three numbers, and according to the second temporal information of third number acquirement reproducible nonvolatile memorizer module.Second time Information is to estimate the first data of write-in to re-reading for the first storage unit elapsed time.Memory management circuitry is also To obtain third temporal information according to the second temporal information and first time information, wherein third temporal information is to estimate The second data are written to the second data elapsed time of reading.
In an exemplary embodiment, above-mentioned memory management circuitry is non-volatile according to third temporal information acquirement duplicative The operation of the second data in property memory module includes：Memory management circuitry determines at least one according to third temporal information The number of first voltage, and the second data are read according to first voltage.
In an exemplary embodiment, first number is inputted a look-up table by above-mentioned memory management circuitry, and is obtained The output of look-up table is using as first time information.
Based on time estimating and measuring method, memory storage apparatus and memory control above-mentioned, that exemplary embodiment of the present invention proposes Circuit unit processed, can be according to the characteristic of reproducible nonvolatile memorizer module in itself, to estimate temporal information.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and coordinate institute's accompanying drawings It is described in detail below.
Description of the drawings
Figure 1A is according to the host system and memory storage apparatus shown by an exemplary embodiment；
Figure 1B is shown according to computer, input/output device and the memory storage apparatus shown by an exemplary embodiment It is intended to；
Fig. 1 C are according to the host system and the schematic diagram of memory storage apparatus shown by an exemplary embodiment；
Fig. 2 is the schematic block diagram for showing memory storage apparatus shown in figure 1A；
Fig. 3 is the vertical view of a NAND string according to shown by an exemplary embodiment；
Fig. 4 is the equivalent circuit diagram of a NAND string according to shown by an exemplary embodiment；
Fig. 5 is the side view according to the NAND string shown by an exemplary embodiment；
Fig. 6 is the schematic diagram that an entity erased cell is shown according to an exemplary embodiment；
Fig. 7 is the schematic block diagram according to the memory control circuit unit shown by an exemplary embodiment；
Fig. 8 is the voltage sequence diagram for showing to read storage unit according to an exemplary embodiment；
Fig. 9 is to show to read voltage according to an exemplary embodiment and sense the graph of relation between electric current；
Figure 10 A~Figure 10 C are the critical voltage distribution maps that multiple first storage units are shown according to an exemplary embodiment；
Figure 11 is the number and temporal information that the first storage unit for belonging to first state is shown according to an exemplary embodiment Graph of relation between the time estimated；
Figure 12 is the flow chart that time estimating and measuring method is shown according to an exemplary embodiment.
Reference sign：
1000：Host system；
1100：Computer；
1102：Microprocessor；
1104：Random access memory (RAM)；
1106：Input/output (I/O) device；
1108：System bus；
1110：Data transmission interface；
1202：Slide-mouse；
1204：Keyboard；
1206：Display；
1208：Printer；
1212：Portable disk；
1214：Memory card；
1216：Solid state disk；
1310：Digital camera；
1312：SD card；
1314：Mmc card；
1316：Memory stick；
1318：CF cards；
1320：Embedded storage device；
100：Memory storage apparatus；
102：Connecting interface unit；
104：Memorizer control circuit unit；
106：Reproducible nonvolatile memorizer module；
108 (0)~108 (R)：Entity erased cell；
300、302、304、306、320、322、601、606：Transistor；
320CG、300CG、302CG、304CG、306CG、322CG：Control grid；
300FG、302FG、304FG、306FG：Floating grid；
326、328：Contact point；
340：Substrate；
330、332、334、336、338：Polysilicon layer；
360th, ST0~STN：NAND string；
SGD、SGS：Selection line；
WL0~WL3：Character line；
BL (0)~BL (N)：Bit line；
602~605：Storage unit；
610：Source electrode line；
702：Memory management circuitry；
704：Host interface；
706：Memory interface；
708：Buffer storage；
710：Electric power management circuit；
712：Error checking and correcting circuit；
T1~t8：Time point；
IFG：Sense electric current；
VFG：Critical voltage；
1020、1030：Curve；
1040、1050、1060：Region；
Vread、V’read：Read voltage；
S1201~S1203：Step.
Specific embodiment
In general, memory storage apparatus (also referred to as, storage system) is including duplicative non-volatile memories Device module and controller (also referred to as, control circuit).Being commonly stored device storage device is used together with host system, so that host System can write data into memory storage apparatus or be read from memory storage apparatus data.
Figure 1A is according to the host system and memory storage apparatus shown by an exemplary embodiment.Figure 1B is according to a model The schematic diagram of computer, input/output device and memory storage apparatus shown by example embodiment.Fig. 1 C are according to example reality Apply the schematic diagram of the host system and memory storage apparatus shown by example.
Figure 1A is please referred to, host system 1000 generally comprises computer 1100 and input/output (input/output, I/O) Device 1106.Computer 1100 includes microprocessor 1102, random access memory (random access memory, RAM) 1104th, system bus 1108 and data transmission interface 1110.Input/output device 1106 includes slide-mouse 1202, the key such as Figure 1B Disk 1204, display 1206 and printer 1208.It will be appreciated that the unrestricted input/output device of device shown in Figure 1B 1106, input/output device 1106 can further include other devices.
In embodiments of the present invention, memory storage apparatus 100 is by data transmission interface 1110 and host system 1000 other elements are electrically connected.Pass through microprocessor 1102, random access memory 1104 and input/output device 1106 Running can write data into memory storage apparatus 100 or read data from memory storage apparatus 100.For example, it deposits Reservoir storage device 100 can be Portable disk 1212, memory card 1214 or solid state disk (Solid State as shown in Figure 1B Drive, SSD) 1216 grades type nonvolatile storage device.
In general, host system 1000 is that can substantially coordinate to store appointing for data with memory storage apparatus 100 Meaning system.Although in this exemplary embodiment, host system 1000 is explained with computer system, however, of the invention another Host system 1000 can be digital camera, video camera, communication device, audio player or video playing in one exemplary embodiment The systems such as device.For example, when host system is digital camera (video camera) 1310, type nonvolatile storage dress It puts then as its used SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF cards 1318 or embedded Storage device 1320 (as shown in Figure 1 C).Embedded storage device 1320 include embedded multi-media card (Embedded MMC, eMMC).It is noted that embedded multi-media card is directly to be electrically connected on the substrate of host system.
Fig. 2 is the schematic block diagram for showing memory storage apparatus shown in figure 1A.
Fig. 2 is please referred to, memory storage apparatus 100 includes connecting interface unit 102, memorizer control circuit unit 104 With reproducible nonvolatile memorizer module 106.
In this exemplary embodiment, connecting interface unit 102 is compatible with Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the present invention is not limited thereto, even Connection interface unit 102 can also meet parallel advanced technology annex (Parallel Advanced Technology Attachment, PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) Standard, secure digital (Secure Digital, SD) interface standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) Interface standard, two generation of ultrahigh speed (Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory Stick, MS) interface standard, multimedia storage card (Multi Media Card, MMC) interface standard, down enter formula multimedia storage card (Embedded Multimedia Card, eMMC) interface standard, general flash memory (Universal Flash Storage, UFS) interface standard, compact flash (Compact Flash, CF) interface standard, integrated form driving electrical interface (Integrated Device Electronics, IDE) standard or other suitable standards.Connecting interface unit 102 can be with depositing Memory control circuit unit 104 is encapsulated in a chip or connecting interface unit 102 is to be laid in one to include memory control Outside the chip of circuit unit 104 processed.
Memorizer control circuit unit 104 is performing multiple logic gates or control with hardware pattern or firmware pattern implementation System instruction, and data are carried out in reproducible nonvolatile memorizer module 106 according to the instruction of host system 1000 The runnings such as be written, read and erase.
Reproducible nonvolatile memorizer module 106 is electrically connected to memorizer control circuit unit 104, and uses The data being written with host system 1000.Reproducible nonvolatile memorizer module 106 has entity erased cell 108 (0)~108 (R).For example, entity erased cell 108 (0)~108 (R) can belong to same memory crystal grain (die) or Belong to different memory crystal grains.By taking NAND type flash memory as an example, an entity erased cell can include multiple NAND strings (NAND string).Each NAND string can include multiple transistors being one another in series.Fig. 3 is according to an exemplary embodiment institute The vertical view of one NAND string is shown.Fig. 4 is the equivalent circuit diagram of a NAND string according to shown by an exemplary embodiment.It please join According to Fig. 3 and Fig. 4, NAND string 360 includes transistor 320,300,302,304,306 and 322.From contact point 326 to contact point Circuit between 328 is alternatively referred to as a bit line.Control grid 320CG on transistor 320 is electrically connected to selection line SGD；Control grid 300CG on transistor 300 is electrically connected to character line WL3；Control grid on transistor 302 302CG is electrically connected to character line WL2；Control grid 304CG on transistor 304 is electrically connected to character line WL1；It is brilliant Control grid 306CG on body pipe 306 is electrically connected to character line WL0；Control grid 322CG on transistor 322 is electricity Property is connected to selection line SGS.Each transistor 300,302,304 and 306 further includes a charge benefit and catches layer.Charge benefit catches layer It is to store electronics or hole.In this exemplary embodiment, electric charge capture layer is referred to as floating grid (floating Gate), material includes the polysilicon through mixing.However, in another exemplary embodiment, electric charge capture layer may include an oxygen SiClx-silicon-nitride and silicon oxide composite bed or other can be used to storage electronics or hole material, it is of the invention and not subject to the limits. In the exemplary embodiment of Fig. 3, transistor 300 has floating grid 300FG；Transistor 302 has floating grid 302FG；It is brilliant Body pipe 304 has floating grid 304FG；Transistor 306 has floating grid 306FG.Here, transistor 300,302,304 with 306 are also referred to as storage unit.
Fig. 5 is the side view according to the NAND string shown by an exemplary embodiment.Please refer to Fig. 3~Fig. 5, NAND string 360 It is provided in substrate 340.Control grid 300CG, 302CG, 304CG and 306CG be separately positioned on floating grid 300FG, On 302FG, 304FG and 306FG.Control grid 300CG, 302CG, 304CG, 306CG and floating grid 300FG, 302FG, Dielectric layer is provided between 304FG, 306FG.It is then set between floating grid 300FG, 302FG, 304FG, 306FG and substrate 340 Oxide layer is put.Neighbouring transistor can share the polysilicon layer 330,332,334,336 and 338 through mixing, and one in Fig. 5 A polysilicon layer can form source electrode or the drain electrode of transistor.When to write the data to (also referred to as program) to transistor 300, 302nd, 304 and 306 when, appropriate voltage can be applied on control grid 320CG and 322CG so that transistor 320 and 322 It can be switched on；And an electric current is had between contact point 326 and contact point 328.One write-in voltage can be applied in and be intended to be compiled Control grid on the transistor of journey, herein for controlling grid 302CG so that electronics or hole meeting in above-mentioned electric current It is moved to floating grid 302FG.After electronics or hole are by injection floating grid 302FG, the critical voltage of transistor 302 It can change, thereby can equally store one or more bits.It is worth noting that, in other exemplary embodiments, NAND String 360 can also include more storage units, and the present invention is not intended to limit the number of storage unit in a NAND string.In addition, Fig. 3~Fig. 5 is an example, and the present invention is not intended to limit storage unit in reproducible nonvolatile memorizer module 106 The electrical connection of structure or circuit.For example, in an exemplary embodiment, multiple storage units are to push away each other repeatedly, thereby Form three-dimensional flash memory.
Fig. 6 is the schematic diagram that an entity erased cell is shown according to an exemplary embodiment.
Fig. 6 is please referred to, by taking entity erased cell 108 (0) as an example, entity erased cell 108 (0) includes multiple NAND strings ST0~STN.NAND string ST0 includes transistor 601,606 and storage unit 602~605.NAND string ST0~STN's and Fig. 4 NAND string 360 is similar, and details are not described herein.Entity erased cell 108 (0) also include a plurality of character line WL0~WL3 with it is a plurality of Bit line BL (0)~BL (N).Each storage unit in entity erased cell 108 (0) can be located at a character line and one On bit line.Multiple storage units on same character line can form one or more entity programming units.Specifically, if Each storage unit can store x bit, then multiple storage units on same character line can at least form x entity and compile Cheng Danyuan, wherein x are positive integer.If positive integer x, more than 1, x entity programming unit on same character line can also be divided Class is lower entity programming unit and upper entity programming unit.However, the present invention is not intended to limit the numerical value of positive integer x.In general, The writing speed of lower entity programming unit can be more than the writing speed of upper entity programming unit.In this exemplary embodiment, entity Programming unit is the minimum unit of programming.That is, entity programming unit is the minimum unit that data are written.For example, entity programming is single Member is physical page or entity fan (sector).If entity programming unit is physical page, each entity programming unit Generally include data bit area and redundancy ratio special zone.Data bit area is fanned comprising multiple entities, to store the data of user, And redundancy ratio special zone is to the data (for example, error correcting code) of storage system.In this exemplary embodiment, each data ratio Special zone includes 32 entities and fans, and the size of an entity fan is 512 bytes (byte, B).However, in other exemplary embodiments In, 8,16 or number more or fewer entities fan are also may include in data bit area, the present invention is not intended to limit entity fan Size and number.
On the other hand, NAND string ST0~STN is electrically connected to source electrode line 610.When entity erased cell 108 (0) will quilt When erasing, a substrate that voltage can be applied in entity erased cell 108 (0) of erasing so that entity erased cell 108 (0) electronics or hole in all floating grids can all leave affiliated floating grid.It is real in this exemplary embodiment Body erased cell is the least unit erased.That is, each entity erased cell contain minimal amount be erased together deposit Storage unit.For example, entity erased cell is solid block.
In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is single-order storage unit (Single Level Cell, SLC) NAND type flash memory module, i.e. 1 bit can be stored in a storage unit.It is however, of the invention It is without being limited thereto, reproducible nonvolatile memorizer module 106 may also be multi-level cell memory (Multi Level Cell, MLC) NAND type flash memory module, Complex Order storage unit (Trinary Level Cell, TLC) NAND type flash Device module, other flash memory modules or other memory modules with the same characteristics.
Fig. 7 is the schematic block diagram according to the memorizer control circuit unit shown by an exemplary embodiment.
Fig. 7 is please referred to, Memory Controller 104 includes memory management circuitry 702, host interface 704 connects with memory Mouth 706.
Memory management circuitry 702 to control memory controller 104 overall operation.Specifically, memory pipe Managing circuit 702 has multiple control instructions, and when memory storage apparatus 100 operates, these control instructions can be performed To carry out the write-in of data, read and the runnings such as erase.
Host interface 704 is electrically connected to memory management circuitry 702 and to receive and identify host system 1000 instructions transmitted and data.That is, the instruction that host system 1000 is transmitted can pass through host interface with data 704 are sent to memory management circuitry 702.In this exemplary embodiment, host interface 704 is compatible with SATA standard.So And, it should be understood that the present invention is not limited thereto, and host interface 704 can also be compatible with PATA standards, IEEE 1394 is marked Standard, PCI Express standards, USB standard, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC mark Standard, UFS standards, CF standards, IDE standards or other suitable data transmission standards.
Memory interface 706 is electrically connected to memory management circuitry 702 and non-volatile to access duplicative Property memory module 106.That is, the data for being intended to be written to reproducible nonvolatile memorizer module 106 can be via depositing Memory interface 706 is converted to the 106 receptible form of institute of reproducible nonvolatile memorizer module.
In an exemplary embodiment of the invention, Memory Controller 104 further includes buffer storage 708, power management electricity Road 710 and error checking and correcting circuit 712.
Buffer storage 708 is electrically connected to memory management circuitry 702 and is configured to temporarily store come from host system 1000 data and the data for instructing or coming from reproducible nonvolatile memorizer module 106.
Electric power management circuit 710 is electrically connected to memory management circuitry 702 and stores to control memory fill Put 100 power supply.
Error checking is electrically connected to memory management circuitry 702 and to perform wrong inspection with correcting circuit 712 It looks into correction program to ensure the correctness of data.Specifically, when memory management circuitry 702 connects from host system 1000 When receiving write instruction, error checking generates corresponding mistake more with the data that correcting circuit 712 can be this corresponding write instruction Code (Error Correcting Code, ECC Code), and memory management circuitry 702 can be by this corresponding write instruction Data be written with corresponding error correcting code into reproducible nonvolatile memorizer module 106.Later, when memory pipe Reason circuit 702 can read the corresponding mistake of this data simultaneously when data are read from reproducible nonvolatile memorizer module 106 Accidentally more code, and error checking can perform read data mistake inspection with correcting circuit 712 according to this error correcting code It looks into and correction program.
Fig. 8 is the voltage sequence diagram for showing to read storage unit according to an exemplary embodiment.
Fig. 6 and Fig. 8 are please referred to, it is assumed herein that transfer signal non-volatile to duplicative for memory management circuitry 702 Memory module 106, to read the data in storage unit 605.Reproducible nonvolatile memorizer module 106 can accordingly Change selection line SGD, SGS, character line WL0~WL3 and the voltage level on bit line BL (0)~BL (N), thereby detection storage The state of unit 605.Specifically, voltage all in the starting stage, Fig. 8 is all low level.In time point t1, selection line Voltage level on SGD can be pulled up (raised) so that transistor 601 is connected.On time point t2, character line WL1~WL3 Voltage level can be pulled up so that storage unit 602~604 is connected, and one is read voltage and can be applied on character line WL0. Voltage level on time point t4, bit line BL (0) can be pulled up to a pre-charge level (pre-charge level). Voltage level on time point t6, selection line SGS can be pulled up that transistor 606 is connected.Reaction is in storage unit 605 Voltage is read, a sensing electric current can be generated on bit line BL (0).According to the size of this sensing electric current, the electricity of bit line BL (0) Voltage level may decline (drop).Specifically, if the reading voltage on character line WL0 is more than facing for storage unit 605 Boundary's voltage, then storage unit 605 can be switched on and the sensing electric current on bit line BL (0) can cause electricity on bit line BL (0) Voltage level declines.If the reading voltage on character line WL0 is not greater than the critical voltage of storage unit 605, storage unit 605 can end and the voltage level on bit line BL (0) can remain unchanged.In general, bit line BL (0) can electrically connect An amplifier is connected to, to detect the voltage level on bit line BL (0).It is worth noting that, Fig. 8 is an example, this The voltage level being not intended to limit on selection line SGD, SGS, character line WL0~3 and bit line BL (0)~BL (N) is invented to be pulled up Time with sequence.
In the exemplary embodiment of Fig. 8, the voltage level on bit line BL (0) can be used for judging that storage unit 605 is Conducting or cut-off, and reproducible nonvolatile memorizer module 106 can generate corresponding verification bit.For example, verification ratio Special " 1 " represents cut-off, and verifies bit " 0 " and represent conducting.It should be noted, however, that with the increase for reading voltage, it is practical Upper storage unit 605 can't become being connected from cut-off suddenly.Therefore, bit is verified not necessarily in another exemplary embodiment Represent the state of cut-off or conducting.Fig. 9 is to show to read voltage according to an exemplary embodiment and sense the relationship between electric current Curve graph.As shown in figure 9, with the increase for reading voltage, sensing electric current can gradually increase.Therefore, in an exemplary embodiment In, reproducible nonvolatile memorizer module 106 setting can verify ratio when sensing electric current and being more than first critical value Specially for " 1 ", when sensing electric current and being less than second critical value if set verification bit as " 0 ".First critical value is faced with second Dividing value can be identical or different, of the invention and not subject to the limits.Alternatively, as shown in figure 8, type nonvolatile mould Block 106 can just set verification bit as " 1 " after the voltage level on bit line BL (0) decrease beyond a critical value. For another angle, verification bit can be used for representing whether the critical voltage of storage unit 605 is more than what is be applied in Read voltage.For example, in fig.9, if sensing electric current is more than current value IFG, then it represents that it reads voltage and is more than critical voltage VFGAnd Verify that bit is " 1 ".However, since sensing electric current is gradually to increase, according to different judgment methods, critical voltage VFG Numerical value can also differ.The present invention is not intended to limit the judgment method of critical voltage in storage unit.In this exemplary embodiment, Verification bit can determine or according to the sensing size of electric current, variable quantity or arbitrary electrical characteristic according to bit line On voltage level determine, but the method that the present invention is not intended to limit decision.
This verification bit can be sent to memory management circuitry 702 by reproducible nonvolatile memorizer module 106.It deposits Reservoir management circuit 702 can be to belong to first state or the second state according to this verification bit decision storage unit 605.Below For the sake of for convenience of description, the first state of storage unit represents whether applied reading voltage is more than storage list with the second state The critical voltage of member.It is to be noted that as verification is than peculiar different deciding means, first state can generation with the second state The different meaning of table, the present invention are not intended to limit first state and the meaning representated by the second state.In other words, storage unit is root First state or the second state are either judged as according to the voltage level on bit line according to sensing electric current.In addition, at it In his exemplary embodiment, reproducible nonvolatile memorizer module 106 can also transmit other signals, character, symbol or It is that number replaces above-mentioned verification bit to memory management circuitry 702, it is of the invention and not subject to the limits.
Figure 10 A~Figure 10 C are the critical voltage distribution maps that multiple first storage units are shown according to an exemplary embodiment.
Figure 10 A~Figure 10 C are please referred to, memory management circuitry 702 can be first write first data into the multiple first storages Unit, Figure 10 A are critical voltage distribution maps when the first data are written into the first storage unit, and wherein horizontal axis is critical electricity Pressure, and the longitudinal axis is storage unit number.These first storage units may belong to identical entity erased cell or different Entity erased cell, it is of the invention and not subject to the limits.The present invention does not limit the number of the first storage unit yet.In this exemplary embodiment In, all bits are all identical in the first data.But in another exemplary embodiment, the first data can also be that random number generates Or generated with any other mode, the present invention is not intended to limit the content of the first data.In addition, the first data can be deposited in memory Storage device 100 is written into when being formatted or is written at any other time point, of the invention and not subject to the limits.
When the first data are written into, the distribution such as curve 1020 of the critical voltage of the first storage unit.However, with when Between increase, although the first data are still stored in the first storage unit, the critical voltage of the first storage unit can decline. Critical voltage and the relationship of time can be represented with below equation (1).
VFG(t)=β tox/ln{(Aβ·t/toxCT)+exp(βtox/VFG(t=0)) } ... (1)
A and β is constant.T represents the time.toxRepresent the thickness of oxide layer in storage unit.VFG(t=0) represent that the time is Critical voltage when 0.VFG(t) critical voltage when time is t is represented.CTRepresent the capacitance of oxide layer in storage unit.From Equation (1) it can be seen that, with the increase of time t, critical voltage VFG(t) it can reduce.For example, as shown in Figure 10 B, passing through The distribution of the critical voltage of the first storage unit can be curve 1030 after after a period of time.In general, compared to curve 1020, curve 1030 past can move to left or become more flat.
In this exemplary embodiment, if memory management circuitry 702 will obtain the time t in aforesaid equation (1), storage Device management circuit 702 can be according to reading voltage VreadThese the first storage units are read, to judge that each first storage is single Member is to belong to first state or the second state.Memory management circuitry 702 can calculate the first storage list for belonging to first state The number (also referred to as first number) of member, and reproducible nonvolatile memorizer module 106 is obtained according to this first number Temporal information (also referred to as first time information).In this exemplary embodiment, if the first storage unit belongs to first state, table Show that the critical voltage of the first storage unit is less than or equal to and read voltage Vread.If the first storage unit belongs to the second state, table Show that the critical voltage of the first storage unit is more than and read voltage Vread.Therefore, first number represents that in region 1,040 first deposits The number of storage unit.(following label is t to first time information1) it is to estimate to be written into this from the first data A little first storage units (such as time point of Figure 10 A), to read voltage VreadTo read the first storage unit have passed through how many Time (such as time point of Figure 10 B).Therefore, if first number is bigger, with first time information t1Estimate the time come It can be bigger.For example, memory management circuitry 702 can be come according to 1020, first numbers of curve and above-mentioned equation (1) Calculate time t.Memory management circuitry 702 can obtain song with multiple reading voltages to scan these first storage units Line 1020 or curve 1020 is obtained according to the hypothesis or model established in advance, it is of the invention and not subject to the limits.Another In exemplary embodiment, first number and first time information t1Between relationship can be calculated in advance and be stored in a lookup In table.Memory management circuitry 702 can by this look-up table of first number input, and obtain the output of this look-up table using as when Between information t1.Can it be 10 years with the maximum value of setting time t, and quantified with 8 bits for example, when establishing look-up table This 10 years, that is, the temporal information for being recorded in look-up table is represented with 8 bits.Therefore the temporal information by look-up table output multiplies Upper a certain constant can estimate above-mentioned time t.However, it is come table with several bits that the present invention, which is not intended to limit temporal information, Show, also do not limit and which kind of mode to estimate time t with.
In another exemplary embodiment, when writing first data into the first storage unit (such as time point of Figure 10 A), Memory management circuitry 702 also can be according to reading voltage V 'readRead these the first storage units, and judge each One storage unit is to belong to first state or the second state.Memory management circuitry 702, which can record, belongs to the of first state The number (also referred to as second number) of one storage unit.For example, second number is the number of the first storage unit in region 1050.It deposits Reservoir management circuit 702 can obtain temporal information t according to the difference between this second number and above-mentioned first number1.At this time Between information t1It is to estimate from Figure 10 A to Figure 10 B elapsed times.If the difference between first number and second number is got over Greatly, then estimating the time come can be bigger.In the same manner, memory management circuitry 702 can also be by first number and second Difference between number is input to a look-up table, and obtains the output of this look-up table using as temporal information t1.In other words, it deposits Reservoir management circuit 702 only just can obtain temporal information t according to first number1, can also be according to first number and second Several differences obtains temporal information t1, it is of the invention and not subject to the limits.
As it was earlier mentioned, the present invention is not intended to limit the meaning of first state and the second state.In above-mentioned exemplary embodiment In, if the first storage unit belongs to first state, then it represents that the critical voltage of the first storage unit, which is less than or equal to, reads voltage Vread；If the first storage unit belongs to the second state, represent that the critical voltage of the first storage unit is more than and read voltage Vread.So And in another exemplary embodiment, if the first storage unit belongs to first state, then it represents that the critical voltage of the first storage unit More than reading voltage Vread；If the first storage unit belongs to the second state, represent the first storage unit critical voltage be less than or Equal to reading voltage Vread.In the same manner, memory management circuitry 702 can calculate for the first storage unit for belonging to first state Number (also referred to as first number).In the case, when first number is smaller, then first time information t1Estimate the time come It can be bigger.On the other hand, in the exemplary embodiment of Figure 10 A~Figure 10 B, voltage V is readreadIt is in curve 1020,1030 Left side.It can also be on the right side of curve 1020,1030 (for example, reading voltage V ' however, reading voltageread)。
In an exemplary embodiment, for being written into one or more pens of reproducible nonvolatile memorizer module 106 Data, memory management circuitry 702 can note down corresponding temporal information.Specifically, under the time point of Figure 10 B, memory One second data are written into reproducible nonvolatile memorizer module 106 management circuit 702, at this time memory management electricity Road 702 can obtain temporal information t according to above-mentioned method1.Therefore, acquired temporal information t1It is to estimate from write-in the One data (such as time point of Figure 10 A) to write-in the second data elapsed time.In an exemplary embodiment, for each Programmed entity programming unit, memory management circuitry 702 can all note down corresponding temporal information.However, memory management Circuit 702 can also note down each entity fan or the programmed temporal information of entity erased cell, and the present invention is not herein Limit.
The temporal information of above-mentioned record can be used for determining how to read being stored in type nonvolatile mould The second data in block 106.As an example it is assumed that being written into the second data and after after a period of time, the first storage is single The critical voltage of member is distributed such as Figure 10 C, and memory management circuitry 702 has received the reading instruction from host system at this time, and And this reads the logical address belonging to instruction instruction the second data of reading.After receiving this and reading instruction, memory management electricity It road 702 can be according to reading voltage VreadThe first storage unit is re-read, to judge that these first storage units are to belong to first State or the second state.Memory management circuitry 702 can calculate the number for the first storage unit for belonging to first state (also referred to as Third number), and according to this third number, to obtain one second temporal information, (following label is t2).For example, Third number is the number of the first storage unit in region 1060, and temporal information t2It is to estimate from the first data are written (such as time point of Figure 10 A) is to re-reading the first storage unit (such as time point of Figure 10 C) elapsed time.Memory pipe Managing circuit 702 can be according to temporal information t2With temporal information t1Obtain a third temporal information.For example, memory management circuitry 702 can be by temporal information t2Subtract temporal information t1To obtain third temporal information.Therefore, this third temporal information is to estimate It surveys from the second data of write-in to reading for the second data elapsed time (that is, to be stored in duplicative non-volatile for the second data 106 elapsed time of memory module).If the second data are stored in reproducible nonvolatile memorizer module 106 and are passed through The time crossed is longer, then wrong probability occurs for the second data bigger.Therefore, when memory management circuitry 702 can be according to third Between information obtain the second data in reproducible nonvolatile memorizer module 106.For example, when the second data are written into It has passed through the coded program of an error correcting code.Memory management circuitry 702 can obtain at least according to third temporal information One first voltage, and the second data are read according to first voltage.If the time that third temporal information is estimated is bigger (that is, the probability of the second data generation mistake is bigger or including more error bits), then need more information to strengthen correcting The ability of mistake.Therefore, in an exemplary embodiment, if the time that third temporal information is estimated is bigger, required One number of voltages is more, can thereby obtain more verification bits (also referred to as soft bit information).These verification bits can be used To perform an error correcting code, e.g. low density parity check code (low density parity code, LDPC).One As for, if the number of first voltage is more, the corrigendum ability of low density parity check code can be better.If it uses low close Parity check code is spent, in another exemplary embodiment, third temporal information can also be used to determine be with hard bit pattern (hard Bit mode) or soft bit pattern (soft bit mode) decode.
In above-mentioned exemplary embodiment, be by the state of the first storage unit come deduce that the second data are stored in can 106 elapsed time of manifolding formula non-volatile memory module.However, in another exemplary embodiment, can also be passed through The state of the storage unit that two data are stored in itself estimates the time.For example, in the time point of Figure 10 B, the second number According to being written into multiple second storage units, and memory management circuitry 702 can read voltage to read the according to one Two storage units and the number for recording the second storage unit for belonging to first state.At the time point of Figure 10 C, memory management electricity Road 702 can read the second storage unit to obtain the second storage unit for belonging to first state at this time further according to voltage is read Number.According to the two numbers, memory management circuitry 702, which can be obtained, to be written into from the second data to the second data institute of reading Elapsed time.
It is noted that in some cases, the time t that aforesaid equation (1) is calculated might have error.Example Such as, if reproducible nonvolatile memorizer module 106 is in the environment of relatively-high temperature, the time t calculated can be compared with Greatly.However, in this exemplary embodiment, since the first data are stored in the second data, identical duplicative is non-volatile to be deposited In memory modules 106, therefore temporal information acquired in aforementioned manners can accurately judge that mistake occurs for the second data Probability.
In the exemplary embodiment of Figure 10 A~Figure 10 C, memory management circuitry 702 can use identical reading voltage VreadTo read the first storage unit to obtain corresponding temporal information.However, in another exemplary embodiment, memory pipe The point in different times of circuit 702 is managed, the first storage unit can be read with different reading voltage.For example, with difference Reading voltage come after reading the first storage unit, memory management circuitry 702 can be according to used reading voltage, above-mentioned Equation (1) and Figure 10 A in curve 1020 obtain temporal information, it is of the invention and not subject to the limits.
Figure 11 is the number and temporal information that the first storage unit for belonging to first state is shown according to an exemplary embodiment Graph of relation between the time estimated.
Figure 10 A and Figure 11 are please referred to, in an exemplary embodiment, memory management circuitry 702 can set reading voltage VreadPositioned at a fringe region of curve 1020 so that as time goes by, belong to of the first storage unit of first state Number is similar to direct ratio (as shown in figure 11) with the time that temporal information is estimated.Specifically, memory management circuitry 702 can Function according to representated by curve 1020 in above-mentioned equation (1) and Figure 10 A obtains a compound function (composition function).Memory management circuitry 702 can take this compound function the integration of critical voltage to take the second differential of time again, And the result after differential is minimized and reads voltage V to obtainread.For example, memory management circuitry 702 can be according to lower section Formula (2) calculates with (3) and reads voltage Vread.Wherein DF (Vth) for the function representated by curve 1020, γ is constant.
Figure 12 is the flow chart that time estimating and measuring method is shown according to an exemplary embodiment.
Figure 12 is please referred to, in step S1201, is write first data into multiple first storage units.In step S1202 In, the first storage unit is read according to a reading voltage, with judge each first storage unit be belong to first state or It is the second state.In step S1203, the number for the first storage unit for belonging to first state is calculated, and is taken according to this number Obtain the temporal information of reproducible nonvolatile memorizer module.However, each step has been described in detail as above in Figure 12, herein just It repeats no more.It is worth noting that, each step can be implemented as multiple procedure codes or circuit in Figure 12, the present invention is not herein Limit.In addition, the method for Figure 12 can arrange in pairs or groups, above example uses, and can also be used alone, of the invention and not subject to the limits.
In conclusion time estimating and measuring method, memory storage apparatus and memory control that exemplary embodiment of the present invention proposes Circuit unit processed can belong to the number of first state to obtain temporal information, and without configurable clock generator with the first storage unit With additional power supply.In addition, due to being to obtain temporal information with reproducible nonvolatile memorizer module characteristic in itself, Therefore the time estimated is more accurate.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent Pipe is described in detail the present invention with reference to foregoing embodiments, it will be understood by those of ordinary skill in the art that：Its according to Can so modify to the technical solution recorded in foregoing embodiments either to which part or all technical features into Row equivalent replacement；And these modifications or replacement, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.

Claims (30)

  1. A kind of 1. time estimating and measuring method, for a reproducible nonvolatile memorizer module, which is characterized in that the duplicative Non-volatile memory module includes multiple storage units, including：
    One first data are written to multiple first storage units into those storage units；
    Those the first storage units are read according to a reading voltage, to judge that each of first storage unit is to belong to one the One state or one second state；And
    One first number of those the first storage units for belonging to the first state is calculated, and this can according to first number acquirement One first time information of manifolding formula non-volatile memory module, wherein, which is written to those the first storages The step of unit, includes：
    Those the first storage units are read according to the reading voltage, with judge each of first storage unit be belong to this first State or second state；And
    Record belongs to one second number of those the first storage units of the first state,
    Wherein, the step of obtaining the first time information according to first number includes：
    The first time information is obtained according to the difference between first number and second number, wherein the first time information is First data are written to reading those the first storage unit elapsed times to estimate.
  2. 2. time estimating and measuring method according to claim 1, which is characterized in that further include：
    One second data are written to the reproducible nonvolatile memorizer module；And
    Record the first time information, wherein the first time information be estimate be written first data to be written this second Data elapsed time.
  3. 3. time estimating and measuring method according to claim 2, which is characterized in that further include：
    It receives one from a host system and reads instruction, second data are read in wherein reading instruction instruction；
    Those the first storage units are re-read according to the reading voltage, with judge those first storage units be belong to this first State or second state, calculate belong to the first state those the first storage units a third number, and according to The third number obtains one second temporal information of the reproducible nonvolatile memorizer module, wherein second temporal information It is to estimate first data are written to re-reading those the first storage unit elapsed times；
    One third temporal information is obtained according to second temporal information and the first time information, the wherein third temporal information is Second data are written to reading the second data elapsed time to estimate.
  4. 4. time estimating and measuring method according to claim 3, which is characterized in that further include：
    The number of an at least first voltage is determined according to the third temporal information, and is read and is somebody's turn to do according to an at least first voltage Second data.
  5. 5. time estimating and measuring method according to claim 1, which is characterized in that each of first storage unit is located at a ratio On special line, and the reaction of each of bit line generates a sensing electric current in the reading voltage, which further includes：
    Voltage level according to caused by each of bit line on the sensing electric current or each of bit line, judges each Those first storage units are to belong to the first state or second state.
  6. A kind of 6. time estimating and measuring method, for a reproducible nonvolatile memorizer module, which is characterized in that the duplicative Non-volatile memory module includes multiple storage units, including：
    One first data are written to multiple first storage units into those storage units；
    Those the first storage units are read according to a reading voltage, to judge that each of first storage unit is to belong to one the One state or one second state；And
    One first number of those the first storage units for belonging to the first state is calculated, and first number input one is searched Table, obtains an output of the look-up table, and the output is multiplied by a constant using as first time information.
  7. 7. time estimating and measuring method according to claim 6, which is characterized in that further include：
    One second data are written to the reproducible nonvolatile memorizer module；And
    Record the first time information, wherein the first time information be estimate be written first data to be written this second Data elapsed time.
  8. 8. time estimating and measuring method according to claim 7, which is characterized in that further include：
    It receives one from a host system and reads instruction, second data are read in wherein reading instruction instruction；
    Those the first storage units are re-read according to the reading voltage, with judge those first storage units be belong to this first State or second state, calculate belong to the first state those the first storage units a third number, and according to The third number obtains one second temporal information of the reproducible nonvolatile memorizer module, wherein second temporal information It is to estimate first data are written to re-reading those the first storage unit elapsed times；
    One third temporal information is obtained according to second temporal information and the first time information, the wherein third temporal information is Second data are written to reading the second data elapsed time to estimate.
  9. 9. time estimating and measuring method according to claim 8, which is characterized in that further include：
    The number of an at least first voltage is determined according to the third temporal information, and is read and is somebody's turn to do according to an at least first voltage Second data.
  10. 10. time estimating and measuring method according to claim 6, which is characterized in that each of first storage unit is located at one On bit line, and the reaction of each of bit line generates a sensing electric current in the reading voltage, which also wraps It includes：
    Voltage level according to caused by each of bit line on the sensing electric current or each of bit line, judges each Those first storage units are to belong to the first state or second state.
  11. 11. a kind of memory storage apparatus, which is characterized in that including：
    One connecting interface unit, is electrically connected to a host system；
    One reproducible nonvolatile memorizer module, including multiple storage units；And
    One memorizer control circuit unit is electrically connected to the connecting interface unit and the type nonvolatile mould Block one first data are written multiple first storage units into those storage units, and reads voltage according to one Those the first storage units are read, to judge that each of first storage unit is to belong to a first state or one second shape State,
    Wherein, the memorizer control circuit unit is calculating the one first of those the first storage units for belonging to the first state Number, and a first time information of the reproducible nonvolatile memorizer module is obtained according to first number, wherein, it should First data are written to the operation of those the first storage units and further included by memorizer control circuit unit：
    The memorizer control circuit unit reads those the first storage units according to the reading voltage, to judge each of first Storage unit is to belong to the first state or second state, and records those the first storage lists for belonging to the first state One second number of member,
    Wherein, which includes according to the operation that first number obtains the first time information：
    The memorizer control circuit unit obtains the first time information according to the difference between first number and second number, Wherein the first time information is to estimate first data are written to reading those the first storage unit elapsed times.
  12. 12. memory storage apparatus according to claim 11, which is characterized in that the memorizer control circuit unit is also used Being written one second data to the reproducible nonvolatile memorizer module, and the first time information is recorded, wherein The first time information is to estimate first data are written to the second data elapsed time is written.
  13. 13. memory storage apparatus according to claim 12, which is characterized in that the memorizer control circuit unit is also used To receive the reading instruction from the host system, second data are read in wherein reading instruction instruction,
    Wherein, the memorizer control circuit unit according to the reading voltage also to re-read those the first storage units, to sentence Break those first storage units be to belong to the first state or second state, calculate belong to the first state those first One third number of storage unit, and obtain the one of the reproducible nonvolatile memorizer module according to the third number Two temporal informations, wherein second temporal information are to estimate that first data are written is single to those first storages are re-read First elapsed time,
    Wherein, the memorizer control circuit unit according to second temporal information and the first time information also obtaining one the Three temporal informations, wherein the third temporal information to estimate be written second data passed through to second data are read Time.
  14. 14. memory storage apparatus according to claim 13, which is characterized in that the memorizer control circuit unit is also used To determine the number of an at least first voltage according to the third temporal information, and according to an at least first voltage read this Two data.
  15. 15. memory storage apparatus according to claim 11, which is characterized in that each of first storage unit is located at On one bit line, and each bit line reacts on the reading voltage and generates a sensing electric current,
    Wherein, each of storage unit is the electricity on the sensing electric current or each bit line according to caused by each bit line Voltage level, which is judged, belongs to the first state or second state.
  16. 16. a kind of memory storage apparatus, which is characterized in that including：
    One connecting interface unit, is electrically connected to a host system；
    One reproducible nonvolatile memorizer module, including multiple storage units；And
    One memorizer control circuit unit is electrically connected to the connecting interface unit and the type nonvolatile mould Block one first data are written multiple first storage units into those storage units, and reads voltage according to one Those the first storage units are read, to judge that each of first storage unit is to belong to a first state or one second shape State,
    Wherein, the memorizer control circuit unit is calculating the one first of those the first storage units for belonging to the first state Number, wherein, which inputs a look-up table by first number, and obtains the one defeated of the look-up table Go out, and the output is multiplied by a constant using as first time information.
  17. 17. memory storage apparatus according to claim 16, which is characterized in that the memorizer control circuit unit is also used Being written one second data to the reproducible nonvolatile memorizer module, and the first time information is recorded, wherein The first time information is to estimate first data are written to the second data elapsed time is written.
  18. 18. memory storage apparatus according to claim 17, which is characterized in that the memorizer control circuit unit is also used To receive the reading instruction from the host system, second data are read in wherein reading instruction instruction,
    Wherein, the memorizer control circuit unit according to the reading voltage also to re-read those the first storage units, to sentence Break those first storage units be to belong to the first state or second state, calculate belong to the first state those first One third number of storage unit, and obtain the one of the reproducible nonvolatile memorizer module according to the third number Two temporal informations, wherein second temporal information are to estimate that first data are written is single to those first storages are re-read First elapsed time,
    Wherein, the memorizer control circuit unit according to second temporal information and the first time information also obtaining one the Three temporal informations, wherein the third temporal information to estimate be written second data passed through to second data are read Time.
  19. 19. memory storage apparatus according to claim 18, which is characterized in that the memorizer control circuit unit is also used To determine the number of an at least first voltage according to the third temporal information, and according to an at least first voltage read this Two data.
  20. 20. memory storage apparatus according to claim 16, which is characterized in that each of first storage unit is located at On one bit line, and each bit line reacts on the reading voltage and generates a sensing electric current,
    Wherein, each of storage unit is the electricity on the sensing electric current or each bit line according to caused by each bit line Voltage level, which is judged, belongs to the first state or second state.
  21. 21. a kind of memorizer control circuit unit, for a reproducible nonvolatile memorizer module, which is characterized in that should Reproducible nonvolatile memorizer module includes multiple storage units, which includes：
    One host interface is electrically connected to a host system；
    One memory interface is electrically connected to the reproducible nonvolatile memorizer module；And
    One memory management circuitry is electrically connected to the host interface and the memory interface, one first data to be written Multiple first storage units into those storage units, and those the first storage units are read according to a reading voltage, To judge that each of first storage unit is to belong to a first state or one second state,
    Wherein, the memory management circuitry is calculating the one first of those the first storage units for belonging to the first state It counts, and a first time information of the reproducible nonvolatile memorizer module is obtained according to first number,
    Wherein, which is written first data to the operation of those the first storage units and further includes：
    The memory management circuitry reads those the first storage units according to the reading voltage, to judge each of first storage Unit is to belong to the first state or second state, and records those the first storage units for belonging to the first state One second number,
    Wherein, which includes according to the operation that first number obtains the first time information：
    The memory management circuitry obtains the first time information according to the difference between first number and second number, wherein The first time information is to estimate first data are written to reading those the first storage unit elapsed times.
  22. 22. memorizer control circuit unit according to claim 21, which is characterized in that the memory management circuitry is also used Being written one second data to the reproducible nonvolatile memorizer module, and the first time information is recorded, wherein The first time information is to estimate first data are written to the second data elapsed time is written.
  23. 23. memorizer control circuit unit according to claim 22, which is characterized in that the memory management circuitry is also used To receive the reading instruction from the host system, second data are read in wherein reading instruction instruction,
    Wherein, the memory management circuitry according to the reading voltage also to re-read those the first storage units, to judge Those first storage units are to belong to the first state or second state, calculate and belong to those of the first state and first deposit One third number of storage unit, and obtain the one second of the reproducible nonvolatile memorizer module according to the third number Temporal information, wherein second temporal information are to estimate first data are written to re-reading those the first storage units Elapsed time,
    Wherein, when the memory management circuitry according to second temporal information and the first time information also to obtain a third Between information, wherein the third temporal information be estimate be written second data to read that second data are passed through when Between.
  24. 24. memorizer control circuit unit according to claim 23, which is characterized in that the memory management circuitry is also used To determine the number of an at least first voltage according to the third temporal information, and according to an at least first voltage read this Two data.
  25. 25. memorizer control circuit unit according to claim 21, which is characterized in that each of first storage unit On a bit line, and each bit line reacts on the reading voltage and generates a sensing electric current,
    Wherein, each of storage unit is the electricity on the sensing electric current or each bit line according to caused by each bit line Voltage level, which is judged, belongs to the first state or second state.
  26. 26. a kind of memorizer control circuit unit, for a reproducible nonvolatile memorizer module, which is characterized in that should Reproducible nonvolatile memorizer module includes multiple storage units, which includes：
    One host interface is electrically connected to a host system；
    One memory interface is electrically connected to the reproducible nonvolatile memorizer module；And
    One memory management circuitry is electrically connected to the host interface and the memory interface, one first data to be written Multiple first storage units into those storage units, and those the first storage units are read according to a reading voltage, To judge that each of first storage unit is to belong to a first state or one second state,
    Wherein, the memory management circuitry is calculating the one first of those the first storage units for belonging to the first state Number,
    Wherein, which inputs a look-up table, and obtain an output of the look-up table by first number, and The output is multiplied by a constant using as first time information.
  27. 27. memorizer control circuit unit according to claim 26, which is characterized in that the memory management circuitry is also used Being written one second data to the reproducible nonvolatile memorizer module, and the first time information is recorded, wherein The first time information is to estimate first data are written to the second data elapsed time is written.
  28. 28. memorizer control circuit unit according to claim 27, which is characterized in that the memory management circuitry is also used To receive the reading instruction from the host system, second data are read in wherein reading instruction instruction,
    Wherein, the memory management circuitry according to the reading voltage also to re-read those the first storage units, to judge Those first storage units are to belong to the first state or second state, calculate and belong to those of the first state and first deposit One third number of storage unit, and obtain the one second of the reproducible nonvolatile memorizer module according to the third number Temporal information, wherein second temporal information are to estimate first data are written to re-reading those the first storage units Elapsed time,
    Wherein, when the memory management circuitry according to second temporal information and the first time information also to obtain a third Between information, wherein the third temporal information be estimate be written second data to read that second data are passed through when Between.
  29. 29. memorizer control circuit unit according to claim 28, which is characterized in that the memory management circuitry is also used To determine the number of an at least first voltage according to the third temporal information, and according to an at least first voltage read this Two data.
  30. 30. memorizer control circuit unit according to claim 26, which is characterized in that each of first storage unit On a bit line, and each bit line reacts on the reading voltage and generates a sensing electric current,
    Wherein, each of storage unit is the electricity on the sensing electric current or each bit line according to caused by each bit line Voltage level, which is judged, belongs to the first state or second state.
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