CN104679441A - Time estimation method, memory storage device and memory control circuit unit - Google Patents
Time estimation method, memory storage device and memory control circuit unit Download PDFInfo
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- CN104679441A CN104679441A CN201310638312.0A CN201310638312A CN104679441A CN 104679441 A CN104679441 A CN 104679441A CN 201310638312 A CN201310638312 A CN 201310638312A CN 104679441 A CN104679441 A CN 104679441A
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Abstract
The invention provides a time estimation method, a memory storage device and a memory control circuit unit. The time estimation method is used for a rewritable non-volatile memory module comprising a plurality of storing units. The method comprises the steps of writing first data into a plurality of first storage units among the storage units; reading the first storage units according to a read voltage so as to judge whether each first storage unit belongs to a first state or a second state; calculating the number of the first storage units belongs to the first state, and obtaining time information of the rewritable non-volatile memory module according to the number.
Description
Technical field
The invention relates to a kind of time estimating and measuring method, and relate to time estimating and measuring method, memory storage apparatus, the memorizer control circuit unit of reproducible nonvolatile memorizer module especially.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, and the demand of consumer to medium is also increased rapidly.Due to reproducible nonvolatile memorizer module (such as, flash memory) there is data non-volatile, power saving, volume are little, and the characteristic such as mechanical structure, so be suitable for use in very much in above-mentioned illustrated various portable multimedia devices.
In general, for data in reproducible nonvolatile memorizer module, if these data can be calculated how long be stored in reproducible nonvolatile memorizer module, then some purposes may be had, such as judge whether these data may be lost, or determine how to read these data.But, to configure a clock or timer is to obtain temporal information, then need extra power supply.Therefore, how to estimate the temporal information of reproducible nonvolatile memorizer module, for this reason the subject under discussion be concerned about of those skilled in the art.
Summary of the invention
The invention provides a kind of time estimating and measuring method, memory storage apparatus and memorizer control circuit unit, the temporal information reproducible nonvolatile memorizer module can be estimated.
The present invention one exemplary embodiment proposes a kind of time estimating and measuring method, for reproducible nonvolatile memorizer module.This reproducible nonvolatile memorizer module comprises multiple storage unit.The method comprises: the first data are write to multiple first storage unit in described storage unit; Read voltage according to one and read the first storage unit, to judge that each first storage unit belongs to the first state or the second state; And calculate the first number belonging to the first storage unit of the first state, and obtain the very first time information of reproducible nonvolatile memorizer module according to the first number.
In an exemplary embodiment, the above-mentioned step first data being write to the first storage unit also comprises: read the first storage unit, to judge that each first storage unit belongs to the first state or the second state according to reading voltage; And record belongs to the second number of the first storage unit of the first state.The above-mentioned step obtaining very first time information according to the first number comprises: obtain very first time information according to the difference between the first number and the second number, and wherein very first time information estimates write first data to reading the first storage unit institute elapsed time.
In an exemplary embodiment, above-mentioned time estimating and measuring method also comprises: the second data are write to reproducible nonvolatile memorizer module; And record very first time information, wherein very first time information estimates write first data to write the second data institute elapsed time.
In an exemplary embodiment, above-mentioned time estimating and measuring method also comprises: receive the reading command from host computer system, its instruction reading second data; Again the first storage unit is read according to reading voltage, to judge that the first storage unit belongs to the first state or the second state, calculate the 3rd number belonging to the first storage unit of the first state, and obtain the second temporal information of reproducible nonvolatile memorizer module according to the 3rd number, wherein the second temporal information estimates write first data to again reading the first storage unit institute elapsed time.The method also comprises: obtain the 3rd temporal information according to the second temporal information and very first time information, and wherein the 3rd temporal information estimates write second data to reading the second data institute elapsed time.
In an exemplary embodiment, above-mentioned time estimating and measuring method also comprises: the number determining at least one the first voltage according to the 3rd temporal information, and reads the second data according to the first voltage.
In an exemplary embodiment, each above-mentioned first storage unit is positioned on a bit line, and each bit line react on read voltage produce a current sensor.This time estimating and measuring method also comprises: the voltage level on the current sensor produced according to each bit line or bit line, judges that each first storage unit belongs to the first state or the second state.
In an exemplary embodiment, the above-mentioned step obtaining very first time information according to the first number comprises: the first number is inputted a look-up table, and the output obtaining look-up table is using as very first time information.
The present invention one exemplary embodiment proposes a kind of memory storage apparatus, comprises connecting interface unit, above-mentioned reproducible nonvolatile memorizer module and memorizer control circuit unit.Connecting interface unit is electrically connected to a host computer system.Memorizer control circuit unit is electrically connected to connecting interface unit and reproducible nonvolatile memorizer module, in order to the first data to be write to multiple first storage unit in described storage unit, and read voltage according to one and read the first storage unit, to judge that each first storage unit belongs to the first state or the second state.Memorizer control circuit unit belongs to the first number of the first storage unit of the first state in order to calculate, and obtains the very first time information of reproducible nonvolatile memorizer module according to the first number.
In an exemplary embodiment, the operation that first data write to the first storage unit also comprises by above-mentioned memorizer control circuit unit: memorizer control circuit unit reads the first storage unit according to reading voltage, to judge that each first storage unit belongs to the first state or the second state, and record belongs to the second number of the first storage unit of the first state.Memorizer control circuit unit obtains very first time information according to the difference between the first number and the second number.Wherein very first time information estimates write first data to reading the first storage unit institute elapsed time.
In an exemplary embodiment, above-mentioned memorizer control circuit unit also in order to the second data are write to reproducible nonvolatile memorizer module, and records very first time information.Wherein very first time information estimates write first data to write the second data institute elapsed time.
In an exemplary embodiment, above-mentioned memorizer control circuit unit is also in order to receive the reading command from host computer system, and it indicates reading second data.Memorizer control circuit unit is also in order to again to read the first storage unit according to reading voltage, to judge that the first storage unit belongs to the first state or the second state, calculate the 3rd number belonging to the first storage unit of the first state, and obtain the second temporal information of reproducible nonvolatile memorizer module according to the 3rd number.Second temporal information estimates write first data to again reading the first storage unit institute elapsed time.Memorizer control circuit unit is also in order to obtain the 3rd temporal information according to the second temporal information and very first time information.3rd temporal information estimates write second data to reading the second data institute elapsed time.
In an exemplary embodiment, above-mentioned memorizer control circuit unit also in order to determine the number of at least one the first voltage according to the 3rd temporal information, and reads the second data according to the first voltage.
In an exemplary embodiment, each above-mentioned first storage unit is positioned on a bit line, and each bit line react on read voltage produce a current sensor.Each storage unit is that the voltage level on the current sensor or each bit line that produce according to each bit line is judged and belongs to the first state or the second state.
In an exemplary embodiment, above-mentioned memorizer control circuit unit is that the first number is inputted a look-up table, and the output obtaining look-up table is using as very first time information.
The present invention one exemplary embodiment proposes a kind of memorizer control circuit unit.For above-mentioned reproducible nonvolatile memorizer module.Memorizer control circuit unit comprises host interface, memory interface and memory management circuitry.Host interface is electrically connected to host computer system.Memory interface is electrically connected to reproducible nonvolatile memorizer module.Memory management circuitry is electrically connected to host interface and memory interface, in order to the first data to be write to multiple first storage unit in described storage unit, and read voltage according to one and read the first storage unit, to judge that each first storage unit belongs to the first state or the second state.Memory management circuitry also in order to calculate the first number belonging to the first storage unit of the first state, and obtains the very first time information of reproducible nonvolatile memorizer module according to the first number.
In an exemplary embodiment, the operation that first data write to the first storage unit also comprises by above-mentioned memory management circuitry: memory management circuitry reads the first storage unit according to reading voltage, to judge that each first storage unit belongs to the first state or the second state, and record belongs to the second number of the first storage unit of the first state.The operation that memory management circuitry obtains very first time information according to the first number comprises: memory management circuitry obtains very first time information according to the difference between the first number and the second number, and wherein very first time information estimates write first data to reading the first storage unit institute elapsed time.
In an exemplary embodiment, above-mentioned memory management circuitry also in order to the second data are write to reproducible nonvolatile memorizer module, and records very first time information.Very first time information estimates write first data to write the second data institute elapsed time.
In an exemplary embodiment, above-mentioned memory management circuitry is also in order to receive the reading command from host computer system, and it indicates reading second data.Memory management circuitry is also in order to again to read the first storage unit according to reading voltage, to judge that the first storage unit belongs to the first state or the second state, calculate the 3rd number belonging to the first storage unit of the first state, and obtain the second temporal information of reproducible nonvolatile memorizer module according to the 3rd number.Second temporal information estimates write first data to again reading the first storage unit institute elapsed time.Memory management circuitry is also in order to obtain the 3rd temporal information according to the second temporal information and very first time information, and wherein the 3rd temporal information estimates write second data to reading the second data institute elapsed time.
In an exemplary embodiment, above-mentioned memory management circuitry comprises according to the operation of the second data that the 3rd temporal information obtains in reproducible nonvolatile memorizer module: memory management circuitry determines the number of at least one the first voltage according to the 3rd temporal information, and reads the second data according to the first voltage.
In an exemplary embodiment, the first number is inputted a look-up table by above-mentioned memory management circuitry, and the output obtaining look-up table is using as very first time information.
Based on above-mentioned, the time estimating and measuring method that exemplary embodiment of the present invention proposes, memory storage apparatus and memorizer control circuit unit, according to the characteristic of reproducible nonvolatile memorizer module itself, can estimate and temporal information.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings to be described in detail below.
Accompanying drawing explanation
Figure 1A is host computer system shown by an exemplary embodiment and memory storage apparatus;
Figure 1B is the schematic diagram of computer, input/output device and memory storage apparatus shown by an exemplary embodiment;
Fig. 1 C is the schematic diagram of host computer system shown by an exemplary embodiment and memory storage apparatus;
Fig. 2 is the schematic block diagram that the memory storage apparatus shown in Figure 1A is shown;
Fig. 3 is the vertical view of a NAND string shown by an exemplary embodiment;
Fig. 4 is the equivalent circuit diagram of a NAND string shown by an exemplary embodiment;
Fig. 5 is the side view of the NAND string shown by an exemplary embodiment;
Fig. 6 is the schematic diagram that an entity erased cell is shown according to an exemplary embodiment;
Fig. 7 is the schematic block diagram of the memory control circuit unit shown by an exemplary embodiment;
Fig. 8 is the voltage sequential chart that reading cells is shown according to an exemplary embodiment;
Fig. 9 illustrates according to an exemplary embodiment graph of relation read between voltage and current sensor;
Figure 10 A ~ Figure 10 C is the critical voltage distribution plan that multiple first storage unit is shown according to an exemplary embodiment;
Figure 11 be according to an exemplary embodiment illustrate the number of the first storage unit belonging to the first state and temporal information estimate graph of relation between time of;
Figure 12 is the process flow diagram that time estimating and measuring method is shown according to an exemplary embodiment.
Description of reference numerals:
1000: host computer system;
1100: computer;
1102: microprocessor;
1104: random-access memory (ram);
1106: I/O (I/O) device;
1108: system bus;
1110: data transmission interface;
1202: slide-mouse;
1204: keyboard;
1206: display;
1208: printer;
1212: Portable disk;
1214: memory card;
1216: solid state hard disc;
1310: digital camera;
1312:SD card;
1314:MMC card;
1316: memory stick;
1318:CF card;
1320: embedded memory storage;
100: memory storage apparatus;
102: connecting interface unit;
104: memorizer control circuit unit;
106: reproducible nonvolatile memorizer module;
108(0) ~ 108(R): entity erased cell;
300,302,304,306,320,322,601,606: transistor;
320CG, 300CG, 302CG, 304CG, 306CG, 322CG: control gate;
300FG, 302FG, 304FG, 306FG: floating grid;
326,328: contact point;
340: substrate;
330,332,334,336,338: polysilicon layer;
360, ST0 ~ STN:NAND string;
SGD, SGS: select line;
WL0 ~ WL3: character line;
BL(0) ~ BL(N): bit line;
602 ~ 605: storage unit;
610: source electrode line;
702: memory management circuitry;
704: host interface;
706: memory interface;
708: memory buffer;
710: electric power management circuit;
712: bug check and correcting circuit;
T1 ~ t8: time point;
I
fG: current sensor;
V
fG: critical voltage;
1020,1030: curve;
1040,1050,1060: region;
V
read, V '
read: read voltage;
S1201 ~ S1203: step.
Embodiment
Generally speaking, memory storage apparatus (also claiming, storage system) comprises reproducible nonvolatile memorizer module and controller (also claiming, control circuit).Usual memory storage apparatus uses together with host computer system, data can be write to memory storage apparatus or read data from memory storage apparatus to make host computer system.
Figure 1A is host computer system shown by an exemplary embodiment and memory storage apparatus.Figure 1B is the schematic diagram of computer, input/output device and memory storage apparatus shown by an exemplary embodiment.Fig. 1 C is the schematic diagram of host computer system shown by an exemplary embodiment and memory storage apparatus.
Please refer to Figure 1A, host computer system 1000 generally comprises computer 1100 and I/O (input/output, I/O) device 1106.Computer 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the slide-mouse 1202 of Figure 1B, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.
In embodiments of the present invention, memory storage apparatus 100 is electrically connected by data transmission interface 1110 other elements with host computer system 1000.Data can be write to memory storage apparatus 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106 or read data from memory storage apparatus 100.Such as, memory storage apparatus 100 can be the type nonvolatile memory storage of Portable disk 1212, memory card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 etc. as shown in Figure 1B.
Generally speaking, host computer system 1000 is any system that can coordinate to store data substantially with memory storage apparatus 100.Although in this exemplary embodiment, host computer system 1000 explains with computer system, but host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.Such as, when host computer system is digital camera (video camera) 1310, type nonvolatile memory storage then for its SD card 1312 used, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded memory storage 1320(as shown in Figure 1 C).Embedded memory storage 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is directly electrically connected on the substrate of host computer system.
Fig. 2 is the schematic block diagram that the memory storage apparatus shown in Figure 1A is shown.
Please refer to Fig. 2, memory storage apparatus 100 comprises connecting interface unit 102, memorizer control circuit unit 104 and reproducible nonvolatile memorizer module 106.
In this exemplary embodiment, connecting interface unit 102 is compatible with Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) standard.But, it must be appreciated, the present invention is not limited thereto, connecting interface unit 102 also can be meet parallel advanced technology annex (Parallel Advanced Technology Attachment, PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, secure digital (Secure Digital, SD) interface standard, a hypervelocity generation (Ultra High Speed-I, UHS-I) interface standard, hypervelocity two generation (Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory Stick, MS) interface standard, multimedia storage card (Multi Media Card, MMC) interface standard, down enters formula multimedia storage card (Embedded Multimedia Card, eMMC) interface standard, general flash memory (Universal Flash Storage, UFS) interface standard, compact flash (Compact Flash, CF) interface standard, integrated form drives electrical interface (Integrated Device Electronics, IDE) standard or other standards be applicable to.Connecting interface unit 102 can be encapsulated in a chip with memorizer control circuit unit 104, or connecting interface unit 102 is laid in one to comprise outside the chip of memorizer control circuit unit 104.
Memorizer control circuit unit 104 in order to perform with multiple logic gate of hardware pattern or firmware pattern implementation or steering order, and according to the instruction of host computer system 1000 carry out in reproducible nonvolatile memorizer module 106 data write, read and the running such as to erase.
Reproducible nonvolatile memorizer module 106 is electrically connected to memorizer control circuit unit 104, and in order to data that host system 1000 writes.Reproducible nonvolatile memorizer module 106 has entity erased cell 108(0) ~ 108(R).Such as, entity erased cell 108(0) ~ 108(R) same memory crystal grain (die) can be belonged to or belong to different memory crystal grain.For NAND type flash memory, an entity erased cell can comprise multiple NAND string (NANDstring).Each NAND string can comprise multiple transistor be one another in series.Fig. 3 is the vertical view of a NAND string shown by an exemplary embodiment.Fig. 4 is the equivalent circuit diagram of a NAND string shown by an exemplary embodiment.Please refer to Fig. 3 and Fig. 4, NAND string 360 includes transistor 320,300,302,304,306 and 322.Also a bit line is can be described as from the circuit between contact point 326 to contact point 328.Control gate 320CG on transistor 320 is electrically connected to select line SGD; Control gate 300CG on transistor 300 is electrically connected to character line WL3; Control gate 302CG on transistor 302 is electrically connected to character line WL2; Control gate 304CG on transistor 304 is electrically connected to character line WL1; Control gate 306CG on transistor 306 is electrically connected to character line WL0; Control gate 322CG on transistor 322 is electrically connected to select line SGS.Each transistor 300,302,304 and 306 also comprises an electric charge and mends and catch layer.Electric charge is mended and caught layer is in order to store electrons or hole.In this exemplary embodiment, electric charge capture layer is called as floating grid (floating gate), and its material comprises the polysilicon through mixing.But in another exemplary embodiment, electric charge capture layer can comprise an oxide-nitride-oxide composite bed, or other can in order to the material in store electrons or hole, and the present invention is also not subject to the limits.In the exemplary embodiment of Fig. 3, transistor 300 has floating grid 300FG; Transistor 302 has floating grid 302FG; Transistor 304 has floating grid 304FG; Transistor 306 has floating grid 306FG.At this, transistor 300,302,304 and 306 also can be called as storage unit.
Fig. 5 is the side view of the NAND string shown by an exemplary embodiment.Please refer to Fig. 3 ~ Fig. 5, NAND string 360 is arranged in substrate 340.Control gate 300CG, 302CG, 304CG and 306CG are separately positioned on floating grid 300FG, 302FG, 304FG and 306FG.Control gate 300CG, 302CG, 304CG, 306CG and be provided with dielectric layer between floating grid 300FG, 302FG, 304FG, 306FG.Then oxide layer is provided with between floating grid 300FG, 302FG, 304FG, 306FG and substrate 340.Transistor contiguous in Fig. 5 can share the polysilicon layer 330,332,334,336 and 338 through mixing, and polysilicon layer can form source electrode or the drain electrode of a transistor.When data will being write (also referred to as programming) to transistor 300,302,304 and 306 time, suitable voltage can be applied on control gate 320CG and 322CG, and transistor 320 and 322 can be switched on; And have an electric current between contact point 326 and contact point 328.Control gate on the transistor that write voltage can be applied in for being programmed, at this for control gate 302CG, makes the electronics in above-mentioned electric current or hole can move to floating grid 302FG.After electronics or hole are injected into floating grid 302FG, the critical voltage of transistor 302 can change, and can store one or more bit equivalently by this.It should be noted that in other exemplary embodiment, NAND string 360 also can comprise more storage unit, and the present invention does not limit the number of storage unit in a NAND string.In addition, Fig. 3 ~ Fig. 5 is an example, and the present invention does not limit the structure of storage unit or the electrical connection of circuit in reproducible nonvolatile memorizer module 106.Such as, in an exemplary embodiment, multiple storage unit pushes away each other repeatedly, forms three-dimensional flash memory by this.
Fig. 6 is the schematic diagram that an entity erased cell is shown according to an exemplary embodiment.
Please refer to Fig. 6, for entity erased cell 108(0), entity erased cell 108(0) include multiple NAND string ST0 ~ STN.NAND string ST0 includes transistor 601,606 and storage unit 602 ~ 605.NAND goes here and there the NAND of ST0 ~ STN and Fig. 4 and goes here and there 360 similar, does not repeat them here.Entity erased cell 108(0) also include many character line WL0 ~ WL3 and many bit line BL(0) ~ BL(N).Entity erased cell 108(0) in each storage unit can be positioned on a character line and a bit line.Multiple storage unit on same character line can form one or more entity programming unit.Specifically, if each storage unit can store x bit, then the multiple storage unit on same character line form x entity programming unit to I haven't seen you for ages, and wherein x is positive integer.If positive integer x is greater than 1, then x entity programming unit on same character line also can be classified as lower entity programming unit and upper entity programming unit.But the present invention does not limit the numerical value of positive integer x.In general, the writing speed of lower entity programming unit can be greater than the writing speed of entity programming unit.In this exemplary embodiment, entity programming unit is the minimum unit of programming.That is, entity programming unit is the minimum unit of write data.Such as, entity programming unit is physical page or entity fan (sector).If entity programming unit is physical page, then each entity programming unit generally includes data bit district and redundancy ratio special zone.Data bit district comprises multiple entity fan, and in order to store the data of user, and redundancy ratio special zone is in order to the data (such as, error correcting code) of storage system.In this exemplary embodiment, each data bit district comprises 32 entity fans, and the size of an entity fan is 512 bytes (byte, B).But, in other exemplary embodiment, also can comprise in data bit district 8,16 or number more or less entity fan, the present invention do not limit entity fan size and number.
On the other hand, NAND string ST0 ~ STN is electrically connected to source electrode line 610.As entity erased cell 108(0) when will be erased, a voltage of erasing can be applied in entity erased cell 108(0) in substrate, make entity erased cell 108(0) in electronics in all floating grid or hole all can leave affiliated floating grid.In this exemplary embodiment, the least unit of entity erased cell for erasing.Also namely, each entity erased cell contain minimal amount in the lump by the storage unit of erasing.Such as, entity erased cell is solid block.
In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is single-order storage unit (Single Level Cell, SLC) NAND type flash memory module, namely can store 1 bit in a storage unit.But, the present invention is not limited thereto, reproducible nonvolatile memorizer module 106 may also be multi-level cell memory (Multi Level Cell, MLC) NAND type flash memory module, Complex Order storage unit (Trinary Level Cell, TLC) NAND type flash memory module, other flash memory module or other there is the memory module of identical characteristics.
Fig. 7 is the schematic block diagram of the memorizer control circuit unit shown by an exemplary embodiment.
Please refer to Fig. 7, Memory Controller 104 comprises memory management circuitry 702, host interface 704 and memory interface 706.
Memory management circuitry 702 is in order to the overall operation of control store controller 104.Specifically, memory management circuitry 702 has multiple steering order, and when memory storage apparatus 100 operates, these steering orders can be performed to carry out data write, read and the running such as to erase.
Host interface 704 is electrically connected to memory management circuitry 702 and in order to receive and to identify the instruction that transmits of host computer system 1000 and data.That is, the instruction that transmits of host computer system 1000 and data can be sent to memory management circuitry 702 by host interface 704.In this exemplary embodiment, host interface 704 is compatible with SATA standard.But, it must be appreciated and the present invention is not limited thereto, host interface 704 also can be compatible with PATA standard, IEEE1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other data transmission standards be applicable to.
Memory interface 706 is electrically connected to memory management circuitry 702 and in order to access reproducible nonvolatile memorizer module 106.That is, the data for writing to reproducible nonvolatile memorizer module 106 can be converted to the receptible form of reproducible nonvolatile memorizer module 106 via memory interface 706.
In the present invention one exemplary embodiment, Memory Controller 104 also comprises memory buffer 708, electric power management circuit 710 and bug check and correcting circuit 712.
Memory buffer 708 is electrically connected to memory management circuitry 702 and comes from the data and instruction of host computer system 1000 in order to temporary or come from the data of reproducible nonvolatile memorizer module 106.
Electric power management circuit 710 is electrically connected to memory management circuitry 702 and in order to the power supply of control store memory storage 100.
Bug check and correcting circuit 712 are electrically connected to memory management circuitry 702 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 702 receives write instruction from host computer system 1000, bug check and correcting circuit 712 can be that the corresponding data that this writes instruction produce corresponding error correcting code (Error Correcting Code, ECC Code), and the data of this write instruction corresponding can write in reproducible nonvolatile memorizer module 106 with corresponding error correcting code by memory management circuitry 702.Afterwards, can read error correcting code corresponding to these data when memory management circuitry 702 reads data from reproducible nonvolatile memorizer module 106, and bug check and correcting circuit 712 can according to this error correcting code to read data execution error inspection and correction programs simultaneously.
Fig. 8 is the voltage sequential chart that reading cells is shown according to an exemplary embodiment.
Please refer to Fig. 6 and Fig. 8, transfer signal to reproducible nonvolatile memorizer module 106, with the data in reading cells 605 in this hypothesis memory management circuitry 702.Reproducible nonvolatile memorizer module 106 can change accordingly selects line SGD, SGS, character line WL0 ~ WL3 and bit line BL(0) ~ BL(N) on voltage level, the state of detection storage unit 605 by this.Specifically, in the starting stage, voltage all in Fig. 8 is all low level.At time point t1, select the voltage level on line SGD can be pulled up (raised) with turn-on transistor 601.At time point t2, the voltage level on character line WL1 ~ WL3 can be pulled up with conducting storage unit 602 ~ 604, and a reading voltage can be applied on character line WL0.At time point t4, bit line BL(0) on voltage level can be pulled up to a pre-charge level (pre-charge level).At time point t6, select the voltage level on line SGS can be pulled up with turn-on transistor 606.The reading voltage of reaction in storage unit 605, bit line BL(0) on can produce a current sensor.According to the size of this current sensor, bit line BL(0) voltage level may decline (drop).Specifically, if the reading voltage on character line WL0 is greater than the critical voltage of storage unit 605, then storage unit 605 can be switched on and bit line BL(0) on current sensor can make bit line BL(0) on voltage level decline.If the reading voltage on character line WL0 is not greater than the critical voltage of storage unit 605, then storage unit 605 can be ended and bit line BL(0) on voltage level can remain unchanged.In general, bit line BL(0) amplifier can be electrically connected to, to detect bit line BL(0) on voltage level.It should be noted that Fig. 8 is an example, the present invention does not limit and selects line SGD, SGS, character line WL0 ~ 3 and bit line BL(0) ~ BL(N) on time of being pulled up of voltage level and order.
In the exemplary embodiment of Fig. 8, bit line BL(0) on voltage level can be used for judging that storage unit 605 is conducting or cut-off, and reproducible nonvolatile memorizer module 106 can produce corresponding checking bit.Such as, checking bit " 1 " representative cut-off, and verify that bit " 0 " represents conducting.But it should be noted that the increase along with reading voltage, in fact storage unit 605 can't become conducting from cut-off suddenly.Therefore, in another exemplary embodiment, verify that bit does not necessarily represent cut-off or the state of conducting.Fig. 9 illustrates according to an exemplary embodiment graph of relation read between voltage and current sensor.As shown in Figure 9, along with reading the increase of voltage, current sensor can increase gradually.Therefore, in an exemplary embodiment, reproducible nonvolatile memorizer module 106 can set checking bit as " 1 " when current sensor is greater than first critical value, if when current sensor is less than second critical value, sets checking bit as " 0 ".First critical value can be identical or different from the second critical value, and the present invention is also not subject to the limits.Or as shown in Figure 8, reproducible nonvolatile memorizer module 106 can at bit line BL(0) on voltage level decrease beyond a critical value and just set checking bit as " 1 " later.With another one angle, checking bit can be used for representing whether the critical voltage of storage unit 605 is greater than the reading voltage be applied in.Such as, in fig .9, if current sensor is greater than current value I
fG, then represent that reading voltage is greater than critical voltage V
fGand checking bit is " 1 ".But, because current sensor is increase gradually, therefore according to different determination methods, critical voltage V
fGnumerical value also can not be identical.The present invention does not limit the determination methods of critical voltage in storage unit.In this exemplary embodiment, checking bit can decide according to the size of current sensor, variable quantity or arbitrary electrical specification, or decides according to the voltage level on bit line, but the method for the present invention's not limit decision.
Reproducible nonvolatile memorizer module 106 can send memory management circuitry 702 to this checking bit.Memory management circuitry 702 can be belong to the first state or the second state according to this checking bit decision storage unit 605.Below for convenience of description for the purpose of, whether the reading voltage that the first state of storage unit and the second state representation apply is greater than the critical voltage of storage unit.But it should be noted, along with checking is than peculiar different deciding means, the first state can represent different meanings from the second state, and the present invention does not limit the first state and the meaning representated by the second state.In other words, storage unit is judged as the first state or the second state according to current sensor or according to the voltage level on bit line.In addition, in other exemplary embodiment, reproducible nonvolatile memorizer module 106 also can transmit other signal, character, symbol or numeral give memory management circuitry 702 to replace above-mentioned checking bit, the present invention is also not subject to the limits.
Figure 10 A ~ Figure 10 C is the critical voltage distribution plan that multiple first storage unit is shown according to an exemplary embodiment.
Please refer to Figure 10, first data first can be write to multiple first storage unit by memory management circuitry 702, Figure 10 A is the critical voltage distribution plans of the first data when being written into the first storage unit, and wherein transverse axis is critical voltage, and the longitudinal axis is storage unit number.These first storage unit can belong to identical entity erased cell or different entity erased cell, and the present invention is also not subject to the limits.The present invention does not limit the number of the first storage unit yet.In this exemplary embodiment, bits all in the first data is all identical.But in another exemplary embodiment, the first data also can be that random number produces or produces with other any-modes, and the present invention does not limit the content of the first data.In addition, the first data can be written into when memory storage apparatus 100 is formatted, or in other arbitrary time point writes, the present invention is also not subject to the limits.
When the first data are written into, the distribution of the critical voltage of the first storage unit is as curve 1020.But along with the increase of time, although the first data are still stored in the first storage unit, the critical voltage of the first storage unit can decline.The relation of critical voltage and time, can represent in order to lower equation (1).
V
FG(t)=βt
ox/ln{(Aβ·t/t
oxC
T)+exp(βt
ox/V
FG(t=0))}…（1）
A and β is constant.T represents the time.T
oxrepresent the thickness of oxide layer in storage unit.V
fG(t=0) critical voltage when expression time is 0.V
fGcritical voltage when () expression time is t t.C
trepresent the capacitance of oxide layer in storage unit.Can learn from equation (1), along with the increase of time t, critical voltage V
fGt () can reduce.For example, as shown in Figure 10 B, can be curve 1030 in the distribution of the critical voltage of the first storage unit after after a while.In general, compared to curve 1020, it is more smooth that curve 1030 can past move to left or become.
In this exemplary embodiment, if memory management circuitry 702 will obtain the time t in aforesaid equation (1), memory management circuitry 702 can according to reading voltage V
readread these the first storage unit, to judge that each first storage unit belongs to the first state or the second state.Memory management circuitry 702 can calculate the number (also claiming the first number) of the first storage unit belonging to the first state, and obtains the temporal information (also claiming very first time information) of reproducible nonvolatile memorizer module 106 according to this first number.In this exemplary embodiment, if the first storage unit belongs to the first state, then represent that the critical voltage of the first storage unit is less than or equal to and read voltage V
read.If the first storage unit belongs to the second state, represent that the critical voltage of the first storage unit is greater than and read voltage V
read.Therefore, the first number represents the number of first storage unit in region 1040.Very first time information (is labeled as temporal information t below
1) be written into these first storage unit (time point as Figure 10 A) in order to estimation from the first data, read voltage V to using
readread the first storage unit to have passed through how long (time point as Figure 10 B).Therefore, if the first number is larger, then very first time information t is used
1time of estimating out can be larger.For example, memory management circuitry 702 according to curve 1020, first number and above-mentioned equation (1), can calculate time t.Memory management circuitry 702 can scan these first storage unit with multiple reading voltage and obtain curve 1020, or according to the hypothesis set up in advance or model obtains curve 1020, the present invention is also not subject to the limits.In another exemplary embodiment, the first number and very first time information t
1between relation can be calculated in advance and be stored in a look-up table.Memory management circuitry 702 can input this look-up table by the first number, and the output obtaining this look-up table is using as temporal information t
1.Such as, when setting up look-up table, can the maximal value of setting-up time t be 10 years, and quantize these 10 years with 8 bits, the temporal information being namely recorded in look-up table represents with 8 bits.Therefore the temporal information that look-up table exports is multiplied by a certain constant just can estimate and above-mentioned time t.But the present invention not binding hours information represents with several bit, do not limit to estimate by which kind of mode yet and time t.
In another exemplary embodiment, when the first data being write to the first storage unit (time point as Figure 10 A), memory management circuitry 702 also can according to reading voltage V '
readread these the first storage unit, and judge that each first storage unit belongs to the first state or the second state.Memory management circuitry 702 can record the number (also claiming the second number) of the first storage unit belonging to the first state.Such as, the second number is the number of the first storage unit in region 1050.Memory management circuitry 702 can obtain temporal information t according to the difference between this second number and first above-mentioned number
1.This temporal information t
1from Figure 10 A to Figure 10 B institute elapsed time in order to estimation.If the difference between the first number and the second number is larger, then time of estimating out can be larger.In the same manner, the difference between the first number and the second number also can be inputed to a look-up table by memory management circuitry 702, and the output obtaining this look-up table is using as temporal information t
1.In other words, memory management circuitry 702 only just can obtain temporal information t according to the first number
1, also can obtain temporal information t according to the difference of the first number and the second number
1, the present invention is also not subject to the limits.
As discussed previously, the present invention does not limit the meaning of the first state and the second state.In above-mentioned exemplary embodiment, if the first storage unit belongs to the first state, then represent that the critical voltage of the first storage unit is less than or equal to and read voltage V
read; If the first storage unit belongs to the second state, represent that the critical voltage of the first storage unit is greater than and read voltage V
read.But, in another exemplary embodiment, if the first storage unit belongs to the first state, then represent that the critical voltage of the first storage unit is greater than and read voltage V
read; If the first storage unit belongs to the second state, represent that the critical voltage of the first storage unit is less than or equal to and read voltage V
read.In the same manner, memory management circuitry 702 can calculate the number (also referred to as the first number) of the first storage unit belonging to the first state.In the case, when the first number is less, then very first time information t
1time of estimating out can be larger.On the other hand, in the exemplary embodiment of Figure 10 A ~ Figure 10 B, read voltage V
readit is the left side at curve 1020,1030.But, read voltage and also (such as, voltage V ' can be read on the right side of curve 1020,1030
read).
In an exemplary embodiment, for one or many data being written into reproducible nonvolatile memorizer module 106, memory management circuitry 702 can note down corresponding temporal information.Specifically, under the time point of Figure 10 B, one second data write in reproducible nonvolatile memorizer module 106 by memory management circuitry 702, and now memory management circuitry 702 can obtain temporal information t according to above-mentioned method
1.Therefore, acquired temporal information t
1from write first data (time point as Figure 10 A) to write second data institute elapsed time in order to estimation.In an exemplary embodiment, for the entity programming unit that each is programmed, memory management circuitry 702 all can note down corresponding temporal information.But memory management circuitry 702 also can note down each entity fan or the temporal information that is programmed of entity erased cell, and the present invention is also not subject to the limits.
The temporal information of above-mentioned record can with deciding how to read the second data be stored in reproducible nonvolatile memorizer module 106.For example, suppose to be written into and after after a while in the second data, the critical voltage distribution of the first storage unit is as Figure 10 C, and now memory management circuitry 702 have received the reading command from host computer system, and the logical address belonging to this reading command instruction reading second data.After receiving this reading command, memory management circuitry 702 can according to reading voltage V
readagain the first storage unit is read, to judge that these first storage unit belong to the first state or the second state.Memory management circuitry 702 can calculate the number (also claim the 3rd number) of the first storage unit belonging to the first state, and obtains one second temporal information according to this 3rd number and (be labeled as temporal information t below
2).Such as, the 3rd number is the number of the first storage unit in region 1060, and temporal information t
2from write first data (time point as Figure 10 A) to again reading the first storage unit (time point as Figure 10 C) institute elapsed time in order to estimation.Memory management circuitry 702 can according to temporal information t
2with temporal information t
1obtain the 3rd temporal information.Such as, memory management circuitry 702 can by temporal information t
2deduct temporal information t
1to obtain the 3rd temporal information.Therefore, this 3rd temporal information is from write second data to reading second data institute elapsed time (that is, the second data are stored in reproducible nonvolatile memorizer module 106 elapsed times) in order to estimation.If the second data are stored in reproducible nonvolatile memorizer module, 106 elapsed times are longer, then the probability that makes a mistake of the second data is larger.Therefore, memory management circuitry 702 can obtain the second data in reproducible nonvolatile memorizer module 106 according to the 3rd temporal information.Such as, the coded program of an error correcting code is have passed through when the second data are written into.Memory management circuitry 702 can obtain at least one first voltage according to the 3rd temporal information, and reads the second data according to the first voltage.If the 3rd temporal information estimate the time larger (that is, the probability that makes a mistake of the second data larger or comprise more error bit), then need more information to strengthen the ability of righting the wrong.Therefore, in an exemplary embodiment, if the 3rd temporal information to estimate the time larger, then the first required number of voltages is more, can obtain more checking bits (also referred to as soft bit information) by this.These checking bits can be used for execution error correcting code, such as, be low density parity check code (low density parity code, LDPC).In general, if the number of the first voltage is more, then the corrigendum ability of low density parity check code can be better.If use low density parity check code, in another exemplary embodiment, the 3rd temporal information also can with deciding to be decode by hard bit mode (hard bit mode) or soft bit mode (soft bit mode).
In above-mentioned exemplary embodiment, be infer that the second data is stored in reproducible nonvolatile memorizer module 106 elapsed times by the state of the first storage unit.But in another exemplary embodiment, the state of the storage unit that also can be stored by the second data itself is estimated and the time.For example, at the time point of Figure 10 B, the second data are written into multiple second storage unit, and memory management circuitry 702 can read the second storage unit according to a reading voltage and record the number belonging to the second storage unit of the first state.At the time point of Figure 10 C, memory management circuitry 702 can read the second storage unit to obtain the number of the second storage unit now belonging to the first state according to reading voltage again.According to these two numbers, memory management circuitry 702 can obtain and be written into reading second data institute elapsed time from the second data.
It is worth mentioning that, in some cases, the time t that aforesaid equation (1) calculates may have error.Such as, if reproducible nonvolatile memorizer module 106 is in the environment of relatively-high temperature, then calculated time t can be larger.But, in this exemplary embodiment, because the first data and the second data are stored in identical reproducible nonvolatile memorizer module 106, therefore can judge by the temporal information acquired by said method the probability that the second data make a mistake exactly.
In the exemplary embodiment of Figure 10 A ~ Figure 10 C, memory management circuitry 702 can use identical reading voltage V
readread the first storage unit to obtain corresponding temporal information.But in another exemplary embodiment, memory management circuitry 702, at different time points, can read the first storage unit with different reading voltage.Such as, after reading the first storage unit with different reading voltage, memory management circuitry 702 can obtain temporal information according to used reading voltage, above-mentioned equation (1) with the curve 1020 in Figure 10 A, and the present invention is also not subject to the limits.
Figure 11 be according to an exemplary embodiment illustrate the number of the first storage unit belonging to the first state and temporal information estimate graph of relation between time of.
Please refer to Figure 10 A and Figure 11, in an exemplary embodiment, memory management circuitry 702 can set and read voltage V
readbe positioned at a fringe region of curve 1020, make along with time process, belong to the number of the first storage unit of the first state and temporal information estimate the time and be similar to direct ratio (as shown in figure 11).Specifically, memory management circuitry 702 can obtain a function of functions (composition function) according to above-mentioned equation (1) and the function representated by curve 1020 in Figure 10 A.The integration that memory management circuitry 702 can get critical voltage to this function of functions gets the second differential of time again, and gets minimum value to the result after differential and read voltage V to obtain
read.Such as, memory management circuitry 702 can calculate according to following equation (2) and (3) and read voltage V
read.Wherein DF(V
th) function representated by curve 1020, γ is constant.
Figure 12 is the process flow diagram that time estimating and measuring method is shown according to an exemplary embodiment.
Please refer to Figure 12, in step S1201, the first data are write to multiple first storage unit.In step S1202, read voltage according to one and read the first storage unit, to judge that each first storage unit belongs to the first state or the second state.In step S1203, calculate the number belonging to the first storage unit of the first state, and obtain the temporal information of reproducible nonvolatile memorizer module according to this number.But in Figure 12, each step has described in detail as above, just repeats no more at this.It should be noted that in Figure 12, each step can implementation be multiple procedure code or circuit, the present invention is also not subject to the limits.In addition, the method for Figure 12 above embodiment of can arranging in pairs or groups uses, and also can be used alone, the present invention is also not subject to the limits.
In sum, the time estimating and measuring method that exemplary embodiment of the present invention proposes, memory storage apparatus and memorizer control circuit unit, can obtain temporal information by the number that the first storage unit belongs to the first state, and without configurable clock generator and extra power supply.In addition, owing to being obtain temporal information by the characteristic of reproducible nonvolatile memorizer module itself, therefore to estimate the time comparatively accurate.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (21)
1. a time estimating and measuring method, for a reproducible nonvolatile memorizer module, is characterized in that, this reproducible nonvolatile memorizer module comprises multiple storage unit, comprising:
One first data are write to multiple first storage unit in those storage unit;
Read voltage according to one and read those the first storage unit, to judge that each those first storage unit belongs to one first state or one second state; And
Calculate one first number belonging to those the first storage unit of this first state, and obtain a very first time information of this reproducible nonvolatile memorizer module according to this first number.
2. time estimating and measuring method according to claim 1, is characterized in that, the step that these first data write to those the first storage unit is comprised:
Those the first storage unit are read, to judge that each those first storage unit belongs to this first state or this second state according to this reading voltage; And
Record belongs to one second number of those the first storage unit of this first state,
Wherein, the step obtaining this very first time information according to this first number comprises:
Obtain this very first time information according to the difference between this first number and this second number, wherein this very first time information is to reading those the first storage unit institute elapsed times in order to these first data of estimation write.
3. time estimating and measuring method according to claim 1, is characterized in that, also comprise:
One second data are write to this reproducible nonvolatile memorizer module; And
Record this very first time information, wherein this very first time information is to writing this second data institute elapsed time in order to these first data of estimation write.
4. time estimating and measuring method according to claim 3, is characterized in that, also comprise:
Receive the reading command from a host computer system, wherein these second data are read in the instruction of this reading command;
Again those the first storage unit are read according to this reading voltage, to judge that those first storage unit belong to this first state or this second state, calculate one the 3rd number belonging to those the first storage unit of this first state, and obtain one second temporal information of this reproducible nonvolatile memorizer module according to the 3rd number, wherein this second temporal information is to again reading those the first storage unit institute elapsed times in order to these first data of estimation write;
Obtain one the 3rd temporal information according to this second temporal information and this very first time information, wherein the 3rd temporal information is to reading this second data institute elapsed time in order to these second data of estimation write.
5. time estimating and measuring method according to claim 4, is characterized in that, also comprise:
Determine the number of at least one first voltage according to the 3rd temporal information, and read this second data according to this at least one first voltage.
6. time estimating and measuring method according to claim 1, is characterized in that, each those first storage unit is positioned on a bit line, and the reaction of each those bit line produces a current sensor at this reading voltage, and this time estimating and measuring method also comprises:
Voltage level on this current sensor produced according to each those bit line or each those bit line, judges that each those first storage unit belongs to this first state or this second state.
7. time estimating and measuring method according to claim 1, is characterized in that, comprises according to the step that this first number obtains this very first time information:
This first number is inputted a look-up table, and obtains one of this look-up table and export using as this very first time information.
8. a memory storage apparatus, is characterized in that, comprising:
One connecting interface unit, in order to be electrically connected to a host computer system;
One reproducible nonvolatile memorizer module, comprises multiple storage unit; And
One memorizer control circuit unit, be electrically connected to this connecting interface unit and this reproducible nonvolatile memorizer module, in order to one first data to be write to multiple first storage unit in those storage unit, and read voltage according to one and read those the first storage unit, to judge that each those first storage unit belongs to one first state or one second state
Wherein, this memorizer control circuit unit belongs to one first number of those the first storage unit of this first state in order to calculate, and obtains a very first time information of this reproducible nonvolatile memorizer module according to this first number.
9. memory storage apparatus according to claim 8, is characterized in that, the operation that these first data write to those the first storage unit also comprises by this memory storage control circuit unit:
This memorizer control circuit unit reads those the first storage unit according to this reading voltage, to judge that each those first storage unit belongs to this first state or this second state, and record belongs to one second number of those the first storage unit of this first state
Wherein, the operation that this memorizer control circuit unit obtains this very first time information according to this first number comprises:
This memorizer control circuit unit obtains this very first time information according to the difference between this first number and this second number, and wherein this very first time information is to reading those the first storage unit institute elapsed times in order to these first data of estimation write.
10. memory storage apparatus according to claim 8, it is characterized in that, this memorizer control circuit unit is also in order to write to this reproducible nonvolatile memorizer module by one second data, and record this very first time information, wherein this very first time information is to writing this second data institute elapsed time in order to these first data of estimation write.
11. memory storage apparatus according to claim 10, is characterized in that, this memorizer control circuit unit is also in order to receive the reading command from this host computer system, and wherein these second data are read in the instruction of this reading command,
Wherein, this memorizer control circuit unit is also again to read those the first storage unit according to this reading voltage, to judge that those first storage unit belong to this first state or this second state, calculate one the 3rd number belonging to those the first storage unit of this first state, and one second temporal information of this reproducible nonvolatile memorizer module is obtained according to the 3rd number, wherein this second temporal information is to again reading those the first storage unit institute elapsed times in order to these first data of estimation write
Wherein, this memorizer control circuit unit is also in order to obtain one the 3rd temporal information according to this second temporal information and this very first time information, and wherein the 3rd temporal information is to reading this second data institute elapsed time in order to these second data of estimation write.
12. memory storage apparatus according to claim 11, is characterized in that, this memorizer control circuit unit also in order to determine the number of at least one first voltage according to the 3rd temporal information, and reads this second data according to this at least one first voltage.
13. memory storage apparatus according to claim 8, is characterized in that, each those first storage unit is positioned on a bit line, and each bit line reacts on this reading voltage produces a current sensor,
Wherein, each those storage unit is that voltage level on this current sensor or each bit line of producing according to each bit line is judged and belongs to this first state or this second state.
14. memory storage apparatus according to claim 8, is characterized in that, this memorizer control circuit unit obtains this very first time information according to this first number, comprising:
This first number is inputted a look-up table by this memorizer control circuit unit, and obtains one of this look-up table and export using as this very first time information.
15. 1 kinds of memorizer control circuit unit, for a reproducible nonvolatile memorizer module, is characterized in that, this reproducible nonvolatile memorizer module comprises multiple storage unit, and this memorizer control circuit unit comprises:
One host interface, in order to be electrically connected to a host computer system;
One memory interface, in order to be electrically connected to this reproducible nonvolatile memorizer module; And
One memory management circuitry, be electrically connected to this host interface and this memory interface, in order to one first data to be write to multiple first storage unit in those storage unit, and read voltage according to one and read those the first storage unit, to judge that each those first storage unit belongs to one first state or one second state
Wherein, this memory management circuitry belongs to one first number of those the first storage unit of this first state in order to calculate, and obtains a very first time information of this reproducible nonvolatile memorizer module according to this first number.
16. memorizer control circuit unit according to claim 15, is characterized in that, these first data are write to those the first storage unit by this memory management circuitry, comprising:
This memory management circuitry reads those the first storage unit according to this reading voltage, to judge that each those first storage unit belongs to this first state or this second state, and record belongs to one second number of those the first storage unit of this first state
Wherein, the operation that this memory management circuitry obtains this very first time information according to this first number comprises:
This memory management circuitry obtains this very first time information according to the difference between this first number and this second number, and wherein this very first time information is to reading those the first storage unit institute elapsed times in order to these first data of estimation write.
17. memorizer control circuit unit according to claim 15, it is characterized in that, this memory management circuitry is also in order to write to this reproducible nonvolatile memorizer module by one second data, and record this very first time information, wherein this very first time information is to writing this second data institute elapsed time in order to these first data of estimation write.
18. memorizer control circuit unit according to claim 17, is characterized in that, this memory management circuitry is also in order to receive the reading command from this host computer system, and wherein these second data are read in the instruction of this reading command,
Wherein, this memory management circuitry is also in order to again to read those the first storage unit according to this reading voltage, to judge that those first storage unit belong to this first state or this second state, calculate one the 3rd number belonging to those the first storage unit of this first state, and one second temporal information of this reproducible nonvolatile memorizer module is obtained according to the 3rd number, wherein this second temporal information is to again reading those the first storage unit institute elapsed times in order to these first data of estimation write
Wherein, this memory management circuitry is also in order to obtain one the 3rd temporal information according to this second temporal information and this very first time information, and wherein the 3rd temporal information is to reading this second data institute elapsed time in order to these second data of estimation write.
19. memorizer control circuit unit according to claim 18, is characterized in that, this memory management circuitry also in order to determine the number of at least one first voltage according to the 3rd temporal information, and reads this second data according to this at least one first voltage.
20. memorizer control circuit unit according to claim 15, is characterized in that, each those first storage unit is positioned on a bit line, and each bit line reacts on this reading voltage produces a current sensor,
Wherein, each those storage unit is that voltage level on this current sensor or each bit of producing according to each bit line is judged and belongs to this first state or this second state.
21. memorizer control circuit unit according to claim 15, is characterized in that, the operation that this memory management circuitry obtains this very first time information according to this first number comprises:
This first number is inputted a look-up table by this memory management circuitry, and obtains one of this look-up table and export using as this very first time information.
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