CN104298571A - Data protection method, memory storage device and memory controller - Google Patents
Data protection method, memory storage device and memory controller Download PDFInfo
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Abstract
The invention provides a data protection method, a memory storage device and a memory controller, and is used for a rewritable nonvolatile memory module. The data protection method comprises the following steps: utilizing data stored in a plurality of first storage units in a plurality of storage units to generate a first error correction code, wherein the first storage units are positioned on a plurality of first word lines and a plurality of first bite lines, and only the data stored in one storage unit is used for generating the first error correction code in the storage units on each first bit line. Therefore, the data in the storage unit can be effectively protected.
Description
Technical field
The invention relates to a kind of data guard method, and relate to a kind of data guard method for reproducible nonvolatile memorizer module, memorizer memory devices and Memory Controller especially.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, and the demand of consumer to Storage Media is also increased rapidly.Due to reproducible nonvolatile memorizer module (such as, flash memory) there is data non-volatile, power saving, volume are little, and the characteristic such as mechanical structure, so be built in above-mentioned illustrated various portable multimedia devices in being applicable to very much.
In general, a reproducible nonvolatile memorizer module can comprise multiple physical blocks, and each physical blocks can comprise multiple storage unit, and each storage unit is positioned in a bit lines and a wordline.Storage unit in same wordline can form one or more physical page, and these physical page can be divided into lower physical page and upper physical page.After lower physical page must first be programmed, upper physical page just can be programmed.Therefore, if a lower physical page stores data, and when the upper physical page of same wordline, there occurs sequencing mistake in programmed bit, then these data stored by lower physical page also may make a mistake.A kind of mode of solution utilizes error-correcting code to protect the data that may make a mistake.But when a storage unit generating program mistake, this sequencing mistake also may to have influence on same bit line other storage unit.That is, many error-correcting codes may be needed to carry out protected data.Therefore, how effective mistake in correcting code protects the data in storage unit, for this reason the subject under discussion be concerned about of those skilled in the art.
Summary of the invention
The invention provides a kind of data guard method, memorizer memory devices and Memory Controller, effectively can protect the data in reproducible nonvolatile memorizer module.
The present invention one exemplary embodiment proposes a kind of data guard method, for controlling a reproducible nonvolatile memorizer module.This reproducible nonvolatile memorizer module comprises many wordline, multiple bit lines and multiple storage unit.Each storage unit is positioned at wherein that wordline is with on a wherein bit lines, and these storage unit form multiple entity erased cell.This data guard method comprises: utilize the data stored by multiple first storage unit in said memory cells to produce one first error-correcting code.These first storage unit are positioned on many first wordline and many first bit lines.In storage unit on each first bit line, the data stored by a storage unit are only had to be produce the first error-correcting code.
In an exemplary embodiment, the first above-mentioned wordline is separated by least one wordline.
In an exemplary embodiment, the first above-mentioned bit line is separated by least one bit line.
In an exemplary embodiment, above-mentioned data guard method also comprises: utilize the data in said memory cells stored by multiple second storage unit to produce one second error-correcting code.These second storage unit are positioned on many second wordline and many second bit lines.In storage unit on each second bit line, the data stored by a storage unit are only had to be produce the second error-correcting code.In addition, above-mentioned first error-correcting code is different from the second error-correcting code.
In an exemplary embodiment, one of them of above-mentioned second bit line is same as one of them of above-mentioned first bit line.
In an exemplary embodiment, one of them of above-mentioned second wordline is same as one of them of above-mentioned first wordline.
In an exemplary embodiment, above-mentioned data guard method also comprises: the first error-correcting code be stored in one of them above-mentioned entity erased cell.
In an exemplary embodiment, above-mentioned data guard method also comprises: the first error-correcting code is divided into multiple part, by the entity program unit of one of them section store wherein corresponding to first wordline; By wherein another section store in the entity program unit corresponding to another first wordline.
The present invention one exemplary embodiment proposes a kind of memorizer memory devices, comprises connector, reproducible nonvolatile memorizer module and Memory Controller.Connector is electrically connected to a host computer system.Reproducible nonvolatile memorizer module comprises many wordline, multiple bit lines and multiple storage unit.Each storage unit is positioned at wherein that wordline is with on a wherein bit lines, and these storage unit form multiple entity erased cell.Memory Controller is electrically connected to connector and reproducible nonvolatile memorizer module, produces one first error-correcting code in order to utilize the data stored by multiple first storage unit in said memory cells.These first storage unit are positioned on many first wordline and many first bit lines.In storage unit on each first bit line, the data stored by a storage unit are only had to be produce the first error-correcting code.
In an exemplary embodiment, above-mentioned Memory Controller is also in order to utilize the data in said memory cells stored by multiple second storage unit to produce one second error-correcting code.These second storage unit are positioned on many second wordline and many second bit lines.In storage unit on each second bit line, the data stored by a storage unit are only had to be produce the second error-correcting code.In addition, above-mentioned first error-correcting code is different from the second error-correcting code.
In an exemplary embodiment, above-mentioned Memory Controller is also in order to be stored in the first error-correcting code in one of them above-mentioned entity erased cell.
In an exemplary embodiment, above-mentioned Memory Controller is also in order to be divided into multiple part by the first error-correcting code, by in the entity program unit of one of them section store wherein corresponding to first wordline, and by wherein another section store in the entity program unit corresponding to another first wordline.
The present invention one exemplary embodiment proposes a kind of Memory Controller, for controlling above-mentioned reproducible nonvolatile memorizer module.This Memory Controller comprises host interface, memory interface and bug check and correcting circuit.Host interface is electrically connected to a host computer system.Memory interface is electrically connected to reproducible nonvolatile memorizer module.Bug check and correcting circuit utilize the data stored by multiple first storage unit in said memory cells to produce one first error-correcting code.These first storage unit are positioned on many first wordline and many first bit lines.In storage unit on each first bit line, the data stored by a storage unit are only had to be produce the first error-correcting code.
In an exemplary embodiment, above-mentioned bug check and correcting circuit are also in order to utilize the data in said memory cells stored by multiple second storage unit to produce one second error-correcting code.These second storage unit are positioned on many second wordline and many second bit lines.In storage unit on each second bit line, the data stored by a storage unit are only had to be produce the second error-correcting code.In addition, above-mentioned first error-correcting code is different from the second error-correcting code.
In an exemplary embodiment, above-mentioned Memory Controller also comprises a memory management circuitry, in order to the first error-correcting code to be stored in one of them above-mentioned entity erased cell.
In an exemplary embodiment, above-mentioned Memory Controller also comprises a memory management circuitry, in order to the first error-correcting code is divided into multiple part, by in the entity program unit of one of them section store wherein corresponding to first wordline, and by wherein another section store in the entity program unit corresponding to another first wordline.
Based on above-mentioned; the data guard method that exemplary embodiment of the present invention proposes, memorizer memory devices and Memory Controller; the data stored by storage unit according to not corresponding lines and in different wordline can produce error-correcting code, by this can more effectively protected data.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A is the schematic diagram of host computer system and the memorizer memory devices illustrated according to an exemplary embodiment;
Figure 1B is the schematic diagram of computer, input/output device and the memorizer memory devices illustrated according to an exemplary embodiment;
Fig. 1 C is the schematic diagram of host computer system and the memorizer memory devices illustrated according to an exemplary embodiment;
Fig. 2 is the schematic block diagram illustrating the memorizer memory devices shown in Figure 1A;
Fig. 3 be according to an exemplary embodiment illustrate the vertical view of NAND string;
Fig. 4 be according to an exemplary embodiment illustrate the equivalent circuit diagram of NAND string;
Fig. 5 is the side view that the NAND illustrated according to an exemplary embodiment goes here and there;
Fig. 6 is the schematic diagram illustrating an entity erased cell according to an exemplary embodiment;
Fig. 7 is the schematic block diagram of the Memory Controller illustrated according to an exemplary embodiment;
Fig. 8 is the schematic diagram illustrating generation first error-correcting code according to an exemplary embodiment;
Fig. 9 ~ Figure 11 be according to an exemplary embodiment illustrate the schematic diagram of generation first error-correcting code.
Description of reference numerals:
1000: host computer system;
1100: computer;
1102: microprocessor;
1104: random access memory;
1106: input/output device;
1108: system bus;
1110: data transmission interface;
1702: mouse;
1704: keyboard;
1706: display;
1208: printer;
1212: portable disk;
1214: storage card;
1216: solid state hard disc;
1310: digital camera;
1312:SD card;
1314:MMC card;
1316: memory stick;
1318:CF card;
1320: embedded storage device;
100: memorizer memory devices;
102: connector;
104: Memory Controller;
106: reproducible nonvolatile memorizer module;
304 (0) ~ 304 (R): entity erased cell;
300,302,304,306,320,322: transistor;
320CG, 300CG, 302CG, 304CG, 306CG, 322CG: control gate;
300FG, 302FG, 304FG, 306FG: floating grid;
326,328: contact point;
340: substrate;
330,332,334,336,338: polysilicon layer;
SGD, SGS: select grid;
WL0 ~ WL3: wordline;
BL (0) ~ BL (N): bit line;
360, ST0 ~ STN:NAND string;
702: memory management circuitry;
704: host interface;
706: memory interface;
708: memory buffer;
710: electric power management circuit;
712: bug check and correcting circuit;
801 ~ 804,811 ~ 814,821 ~ 824,831 ~ 834,901,911 ~ 913,921 ~ 923,843: storage unit.
Embodiment
Generally speaking, memorizer memory devices (also known as, memory storage system) comprises reproducible nonvolatile memorizer module and controller (also known as, control circuit).Usual memorizer memory devices uses together with host computer system, data can be write to memorizer memory devices or read data from memorizer memory devices to make host computer system.
Figure 1A is the schematic diagram of host computer system and the memorizer memory devices illustrated according to an exemplary embodiment.
Please refer to Figure 1A, host computer system 1000 generally comprises computer 1100 and I/O (input/output, I/O) device 1106.Computer 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the mouse 1702 of Figure 1B, keyboard 1704, display 1706 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.
In embodiments of the present invention, memorizer memory devices 100 is electrically connected by data transmission interface 1110 other elements with host computer system 1000.Data can be write to memorizer memory devices 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106 or read data from memorizer memory devices 100.Such as, memorizer memory devices 100 can be the type nonvolatile storage device of portable disk 1212, storage card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 etc. as shown in Figure 1B.
Generally speaking, host computer system 1000 is to coordinate any system with storage data substantially with memorizer memory devices 100.Although in this exemplary embodiment, host computer system 1000 explains with computer system, but host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.Such as, when host computer system is digital camera (video camera) 1310, type nonvolatile storage device is then its SD card 1312 used, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded storage device 1320 (as shown in Figure 1 C).Embedded storage device 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is directly electrically connected on the substrate of host computer system.
Fig. 2 is the schematic block diagram illustrating the memorizer memory devices shown in Figure 1A.
Please refer to Fig. 2, memorizer memory devices 100 comprises connector 102, Memory Controller 104 and reproducible nonvolatile memorizer module 106.
In this exemplary embodiment, connector 102 is compatible to advanced annex (Serial Advanced Technology Attachment, the SATA) standard of sequence.But, it must be appreciated, the present invention is not limited thereto, connector 102 can also be meet advanced annex arranged side by side (Parallel Advanced Technology Attachment, PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, safe digital (Secure Digital, SD) interface standard, a hypervelocity generation (Ultra High Speed-I, UHS-I) interface standard, hypervelocity two generation (Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory Stick, MS) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, built-in multimedia memory card (Embedded Multimedia Card, eMMC) interface standard, Common Flash Memory (Universal Flash Storage, UFS) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other standards be applicable to.
Memory Controller 104 in order to perform in the form of hardware or multiple logic gate of form of firmware implementation or steering order, and according to the instruction of host computer system 1000 carry out in reproducible nonvolatile memorizer module 106 data write, read and the operation such as to erase.
Reproducible nonvolatile memorizer module 106 is electrically connected to Memory Controller 104, and in order to store the data that host computer system 1000 writes.Reproducible nonvolatile memorizer module 106 has entity erased cell 304 (0) ~ 304 (R).Such as, entity erased cell 304 (0) ~ 304 (R) can belong to same memory crystal grain (die) or belong to different memory crystal grain.Each entity erased cell has a plurality of entity program unit respectively, and the entity program unit belonging to same entity erased cell can be written independently and side by side be erased.Such as, each entity erased cell is made up of 128 entity program unit.But it must be appreciated, the present invention is not limited thereto, each entity erased cell can be made up of 64 entity program unit, 256 entity program unit or other any entity program unit.
For NAND flash memory, an entity erased cell can comprise multiple NAND string (NAND string).Each NAND string can comprise multiple transistor be one another in series.Fig. 3 be according to an exemplary embodiment illustrate the vertical view of NAND string.Fig. 4 be according to an exemplary embodiment illustrate the equivalent circuit diagram of NAND string.Please refer to Fig. 3 and Fig. 4, NAND string 360 includes transistor 320,300,302,304,306 and 322.NAND string 360 is electrically connected to contact point 326 by transistor 320, and NAND string 360 is electrically connected to contact point 328 by transistor 322.Also a bit lines is can be described as from the circuit between contact point 326 to contact point 328.Control gate 320CG is electrically connected to select line SGD, and the voltage applied on control gate 320CG can be used for controlling transistor 320.Control gate 322CG is electrically connected to select line SGS, and the voltage put on control gate 322CG can be used for controlling transistor 322.Each transistor 300,302,304 and 306 has a control gate and a floating grid (floating gate).The voltage putting on control gate can be used to control corresponding transistor 300,302,304 and 306, and floating grid can be used to store one or more bit.Such as, transistor 300 has control gate 300CG and floating grid 300FG; Transistor 302 has control gate 302CG and floating grid 302FG; Transistor 304 has control gate 304CG and floating grid 304FG; Transistor 306 has control gate 306CG and floating grid 306FG.Control gate 300CG can be electrically connected to wordline WL3, and control gate 302CG can be electrically connected to wordline WL2, and control gate 304CG can be electrically connected to wordline WL1, and control gate 306CG can be electrically connected to wordline WL0.At this, transistor 300,302,304 and 306 also can be called as storage unit.
Fig. 5 is the side view that the NAND illustrated according to an exemplary embodiment goes here and there.Please refer to Fig. 5, NAND string 360 is arranged in substrate 340.Control gate 300CG, 302CG, 304CG and 306CG are separately positioned on floating grid 300FG, 302FG, 304FG and 306FG.Dielectric layer can be arranged on control gate 300CG, 302CG, 304CG, 306CG and between floating grid 300FG, 302FG, 304FG, 306FG.An oxide layer can be arranged between floating grid 300FG, 302FG, 304FG, 306FG and substrate 340.Contiguous storage unit can share the polysilicon layer 330,332,334,336 and 338 through mixing, and polysilicon layer can form source electrode or the drain electrode of a storage unit.Such as, polysilicon layer 332 is the drain electrode of transistor 306 and the source electrode of transistor 304; Polysilicon layer 334 is the drain electrode of transistor 304 and the source electrode of transistor 302; Polysilicon layer 336 is the drain electrode of transistor 302 and the source electrode of transistor 300, by that analogy.When electronics or electric hole are injected into floating grid 300FG, 302FG, 304FG or 306FG, the critical voltage of corresponding transistor can change, by this can equivalently in order to store one or more bit.It should be noted that in other exemplary embodiment, NAND string 360 also can comprise more storage unit, and the present invention does not limit the number of storage unit in a NAND string.
Fig. 6 is the schematic diagram illustrating an entity erased cell according to an exemplary embodiment.
Please refer to Fig. 6, for entity erased cell 304 (0), entity erased cell 304 (0) includes multiple NAND string ST0 ~ STN.Entity erased cell 304 (0) also includes many wordline WL0 ~ WL3 and multiple bit lines BL (0) ~ BL (N).Each storage unit in entity erased cell 304 (0) can be positioned on a wordline and a bit lines.Multiple storage unit in same wordline can form one or more entity program unit.Specifically, if each storage unit can store x bit, then the multiple storage unit in same wordline can form x entity program unit, and wherein x is positive integer.If positive integer x is greater than 1, then x entity program unit in same wordline also can be classified as lower entity program unit and upper entity program unit.But the present invention does not limit the numerical value of positive integer x.In general, entity erased cell is the least unit of erasing.That is, each entity erased cell contain minimal amount in the lump by the storage unit of erasing.In an exemplary embodiment, entity erased cell also can be called as physical blocks, and entity program unit can be called as physical page or entity fan (sector).
In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is multi-level cell memory (Multi Level Cell, MLC) NAND flash memory module, namely can store at least 2 bits in a storage unit.But, the present invention is not limited thereto, reproducible nonvolatile memorizer module 106 also single-order storage unit (Single Level Cell, SLC) NAND flash memory module, Complex Order storage unit (Trinary Level Cell, TLC) NAND flash memory module, other flash memory modules or other there is the memory module of identical characteristics.Or in an exemplary embodiment, reproducible nonvolatile memorizer module 106 can be three-dimensional NAND flash memory module, and this area has and usually knows that the knowledgeable should understand the configuration of wordline and bit line in three dimensional NAND type flash memory, does not repeat at this.
Fig. 7 is the schematic block diagram of the Memory Controller illustrated according to an exemplary embodiment.
Please refer to Fig. 7, Memory Controller 104 comprises memory management circuitry 702, host interface 704 and memory interface 706.
Memory management circuitry 702 is in order to the integrated operation of control store controller 104.Specifically, memory management circuitry 702 has multiple steering order, and when memorizer memory devices 100 operates, these steering orders can be performed to carry out data write, read and the operation such as to erase.
Host interface 704 is electrically connected to memory management circuitry 702 and in order to receive and to identify the instruction that transmits of host computer system 1000 and data.That is, the instruction that transmits of host computer system 1000 and data can be sent to memory management circuitry 702 by host interface 704.In this exemplary embodiment, host interface 704 is compatible to SATA standard.But, it must be appreciated and the present invention is not limited thereto, host interface 704 can also be compatible to PATA standard, IEEE1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other data transmission standards be applicable to.
Memory interface 706 is electrically connected to memory management circuitry 702 and in order to access reproducible nonvolatile memorizer module 106.That is, the data for writing to reproducible nonvolatile memorizer module 106 can be converted to the receptible form of reproducible nonvolatile memorizer module 106 via memory interface 706.
In the present invention one exemplary embodiment, Memory Controller 104 also comprises memory buffer 708, electric power management circuit 710 and bug check and correcting circuit 712.
Memory buffer 708 is electrically connected to memory management circuitry 702 and comes from the data and instruction of host computer system 1000 in order to temporary or come from the data of reproducible nonvolatile memorizer module 106.
Electric power management circuit 710 is electrically connected to memory management circuitry 702 and in order to the power supply of control store storage device 100.
Bug check and correcting circuit 712 are electrically connected to memory management circuitry 702 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 702 receives write instruction from host computer system 1000, bug check and correcting circuit 712 can be that the corresponding data that this writes instruction produce corresponding error-correcting code (Error Correcting Code, ECC Code), and the data of this write instruction corresponding can write in reproducible nonvolatile memorizer module 106 with corresponding error-correcting code by memory management circuitry 702.Afterwards, can read error-correcting code corresponding to these data when memory management circuitry 702 reads data from reproducible nonvolatile memorizer module 106, and bug check and correcting circuit 712 can according to this error-correcting code to read data execution error inspection and correction programs simultaneously.
The type of above-mentioned error-correcting code can be odd and even correction code (parity checking code), channel coding (channel coding) or other types.Such as, the error-correcting code produced can be mutual exclusion or (exclusive or, XOR) result, Hamming code (hamming code), low-density parity check code (the low density parity check code of computing, LDPC code), vortex code (turbo code) or Reed Solomon code (Reed-solomon code, RS code), the present invention is also not subject to the limits.If the length ratio of data and error-correcting code is m:n, then represent that length is that the data of m can correspond to the error-correcting code that length is n, wherein m and n is positive integer.The present invention does not limit the value of positive integer m and positive integer n yet.
In this exemplary embodiment, bug check and correcting circuit 712 can produce an error-correcting code according to data stored in the first storage unit multiple in entity erased cell.These first storage unit are positioned in many first wordline with on many first bit lines.Specifically, on each first bit line, only have the data stored by a storage unit can be used to generation first error-correcting code.Thus, if there occurs mistake when data being write to an entity program unit, and when this mistake also have impact on other storage unit in same position/wordline, then the first above-mentioned error-correcting code can be used to correct this mistake.Below the multiple exemplary embodiment of act is illustrated the different aspects of generation first error-correcting code.
Fig. 8 is the schematic diagram illustrating generation first error-correcting code according to an exemplary embodiment.
Please refer to Fig. 8, at this for storage unit 801 ~ 804,811 ~ 814,821 ~ 824 and 831 ~ 834.For simplicity, Fig. 8 does not show and selects grid, floating grid and control gate.In this exemplary embodiment, bug check and correcting circuit 712 produce the first error-correcting code to I haven't seen you for ages according to data stored in storage unit 801,812,823,834 (be labeled as " A ").Storage unit 801,812,823,834 is positioned at bit line BL (0) ~ BL (3) (also known as the first bit line) with on wordline WL0 ~ WL3 (also known as the first wordline).It should be noted that to only have the data stored by a storage unit can be used to generation first error-correcting code on each bit lines BL (0) ~ BL (3).Such as, bit line BL (0) only have the data stored by storage unit 801 can be used to generation first error-correcting code.Similarly, bit line BL (1) only have the data stored by storage unit 812 can be used to generation first error-correcting code.Thus, when generating program mistake, the first error-correcting code can have good corrigendum ability.For example, data are had to be the lower entity program unit be stored in wordline WL2.Suppose to there occurs sequencing mistake when data being write to the upper entity program unit corresponding to wordline WL2, and this mistake occurs in storage unit 812.In the case, originally the data be stored in storage unit 812 may make a mistake, and the data in storage unit 811 and 813 on same bit line BL (1) also may make a mistake.But for the first error-correcting code, above-mentioned possible mistake only can affect bit stored in a storage unit, and therefore the first error-correcting code can be used to the mistake in correcting storing unit 812.
In an exemplary embodiment, bug check and correcting circuit 712 produce second error-correcting code to I haven't seen you for ages according to data stored in storage unit 811,822,833 (be labeled as " B ").Wherein, storage unit 811,822,833 is positioned on bit line BL (1) ~ BL (3) (also known as the second bit line) and on wordline WL1 ~ WL3 (also known as the second wordline).Each the second bit line BL (1) ~ BL (3) only have the data stored by a storage unit can be used to generation second error-correcting code.Such as, bit line BL (1) only have the data stored by storage unit 811 can be used to generation second error-correcting code.In the same manner, bit line BL (2) only have the data stored by storage unit 822 can be used to generation second error-correcting code.In this exemplary embodiment, storage unit 811 and storage unit 801 are positioned on same wordline WL3, and be lay respectively at two adjacent bit lines BL (1) with on BL (0).In addition, storage unit 811 and storage unit 812 are positioned on same bit line BL (1), and be lay respectively on two adjacent wordline WL3 and WL2.This second error-correcting code is different from the first above-mentioned error-correcting code.Second error-correcting code be used to correcting storing unit 811,822, with 833 in mistake.In an exemplary embodiment, bug check all can produce corresponding error-correcting code with correcting circuit 712 to the data in all storage unit.
Fig. 9 ~ Figure 11 be according to an exemplary embodiment illustrate the schematic diagram of generation first error-correcting code.
Please refer to Fig. 9, in the exemplary embodiment of Fig. 9, bug check and correcting circuit 712 can utilize the data stored by multiple storage unit in many wordline to produce the first error-correcting code.For example, bug check and correcting circuit 712 can utilize the data in storage unit 801,811 to storage unit 901, data in storage unit 911,912 to storage unit 913, and storage unit 921, data in 922 to storage unit 923 produce the first error-correcting code.Specifically, on each bit lines Bl (0) ~ BL (N), only have the data stored by a storage unit can be used to generation first error-correcting code.In this exemplary embodiment, bug check and correcting circuit 712 can obtain equal number (such as from each wordline, 1k bit group) data, namely the size of storage unit 801, data stored by 811 to storage unit 901 is 1k bit group, and the size of data stored by storage unit 911 ~ 913 is also 1k bit group.In this exemplary embodiment, the Minimal Protective unit of the first error-correcting code is 1k bit group, and Minimal Protective unit also can be described as symbol (symbol).That is bug check and correcting circuit 712 obtain from each wordline the data that size is same as Minimal Protective unit.But according to different error-correcting codes, the size of Minimal Protective unit also can not be identical.That is, the present invention does not limit the data that will obtain how much quantity from each wordline and produces the first error-correcting code.Or for different wordline, the data that bug check and correcting circuit 712 also can obtain varying number produce the first error-correcting code.
Please refer to Figure 10, in the exemplary embodiment of Figure 10, bug check and correcting circuit 712 are at least produce the first error-correcting code according to storage unit 801, storage unit 822 with the data stored by storage unit 843.Specifically, the bit line BL (2) that the bit line BL (0) that is positioned at of storage unit 801 and storage unit 822 are positioned at is separated by a bit lines; A bit lines and the bit line BL (4) that the bit line BL (2) that storage unit 822 is positioned at and storage unit 843 are positioned at is separated by.But in another exemplary embodiment, bug check and correcting circuit 712 also can from being separated by two with up line and the storage unit being arranged in different wordline obtains data to produce the first error-correcting code.
In another exemplary embodiment, bug check and correcting circuit 712 are at least produce the first error-correcting code according to storage unit 801 and the data stored by storage unit 813.Specifically, the wordline WL1 that the wordline WL3 that is positioned at of storage unit 801 and storage unit 813 are positioned at is separated by a wordline.But in another exemplary embodiment, bug check and correcting circuit 712 also can from being separated by more than two wordline and the storage unit being arranged in not corresponding lines obtains data to produce the first error-correcting code.
Please refer to Figure 11, in the exemplary embodiment of Figure 11, bug check and correcting circuit 712 produce the first error-correcting code to I haven't seen you for ages according to data stored in storage unit 802,811,824 and 833.Or in another exemplary embodiment, bug check and correcting circuit 712 also can produce the first error-correcting code according to data stored in storage unit 804,813,822 and 831.That is, the present invention does not limit the position of the storage unit for generation first error-correcting code (or second error-correcting code).
After bug check and correcting circuit 712 produce the first error-correcting code (or second error-correcting code), produced error-correcting code can be write to one of them of entity erased cell 304 (0) ~ 304 (R) by memory management circuitry 710.In an exemplary embodiment, bug check and correcting circuit 712 obtain data to produce error-correcting code from entity erased cell 304 (0), and produced error-correcting code can write in same entity erased cell 304 (0) by memory management circuitry 710.But in another exemplary embodiment, error-correcting code also can be write to another entity erased cell by memory management circuitry 710, and the present invention is also not subject to the limits.
In an exemplary embodiment, an entity program unit can comprise a data bit area and a redundancy ratio special zone.Storage unit in data bit district stores user's data.Storage unit in redundancy ratio special zone can in order to stocking system data.If bug check and correcting circuit 712 produce the first error-correcting code according to the data in data bit district in multiple first instance programmed cell, then the first produced error-correcting code can be stored in these first instance programmed cell by bug check and correcting circuit 712 dispersedly.For example, please refer to back Fig. 9, bug check and correcting circuit 712 obtain data from the entity program unit corresponding to wordline WL1 ~ WL3, and therefore bug check and correcting circuit 712 can be divided into three parts the first produced error-correcting code.One of them part can be stored in (such as, redundancy ratio special zone) in the entity program unit corresponding to wordline WL1; Two other part then can be stored in the entity program unit (such as, redundancy ratio special zone) corresponding to wordline WL2 and WL3 respectively.But in another exemplary embodiment, the first error-correcting code produced also can all be stored in an entity program unit, and the present invention is also not subject to the limits.Or in another exemplary embodiment, the first error-correcting code produced is dispersed in the data bit district of multiple entity program unit, and the present invention is also not subject to the limits.
In this exemplary embodiment, error-correcting code produced by bug check and correcting circuit 712.But in another exemplary embodiment, error-correcting code also can be produced by memory management circuitry 710.For example, the operation of bug check and correcting circuit 712 can implementation be multiple procedure code, and these procedure codes are performed by memory management circuitry 710.The present invention one exemplary embodiment proposes a data guard method, and it can comprise the operation of bug check and correcting circuit 712, or the step that said procedure code is formed.The present invention does not limit and carrys out implementation data guard method by hardware or the mode of software.
In sum, the data guard method that exemplary embodiment of the present invention proposes, memorizer memory devices and Memory Controller, meeting basis not corresponding lines produces the first error-correcting code from the data stored by the storage unit in different wordline.Thus, when in an entity program unit, several storage unit make a mistake, and this erroneous effects to other storage unit on same bit line (or wordline) time, the first error-correcting code can be used to correct the mistake occurred.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (24)
1. a data guard method; for controlling a reproducible nonvolatile memorizer module; it is characterized in that; this reproducible nonvolatile memorizer module comprises many wordline, multiple bit lines and multiple storage unit; each those storage unit is in one of them of one of them and those bit lines being positioned at those wordline; and form multiple entity erased cell by those storage unit, this data guard method comprises:
Utilize the data in those storage unit stored by multiple first storage unit to produce one first error-correcting code, wherein those first storage unit are arranged on many first wordline of those wordline and many first bit lines of those bit lines,
Wherein, in those storage unit at each on those first bit lines, only have the data stored by a storage unit in order to produce this first error-correcting code.
2. data guard method according to claim 1, is characterized in that, those first wordline are separated by least one wordline.
3. data guard method according to claim 1, is characterized in that, those first bit lines are separated by least one bit line.
4. data guard method according to claim 1, is characterized in that, also comprises:
Utilize the data in those storage unit stored by multiple second storage unit to produce one second error-correcting code, wherein those second storage unit are arranged on many second wordline of those wordline and many second bit lines of those bit lines,
Wherein, in those storage unit at each on those second bit lines, only have the data stored by a storage unit in order to produce this second error-correcting code, and this first error-correcting code is different from this second error-correcting code.
5. data guard method according to claim 4, is characterized in that, one of them of those the second bit lines is same as one of them of those the first bit lines.
6. data guard method according to claim 4, is characterized in that, one of them of those the second wordline is same as one of them of those the first wordline.
7. data guard method according to claim 1, is characterized in that, also comprises:
This first error-correcting code is stored in one of them of those entity erased cell.
8. data guard method according to claim 1, is characterized in that, also comprises:
This first error-correcting code is divided into multiple part, one of them of those parts is stored in those the first wordline one of them corresponding to entity program unit in; And
Wherein another of those parts is stored in the entity program unit corresponding to wherein another of those the first wordline.
9. a memorizer memory devices, is characterized in that, comprising:
A connector, in order to be electrically connected to a host computer system;
One reproducible nonvolatile memorizer module, comprise many wordline, multiple bit lines and multiple storage unit, and each those storage unit is in one of them of one of them and those bit lines being positioned at those wordline, and forms multiple entity erased cell by those storage unit; And
One Memory Controller, be electrically connected to this connector and this reproducible nonvolatile memorizer module, one first error-correcting code is produced in order to utilize the data in those storage unit stored by multiple first storage unit, wherein those first storage unit are arranged on many first wordline of those wordline and many first bit lines of those bit lines
Wherein, in those storage unit at each on those first bit lines, only have the data stored by a storage unit in order to produce this first error-correcting code.
10. memorizer memory devices according to claim 9, is characterized in that, those first wordline are separated by least one wordline.
11. memorizer memory devices according to claim 9, is characterized in that, those first bit lines are separated by least one bit line.
12. memorizer memory devices according to claim 9, it is characterized in that, this Memory Controller is also in order to utilize the data in those storage unit stored by multiple second storage unit to produce one second error-correcting code, wherein those second storage unit are arranged on many second wordline of those wordline and many second bit lines of those bit lines
Wherein, in those storage unit at each on those second bit lines, only have the data stored by a storage unit in order to produce this second error-correcting code, and this first error-correcting code is different from this second error-correcting code.
13. memorizer memory devices according to claim 12, is characterized in that, one of them of those the second bit lines is same as one of them of those the first bit lines.
14. memorizer memory devices according to claim 12, is characterized in that, one of them of those the second wordline is same as one of them of those the first wordline.
15. memorizer memory devices according to claim 9, is characterized in that, this Memory Controller is also in order to be stored in this first error-correcting code in one of them of those entity erased cell.
16. memorizer memory devices according to claim 9, it is characterized in that, this Memory Controller is also in order to be divided into multiple part by this first error-correcting code, one of them of those parts is stored in those the first wordline one of them corresponding to entity program unit in, and wherein another of those parts to be stored in the entity program unit corresponding to wherein another of those the first wordline.
17. 1 kinds of Memory Controllers, for controlling a reproducible nonvolatile memorizer module, it is characterized in that, this reproducible nonvolatile memorizer module comprises many wordline, multiple bit lines and multiple storage unit, and each those storage unit is in one of them of one of them and those bit lines being positioned at those wordline, and form multiple entity erased cell by those storage unit, this Memory Controller comprises:
One host interface, in order to be electrically connected to a host computer system;
One memory interface, in order to be electrically connected to this reproducible nonvolatile memorizer module; And
One bug check and correcting circuit, one first error-correcting code is produced in order to utilize the data in those storage unit stored by multiple first storage unit, wherein those first storage unit are arranged on many first wordline of those wordline and many first bit lines of those bit lines
Wherein, in those storage unit at each on those first bit lines, only have the data stored by a storage unit in order to produce this first error-correcting code.
18. Memory Controllers according to claim 17, is characterized in that, those first wordline are separated by least one wordline.
19. Memory Controllers according to claim 17, is characterized in that, those first bit lines are separated by least one bit line.
20. Memory Controllers according to claim 17, it is characterized in that, this bug check and correcting circuit are also in order to utilize the data in those storage unit stored by multiple second storage unit to produce one second error-correcting code, wherein those second storage unit are arranged on many second wordline of those wordline and many second bit lines of those bit lines
Wherein, in those storage unit at each on those second bit lines, only have the data stored by a storage unit in order to produce this second error-correcting code, and this first error-correcting code is different from this second error-correcting code.
21. Memory Controllers according to claim 20, is characterized in that, one of them of those the second bit lines is same as one of them of those the first bit lines.
22. Memory Controllers according to claim 21, is characterized in that, one of them of those the second wordline is same as one of them of those the first wordline.
23. Memory Controllers according to claim 17, is characterized in that, also comprise:
One memory management circuitry, in order to be stored in this first error-correcting code in one of them of those entity erased cell.
24. Memory Controllers according to claim 17, is characterized in that, also comprise:
One memory management circuitry, in order to this first error-correcting code is divided into multiple part, one of them of those parts is stored in those the first wordline one of them corresponding to entity program unit in, and wherein another of those parts to be stored in the entity program unit corresponding to wherein another of those the first wordline.
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