CN1223444A

CN1223444A - Semiconductor memory device having ECC circuit

Info

Publication number: CN1223444A
Application number: CN 98124912
Authority: CN
Inventors: 蛯原信幸; 落合雅实
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1997-11-14
Filing date: 1998-11-13
Publication date: 1999-07-21

Abstract

To provide a semiconductor memory device having an ECC circuit whereof checker-data inspection of memory cells in the user areas and the ECC areas can be performed at once, the ECC code generation circuit generates the ECC code of six bits whereof logic of each bit has XOR logic of each of six different combinations of 15 bits of the data set of 32 bits, and addresses in every user areas of the bit-columns are arranged in an order of 1, 4, 2, 5, 3, 6, . . . , b, f.

Description

Semiconductor storage unit with error checking and correction circuit

The present invention relates to have the semiconductor storage unit of the error checking and correction that is used to proofread and correct the error in data that causes by the storage unit defective (below be abbreviated as ECC) circuit.

Fig. 4 is the synoptic diagram that expression ECC code produces the conventional example of circuit.

In order to check and proofread and correct a bit-errors in 32 bit data, need six ECC code.In the conventional example of Fig. 4, every of the ECC code (from each output of the lead-out terminal O0-O5 of Fig. 4) should so produce so that have from XOR (XOR) logic of each different combination of 14 of 32 bit data of input end D00-D31 output (being represented by the circle that each symbol by the XOR gate circuit at it is connected on a plurality of horizontal lines of a corresponding lead-out terminal O0-O5).

Fig. 5 is that expression has the synoptic diagram of data read/write of conventional semiconductor storage unit that the ECC code that uses Fig. 4 produces the ECC circuit of circuit.

As the input data D[31:0 that provides 32] when wanting in the write storage unit array 52, will produce circuit 51 from input data D[31:0 by the ECC code] produce 6 ECC code O[5:0], as description in conjunction with Fig. 4.

Be divided into four address 4n by 88 ground, 4n+1,4n+2 and 4n+3 (n=0,1,2 ...) memory cell array 52 in write 32 input data D[31:0].Just, for example, when n=0, first 8 D[7:0 of input data] be written in the storage unit of address 0 of the user area of ranking BIT0-BIT7.In the same way, second, third and the 4th 8 D[15:8], D[23:16] and D[31:24] write respectively in the

address

1,2 and 3 storage unit of the user area of ranking BIT0-BIT7.

With 32 input data D[31:0] side by side, from input data D[31:0] 6 ECC code O[5:0 producing] be written into the storage unit of address 4n in the ECC zone of ranking BIT0-BIT5 (rank BIT6-BIT7 and do not have the ECC zone).That is, ECC code O[5:0] the storage unit of first to the 6th address 0 that when n=0, is written into the ECC zone of ranking BIT0-BIT5 in, when n=1, be written in the storage unit on ground in the ECC zone of ranking BIT0-BIT5.

Like this, in the conventional example of Fig. 5, write fashionable continuously in the input data, by increasing n, 38 38 ground, in 32 input data and their 6 ECC code write storage unit arrays 52, and four group of 38 bit data is written in each sub-line of memory cell array 52.

When data are read from memory cell array 52, four address 4n from the user area of ranking BIT0-BIT7,4n+1,4n+2,32 user area data RD[31:0 with 4n+3] and from 6 ECC area data RO[5:0 of the corresponding address 4n in the ECC zone of ranking BIT0-BIT5] read side by side, and offer Error-Correcting Circuit 53.Even at user area RD[31:0] and ECC area data RO[5:0] 38 in have a bit-errors and from memory cell array 52, be read out, Error-Correcting Circuit 53 also can produce again to have and use ECC area data RO[5:0] input data D[31:0] 32 output data DO[31:0 of identical logic].

The product of explanation memory cell array detects now.

Before loading storage unit, if any defective is arranged in the memory cell array that will load onto ship, for example (interference) defective is disturbed in the position, and the product that be used to check detects.Verifier-data write and read is to be used for a kind of method that product detects.

Fig. 6 is the synoptic diagram that expression is written in the verifier-data in the user area of ranking one of BIT0-BIT5 (the ECC zone is not provided) (for example BIT0) in ranking BIT6-BIT7 of memory cell array 52 of Fig. 5.When verifier-data are write, provide the input data in memory cell array, to constitute grid figure (checkerboard pattern), thereby logic ' 0 ' and logic ' 1 ' are alternately write in level and the vertical direction, to be read out and to use simultaneously the hardware logic check.

Fig. 7 is the synoptic diagram of the bitmap example of expression verifier-data.

In order in ranking the user area of BIT0-BIT, to write grid figure as shown in Figure 6,32 input data D[31:0 with bitmap BP11 of Fig. 7] by n is increased to 3 from 0, write on for four times on the word line #1 of Fig. 5, then, the input data D[31:0 that has another bitmap BP12 of Fig. 7] by being increased to 7 from 4, n write on next word line #2 by four times.By repeating these programs, the grid figure is written in each the user area of ranking BIT0-BIT7.

But in the ECC zone of ranking BIT0-BIT7 of the memory cell array 52 of Fig. 5, when verifier-data of bitmap BP11 with Fig. 7 and BP12 were written in the user area, storage unit can not constitute the grid figure.

Producing circuit 51 by ECC code from input data D[31:0 with Fig. 4] 14 XORs produce ECC code O[5:1] time, for two bitmap BP11 and BP12, ECC code O[5:1] become ' 100001 '.Therefore, the logic of each storage unit in the ECC zone is being ranked BIT0 and is being ranked among the BIT5 and become ' 1 ', as shown in Figure 6, in ranking BIT1-BIT4, become ' 0 ', thereby the storage unit in the ECC zone can not be checked simultaneously with the storage unit in the user area.

Therefore, in having the conventional semiconductor storage unit of ECC circuit, should carry out twice with the product detection of verifier-data write and read, once be used for the user area, once be used for the ECC zone, use special verifier-data in the ECC zone, to constitute the grid figure.

The detection of twice verifier-data increases the cost of product.

And, also reduced the yield rate of semiconductor storage unit.In the semiconductor storage unit with ECC circuit, the bit-errors in 32 bit data can be from normal moveout correction.In other words, even a defective is arranged in 38 storage unit of address location, this address location is exactly, rank the address 4n of the user area of BIT0-BIT7,4n+1, the address 4n in the ECC zone of ranking BIT0-BIT5 of 4n+2 and 4n+3 and semiconductor storage unit also can use and not have problem.But in having the conventional semiconductor storage unit of ECC circuit, for user area and ECC zone, verifier-Data Detection should separately be carried out.Therefore, when finding a defective in 6 groups in the address in ECC zone in verifier-Data Detection, this semiconductor storage unit just is a waste product.

These are the problems that have in the conventional semiconductor storage unit of ECC circuit.

Therefore, fundamental purpose of the present invention provides the semiconductor storage unit with ECC circuit, the detection of the verifier-data of the storage unit in its user area and the ECC zone can once be carried out, by reducing the decline of the yield rate that detects number of times and avoid producing, improved the throughput rate of semiconductor storage unit owing to unnecessary waste product.

For realizing this purpose, in semiconductor storage unit of the present invention, the ECC code produces the ECC code that circuit produces six, its logic of every has each xor logic of six different combinations of 15 of 32 bit data groups, ground in each user area of ranking is according to 1,4, and 2,5,3,6 ... b, the series arrangement of f.

When in semiconductor storage unit, writing the grid figure, when carrying out the verifier of memory cell array-Data Detection, respectively the address of user area 4n to 4n+3 and 4 (n+1) in 4 (n+1)+3, ECC code ' 000000 ' and ' 111111 ' in the address 4n and 4 (n+1) that is write the ECC zone respectively, 32 first data set with logic ' 0 ' is alternately write on the positions of odd wordlines with 32 second data set with logic ' 1 ', and alternately write on the word line of even number according to the reverse order of positions of odd wordlines, n is not less than 0 integer.

Therefore, in semiconductor storage unit according to present embodiment, the detection of the verifier-data in user area that all rank and ECC zone can once be carried out, this can reduce to half with detecting number of times, and avoided in address location, having the unnecessary waste product of the memory cell array of a permissible defective, improved the throughput rate of semiconductor storage unit.

By reading following detailed description, appended claims and accompanying drawing, aforementioned, other purpose of the present invention, characteristics and advantage are more obvious, and identical mark is represented identical or corresponding part in the accompanying drawing.

In the accompanying drawing:

Fig. 1 represents the synoptic diagram of ECC code generation circuit according to an embodiment of the invention;

Fig. 2 is the bitmap example BP1 of expression complementation (complementary) data set that is used in the embodiment that is used for writing the grid figure and the synoptic diagram of BP2;

Fig. 3 is expression according to each the synoptic diagram of example of address arrangement that ranks of the memory cell array of present embodiment;

Fig. 4 is the synoptic diagram that expression ECC code produces the conventional example of circuit;

Fig. 5 is that expression uses the ECC code of Fig. 4 to produce the conventional semiconductor storage unit synoptic diagram with ECC circuit of circuit;

Fig. 6 is the synoptic diagram that expression is written in the verifier-data in the user area of ranking one of BIT0-BIT5 of memory cell array 52 of Fig. 5;

Fig. 7 is the synoptic diagram that the ECC code of expression by Fig. 4 produces the bitmap example of verifier-data that circuit produces and ECC code.

Embodiments of the invention are described with reference to the accompanying drawings.

If can prepare have bitmap complimentary to one another two data sets, it is another the phase antilogical of corresponding position that every of one of bitmap has bitmap, and, this two data set also provides two ECC codes complimentary to one another simultaneously, then by the address according to the suitable order form memory cell, the grid figure can be by in write-once user area and the ECC zone.

But, produce circuit by the conventional ECC code shown in Fig. 4, its output ECC code, its every xor logic with combination of even number (14) position, the any a pair of of two complementary data groups can provide identical ECC code, because the xor logic of the data of even bit is identical with the xor logic of the complementary data of even bit.

Therefore, the ECC code of present embodiment produces the ECC code that circuit produces six of O0-O5, and its every has from the xor logic of each various combination of 15 (odd numbers) position that the input data of 32 D00-D31 are selected, as shown in Figure 1.

Fig. 2 is the expression bitmap example BP1 of complementary data group in the present embodiment and the synoptic diagram of BP2.All positions of the first bitmap BP1 have logic ' 0 ', and the ECC code of Fig. 1 produces circuit and produces ' 000000 ' ECC code, its six six various combination xor logics of 15 with first bitmap BP1, all positions of the second bitmap BP2 have logic ' 1 ' simultaneously, and ECC code generation circuit produces ' 111111 ' complementary ECC code in the same way.

Fig. 3 is expression according to each the synoptic diagram of example of address arrangement that ranks BIT0-BIT5 of the memory cell array of the embodiment of the same structure of the memory cell array 52 with Fig. 5.In the memory cell array of Fig. 3,16 address 0-f (sexadecimal) of the first word line #1 are according to 0,4,1,5,2,6 ..., b, f, series arrangement, thus the bit data of two continuous data sets is alternately arranged.In an identical manner, 16 address 10-1f of the second word line #2 are according to 10,14,11,15 ..., 1b, 1f, etc. series arrangement, at word line #3, #4 ..., also in not having the user area of ranking BIT7 and BIT7 in ECC zone, also arrange in the same way the address.

Therefore, by n from 0 be increased to 3 on the first word line #1 (with at positions of odd wordlines #3, #5 ...)

address

4n, 4n+1, among 4n+2 and the 4n+3 alternately according to BP1, BP2, BP1, BP2 order and by n from 4 be increased to 7 the second word line #2 (with at even wordline #4, #6,) on

address

4n, 4n+1, among 4n+2 and the 4n+3 according to BP1, BP2, BP1, BP2 order is write bitmap BP1 with Fig. 2 and 32 a pair of complementary data group of BP2, can be once writing in all user area of ranking BIT0-BIT7 and ECC zone as the grid figure among Fig. 3.

Like this, the all user areas of ranking and the verifier-Data Detection in ECC zone can once be carried out in according to the semiconductor storage unit of present embodiment, like this reduced to half detection time, and avoided in address location, having the unnecessary waste product of the memory cell array of a defective of allowing, thereby improved the throughput rate of semiconductor storage unit.

The present invention has been told about in conjunction with the BP1 of Fig. 3 and the bitmap example of BP2 in the front.But, produce appropriate length any of a pair of ECC code to the complementary data group can the order of row-and-column address be used to write the grid figure by rank among the BIT0-BIT7 suitably at each, even bitmap BP1 and BP2 are too the simplest.

Claims

1. semiconductor storage unit, the memory cell array that it has ECC (error checking and correction) circuit and comprises user area and ECC zone, this ECC circuit comprises:

A kind of ECC code produces circuit, be used for producing from the data set that will write the user area and write ECC code the ECC zone, the logic of this every ECC code has the xor logic (XOR) of each various combination of a certain odd bits of this data set respectively.

2. semiconductor storage unit according to claim 1, wherein the ECC code produces circuit and produces six ECC codes, and its logic of every has each xor logic of six various combinations of 15 of 32 bit data groups.

3. semiconductor storage unit according to claim 1, wherein when a pair of complementary data group was alternately write on the word line of memory cell array, the address was according to arranging in ranking at each to constitute the grid figure.

4. semiconductor storage unit according to claim 2, wherein arrange in the following order the address in each user area: 4n, 4 (n+1), 4n+1,4 (n+1)+1,4n+2,4 (n+1)+2,4n+3,4 (n+1)+3,4 (n+2), 4 (n+3), 4 (n+2)+1,4 (n+3)+1 ... and the address in each ECC zone is according to 4n, 4 (n+1), 4 (n+2), arrange, in memory cell array, n is not less than 0 integer; With

When carrying out the verifier of memory cell array-Data Detection, respectively the address of user area 4n to 4n+3 and 4 (n+1) in 4 (n+1)+3, ECC code in the address 4n and 4 (n+1) that is write the ECC zone respectively, 32 first data set with logic ' 0 ' is alternately write on the positions of odd wordlines with 32 second data set with logic ' 1 ', and is alternately write on the even wordline according to the reverse order of positions of odd wordlines.