CN104298571B - Data guard method, memorizer memory devices and Memory Controller - Google Patents
Data guard method, memorizer memory devices and Memory Controller Download PDFInfo
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Abstract
The present invention provides a kind of data guard method, memorizer memory devices and Memory Controller, for a reproducible nonvolatile memorizer module.This data guard method includes：One first error-correcting code is produced using the data stored by multiple first memory cell in multiple memory cell.These first memory cell are located on a plurality of first wordline and a plurality of first bit line.In memory cell on each the first bit line, the data stored by only one of which memory cell are to produce the first error-correcting code.Thereby, the data in memory cell can effectively be protected.
Description
Technical field
The invention relates to a kind of data guard method, and it is non-volatile for duplicative in particular to one kind
Data guard method, memorizer memory devices and the Memory Controller of memory module.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years so that consumer is to storage
The demand of media also rapidly increases.Due to reproducible nonvolatile memorizer module（For example, flash memory）It is non-volatile with data
Property, power saving, small volume, and without characteristics such as mechanical structures, so being especially suitable for being built into above-mentioned illustrated various portable
In multimedia device.
In general, a reproducible nonvolatile memorizer module can include multiple physical blocks, each entity
Block can include multiple memory cell, and each memory cell is located on a bit line and a wordline.In same wordline
Memory cell can constitute one or more physical pages, and these physical pages can be divided into lower physical page and upper physical page
Face.After lower physical page must be first programmed, upper physical page can be just programmed.Therefore, if a lower physical page
Data have been stored, and sequencing mistake is there occurs in upper physical page of the programmed bit in same wordline, then the lower reality
Data stored by the body page be able to may also make a mistake.A kind of mode of solution is that possible hair is protected using error-correcting code
The data of raw mistake.However, when a memory cell generating program mistake, this sequencing mistake may also be influenced whether together
Other memory cell on one bit line.That is, it may be desirable to which many error-correcting codes protect data.Therefore, such as
What effective data protected using error-correcting code in memory cell, is this art personnel subject under discussion of concern.
The content of the invention
The present invention provides a kind of data guard method, memorizer memory devices and Memory Controller, can effectively protect
The data protected in reproducible nonvolatile memorizer module.
An exemplary embodiment of the invention proposes a kind of data guard method, for controlling a duplicative non-volatile memories
Device module.This reproducible nonvolatile memorizer module includes a plurality of wordline, multiple bit lines and multiple memory cell.Each
Memory cell is to be located therein a wordline and on wherein one bit line, and these memory cell constitute multiple entities and erased list
Member.This data guard method includes：Produced using the data stored by multiple first memory cell in said memory cells
One first error-correcting code.These first memory cell are located on a plurality of first wordline and a plurality of first bit line.At each
In memory cell on first bit line, the data stored by only one of which memory cell are to produce the first error-correcting code.
In an exemplary embodiment, the first above-mentioned wordline is separated by least one wordline.
In an exemplary embodiment, the first above-mentioned bit line is separated by least one bit line.
In an exemplary embodiment, above-mentioned data guard method also includes：Utilize in said memory cells multiple second
Data stored by memory cell produce one second error-correcting code.These second memory cell are to be located at a plurality of second wordline
With on a plurality of second bit line.In memory cell on each the second bit line, the data stored by only one of which memory cell
It is to produce the second error-correcting code.In addition, above-mentioned first error-correcting code is different from the second error-correcting code.
In an exemplary embodiment, one of above-mentioned second bit line be the same as above-mentioned first bit line wherein it
One.
In an exemplary embodiment, one of above-mentioned second wordline be the same as above-mentioned first wordline wherein it
One.
In an exemplary embodiment, above-mentioned data guard method also includes：First error-correcting code is stored in above-mentioned
One of entity erased cell in.
In an exemplary embodiment, above-mentioned data guard method also includes：First error-correcting code is divided into multiple portions
Point, by one of section store in the entity program unit corresponding to wherein one the first wordline；By other in which
Section store is in the entity program unit corresponding to another the first wordline.
A kind of memorizer memory devices of exemplary embodiment proposition of the invention, including connector, duplicative are non-volatile
Memory module and Memory Controller.Connector is to be electrically connected to a host computer system.Duplicative is non-volatile to be deposited
Memory modules include a plurality of wordline, multiple bit lines and multiple memory cell.Each memory cell is to be located therein a wordline
With on wherein one bit line, and these memory cell constitute multiple entity erased cells.Memory Controller is to be electrically connected with
To connector and reproducible nonvolatile memorizer module, to utilize multiple first memory cell in said memory cells
Stored data produce one first error-correcting code.These first memory cell are to be located at a plurality of first wordline and a plurality of the
On one bit line.In memory cell on each the first bit line, the data stored by only one of which memory cell are to produce
Raw first error-correcting code.
In an exemplary embodiment, above-mentioned Memory Controller using in said memory cells multiple second also to deposit
Data stored by storage unit produce one second error-correcting code.These second memory cell be located at a plurality of second wordline with
On a plurality of second bit line.In memory cell on each the second bit line, the data stored by only one of which memory cell are
To produce the second error-correcting code.In addition, above-mentioned first error-correcting code is different from the second error-correcting code.
In an exemplary embodiment, above-mentioned Memory Controller is also above-mentioned the first error-correcting code to be stored in
In one of entity erased cell.
In an exemplary embodiment, above-mentioned Memory Controller by the first error-correcting code also to be divided into multiple portions
Point, by one of section store in the entity program unit corresponding to wherein one the first wordline, and will be wherein another
One section store is in the entity program unit corresponding to another the first wordline.
An exemplary embodiment of the invention proposes a kind of Memory Controller, for controlling above-mentioned duplicative non-volatile
Memory module.This Memory Controller includes HPI, memory interface and error checking and correcting circuit.Main frame
Interface is to be electrically connected to a host computer system.Memory interface is to be electrically connected to duplicative non-volatile memories
Device module.Error checking is to utilize the number stored by multiple first memory cell in said memory cells with correcting circuit
According to producing one first error-correcting code.These first memory cell are located on a plurality of first wordline and a plurality of first bit line.
In memory cell on each the first bit line, the data stored by only one of which memory cell are to produce the first mistake
Correcting code.
In an exemplary embodiment, above-mentioned error checking and correcting circuit is multiple in said memory cells also to utilize
Data stored by second memory cell produce one second error-correcting code.These second memory cell are to be located at a plurality of second
In wordline and a plurality of second bit line.In memory cell on each the second bit line, stored by only one of which memory cell
Data are to produce the second error-correcting code.In addition, above-mentioned first error-correcting code is different from the second error-correcting code.
In an exemplary embodiment, above-mentioned Memory Controller also includes a memory management circuitry, to by first
Error-correcting code is stored in above-mentioned one of entity erased cell.
In an exemplary embodiment, above-mentioned Memory Controller also includes a memory management circuitry, to by first
Error-correcting code is divided into some, by the entity program corresponding to one of section store wherein first wordline
In unit, and by other in which section store in the entity program unit corresponding to another the first wordline.
Based on above-mentioned, data guard method, memorizer memory devices and memory control that exemplary embodiment of the present invention is proposed
Device processed, can produce error-correcting code according to the data stored by the memory cell on not corresponding lines and different wordline, thereby may be used
More effectively to protect data.
For the features described above and advantage of the present invention can be become apparent, special embodiment below, and it is detailed to coordinate accompanying drawing to make
Carefully it is described as follows.
Brief description of the drawings
Figure 1A is the schematic diagram of host computer system according to depicted in an exemplary embodiment and memorizer memory devices；
Figure 1B is showing for computer according to depicted in an exemplary embodiment, input/output device and memorizer memory devices
It is intended to；
Fig. 1 C are the schematic diagrames of host computer system according to depicted in an exemplary embodiment and memorizer memory devices；
Fig. 2 is the schematic block diagram for illustrating the memorizer memory devices shown in Figure 1A；
Fig. 3 is the top view of a NAND string according to depicted in an exemplary embodiment；
Fig. 4 is the equivalent circuit diagram of a NAND string according to depicted in an exemplary embodiment；
Fig. 5 is the side view of the NAND string according to depicted in an exemplary embodiment；
Fig. 6 is the schematic diagram that an entity erased cell is illustrated according to an exemplary embodiment；
Fig. 7 is the schematic block diagram of the Memory Controller according to depicted in an exemplary embodiment；
Fig. 8 is that the schematic diagram for producing the first error-correcting code is illustrated according to an exemplary embodiment；
Fig. 9~Figure 11 is the schematic diagram that the first error-correcting code is produced according to depicted in an exemplary embodiment.
Description of reference numerals：
1000：Host computer system；
1100：Computer；
1102：Microprocessor；
1104：Random access memory；
1106：Input/output device；
1108：System bus；
1110：Data transmission interface；
1702：Mouse；
1704：Keyboard；
1706：Display；
1208：Printer；
1212：Portable disk；
1214：Storage card；
1216：Solid state hard disc；
1310：Digital camera；
1312：SD card；
1314：Mmc card；
1316：Memory stick；
1318：CF cards；
1320：Embedded storage device；
100：Memorizer memory devices；
102：Connector；
104：Memory Controller；
106：Reproducible nonvolatile memorizer module；
304 (0)~304 (R)：Entity erased cell；
300、302、304、306、320、322：Transistor；
320CG、300CG、302CG、304CG、306CG、322CG：Control gate；
300FG、302FG、304FG、306FG：Floating grid；
326、328：Contact point；
340：Substrate；
330、332、334、336、338：Polysilicon layer；
SGD、SGS：Select grid；
WL0~WL3：Wordline；
BL (0)~BL (N)：Bit line；
360th, ST0~STN：NAND string；
702：Memory management circuitry；
704：HPI；
706：Memory interface；
708：Buffer storage；
710：Electric power management circuit；
712：Error checking and correcting circuit；
801~804,811~814,821~824,831~834,901,911~913,921~923,843：Storage is single
Member.
Embodiment
In general, memorizer memory devices (also known as, memory storage system) include duplicative non-volatile memories
Device module and controller (also known as, controlling circuit).Being commonly stored device storage device is used together with host computer system, so that main frame
System can write data into memorizer memory devices or be read from memorizer memory devices data.
Figure 1A is the schematic diagram of host computer system according to depicted in an exemplary embodiment and memorizer memory devices.
Figure 1A is refer to, host computer system 1000 generally comprises computer 1100 and input/output (input/output, I/O)
Device 1106.Computer 1100 includes microprocessor 1102, random access memory (random access memory, RAM)
1104th, system bus 1108 and data transmission interface 1110.Input/output device 1106 includes mouse 1702, the key such as Figure 1B
Disk 1704, display 1706 and printer 1208.It will be appreciated that the unrestricted input/output device of device shown in Figure 1B
1106, input/output device 1106 can also include other devices.
In embodiments of the present invention, memorizer memory devices 100 are by data transmission interface 1110 and host computer system
1000 other elements are electrically connected with.Pass through microprocessor 1102, random access memory 1104 and input/output device 1106
Running can write data into memorizer memory devices 100 or read data from memorizer memory devices 100.For example, depositing
Reservoir storage device 100 can be portable disk 1212, storage card 1214 or solid state hard disc (Solid State as shown in Figure 1B
Drive, SSD) 1216 grades type nonvolatile storage device.
In general, host computer system 1000 is that substantially can coordinate to store appointing for data with memorizer memory devices 100
Meaning system.Although in this exemplary embodiment, host computer system 1000 is explained with computer system, however, of the invention another
Host computer system 1000 can be digital camera, video camera, communicator, audio player or video playback in one exemplary embodiment
The systems such as device.For example, when host computer system is digital camera (video camera) 1310, type nonvolatile storage dress
Put is then its used SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF cards 1318 or embedded
Storage device 1320 (as shown in Figure 1 C).Embedded storage device 1320 include embedded multi-media card (Embedded MMC,
eMMC).It is noted that embedded multi-media card is directly to be electrically connected on the substrate of host computer system.
Fig. 2 is the schematic block diagram for illustrating the memorizer memory devices shown in Figure 1A.
Fig. 2 is refer to, it is non-that memorizer memory devices 100 include connector 102, Memory Controller 104 and duplicative
Volatile 106.
In this exemplary embodiment, connector 102 is to be compatible to the advanced annex of sequence (Serial Advanced
Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not restricted to this, connector 102 is also
Can meet advanced annex (Parallel Advanced Technology Attachment, PATA) standard arranged side by side, electrically
Marked with Electronic Engineering Association (Institute of Electrical and Electronic Engineers, IEEE) 1394
Accurate, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI
Express) standard, universal serial bus (Universal Serial Bus, USB) standard, safe digital (Secure
Digital, SD) interface standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) interface standard, the generation of ultrahigh speed two
(Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory Stick, MS) interface standard, multimedia storage
Deposit card (Multi Media Card, MMC) interface standard, built-in multimedia memory card (Embedded Multimedia
Card, eMMC) interface standard, Common Flash Memory (Universal Flash Storage, UFS) interface standard, compact flash
(Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics,
IDE) standard or other suitable standards.
Memory Controller 104 to perform in the form of hardware or form of firmware implementation multiple gates or control refer to
Order, and according to the instruction of host computer system 1000 carried out in reproducible nonvolatile memorizer module 106 data write-in,
The operation such as read and erase.
Reproducible nonvolatile memorizer module 106 is electrically connected to Memory Controller 104, and to store
The data that host computer system 1000 is write.Reproducible nonvolatile memorizer module 106 has entity erased cell 304 (0)
~304 (R).For example, entity erased cell 304 (0)~304 (R) can belong to same memory crystal grain (die) or belong to not
Same memory crystal grain.Each entity erased cell has a plurality of entity program units respectively, and belongs to same reality
The entity program unit of body erased cell can be written independently and simultaneously be erased.For example, each entity erased cell
It is made up of 128 entity program units.However, it is necessary to be appreciated that, the invention is not restricted to this, each entity is erased list
Member is can be by 64 entity program units, 256 entity program units or other any entity program unit institute group
Into.
By taking NAND-type flash memory as an example, an entity erased cell can include multiple NAND strings (NAND string).Each
NAND string can include multiple transistors being one another in series.Fig. 3 is the vertical view of a NAND string according to depicted in an exemplary embodiment
Figure.Fig. 4 is the equivalent circuit diagram of a NAND string according to depicted in an exemplary embodiment.It refer to Fig. 3 and Fig. 4, NAND string 360
Include transistor 320,300,302,304,306 and 322.NAND string 360 is electrically connected to contact point 326 by transistor 320,
And NAND string 360 is electrically connected to contact point 328 by transistor 322.From contact point 326 to the circuit between contact point 328 also
It can be described as a bit line.Control gate 320CG is electrically connected to selection line SGD, and applies the electricity on control gate 320CG
Pressure can be for controlling transistor 320.Control gate 322CG is electrically connected to selection line SGS, and puts on control gate
Voltage on 322CG can be for controlling transistor 322.Each transistor 300,302,304 and 306 has a control gate
Pole and a floating grid (floating gate).The voltage for putting on control gate can be used to control corresponding transistor
300th, 302,304 and 306, and floating grid can be used to store one or more bits.For example, transistor 300 has control gate
300CG and floating grid 300FG；Transistor 302 has control gate 302CG and floating grid 302FG；Transistor 304 has
Control gate 304CG and floating grid 304FG；Transistor 306 has control gate 306CG and floating grid 306FG.Control gate
Pole 300CG can be electrically connected to wordline WL3, and control gate 302CG can be electrically connected to wordline WL2, and control gate 304CG can electricity
Property is connected to wordline WL1, and control gate 306CG can be electrically connected to wordline WL0.Here, transistor 300,302,304 with
306 are also referred to alternatively as memory cell.
Fig. 5 is the side view of the NAND string according to depicted in an exemplary embodiment.Fig. 5 is refer to, NAND string 360 is to set
In substrate 340.Control gate 300CG, 302CG, 304CG and 306CG be separately positioned on floating grid 300FG, 302FG,
On 304FG and 306FG.One dielectric layer can be arranged on control gate 300CG, 302CG, 304CG, 306CG and floating grid
Between 300FG, 302FG, 304FG, 306FG.One oxide layer can be arranged on floating grid 300FG, 302FG, 304FG,
Between 306FG and substrate 340.Neighbouring memory cell can share the polysilicon layer 330,332,334,336 and 338 through mixing,
And a polysilicon layer can form source electrode or the drain electrode of memory cell.For example, polysilicon layer 332 is transistor 306
Drain electrode and the source electrode of transistor 304；Polysilicon layer 334 is source electrode of the drain electrode with transistor 302 of transistor 304；Polysilicon layer
336 be source electrode of the drain electrode with transistor 300 of transistor 302, by that analogy.When electronics or electric hole are injected into floating grid
When 300FG, 302FG, 304FG or 306FG, the critical voltage of corresponding transistor can change, thereby can be equally to store up
Deposit one or more bits.It is worth noting that, in other exemplary embodiments, NAND string 360 can also include more depositing
Storage unit, the present invention is not intended to limit the number of memory cell in a NAND string.
Fig. 6 is the schematic diagram that an entity erased cell is illustrated according to an exemplary embodiment.
Fig. 6 is refer to, by taking entity erased cell 304 (0) as an example, entity erased cell 304 (0) includes multiple NAND strings
ST0~STN.Entity erased cell 304 (0) also includes a plurality of wordline WL0~WL3 and multiple bit lines BL (0)~BL (N).It is real
Each memory cell in body erased cell 304 (0) can be located in a wordline and a bit line.In same wordline
Multiple memory cell can form one or more entity program units.Specifically, if each memory cell can store x ratio
Spy, then multiple memory cell in same wordline can form x entity program unit, wherein x is positive integer.If positive integer
X is more than 1, then x entity program unit in same wordline can also be classified as lower entity program unit and upper entity
Programmed cell.However, the present invention is not intended to limit positive integer x numerical value.In general, entity erased cell is the minimum erased
Unit.That is, each entity erased cell contains the memory cell being erased in the lump of minimal amount.In an exemplary embodiment
In, entity erased cell is also referred to alternatively as physical blocks, and entity program unit is referred to alternatively as physical page or entity fan
(sector)。
In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is multi-level cell memory (Multi
Level Cell, MLC) at least two bit can be stored in the memory cell of NAND-type flash memory module, i.e., one.However, the present invention is not
It is limited to this, reproducible nonvolatile memorizer module 106 also can be single-order memory cell (Single Level Cell, SLC)
NAND-type flash memory module, Complex Order memory cell（Trinary Level Cell,TLC）NAND-type flash memory module, other flash memories
Module or other there is the memory module of identical characteristic.Or, in an exemplary embodiment, duplicative non-volatile memories
Device module 106 can be three-dimensional NAND-type flash memory module, and one skilled in the art should be appreciated that three dimensional NAND type
The configuration of wordline and bit line, is not repeated herein in flash memory.
Fig. 7 is the schematic block diagram of the Memory Controller according to depicted in an exemplary embodiment.
Fig. 7 is refer to, Memory Controller 104 includes memory management circuitry 702, HPI 704 and connect with memory
Mouth 706.
Memory management circuitry 702 is used to the integrated operation of control memory controller 104.Specifically, memory pipe
Managing circuit 702 has multiple control instructions, and when memorizer memory devices 100 are operated, these control instructions can be performed
To carry out the write-in of data, read and the operation such as erase.
HPI 704 is electrically connected to memory management circuitry 702 and to receive and identification host computer system
1000 instructions transmitted and data.That is, the instruction that host computer system 1000 is transmitted can be by HPI with data
704 are sent to memory management circuitry 702.In this exemplary embodiment, HPI 704 is to be compatible to SATA standard.So
And, it should be understood that the invention is not restricted to this, HPI 704 can also be compatible to PATA standards, IEEE1394 standards,
PCI Express standards, USB standard, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards,
UFS standards, CF standards, IDE standards or other suitable data transmission standards.
Memory interface 706 is electrically connected to memory management circuitry 702 and non-volatile to access duplicative
Property memory module 106.That is, the data for being intended to write to reproducible nonvolatile memorizer module 106 can be via depositing
Memory interface 706 is converted to the receptible form of the institute of reproducible nonvolatile memorizer module 106.
In an exemplary embodiment of the invention, Memory Controller 104 also includes buffer storage 708, power management electricity
Road 710 and error checking and correcting circuit 712.
Buffer storage 708 is electrically connected to memory management circuitry 702 and is configured to temporarily store come from host computer system
1000 data and the data for instructing or coming from reproducible nonvolatile memorizer module 106.
Electric power management circuit 710 is electrically connected to memory management circuitry 702 and stores dress to control memory
Put 100 power supply.
Error checking is electrically connected to memory management circuitry 702 and to perform wrong inspection with correcting circuit 712
Look into correction program to ensure the correctness of data.Specifically, when memory management circuitry 702 connects from host computer system 1000
When receiving write instruction, error checking can produce corresponding wrong school with correcting circuit 712 for the data of this corresponding write instruction
Code (Error Correcting Code, ECC Code), and memory management circuitry 702 can be by this write instruction of correspondence
Data write with corresponding error-correcting code into reproducible nonvolatile memorizer module 106.Afterwards, when memory pipe
Reason circuit 702 can read the corresponding mistake of this data simultaneously when data are read from reproducible nonvolatile memorizer module 106
Correcting code, and error checking can perform mistake inspection according to this error-correcting code with correcting circuit 712 to the data read by mistake
Look into and correction program.
The type of above-mentioned error-correcting code can be odd and even correction code (parity checking code), channel coding
(channel coding) or other types.For example, produced error-correcting code can be mutual exclusion or (exclusive
Or, XOR) result of computing, Hamming code (hamming code), low-density parity check code (low density parity
Check code, LDPC code), vortex code (turbo code) or Reed Solomon code (Reed-solomon code, RS
Code), it is of the invention and not subject to the limits.If the length ratio of data and error-correcting code is m:N, then it represents that length is m data
It can correspond to the error-correcting code that length is n, wherein m and n is positive integer.The present invention does not limit positive integer m and positive integer n yet
Value.
In this exemplary embodiment, error checking can be deposited with correcting circuit 712 according in entity erased cell multiple first
Stored data produce an error-correcting code in storage unit.These first memory cell are located in a plurality of first wordline
With on a plurality of first bit line.Specifically, on each the first bit line, the data stored by only one of which memory cell can quilt
For producing the first error-correcting code.If consequently, it is possible to there occurs mistake when writing the data to an entity program unit
By mistake, and this mistake is when also have impact on other memory cell in same position/wordline, then the first above-mentioned error-correcting code can
For correcting this mistake.Illustrate the different aspects for producing the first error-correcting code by multiple exemplary embodiments are lifted below.
Fig. 8 is that the schematic diagram for producing the first error-correcting code is illustrated according to an exemplary embodiment.
Fig. 8 is refer to, herein by taking memory cell 801~804,811~814,821~824 and 831~834 as an example.In order to
For the sake of simplification, Fig. 8 does not show selection grid, floating grid and control gate.In this exemplary embodiment, error checking with
Correcting circuit 712 can at least produce the according to data stored in memory cell 801,812,823,834 (be labeled as " A ")
One error-correcting code.Memory cell 801,812,823,834 is to be located at bit line BL (0)~BL (3) (also known as the first bit line) and word
On line WL0~WL3 (also known as the first wordline).It is worth noting that, only one of which is deposited on each bit line BL (0)~BL (3)
Data stored by storage unit can be used to produce the first error-correcting code.For example, there was only memory cell 801 on bit line BL (0)
Stored data can be used to produce the first error-correcting code.Similarly, memory cell 812 is stored up on bit line BL (1)
The data deposited can be used to produce the first error-correcting code.Consequently, it is possible in generating program mistake, the first error-correcting code
There can be preferable corrigendum ability.For example, a pen data is previously stored the lower entity program unit in wordline WL2.
Assuming that sequencing mistake is there occurs when writing data into upper entity program unit corresponding to wordline WL2, and this is wrong
It is to occur in memory cell 812 by mistake.In the case, mistake may occur for the data being stored in originally in memory cell 812
Miss, and the memory cell 811 on same bit line BL (1) be able to may also make a mistake with the data in 813.However, right
For the first error-correcting code, above-mentioned possible mistake can only influence in a memory cell stored bit, therefore the
One error-correcting code can be used to the mistake in correcting storing unit 812.
In an exemplary embodiment, error checking at least can be according in memory cell 811,822,833 with correcting circuit 712
Stored data (be labeled as " B ") produce second error-correcting code.Wherein, memory cell 811,822,833 is position
In on bit line BL (1)~BL (3) (also known as the second bit line) with wordline WL1~WL3 (also known as the second wordline).Each second
Data on line BL (1)~BL (3) stored by only one of which memory cell can be used to produce the second error-correcting code.For example,
Only have the data stored by memory cell 811 to be used to produce the second error-correcting code on bit line BL (1).In the same manner, bit line
Only have the data stored by memory cell 822 to be used to produce the second error-correcting code on BL (2).In this exemplary embodiment
In, memory cell 811 with memory cell 801 is located on same wordline WL3, and is to be located at two adjacent bit lines respectively
On BL (1) and BL (0).In addition, memory cell 811 and memory cell 812 are located on same bit line BL (1), and it is point
On two wordline WL3 and WL2 that Wei Yu be not adjacent.This second error-correcting code is different from the first above-mentioned error-correcting code.The
Two error-correcting codes are the mistakes in correcting storing unit 811,822 and 833.In an exemplary embodiment, error checking
Corresponding error-correcting code can be all produced with the data in 712 pairs of all memory cell of correcting circuit.
Fig. 9~Figure 11 is the schematic diagram that the first error-correcting code is produced according to depicted in an exemplary embodiment.
Fig. 9 is refer to, in Fig. 9 exemplary embodiment, error checking can be using in a plurality of wordline with correcting circuit 712
Data stored by multiple memory cell produce the first error-correcting code.For example, error checking and the meeting of correcting circuit 712
Utilize 801,811 data into memory cell 901 of memory cell, 911,912 number into memory cell 913 of memory cell
According to, and memory cell 921,922 data into memory cell 923 produce the first error-correcting code.Specifically, every
On one bit line Bl (0)~BL (N), the data stored by only one of which memory cell can be used to produce the first error correction
Code.In this exemplary embodiment, error checking can obtain identical quantity (for example, 1k with correcting circuit 712 from each wordline
Bit group) data, i.e., memory cell 801,811 to the data stored by memory cell 901 size be 1k bit groups, and
The size of data stored by memory cell 911~913 is also 1k bit groups.In this exemplary embodiment, the first error correction
The Minimal Protective unit of code is 1k bit groups, and Minimal Protective unit is also referred to as symbol (symbol).That is, error checking with
Correcting circuit 712 is that the data that size is same as Minimal Protective unit are obtained from each wordline.However, according to different mistakes
Correcting code is missed, the size of Minimal Protective unit also will not be identical.To be taken that is, the present invention is not intended to limit from each wordline
Much the data of small number produce the first error-correcting code.Or, for different wordline, error checking and correcting circuit
712 can also obtain the data of varying number to produce the first error-correcting code.
Figure 10 is refer to, in Figure 10 exemplary embodiment, error checking is single at least according to storage with correcting circuit 712
Member 801, memory cell 822 produce the first error-correcting code with the data stored by memory cell 843.Specifically, store
The bit line BL (0) that unit 801 is located at is separated by a bit line with the bit line BL (2) that memory cell 822 is located at；And store list
The bit line BL (2) that member 822 is located at is separated by a bit line with the bit line BL (4) that memory cell 843 is located at.However, another
In exemplary embodiment, error checking and correcting circuit 712 can also be from being separated by two depositing with up line and positioned at different wordline
Data are obtained in storage unit to produce the first error-correcting code.
In another exemplary embodiment, error checking is single with storage at least according to memory cell 801 with correcting circuit 712
Data stored by member 813 produce the first error-correcting code.Specifically, the wordline WL3 that memory cell 801 is located at is with depositing
The wordline WL1 that storage unit 813 is located at is separated by a wordline.However, in another exemplary embodiment, error checking and correction electricity
Road 712 can also obtain data to produce the first mistake from being separated by more than two wordline and being located at the not memory cell of corresponding lines
Correcting code.
Figure 11 is refer to, in Figure 11 exemplary embodiment, error checking at least can be single according to storage with correcting circuit 712
Data stored by member 802,811,824 and 833 produce the first error-correcting code.Or, in another exemplary embodiment,
Error checking and correcting circuit 712 can also be according to stored by memory cell 804,813,822 and 831 data produce the
One error-correcting code.That is, the present invention is not intended to limit for producing the first error-correcting code (or second error-correcting code)
Memory cell position.
After error checking and correcting circuit 712 produce the first error-correcting code (or second error-correcting code), storage
Device management circuit 710 can write produced error-correcting code to wherein the one of entity erased cell 304 (0)~304 (R)
It is individual.In an exemplary embodiment, error checking and correcting circuit 712 are to obtain data from entity erased cell 304 (0) to produce
Raw error-correcting code, and produced error-correcting code can write same entity and erased list by memory management circuitry 710
In first 304 (0).However, in another exemplary embodiment, memory management circuitry 710 error-correcting code can also be write to
Another entity erased cell, it is of the invention and not subject to the limits.
In an exemplary embodiment, an entity program unit can include a data bit area and a redundant bit
Area.Memory cell in data bit area is to store user's data.Memory cell in redundancy ratio special zone can be used to storage
Deposit system data.If error checking and correcting circuit 712 are according in multiple first instance programmed cells in data bit area
Data produce the first error-correcting code, then error checking can be by produced the first error-correcting code with correcting circuit 712
Dispersedly it is stored in these first instance programmed cells.For example, Fig. 9, error checking and correcting circuit be refer to back
712 be that data are obtained from the entity program unit corresponding to wordline WL1~WL3, therefore error checking and correcting circuit 712
The first produced error-correcting code can be divided into three parts.One of part can be stored in corresponding to wordline WL1
In entity program unit (for example, redundancy ratio special zone)；Two other part can then be stored in wordline WL2 and WL3 institutes respectively
Corresponding entity program unit (for example, redundancy ratio special zone).However, in another exemplary embodiment, produced first is wrong
Correcting code can also be all stored within an entity program unit by mistake, of the invention and not subject to the limits.Or, in another model
In example embodiment, the first produced error-correcting code is dispersed in the data bit area of multiple entity program units, this
Invent and not subject to the limits.
In this exemplary embodiment, error-correcting code is as produced by error checking and correcting circuit 712.But in another model
In example embodiment, error-correcting code can also be produced by memory management circuitry 710.For example, error checking and correction electricity
The operation on road 712 can be implemented as multiple procedure codes, and these procedure codes are performed by memory management circuitry 710.This hair
A bright exemplary embodiment proposes a data guard method, and it can include error checking and the operation of correcting circuit 712, either
The step of said procedure code is formed.The present invention is not intended to limit with the mode of hardware or software come implementation data guard method.
In summary, exemplary embodiment of the present invention is proposed data guard method, memorizer memory devices and memory control
Device processed, understands the data according to stored by not corresponding lines from the memory cell in different wordline to produce the first error-correcting code.Such as
This one, when several memory cell make a mistake in an entity program unit, and this erroneous effects is to same bit line
During other memory cell in (or wordline), the first error-correcting code can be used to correct the mistake of generation.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent
The present invention is described in detail with reference to foregoing embodiments for pipe, it will be understood by those within the art that：Its according to
The technical scheme described in foregoing embodiments can so be modified, or which part or all technical characteristic are entered
Row equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology
The scope of scheme.
Claims (24)
1. a kind of data guard method, for controlling a reproducible nonvolatile memorizer module, it is characterised in that this can be answered
Writing formula non-volatile memory module includes a plurality of wordline, multiple bit lines and multiple memory cell, and those each memory cell are
On one of one of those wordline and those bit lines, and constitute multiple entities by those memory cell and smear
Except unit, the data guard method includes：
One first error-correcting code is produced using the data stored by multiple first memory cell in those memory cell, wherein
Those first memory cell are located in a plurality of first wordline in those wordline and a plurality of first bit line in those bit lines,
Wherein, in those memory cell on those each first bit lines, only one of which memory cell belongs to those and first deposited
Storage unit, and only produce first error correction to belong to the data stored by the memory cell of those the first memory cell
Code.
2. data guard method according to claim 1, it is characterised in that those first wordline are separated by least one
Wordline.
3. data guard method according to claim 1, it is characterised in that those first bit lines are separated by least one
Bit line.
4. data guard method according to claim 1, it is characterised in that also include：
One second error-correcting code is produced using the data stored by multiple second memory cell in those memory cell, wherein
Those second memory cell are located in a plurality of second wordline in those wordline and a plurality of second bit line in those bit lines,
Wherein, in those memory cell on those each second bit lines, only one of which memory cell belongs to those and second deposited
Storage unit, and only produce second error correction to belong to the data stored by the memory cell of those the second memory cell
Code, and first error-correcting code is different from second error-correcting code.
5. data guard method according to claim 4, it is characterised in that one of those second bit lines are same as
One of those first bit lines.
6. data guard method according to claim 4, it is characterised in that one of those second wordline are same as
One of those first wordline.
7. data guard method according to claim 1, it is characterised in that also include：
First error-correcting code is stored in one of those entity erased cells.
8. data guard method according to claim 1, it is characterised in that also include：
First error-correcting code is divided into some, one of those parts are stored in its of those the first wordline
One of corresponding to entity program unit in；And
By wherein another another corresponding entity program list therein for being stored in those the first wordline of those parts
In member.
9. a kind of memorizer memory devices, it is characterised in that including：
A connector, is electrically connected to a host computer system；
One reproducible nonvolatile memorizer module, including a plurality of wordline, multiple bit lines and multiple memory cell, and it is each
Those memory cell are located on one of one of those wordline and those bit lines, and by those memory cell
Constitute multiple entity erased cells；And
One Memory Controller, is electrically connected to the connector and the reproducible nonvolatile memorizer module, to utilize
Data in those memory cell stored by multiple first memory cell produce one first error-correcting code, wherein those first
Memory cell is located in a plurality of first wordline in those wordline and a plurality of first bit line in those bit lines,
Wherein, in those memory cell on those each first bit lines, only one of which memory cell belongs to those and first deposited
Storage unit, and only produce first error correction to belong to the data stored by the memory cell of those the first memory cell
Code.
10. memorizer memory devices according to claim 9, it is characterised in that those first wordline are separated by least
One wordline.
11. memorizer memory devices according to claim 9, it is characterised in that those first bit lines are separated by least
One bit line.
12. memorizer memory devices according to claim 9, it is characterised in that the Memory Controller is also to utilize
Data in those memory cell stored by multiple second memory cell produce one second error-correcting code, wherein those second
Memory cell is located in a plurality of second wordline in those wordline and a plurality of second bit line in those bit lines,
Wherein, in those memory cell on those each second bit lines, only one of which memory cell belongs to those and second deposited
Storage unit, and only produce second error correction to belong to the data stored by the memory cell of those the second memory cell
Code, and first error-correcting code is different from second error-correcting code.
13. memorizer memory devices according to claim 12, it is characterised in that one of those second bit lines phase
It is same as one of those first bit lines.
14. memorizer memory devices according to claim 12, it is characterised in that one of those second wordline phase
It is same as one of those first wordline.
15. memorizer memory devices according to claim 9, it is characterised in that the Memory Controller was also to should
First error-correcting code is stored in one of those entity erased cells.
16. memorizer memory devices according to claim 9, it is characterised in that the Memory Controller was also to should
First error-correcting code is divided into some, and one of those parts are stored in into one of those first wordline institute
In corresponding entity program unit, and the therein of those parts another is stored in the therein another of those the first wordline
In entity program unit corresponding to one.
17. a kind of Memory Controller, for controlling a reproducible nonvolatile memorizer module, it is characterised in that this can
Manifolding formula non-volatile memory module includes a plurality of wordline, multiple bit lines and multiple memory cell, and those each storages
Unit is located on one of one of those wordline and those bit lines, and constitutes multiple by those memory cell
Entity erased cell, the Memory Controller includes：
One HPI, is electrically connected to a host computer system；
One memory interface, is electrically connected to the reproducible nonvolatile memorizer module；And
One error checking and correcting circuit, to using the data stored by multiple first memory cell in those memory cell come
One first error-correcting code is produced, wherein those first memory cell are located at a plurality of first wordline in those wordline and those positions
On a plurality of first bit line in line,
Wherein, in those memory cell on those each first bit lines, only one of which memory cell belongs to those and first deposited
Storage unit, and only produce first error correction to belong to the data stored by the memory cell of those the first memory cell
Code.
18. Memory Controller according to claim 17, it is characterised in that those first wordline are separated by least one
Bar wordline.
19. Memory Controller according to claim 17, it is characterised in that those first bit lines are separated by least one
Bar bit line.
20. Memory Controller according to claim 17, it is characterised in that the error checking is also used to correcting circuit
One second error-correcting code is produced using the data stored by multiple second memory cell in those memory cell, wherein those
Second memory cell is located in a plurality of second wordline in those wordline and a plurality of second bit line in those bit lines,
Wherein, in those memory cell on those each second bit lines, only one of which memory cell belongs to those and second deposited
Storage unit, and only produce second error correction to belong to the data stored by the memory cell of those the second memory cell
Code, and first error-correcting code is different from second error-correcting code.
21. Memory Controller according to claim 20, it is characterised in that one of those second bit lines are identical
In one of those first bit lines.
22. Memory Controller according to claim 21, it is characterised in that one of those second wordline are identical
In one of those first wordline.
23. Memory Controller according to claim 17, it is characterised in that also include：
One memory management circuitry, first error-correcting code is stored in into one of those entity erased cells
In.
24. Memory Controller according to claim 17, it is characterised in that also include：
One memory management circuitry, first error-correcting code is divided into some, by one of those parts
It is stored in the entity program unit corresponding to one of those first wordline, and by the wherein another of those parts
One is stored in another corresponding entity program unit therein of those the first wordline.
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|---|---|---|---|---|
| CN1223444A (en) * | 1997-11-14 | 1999-07-21 | 日本电气株式会社 | Semiconductor memory device having ECC circuit |
| CN1288236A (en) * | 1999-09-14 | 2001-03-21 | 因芬尼昂技术股份公司 | Integrated storage unit having storage cells and reference unit |
| CN101167140A (en) * | 2005-03-24 | 2008-04-23 | 飞思卡尔半导体公司 | Memory having a portion that can be switched between use as data and use as error correction code (ECC) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8499229B2 (en) * | 2007-11-21 | 2013-07-30 | Micro Technology, Inc. | Method and apparatus for reading data from flash memory |
| KR101574208B1 (en) * | 2009-03-31 | 2015-12-07 | 삼성전자주식회사 | Nonvolatile memory device memory system including the same and operating method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1223444A (en) * | 1997-11-14 | 1999-07-21 | 日本电气株式会社 | Semiconductor memory device having ECC circuit |
| CN1288236A (en) * | 1999-09-14 | 2001-03-21 | 因芬尼昂技术股份公司 | Integrated storage unit having storage cells and reference unit |
| CN101167140A (en) * | 2005-03-24 | 2008-04-23 | 飞思卡尔半导体公司 | Memory having a portion that can be switched between use as data and use as error correction code (ECC) |
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