CN105022674A - Decoding method, memory storage device and memory control circuit unit - Google Patents

Abstract

The invention provides a decoding method, a memory storage device and a memory control circuit unit. The decoding method comprises the following steps: sending a reading order sequence, wherein the reading order sequence is used for reading memory units to obtain a plurality of first verification bits; according to the first verification bits, executing a first decoding program, and judging whether a first effective code word is generated or not; if no first effective code words are generated, sending another reading instruction sequence to obtain a plurality of second verification bits; according to the second verification bits, calculating a total number of the memory units which meet a specific condition; according to the total number, obtaining channel reliability information; and according to the channel reliability information, executing a second decoding program. Therefore, decoding correction capability is improved.

Description

Coding/decoding method, memory storage apparatus, memorizer control circuit unit

Technical field

The invention relates to a kind of coding/decoding method, and relate to a kind of coding/decoding method of reproducible nonvolatile memorizer module, memory storage apparatus and memorizer control circuit unit especially.

Background technology

Digital camera, mobile phone and MP3 player are very rapid in growth over the years, and the demand of consumer to medium is also increased rapidly.Due to reproducible nonvolatile memorizer module (such as, flash memory) there is data non-volatile, power saving, volume are little, and the characteristic such as mechanical structure, so be loaded in above-mentioned illustrated various portable multimedia devices in being applicable to very much.

In general, the data writing to reproducible nonvolatile memorizer module all can be encoded according to an error correcting code.The data read from reproducible nonvolatile memorizer module also can through corresponding decoding program.But the corrigendum ability of error correcting code has its upper limit, and the probability that in reproducible nonvolatile memorizer module, data make a mistake can change together along with serviceable life.In general, if the number of times of erasing of an entity erased cell adds in reproducible nonvolatile memorizer module, then the probability that data make a mistake also can increase, the situation of the bit that may cause righting the wrong.Therefore, how to increase the corrigendum ability of decoding, for this reason the subject under discussion be concerned about of those skilled in the art.

Summary of the invention

The invention provides a kind of coding/decoding method, memory storage apparatus and memorizer control circuit unit, the corrigendum ability of decoding can be increased.

The present invention one exemplary embodiment proposes a kind of coding/decoding method, and for reproducible nonvolatile memorizer module, wherein reproducible nonvolatile memorizer module comprises multiple first storage unit.This coding/decoding method comprises: send the first reading command sequence, and wherein the first reading command sequence reads the first storage unit to obtain multiple first checking bit in order to read voltage according to first; Perform one first decoding program according to the first checking bit, and judge whether the first decoding program produces first effective code word; If the first decoding program does not produce first effective code word, send the second reading command sequence, wherein the second reading command sequence is in order to read the first storage unit repeatedly to obtain multiple second checking bit; The sum that the first storage unit meets specified conditions is calculated according to the second checking bit; First passage reliability information is obtained according to this sum; And perform one second decoding program according to first passage reliability information.

In an exemplary embodiment, above-mentioned coding/decoding method also comprises: the second checking bit input one is preset log likelihood ratio look-up table to obtain second channel reliability information; And perform the second decoding program according to second channel reliability information.

In an exemplary embodiment, above-mentionedly calculate according to the second checking bit the step that the first storage unit meets the sum of specified conditions and comprise: according to the second checking bit one critical voltage of each the first storage unit is categorized as one of them of multiple interval; And calculate the sum of the first storage unit that each interval comprises.

In an exemplary embodiment, above-mentioned coding/decoding method also comprises: obtain the first data; One randomize routine is performed to obtain the second data to the first data; And send a write instruction sequence, wherein write instruction sequence in order to the second data to be write in the first storage unit.

In an exemplary embodiment, above-mentioned coding/decoding method also comprises: obtain one according to described sum and preset reading voltage.

In an exemplary embodiment, the second above-mentioned reading command sequence reads described first storage unit repeatedly to obtain described second checking bit in order to read voltage according to one second.

In an exemplary embodiment, the second above-mentioned reading command sequence reads described first storage unit to obtain described second checking bit in order to read voltage according to multiple second.

The present invention one exemplary embodiment proposes a kind of memory storage apparatus, comprises connecting interface unit, reproducible nonvolatile memorizer module and memorizer control circuit unit.Connecting interface unit is electrically connected to host computer system.Reproducible nonvolatile memorizer module comprises multiple first storage unit.Memorizer control circuit unit is electrically connected to connecting interface unit and reproducible nonvolatile memorizer module, in order to send the first reading command sequence.This first reading command sequence reads the first storage unit to obtain multiple first checking bit in order to read voltage according to first.Memorizer control circuit unit in order to perform the first decoding program according to the first checking bit, and judges whether the first decoding program produces first effective code word.If the first decoding program does not produce first effective code word, memorizer control circuit unit is in order to send the second reading command sequence, and wherein the second reading command sequence is in order to read the first storage unit repeatedly to obtain multiple second checking bit.Memorizer control circuit unit also in order to calculate the sum that the first storage unit meets specified conditions according to the second checking bit, obtains first passage reliability information according to this sum, and performs one second decoding program according to first passage reliability information.

In an exemplary embodiment, memorizer control circuit unit also in order to the second checking bit input is preset log likelihood ratio look-up table to obtain second channel reliability information, and performs the second decoding program according to second channel reliability information.

In an exemplary embodiment, above-mentioned memorizer control circuit unit calculates according to the second checking bit the operation that the first storage unit meets the sum of specified conditions and comprises: the critical voltage of each the first storage unit to be categorized as one of them of multiple interval according to the second checking bit by memorizer control circuit unit; Memorizer control circuit unit calculates the sum of the first storage unit that each interval comprises.

In an exemplary embodiment, above-mentioned memorizer control circuit unit is also in order to obtain the first data, randomize routine is performed to obtain the second data to the first data, and sends a write instruction sequence, wherein write instruction sequence in order to the second data to be write in the first storage unit.

In an exemplary embodiment, above-mentioned memorizer control circuit unit also presets reading voltage in order to obtain one according to described sum.

The present invention one exemplary embodiment proposes a kind of memorizer control circuit unit, for controlling above-mentioned reproducible nonvolatile memorizer module.This memorizer control circuit unit comprises host interface, memory interface, memory management circuitry and error checking and correction circuit.Host interface is electrically connected to host computer system.Memory interface is electrically connected to reproducible nonvolatile memorizer module.Memory management circuitry is electrically connected to host interface and memory interface, and in order to send the first reading command sequence, wherein the first reading command sequence reads the first storage unit to obtain multiple first checking bit in order to read voltage according to first.Error checking and correction circuit is in order to perform one first decoding program according to the first checking bit, and judges whether the first decoding program produces first effective code word.If the first decoding program does not produce first effective code word, memory management circuitry is in order to send the second reading command sequence, and wherein the second reading command sequence is in order to read the first storage unit repeatedly to obtain multiple second checking bit.The sum that memory management circuitry meets specified conditions in order to calculate the first storage unit according to the second checking bit, and obtain first passage reliability information according to this sum.Error checking and correction circuit is also in order to perform the second decoding program according to first passage reliability information.

In an exemplary embodiment, memory management circuit is also in order to preset log likelihood ratio look-up table to obtain second channel reliability information by the second checking bit input one, and error checking and correction circuit is in order to perform the second decoding program according to second channel reliability information.

In an exemplary embodiment, above-mentioned memory management circuitry calculates according to the second checking bit the operation that the first storage unit meets the sum of specified conditions and comprises: a critical voltage of each the first storage unit to be categorized as one of them of multiple interval according to the second checking bit by memory management circuitry; And memory management circuitry calculates the sum of the first storage unit that each interval comprises.

In an exemplary embodiment, above-mentioned memory management circuitry is also in order to obtain the first data, one randomize routine is performed to obtain the second data to the first data, and sends a write instruction sequence, wherein write instruction sequence in order to the second data to be write in the first storage unit.

In an exemplary embodiment, above-mentioned memory management circuitry also reads voltage in order to obtain according to described sum to preset.

Based on above-mentioned, in the coding/decoding method that exemplary embodiment of the present invention proposes, memory storage apparatus and memorizer control circuit unit, due to can be instant obtain channel reliability information, therefore can increase the corrigendum ability of decoding.

For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.

Accompanying drawing explanation

Fig. 1 is the schematic diagram of host computer system shown by an exemplary embodiment and memory storage apparatus;

Fig. 2 is the schematic diagram of computer, input/output device and memory storage apparatus shown by an exemplary embodiment;

Fig. 3 is the schematic diagram of host computer system shown by an exemplary embodiment and memory storage apparatus;

Fig. 4 is the schematic block diagram that the memory storage apparatus shown in Fig. 1 is shown;

Fig. 5 is the schematic block diagram of the reproducible nonvolatile memorizer module shown by an exemplary embodiment;

Fig. 6 is the schematic diagram of the memory cell array shown by an exemplary embodiment;

Fig. 7 is the statistical figure of the grid voltage corresponding to write data be stored in shown by an exemplary embodiment in memory cell array;

Fig. 8 is the schematic diagram reading data from storage unit shown by an exemplary embodiment;

Fig. 9 is the schematic diagram reading data from storage unit shown by another exemplary embodiment;

Figure 10 is the schematic diagram of the management reproducible nonvolatile memorizer module shown by an exemplary embodiment;

Figure 11 is the schematic block diagram of the memorizer control circuit unit shown by an exemplary embodiment;

Figure 12 is the schematic diagram that parity matrix is shown according to an exemplary embodiment;

Figure 13 illustrates according to an exemplary embodiment schematic diagram reading checking bit;

Figure 14 is the process flow diagram that coding/decoding method is shown according to an exemplary embodiment.

Description of reference numerals

1000: host computer system;

1100: computer;

1102: microprocessor;

1104: random access memory;

1106: input/output device;

1108: system bus;

1110: data transmission interface;

1202: mouse;

1204: keyboard;

1206: display;

1208: printer;

1212:U dish;

1214: memory card;

1216: solid state hard disc;

1310: digital camera;

1312:SD card;

1314:MMC card;

1316: memory stick;

1318:CF card;

1320: embedded memory storage;

100: memory storage apparatus;

102: connecting interface unit;

104: memorizer control circuit unit;

106: reproducible nonvolatile memorizer module;

2202: memory cell array;

2204: character line control circuit;

2206: bit line control circuit;

2208: row decoder;

2210: data input/output (i/o) buffer;

2212: control circuit;

702: storage unit;

704: bit line;

706: character line;

708: source electrode line;

712: select grid leak gated transistors;

714: select grid source transistor;

SGS: select grid source electrode;

SGD: select grid leak pole;

LSB: minimum effective bit;

CSB: middle significant bit;

MSB: the highest significant bit;

VA, VB, VC, VD, VE, VF, VG, V ₁~ V ₅: read voltage;

400 (0) ~ 400 (N): entity erased cell;

202: memory management circuitry;

204: host interface;

206: memory interface;

208: error checking and correction circuit;

210: memory buffer;

212: electric power management circuit;

1330: bipartite graph;

1332 (1) ~ 1332 (k): parity node;

1334 (1) ~ 1334 (n): information node;

L ₁~ L _n: channel reliability information;

L _{i → j}, L _{j → i}: reliability information;

1510,1520: store status;

1501 ~ 1506: interval;

B ₁~ b ₅: checking bit;

S1401 ~ S1408: step.

Embodiment

Generally speaking, memory storage apparatus (also claiming, storage system) comprises reproducible nonvolatile memorizer module and controller (also claiming, control circuit).Usual memory storage apparatus uses together with host computer system, data can be write to memory storage apparatus or read data from memory storage apparatus to make host computer system.

Fig. 1 is the schematic diagram of host computer system shown by an exemplary embodiment and memory storage apparatus.Fig. 2 is the schematic diagram of computer, input/output device and memory storage apparatus shown by an exemplary embodiment.

Please refer to Fig. 1, host computer system 1000 generally comprises computer 1100 and I/O (input/output, I/O) device 1106.Computer 1100 comprises microprocessor 1102, random access memory (random accessmemory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the mouse 1202 of Fig. 2, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Fig. 2, input/output device 1106 can also comprise other devices.

In one of the present invention exemplary embodiment, memory storage apparatus 100 is electrically connected with other elements of host computer system 1000 by data transmission interface 1110.Data can be write to memory storage apparatus 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106 or read data from memory storage apparatus 100.Such as, memory storage apparatus 100 can be the type nonvolatile memory storage of USB flash disk 1212, memory card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 etc. as shown in Figure 2.

Fig. 3 is the schematic diagram of host computer system shown by an exemplary embodiment and memory storage apparatus.

Generally speaking, host computer system 1000 is any system that can coordinate to store data substantially with memory storage apparatus 100.Although in this exemplary embodiment, host computer system 1000 explains with computer system, but host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.Such as, when host computer system is digital camera (video camera) 1310, type nonvolatile memory storage is then its SD card 1312 used, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded memory storage 1320 (as shown in Figure 3).Embedded memory storage 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is directly electrically connected on the substrate of host computer system.

Fig. 4 is the schematic block diagram that the memory storage apparatus shown in Fig. 1 is shown.

Please refer to Fig. 4, memory storage apparatus 100 comprises connecting interface unit 102, memorizer control circuit unit 104 and reproducible nonvolatile memorizer module 106.

In this exemplary embodiment, connecting interface unit 102 is compatible to advanced annex (SerialAdvanced Technology Attachment, the SATA) standard of sequence.But, it must be appreciated, the present invention is not limited thereto, connecting interface unit 102 also can be meet advanced annex arranged side by side (Parallel AdvancedTechnology Attachment, PATA) standard, Institute of Electrical and Electric Engineers (Institute ofElectrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, secure digital (Secure Digital, SD) interface standard, a hypervelocity generation (Ultra High Speed-I, UHS-I) interface standard, hypervelocity two generation (Ultra HighSpeed-II, UHS-II) interface standard, memory stick (Memory Stick, MS) interface standard, multimedia storage card (Multi Media Card, MMC) interface standard, down enters formula multimedia storage card (EmbeddedMultimedia Card, eMMC) interface standard, general flash memory (Universal FlashStorage, UFS) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other standards be applicable to.Connecting interface unit 102 can be encapsulated in a chip with memorizer control circuit unit 104, or connecting interface unit 102 is laid in one to comprise outside the chip of memorizer control circuit unit 104.

Memorizer control circuit unit 104 in order to perform with multiple logic gate of hardware pattern or firmware pattern implementation or steering order, and according to the instruction of host computer system 1000 carry out in reproducible nonvolatile memorizer module 106 data write, read and the running such as to erase.

Reproducible nonvolatile memorizer module 106 is electrically connected to memorizer control circuit unit 104, and in order to data that host system 1000 writes.Reproducible nonvolatile memorizer module 106 can be single-order storage unit (Single Level Cell, SLC) NAND type flash memory module, multi-level cell memory (Multi Level Cell, MLC) NAND type flash memory module (namely, the flash memory module of 2 Bit datas can be stored) in a storage unit, Complex Order storage unit (Triple Level Cell, TLC) NAND type flash memory module (namely, the flash memory module of 3 Bit datas can be stored) in a storage unit, other flash memory module or other there is the memory module of identical characteristics.

Fig. 5 is the schematic block diagram of the reproducible nonvolatile memorizer module shown by an exemplary embodiment.Fig. 6 is the schematic diagram of the memory cell array shown by an exemplary embodiment.

Please refer to Fig. 5, reproducible nonvolatile memorizer module 106 comprises memory cell array 2202, character line control circuit 2204, bit line control circuit 2206, row decoder (column decoder) 2208, data input/output (i/o) buffer 2210 and control circuit 2212.

In this exemplary embodiment, memory cell array 2202 can comprise storing multiple storage unit 702 of data, multiple selection grid leak pole (select gate drain, SGD) transistor 712 and multiple selection grid source electrode (select gate source, SGS) transistor 714 and connect many bit lines 704 of this little storage unit, many character lines 706, with common source line 708 (as shown in Figure 6).Storage unit 702 is configured in bit line 704 with on the point of crossing of character line 706 with array way (or solid stack mode).When receiving write instruction or reading command from memorizer control circuit unit 104, control circuit 2212 meeting control character line control circuit 2204, bit line control circuit 2206, row decoder 2208, data input/output (i/o) buffer 2210 writes data and reads data to memory cell array 2202 or from memory cell array 2202, wherein character line control circuit 2204 is in order to control the voltage being imparted to character line 706, bit line control circuit 2206 is in order to control the voltage being imparted to bit line 704, row decoder 2208 according to the row address in instruction to select corresponding bit line, and data input/output (i/o) buffer 2210 is in order to temporal data.

Storage unit in reproducible nonvolatile memorizer module 106 is to store many bits (bits) with the change of critical voltage.Specifically, an electric charge capture layer is had between the control gate (control gate) of each storage unit and passage.By bestowing a write voltage to control gate, the amount of electrons of electric charge capture layer can be changed, thus change the critical voltage of storage unit.This program changing critical voltage is also referred to as " writing to storage unit data " or " sequencing storage unit ".Along with the change of critical voltage, each storage unit of memory cell array 2202 has multiple store status.And can judge storage unit belongs to which store status, obtains the bit that storage unit stores by this by reading voltage.

Fig. 7 is the statistical figure of the grid voltage corresponding to write data be stored in shown by an exemplary embodiment in memory cell array.

Please refer to Fig. 7, for MLC NAND type flash memory, along with different critical voltages, each storage unit has 4 kinds of store statuss, and this little store status represents the bit such as " 11 ", " 10 ", " 00 " and " 01 " respectively.In other words, each store status comprises minimum effective bit (LeastSignificant Bit, LSB) and the highest significant bit (Most Significant Bit, MSB).In this exemplary embodiment, the 1st bit counted from left side in store status (that is, " 11 ", " 10 ", " 00 " and " 01 ") is LSB, and the count from left side the 2nd bit is MSB.Therefore, in this exemplary embodiment, each storage unit can store 2 bits.It must be appreciated, critical voltage illustrated in fig. 7 and store status thereof to should be only an example.In another exemplary embodiment of the present invention, critical voltage and store status corresponding may also be along with critical voltage is larger and arrange with " 00 " with " 11 ", " 10 ", " 01 ", or other arrange.In addition, in another exemplary embodiment, the 1st bit that also definable is counted from left side is MSB, and the count from left side the 2nd bit is LSB.

Fig. 8 is the schematic diagram reading data from storage unit shown by an exemplary embodiment, and it is for MLC NAND type flash memory.

Please refer to Fig. 8, the reading running of the storage unit of memory cell array 2202 reads voltage in control gate by bestowing, and by the conducting state of memory cell channel, carrys out the data that recognition memory cell stores.Checking bit (VA) be in order to instruction bestow read voltage VA time memory cell channel whether be conducting; Checking bit (VC) is that when bestowing reading voltage VC in order to instruction, whether memory cell channel is conducting; Checking bit (VB) is that when bestowing reading voltage VB in order to instruction, whether memory cell channel is conducting.Represent corresponding memory cell channel conducting when this hypothesis verification bit is " 1 ", and verify that bit represents when being " 0 " that corresponding memory cell channel does not have conducting.As shown in Figure 8, can judge storage unit is in which store status by checking bit (VA) ~ (VC), and then obtain stored bit.

Fig. 9 is the schematic diagram reading data from storage unit shown by another exemplary embodiment.

Please refer to Fig. 9, for a TLC NAND type flash memory, the minimum effective bit LSB that each store status comprises the 1st bit that left side is counted, the middle significant bit (Center Significant Bit, CSB) of the 2nd bit counted from left side and the highest significant bit MSB of the 3rd bit counted from left side.In this example, according to different critical voltages, storage unit has 8 kinds of store statuss (that is, " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 " and " 011 ").By applying to read voltage VA ~ VG in control gate, can the bit that stores of recognition memory cell.Wherein, what deserves to be explained is that putting in order of these 8 kinds of store statuss can be ordered according to the design of manufacturer, the non-arrangement mode with this example is limited.

Figure 10 is the schematic diagram of the management reproducible nonvolatile memorizer module shown by an exemplary embodiment.

Please refer to Figure 10, the storage unit 702 of reproducible nonvolatile memorizer module 106 can form multiple entity program unit, and this little entity program unit can form multiple entity erased cell 400 (0) ~ 400 (N).Specifically, the storage unit on same character line can form one or more entity program unit.If each storage unit can store the bit of more than 2, then the entity program unit on same character line can be classified as lower entity program unit and upper entity program unit.Such as, the LSB of each storage unit belongs to lower entity program unit, and the MSB of each storage unit belongs to entity program unit.In general, in MLC NAND type flash memory, the writing speed of lower entity program unit can be greater than the writing speed of entity program unit, or the reliability of lower entity program unit is the reliability higher than upper entity program unit.In this exemplary embodiment, entity program unit is the minimum unit of sequencing.That is, entity program unit is the minimum unit of write data.Such as, entity program unit is physical page or entity fan (sector).If entity program unit is physical page, then each entity program unit generally includes data bit district and redundancy ratio special zone.Data bit district comprises multiple entity fan, and in order to store the data of user, and redundancy ratio special zone is in order to the data (such as, error correcting code) of storage system.In this exemplary embodiment, each data bit district comprises 32 entity fans, and the size of an entity fan is 512 bit groups (byte, B).But, in other exemplary embodiment, also can comprise in data bit district 8,16 or number more or less entity fan, the present invention do not limit entity fan size and number.On the other hand, entity erased cell is the least unit of erasing.Also namely, each entity erased cell contain minimal amount in the lump by the storage unit of erasing.Such as, entity erased cell is physical blocks.

Figure 11 is the schematic block diagram of the memorizer control circuit unit shown by an exemplary embodiment.It must be appreciated, the structure of the memorizer control circuit unit shown in Figure 11 is only an example, and the present invention is not as limit.

Please refer to Figure 11, memorizer control circuit unit 104 comprises memory management circuitry 202, host interface 204, memory interface 206 and error checking and correction circuit 208.

Memory management circuitry 202 is in order to the overall operation of control store control circuit unit 104.Specifically, memory management circuitry 202 has multiple steering order, and when memory storage apparatus 100 operates, this little steering order can be performed to carry out data write, read and the running such as to erase.In addition, when memory management circuitry 202 pairs of reproducible nonvolatile memorizer module 106 perform reading, write, to erase etc. running time, be come to reproducible nonvolatile memorizer module 106 by sending one or more instruction sequence.When the operation of memory management circuitry 202 is below described, be equal to the operation that memorizer control circuit unit 104 is described, below and repeat no more.

In this exemplary embodiment, the steering order of memory management circuitry 202 carrys out implementation with firmware pattern.Such as, memory management circuitry 202 has microprocessor unit (not shown) and read only memory (not shown), and this little steering order is burned onto in this read only memory.When memory storage apparatus 100 operates, this little steering order can by microprocessor unit perform to carry out data write, read and the running such as to erase.

In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also can procedure code pattern be stored in the specific region (such as, being exclusively used in the system region of storage system data in memory module) of reproducible nonvolatile memorizer module 106.In addition, memory management circuitry 202 has microprocessor unit (not shown), read only memory (not shown) and random access memory (not shown).Particularly, this read only memory has driving code, and when memorizer control circuit unit 104 is enabled, microprocessor unit first can perform this and drive code section the steering order be stored in reproducible nonvolatile memorizer module 106 to be loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can operate this little steering order with carry out data write, read and the running such as to erase.

In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also a hardware pattern can carry out implementation.Such as, memory management circuitry 202 comprises microcontroller, Storage Unit Management circuit, storer write circuit, memory reading circuitry, storer erase circuit and data processing circuit.Erase circuit and data processing circuit of Storage Unit Management circuit, storer write circuit, memory reading circuitry, storer is electrically connected to microcontroller.Wherein, Storage Unit Management circuit is in order to manage the physical blocks of reproducible nonvolatile memorizer module 106; Storer write circuit is in order to assign write instruction data to be write in reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Memory reading circuitry is in order to assign reading command to read data from reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Storer erases circuit in order to assign instruction of erasing to reproducible nonvolatile memorizer module 106 data to be erased from reproducible nonvolatile memorizer module 106; And data processing circuit is in order to the data processed for writing to reproducible nonvolatile memorizer module 106 and the data read from reproducible nonvolatile memorizer module 106.

Host interface 204 is electrically connected to memory management circuitry 202 and in order to receive and to identify the instruction that transmits of host computer system 1000 and data.That is, the instruction that transmits of host computer system 1000 and data can be sent to memory management circuitry 202 by host interface 204.In this exemplary embodiment, host interface 204 is compatible to SATA standard.But, it must be appreciated and the present invention is not limited thereto, host interface 204 also can be compatible to PATA standard, IEEE1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other data transmission standards be applicable to.

Memory interface 206 is electrically connected to memory management circuitry 202 and in order to access reproducible nonvolatile memorizer module 106.That is, the data for writing to reproducible nonvolatile memorizer module 106 can be converted to the receptible form of reproducible nonvolatile memorizer module 106 via memory interface 206.

Error checking and correction circuit 208 is electrically connected to memory management circuitry 202 and in order to error detection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives write instruction from host computer system 1000, error checking and correction circuit 208 can be that the data of this write instruction corresponding produce corresponding error correcting code (error correcting code, or error-detecting code (error detecting code ECC), EDC), and memory management circuitry 202 data of this write instruction corresponding can be write in reproducible nonvolatile memorizer module 106 with corresponding error correcting code or error-detecting code.Afterwards, can read error correcting code corresponding to these data or error-detecting code when memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106, and error checking and correction circuit 208 can according to this error correcting code or error-detecting code to read data error detection and correction program simultaneously.In this exemplary embodiment, error checking and correction circuit 208 use low-density checksum correcting code (low density parity code, LDPC).But in another exemplary embodiment, what error checking and correction circuit 208 used also can be BCH code, convolution code (convolutional code), turbine code (turbo code).

In low-density checksum correcting code, be define effective code word with a parity matrix.Below parity matrix is labeled as matrix H, and a code word is labeled as CW.According to following equation (1), if parity check matrix H is null vector with being multiplied of code word CW, represent that code word CW is effective code word.Wherein operator represent the matrix multiple of mould 2 (mod2).In other words, the kernel (null space) of matrix H just contains all effective code words.But the present invention does not limit the content of code word CW.Such as, code word CW also can comprise the error correcting code or error-detecting code that produce by any algorithm.

$H\⊗{\mathrm{CW}}^T=0...\left(1\right)$

Wherein the dimension of matrix H is that k-takes advantage of-n (k-by-n), and the dimension of code word CW is that 1-takes advantage of-n.K and n is positive integer.Include information bit and parity bits in code word CW, namely code word CW can be expressed as [M P], and wherein vector M is made up of information bit, and vectorial P is made up of parity bits.The dimension of vector M is that 1-takes advantage of-(n-k), and the dimension of vectorial P is 1-takes advantage of-k.Below information bit and parity bits are referred to as data bit.In other words, have n data bit in code word CW, wherein the length of information bit is (n-k) bit, and the length of parity bits is k bit, and namely the code check (coderate) of code word CW is (n-k)/n.

In general can use one when encoding and produce matrix (being labeled as G below), make all can meet following equation (2) for arbitrary vector M.The dimension wherein producing matrix G is (n-k)-take advantage of-n.

$M\⊗G=\left[\mathrm{MP}\right]=\mathrm{CW}...\left(2\right)$

The code word CW produced by equation (2) is effective code word.Therefore equation (2) can be substituted into equation (1), obtain following equation (3) by this.

$H\⊗G^T\⊗M^T=0...\left(3\right)$

Because vector M can be arbitrary vector, therefore following equation (4) inherently meets.That is, after decision parity check matrix H, corresponding generation matrix G also can be determined.

$H\⊗G^T=0...\left(4\right)$

When a decoding code word CW, first can perform a parity checking program to the data bit in code word, such as parity check matrix H and code word CW phase are multiplied by generation vector (being labeled as S below, as Suo Shi following equation (5)).If vectorial S is null vector, then can direct output codons CW.If vectorial S is not null vector, then represent that code word CW is not effective code word.

$H\⊗{\mathrm{CW}}^T=S...\left(5\right)$

The dimension of vector S is that k-takes advantage of-1, and wherein each element is also referred to as syndrome (syndrome).If code word CW is not effective code word, then error checking and correction circuit 208 can perform a decoding program, to attempt correcting the error bit in code word CW.

Figure 12 is the schematic diagram that parity matrix is shown according to an exemplary embodiment.

Please refer to Figure 12, in general, parity check matrix H can be expressed as bipartite graph (bipartitegraph) 1330, comprises parity node 1332 (1) ~ 1332 (k) and information node 1334 (1) ~ 1334 (n).Each parity node 1332 (1) ~ 1332 (k) corresponds to a syndrome, and each information node 1334 (1) ~ 1334 (n) is a corresponding data bit.Corresponding relation (that is, the connection relationship between information node 1334 (1) ~ 1334 (n) and parity node 1332 (1) ~ 1332 (k)) between data bit and syndrome produced according to parity matrix.Specifically, if the element of the i-th row jth row is 1 in parity matrix, then i-th parity node 1332 (i) just can be connected to a jth information node 1334 (j), and wherein i and j is positive integer.

When memory management circuitry 202 reads n data bit (forming a code word) from reproducible nonvolatile memorizer module 106, when memory management circuitry 202 also can obtain a channel reliability information of each data bit.This channel reliability information represents that corresponding data bit is decoded as bit " 1 " or the probability of " 0 " (or claiming confidence degree), describes in detail more below.In bipartite graph 1330, information node 1334 (1) ~ 1334 (n) also can receive corresponding channel reliability information.Such as, information node 1334 (1) can receive the channel reliability information L of the 1st data bit ₁, and information node 1334 (j) can receive the channel reliability information L of a jth data bit _j.

Error checking and correction circuit 208 can according to the structure of bipartite graph 1330 and channel reliability information L ₁~ L _nperform decoding program, wherein decoding program can comprise iterative decoding.Specifically, in iterative decoding, information node 1334 (1) ~ 1334 (n) can calculate reliability information to parity node 1332 (1) ~ 1332 (k), and parity node 1332 (1) ~ 1332 (k) also can calculate reliability information to information node 1334 (1) ~ 1334 (n).These reliability informations can transmit along the limit (edge) in these bipartite graphs 1330.Such as, that parity node 1332 (i) sends information node 1334 (j) to is reliability information L _{i → j}, and information node 1334 (j) sends parity node 1332 (i) to is reliability information L _{j → i}.These reliability informations are used to expression node and think the probability (also referred to as confidence degree) that some data bits are decoded as " 1 " or " 0 " has how many.For example, reliability information L _{j → i}represent that information node 1334 (j) thinks that a jth data bit is decoded as the confidence degree (just can be or bearing) of " 1 " or " 0 ", and reliability information L _{i → j}represent that parity node 1332 (i) thinks that a jth data bit is decoded as the confidence degree of " 1 " or " 0 ".And information node 1334 (1) ~ 1334 (n) and parity node 1332 (1) ~ 1332 (k) can calculate the reliability information of output according to the reliability information inputted, it is similar to the conditional probability that calculating data bit is decoded as " 1 " or " 0 ".Therefore, the process of above-mentioned transmission reliability information is otherwise known as belief propagation (beliefpropagation).

When adopting different algorithms, information node 1334 (1) ~ 1334 (n) and/or parity node 1332 (1) ~ 1332 (k) can calculate different reliability informations.Such as, error checking and correction circuit 208 can adopt summation-product algorithm (Sum-Product Algorithm), minimum value-summation algorithm (Min-Sum Algorithm) or bit reversal algorithm (bit-flipping Algorithm), and the present invention does not limit to adopt which kind of algorithm.

In the iteration each time of iterative decoding, information node 1334 (1) ~ 1334 (n) meeting transfer reliability information is to parity node 1332 (1) ~ 1332 (k), and parity node 1332 (1) ~ 1332 (k) meeting transfer reliability information is to information node 1334 (1) ~ 1334 (n).After iteration each time, information node 1334 (1) ~ 1334 (n) can calculate each data bit according to current reliability information should be decoded as bit " 1 " or " 0 ".Next perform parity checking program to these data bits calculated, the code word formed by data bit is multiplied with parity matrix, judges whether this code word is effective code word by this.If the code word produced is effective code word, then iterative decoding can stop.If the code word produced is not effective code word, then can carry out iteration next time.If the iterations of iterative decoding is more than a preset value, then iterative decoding also can stop, and represents and decodes unsuccessfully.

Figure 13 illustrates according to an exemplary embodiment schematic diagram reading checking bit.Please refer to Figure 13, what belong to that storage unit of store status 1510 stores in this hypothesis is bit " 1 ", and the storage unit belonging to store status 1520 stores is bit " 0 ".Store status 1510 and store status 1520 have the overlapping of part, also namely voltage is read at some, the storage unit that part belongs to store status 1510 can be identified as and belong to store status 1520, and the storage unit that part belongs to store status 1520 can be identified as and belongs to store status 1510.When applying reads voltage after the control gate of storage unit, along with memory cell channel whether conducting, the checking bit acquired by memory management circuitry 202 can be " 0 " or " 1 ".If when this hypothesis memory cell channel does not have conducting, corresponding checking bit is " 0 ", otherwise is then " 1 ".In this exemplary embodiment, if memory management circuitry 202 is applied with read voltage V ₁~ V ₅to a certain storage unit, then memory management circuitry 202 can obtain 5 checking bits.For example, voltage V is read ₁correspond to checking bit b ₁; Read voltage V ₂correspond to checking bit b ₂; Read voltage V ₃correspond to checking bit b ₃; Read voltage V ₄correspond to checking bit b ₄; Read voltage V ₅correspond to checking bit b ₅.If the critical voltage of a storage unit is interval 1501, then from checking bit b ₁to checking bit b ₅, the checking bit acquired by memory management circuitry 202 can be " 11111 "; If the critical voltage of storage unit is interval 1502, then verify that bit can be " 01111 "; If the critical voltage of storage unit is interval 1503, then verify that bit can be " 00111 "; If the critical voltage of storage unit is interval 1504, then verify that bit can be " 00011 "; If the critical voltage of storage unit is interval 1505, then verify that bit can be " 00001 "; If the critical voltage of storage unit is interval 1506, then verify that bit can be " 00000 ".In another exemplary embodiment, reproducible nonvolatile memorizer module 106 also can by checking bit b ₁~ b ₅after doing computing, the checking bit after computing is sent to memory management circuitry 202.Such as, bit b is verified ₂with b ₄can mutual exclusion or computing be carried out, and verify bit b ₁with b ₅can carry out mutual exclusion or computing, memory management circuitry 202 only can obtain 3 checking bits thus.The present invention does not limit number and the content of checking bit.

In this exemplary embodiment, read voltage V ₁~ V ₅one of them can be set to sign (sign) and read voltage.This sign reads voltage and why is used to determination data bit.Such as, if read voltage V ₃for sign reads voltage, then data bit can be same as checking bit b ₃; If read voltage V ₂for sign reads voltage, then data bit can be same as checking bit b ₂, by that analogy.In each interval, belong to the probability of store status 1510 according to storage unit and belong to the probability of store status 1520, log likelihood ratio (Log Likelihood Ratio can be calculated, LLR), this log likelihood ratio is also referred to as the channel reliability information of data bit and in this exemplary embodiment.In an exemplary embodiment, the log likelihood ratio corresponding to each interval can be calculated in advance and be stored in a log likelihood ratio look-up table.Memory management circuitry 202 can according to checking bit b ₁~ b ₅produce an index, and this index is inputted in this log likelihood ratio look-up table, obtain corresponding log likelihood ratio by this using as channel reliability information.Acquired channel reliability information (that is, the L in Figure 12 ₁~ L _n) just can perform above-mentioned iterative decoding.In an exemplary embodiment, if set different signs to read voltage, then different log likelihood ratio look-up tables can be used to obtain channel reliability information.

In above-mentioned exemplary embodiment, if the number reading voltage is x, then can separate x+1 interval, wherein x is positive integer.But the present invention does not limit x reading voltage can produce several interval.(such as, only use if to read the number of voltage be 1 and read voltage V ₃), then carried out decoding program is also referred to as hard bit mode decoding program.If the number reading voltage is greater than 1, then carried out decoding program is also referred to as soft bit mode decoding program.In general, the information that hard bit mode decoding program uses is less, the error bit negligible amounts that can correct, but execution speed is very fast; And the information that soft bit mode decoding program uses is more, therefore can correct more error bit, but execution speed is also slow.In addition, in an exemplary embodiment, when carrying out hard bit mode decoding program, memory management circuitry 202 directly can calculate channel reliability information according to acquired checking bit, can't pass through log likelihood ratio look-up table.Such as, if checking bit is " 1 ", then channel reliability information can be set as y; If checking bit is " 0 ", then channel reliability information can be set as-y, and wherein y is real number.

In this exemplary embodiment, error checking and correction circuit 208 use low-density checksum correcting code.But in another exemplary embodiment, what error checking and correction circuit 208 used also can be BCH code, convolution code, turbine code or other there is the algorithm of hard bit mode decoding program and soft bit mode decoding program.In addition, above-mentioned channel reliability information also can be used in arbitrary algorithm.In other words, above-mentioned hard bit mode decoding program and soft bit mode decoding program also can belong to the algorithms such as BCH code, convolution code or turbine code.Specifically, in this exemplary embodiment, if hard bit mode decoding program does not produce effective code word, memory management circuitry 202 can be set up a new log likelihood ratio look-up table according to acquired checking bit and carry out recording channel reliability information, and default log likelihood ratio look-up table can not be used to obtain channel reliability information.Therefore, the channel reliability information used comparatively meets the actual distribution state of the critical voltage of storage unit.In addition, hard bit mode decoding program and soft bit mode decoding program can be adopted simultaneously or are adopted separately, and the present invention is not subject to the limits.

In an exemplary embodiment, when reading the data in multiple first storage unit, memory management circuitry 202 first can send one first reading command sequence, in order to read these first storage unit and to obtain multiple first checking bit.In an exemplary embodiment, these first storage unit belong to same entity program unit (being such as the decoding specification according to BCH code).Such as, the first reading command sequence is in order to read an entity program unit to obtain the first checking bit according to one or more the first reading voltage.Such as, the first reading voltage is the reading voltage V in Figure 13 ₃.But in another exemplary embodiment, these first storage unit also can be belong to same entity fan, same entity erased cell, same error correction frame (ECC frame) or distribute arbitrarily.Error checking and correction circuit 208 can perform one first decoding program according to these the first checking bits, and judges whether the first decoding program produces effective code word (also claiming first effective code word).If the first decoding program does not produce effective code word, memory management circuitry 202 can send the second reading command sequence, in order to read the first storage unit according to one or more the second reading voltage repeatedly to obtain multiple second checking bit.Such as, in an exemplary embodiment, the second reading voltage can be the reading voltage V in Figure 13 ₁, V ₂, V ₃, V ₄with V ₅one of them, and the second reading command sequence in order to instruction according to this second read voltage read same entity program unit repeatedly, to obtain the second checking bit.Or in an exemplary embodiment, the second reading voltage includes the reading voltage V in Figure 13 ₁, V ₂, V ₃, V ₄with V ₅at least wherein two, and the second reading command sequence in order to instruction according to this little second read voltage read same entity program unit repeatedly, to obtain the second checking bit.In addition, in an exemplary embodiment, if the first reading voltage comprises V ₃, then the second reading voltage includes V ₁, V ₂, V ₄with V ₅at least wherein two, and get rid of V ₃.

Memory management circuitry 202 can according to these second checking bits calculate the first storage unit meet specified conditions one sum.For example, memory management circuitry 202 can according to the critical voltage of second checking bit decision each the first storage unit be drop in interval 1501 ~ 1506 which, and calculate the sum of the first storage unit that each interval 1501 ~ 1506 comprises.But above-mentioned specified conditions also can be used for judging that second verifies whether bit is " 1 " or " 0 ", and above-mentioned sum can indicate that how many second checking bits are " 1 " or " 0 ", and the present invention does not limit the content of specified conditions.

Next, memory management circuitry 202 can obtain first passage reliability information according to the sum of the first storage unit meeting specified conditions.Such as, the curve that one can form " V " font can be depicted according to the sum of the first storage unit in interval 1501 ~ 1506, the first reliability information corresponding to part in the middle of " V " font curve can comparatively close to 0, and the absolute value of the first reliability information corresponding to part in " V " font curve both sides is larger.Or memory management circuitry 202 also can utilize a log likelihood ratio look-up table, and above-mentioned sum is inputted this log likelihood ratio look-up table to obtain first passage reliability information, the present invention is also not subject to the limits.Then, error checking and correction circuit 208 can perform the second decoding program according to acquired first passage reliability.The first passage reliability used owing to performing the second decoding program is instant generation, and therefore these first passage reliability informations comparatively meet the first storage unit store status instantly, and the second decoding program has good corrigendum ability by this.In addition, the first passage reliability that can obtain acquired by first passage reliability information and utilization according to the sum of the first storage unit meeting specified conditions at present due to error checking and correction circuit 208 performs the second decoding program, so memory management circuitry 202 does not now need reading one can be stored in the log likelihood ratio look-up table in reproducible nonvolatile memorizer module 106 or go scanning reproducible nonvolatile memorizer module 106 to perform the second decoding program to adjust reading voltage.

In addition, in an exemplary embodiment, memory management circuitry 202 also can skip over the first decoding program, and directly send the second reading command sequence, to read the first storage unit repeatedly to obtain above-mentioned second checking bit, and perform above-mentioned according to the second checking bit calculate the first storage unit meet the sum of specified conditions operation, above-mentionedly obtain the operation of channel reliability information and above-mentioned second decoding program according to this sum.

In an exemplary embodiment, after the sum obtaining the first storage unit in each interval 1501 ~ 1506, also can obtain one according to these sums and preset reading voltage.Such as, the voltage sets corresponding to part minimum in above-mentioned " V " font curve can be read voltage for presetting by memory management circuitry 202.When lower secondary reading the first storage unit, memory management circuitry 202 just can be preset reading voltage according to this and read the first storage unit to perform the first decoding program or the second decoding program.

It should be noted that the above-mentioned sum meeting the first storage unit of specified conditions likely can be relevant with the content of the data that the first storage unit stores.Such as, if the data that the first storage unit stores are bit " 1 " entirely, then what in interval 1501, the number of the first storage unit can be relative is more.But in an exemplary embodiment, when memory management circuitry 202 obtains one first data, and when the first data will be write to the first storage unit, memory management circuitry 202 first can perform a randomize routine to obtain the second data to the first data.Such as, memory management circuitry 202 can obtain a random data and this random data and the first data are done arbitrary logical operation to obtain the second data.But, the content of the present invention's not restricted randomization program.Following memory management circuitry 202 can write to the first storage unit the second data.Thus, the above-mentioned sum meeting the first storage unit of specified conditions is just not easy relevant with the content of the data that the first storage unit stores.

In an exemplary embodiment, if the second above-mentioned decoding program does not produce effective code word (yet claiming second effective code word), then memory management circuitry 202 can utilize default log likelihood ratio look-up table again to obtain channel reliability information (also referred to as the second reliability information), and re-executes the second decoding program.For example, these default log likelihood ratio look-up tables provided by the manufacturer of reproducible nonvolatile memorizer module 106.When the first passage reliability information of above-mentioned instant generation cannot produce effective code word, memory management circuitry 202 above-mentioned second checking bit can be inputed to default log likelihood ratio look-up table one of them to obtain second channel reliability information.Error checking and correction circuit 208 also can perform the second decoding program according to second channel reliability information.If utilize the second decoding program performed by above-mentioned default log likelihood ratio look-up table still not produce effective code word, error checking and correction circuit 208 can attempt other default log likelihood ratio look-up table.If the second channel reliability information that all default log likelihood ratio look-up tables produce all cannot produce effective code word, then represent and decode unsuccessfully.

In addition, in an exemplary embodiment, after obtaining above-mentioned second checking bit, memory management circuitry 202 first to utilize default log likelihood ratio look-up table to obtain the second reliability information, and error checking and correction circuit 208 can perform the second decoding program according to this second reliability information.Then, if default log likelihood ratio look-up table that is whole or a predetermined number has all been previously used, and the second decoding program performed by the second reliability information still cannot produce effective code word, then memory management circuitry 202 just can perform and above-mentionedly calculate the first storage unit meet the operation of the sum of specified conditions and the above-mentioned operation obtaining first passage reliability information according to this sum according to the second checking bit, and error checking and correction circuit 208 can perform the second decoding program according to first passage reliability information.That is, in an exemplary embodiment, only have when default log likelihood ratio look-up table does not apply use partly or completely, just can go immediately to obtain first passage reliability information, and perform the second decoding program according to this.By this, speed and the stability of decoding can be promoted.

It is worth mentioning that, in an exemplary embodiment, be using hard bit mode decoding program as above-mentioned first decoding program, and using soft bit mode decoding program as above-mentioned second decoding program.But in another exemplary embodiment, above-mentioned first decoding program also can be soft bit mode decoding program, and/or above-mentioned second decoding program also can be hard bit mode decoding program.

Figure 14 is the process flow diagram that coding/decoding method is shown according to an exemplary embodiment.

In step S1401, send the first reading command sequence, read the first storage unit to obtain multiple first checking bit in order to read voltage according to first.In step S1402, perform the first decoding program according to the first checking bit.In step S1403, judge whether to produce effective code word.If the first decoding program produces effective code word, in step S1404, export effective code word.If the first decoding program does not produce effective code word, in step S1405, send the second reading command sequence, in order to read the first storage unit repeatedly to obtain multiple second checking bit.In step S1406, calculate according to the second checking bit the sum that the first storage unit meets specified conditions.In step S1407, obtain first passage reliability information according to above-mentioned sum.In step S1408, perform the second decoding program according to first passage reliability information.

But in Figure 14, each step has described in detail as above, just repeats no more at this.It should be noted that in Figure 14, each step can implementation be multiple procedure code or circuit, the present invention is also not subject to the limits.In addition, the method for Figure 14 above embodiment of can arranging in pairs or groups uses, and also can be used alone, the present invention is also not subject to the limits.

In sum, the coding/decoding method that exemplary embodiment of the present invention proposes, memory storage apparatus and memorizer control circuit unit, can after the first decoding program failure, obtain to make carbon copies and show nonvolatile memory channel reliability information instantly or preset and read voltage, the corrigendum ability of decoding can be increased by this.

Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.

Claims (21)

1. a coding/decoding method, for a reproducible nonvolatile memorizer module, is characterized in that, this reproducible nonvolatile memorizer module comprises multiple first storage unit, and this coding/decoding method comprises:

Send one first reading command sequence, wherein this first reading command sequence reads those first storage unit to obtain multiple first checking bit in order to read voltage according to one first;

Perform one first decoding program according to those the first checking bits, and judge whether this first decoding program produces one first effective code word;

If this first decoding program does not produce this first effective code word, send one second reading command sequence, wherein this second reading command sequence is in order to read those first storage unit repeatedly to obtain multiple second checking bit;

According to those second checking bits calculate those first storage unit meet specified conditions one sum;

A first passage reliability information is obtained according to this sum; And

One second decoding program is performed according to this first passage reliability information.

2. coding/decoding method according to claim 1, is characterized in that, also comprises:

Those the second checking bit inputs one are preset log likelihood ratio look-up table to obtain a second channel reliability information; And

This second decoding program is performed according to this second channel reliability information.

3. coding/decoding method according to claim 1, is characterized in that, calculates the step that those first storage unit meet this sum of these specified conditions comprise according to those the second checking bits:

One of them of multiple interval is categorized as according to a critical voltage of those the second checking bits those first storage unit by each; And

Calculate the sum of those the first storage unit that each those interval comprises.

4. coding/decoding method according to claim 1, is characterized in that, also comprises:

Obtain one first data;

One randomize routine is performed to obtain one second data to these first data; And

Send a write instruction sequence, wherein this write instruction sequence is in order to write to these second data in those first storage unit.

5. coding/decoding method according to claim 1, is characterized in that, also comprises:

Obtain one according to this sum and preset reading voltage.

6. coding/decoding method according to claim 1, is characterized in that, this second reading command sequence reads those first storage unit repeatedly to obtain those the second checking bits in order to read voltage according to one second.

7. coding/decoding method according to claim 1, is characterized in that, this second reading command sequence reads those first storage unit to obtain those the second checking bits in order to read voltage according to multiple second.

8. a memory storage apparatus, is characterized in that, comprising:

One connecting interface unit, in order to be electrically connected to a host computer system;

One reproducible nonvolatile memorizer module, comprises multiple first storage unit; And

One memorizer control circuit unit, be electrically connected to this connecting interface unit and this reproducible nonvolatile memorizer module, in order to send one first reading command sequence, wherein this first reading command sequence reads those first storage unit to obtain multiple first checking bit in order to read voltage according to one first

Wherein, this memorizer control circuit unit in order to perform one first decoding program according to those the first checking bits, and judges whether this first decoding program produces one first effective code word,

If this first decoding program does not produce this first effective code word, this memorizer control circuit unit is in order to send one second reading command sequence, and wherein this second reading command sequence is in order to read those first storage unit repeatedly to obtain multiple second checking bit,

Wherein, the sum that this memorizer control circuit unit meets specified conditions in order to calculate those first storage unit according to those the second checking bits, obtain a first passage reliability information according to this sum, and perform one second decoding program according to this first passage reliability information.

9. memory storage apparatus according to claim 8, it is characterized in that, this memorizer control circuit unit also in order to those the second checking bit inputs one are preset log likelihood ratio look-up table to obtain a second channel reliability information, and performs this second decoding program according to this second channel reliability information.

10. memory storage apparatus according to claim 8, is characterized in that, this memorizer control circuit unit calculates according to those the second checking bits the operation that those first storage unit meet this sum of these specified conditions and comprises:

This memorizer control circuit unit is categorized as one of them of multiple interval according to a critical voltage of those the second checking bits those first storage unit by each; And

This memorizer control circuit unit calculates the sum of those the first storage unit that each those interval comprises.

11. memory storage apparatus according to claim 8, it is characterized in that, this memorizer control circuit unit is also in order to obtain one first data, one randomize routine is performed to obtain one second data to these first data, and send a write instruction sequence, wherein this write instruction sequence is in order to write to these second data in those first storage unit.

12. memory storage apparatus according to claim 8, is characterized in that, this memorizer control circuit unit also presets reading voltage in order to obtain one according to this sum.

13. memory storage apparatus according to claim 8, is characterized in that, this second reading command sequence reads those first storage unit repeatedly to obtain those the second checking bits in order to read voltage according to one second.

14. memory storage apparatus according to claim 8, is characterized in that, this second reading command sequence reads those first storage unit to obtain those the second checking bits in order to read voltage according to multiple second.

15. 1 kinds of memorizer control circuit unit, for controlling a reproducible nonvolatile memorizer module, is characterized in that, this reproducible nonvolatile memorizer module comprises multiple first storage unit, and this memorizer control circuit unit comprises:

One host interface, in order to be electrically connected to a host computer system;

One memory interface, in order to be electrically connected to this reproducible nonvolatile memorizer module;

One memory management circuitry, be electrically connected to this host interface and this memory interface, in order to send one first reading command sequence, wherein this first reading command sequence reads those first storage unit to obtain multiple first checking bit in order to read voltage according to one first; And

One error checking and correction circuit, in order to perform one first decoding program according to those the first checking bits, and judges whether this first decoding program produces one first effective code word,

If this first decoding program does not produce this first effective code word, this memory management circuitry is in order to send one second reading command sequence, and wherein this second reading command sequence is in order to read those first storage unit repeatedly to obtain multiple second checking bit,

Wherein, the sum that this memory management circuitry meets specified conditions in order to calculate those first storage unit according to those the second checking bits, and obtain a first passage reliability information according to this sum,

Wherein, this error checking and correction circuit is in order to perform one second decoding program according to this first passage reliability information.

16. memorizer control circuit unit according to claim 15, it is characterized in that, this memory management circuit is also in order to preset log likelihood ratio look-up table to obtain a second channel reliability information by those the second checking bit inputs one, and this error checking and correction circuit is in order to perform this second decoding program according to this second channel reliability information.

17. memorizer control circuit unit according to claim 15, is characterized in that, this memory management circuitry calculates according to those the second checking bits the operation that those first storage unit meet this sum of these specified conditions and comprises:

This memory management circuitry is categorized as one of them of multiple interval according to a critical voltage of those the second checking bits those first storage unit by each; And

This memory management circuitry calculates the sum of those the first storage unit that each those interval comprises.

18. memorizer control circuit unit according to claim 15, it is characterized in that, this memory management circuitry is also in order to obtain one first data, one randomize routine is performed to obtain one second data to these first data, and send a write instruction sequence, wherein this write instruction sequence is in order to write to these second data in those first storage unit.

19. memorizer control circuit unit according to claim 15, is characterized in that, this memory management circuitry also presets reading voltage in order to obtain one according to this sum.

20. memorizer control circuit unit according to claim 15, is characterized in that, this second reading command sequence reads those first storage unit repeatedly to obtain those the second checking bits in order to read voltage according to one second.

21. memorizer control circuit unit according to claim 15, is characterized in that, this second reading command sequence reads those first storage unit to obtain those the second checking bits in order to read voltage according to multiple second.