CN111324478B - Decoding method, memory control circuit unit and memory storage device - Google Patents

Decoding method, memory control circuit unit and memory storage device Download PDF

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Publication number
CN111324478B
CN111324478B CN201811530594.1A CN201811530594A CN111324478B CN 111324478 B CN111324478 B CN 111324478B CN 201811530594 A CN201811530594 A CN 201811530594A CN 111324478 B CN111324478 B CN 111324478B
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data
threshold value
memory
ratio
physical
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CN111324478A (en
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林纬
许祐诚
陈思玮
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a decoding method, a memory control circuit unit and a memory storage device. The method comprises the following steps: reading the first physical programming unit by using the first reading voltage to obtain first data; judging whether a first ratio of a first number of first bit values to a second number of second bit values in the first data is larger than a threshold value; when the first proportion is not larger than the threshold value, performing decoding operation according to the first data to generate first decoded data and outputting the first decoded data; and when the first ratio is greater than the threshold value, not performing decoding operation according to the first data.

Description

Decoding method, memory control circuit unit and memory storage device
Technical Field
The invention relates to a decoding method, a memory control circuit unit and a memory storage device.
Background
Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, such that consumer demand for storage media has also increased rapidly. Since the rewritable nonvolatile memory module (e.g., flash memory) has the characteristics of nonvolatile data, power saving, small size, no mechanical structure, etc., it is very suitable for being built in the various portable multimedia devices as exemplified above.
Generally, when a read voltage is used to read data from a rewritable nonvolatile memory module, the memory management circuit can decode the read data to obtain the data to be read. However, when decoding fails, the memory management circuit performs a re-Read (Retry-Read) mechanism to re-acquire another Read voltage, and uses the other Read voltage to Read to re-acquire the Read data and decode. The memory management circuit performs the decoding operation according to the retrieved verification bits to retrieve another decoded data composed of a plurality of decoding bits. The mechanism for re-acquiring the read voltage to re-read may be repeatedly performed until the number of times exceeds the preset number of times.
In particular, in the re-reading mechanism, the memory management circuit usually reads a data and re-obtains another read voltage to perform a read operation when a decoding operation performed according to the data fails. In other words, before another read voltage is obtained, two steps of "read" and "decode" are usually performed, and when the decode fails, another read voltage is obtained to perform the read operation. However, the more times the read voltage is retrieved, the more time it takes. Therefore, how to reduce the execution time of the re-reading mechanism is one of the problems to be solved by those skilled in the art.
Disclosure of Invention
The invention provides a decoding method, a memory control circuit unit and a memory storage device, which can reduce the execution time of a re-reading mechanism and further improve the data reading efficiency.
The invention provides a decoding method, which is used for a rewritable nonvolatile memory module, the rewritable nonvolatile memory module is provided with a plurality of physical erasing units, each physical erasing unit in the plurality of physical erasing units is provided with a plurality of physical programming units, and the decoding method comprises the following steps: reading a first physical programming unit of a first physical erasing unit in the plurality of physical erasing units by using a first reading voltage in the plurality of reading voltages to obtain first data; judging whether a first ratio of a first number of first bit values to a second number of second bit values in the first data is larger than a threshold value or not; when the first proportion is not larger than the threshold value, performing a decoding operation according to the first data to generate first decoded data, and outputting the first decoded data; and when the first ratio is greater than the threshold value, not performing the decoding operation according to the first data.
In an embodiment of the present invention, the step of determining whether the first ratio of the first number of the first bit values and the second number of the second bit values in the first data is greater than the threshold value includes: calculating a difference between the first number and the second number; when the quotient obtained by dividing the difference by a first numerical value is not larger than the threshold value, judging that the first ratio is not larger than the threshold value; and when the quotient obtained by dividing the difference by the first numerical value is larger than the threshold value, judging that the first ratio is larger than the threshold value. Wherein the first value is a sum of the first number and the second number.
In one embodiment of the present invention, the threshold value is ten percent.
In an embodiment of the invention, when the first ratio is greater than the threshold value, the method further includes: reading the first physical programming unit by using a second reading voltage in the plurality of reading voltages to obtain second data; judging whether a second ratio of a third number of the first bit values to a fourth number of the second bit values in the second data is greater than the threshold value; when the second proportion is not greater than the threshold value, performing the decoding operation according to the second data to generate second decoded data, and outputting the second decoded data; and when the second ratio is greater than the threshold value, not performing the decoding operation according to the second data.
In an embodiment of the present invention, before the step of reading the first physical program unit of the first physical erase unit of the plurality of physical erase units using the first read voltage of the plurality of read voltages to obtain the first data, the method further includes: receiving a write command from a host system for writing a third data to the rewritable nonvolatile memory module; performing a scrambling operation on the third data according to the write command to generate scrambled data (scrambled data), wherein a third ratio of a fifth number of the first bit values to a sixth number of the second bit values in the scrambled data is not greater than the threshold value; and writing the scrambled data to the first physical programming unit.
The invention provides a memory control circuit unit, which is used for a rewritable nonvolatile memory module, the rewritable nonvolatile memory module is provided with a plurality of physical erasing units, each physical erasing unit in the plurality of physical erasing units is provided with a plurality of physical programming units, and the memory control circuit unit comprises: host interface, memory interface and memory management circuitry. The host interface is used for being electrically connected to the host system. The memory interface is electrically connected to the rewritable nonvolatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used for executing the following operations: reading a first physical programming unit of a first physical erasing unit in the plurality of physical erasing units by using a first reading voltage in the plurality of reading voltages to obtain first data; judging whether a first ratio of a first number of first bit values to a second number of second bit values in the first data is larger than a threshold value or not; when the first proportion is not larger than the threshold value, performing a decoding operation according to the first data to generate first decoded data, and outputting the first decoded data; and when the first ratio is greater than the threshold value, not performing the decoding operation according to the first data.
In an embodiment of the present invention, in the operation of determining whether the first proportion of the first number of the first bit values and the second number of the second bit values in the first data is greater than the threshold value, the memory management circuit is further configured to calculate a difference between the first number and the second number. When the quotient obtained by dividing the difference by a first value is not greater than the threshold value, the memory management circuit is further configured to determine that the first ratio is not greater than the threshold value. The memory management circuit is further configured to determine that the first ratio is greater than the threshold value when a quotient obtained by dividing the difference by the first value is greater than the threshold value. Wherein the first value is the sum of the first number and the second number.
In one embodiment of the present invention, the threshold value is ten percent.
In an embodiment of the invention, when the first ratio is greater than the threshold value, the memory management circuit is further configured to read the first physical programming unit to obtain a second data using a second read voltage of the plurality of read voltages. The memory management circuit is further configured to determine whether a second ratio of a third number of the first bit values to a fourth number of the second bit values in the second data is greater than the threshold value. When the second ratio is not greater than the threshold value, the memory management circuit is further configured to perform the decoding operation according to the second data to generate a second decoded data, and output the second decoded data. When the second ratio is greater than the threshold, the memory management circuit does not perform the decoding operation based on the second data.
In an embodiment of the present invention, before the operation of reading the first physical program unit of the first physical erase unit of the plurality of physical erase units to obtain the first data using the first read voltage of the plurality of read voltages, the memory management circuit is further configured to receive a write command from the host system to write a third data to the rewritable nonvolatile memory module. The memory management circuit is further configured to perform a scrambling operation on the third data according to the write instruction to generate scrambled data (scrambled data), wherein a third ratio of a fifth number of the first bit values to a sixth number of the second bit values in the scrambled data is not greater than the threshold value. The memory management circuit is also configured to write the scrambled data to the first physical programming unit.
The invention provides a memory storage device. The memory storage device includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being electrically connected to a host system. The rewritable nonvolatile memory module is provided with a plurality of physical erasing units, and each physical erasing unit in the plurality of physical erasing units is provided with a plurality of physical programming units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for executing the following operations: reading a first physical programming unit of a first physical erasing unit in the plurality of physical erasing units by using a first reading voltage in the plurality of reading voltages to obtain first data; judging whether a first ratio of a first number of first bit values to a second number of second bit values in the first data is larger than a threshold value or not; when the first proportion is not larger than the threshold value, performing a decoding operation according to the first data to generate first decoded data, and outputting the first decoded data; and when the first ratio is greater than the threshold value, not performing the decoding operation according to the first data.
In an embodiment of the present invention, in the operation of determining whether the first ratio of the first number of the first bit values and the second number of the second bit values in the first data is greater than the threshold value, the memory control circuit unit is further configured to calculate a difference between the first number and the second number. When the quotient obtained by dividing the difference by a first value is not greater than the threshold value, the memory control circuit unit is further configured to determine that the first ratio is not greater than the threshold value. When the quotient obtained by dividing the difference by the first value is greater than the threshold value, the memory control circuit unit is further configured to determine that the first ratio is greater than the threshold value. Wherein the first value is the sum of the first number and the second number.
In one embodiment of the present invention, the threshold value is ten percent.
In an embodiment of the invention, when the first ratio is greater than the threshold value, the memory control circuit unit is further configured to read the first physical programming unit to obtain a second data using a second read voltage of the plurality of read voltages. The memory control circuit unit is further configured to determine whether a second ratio of a third number of the first bit values to a fourth number of the second bit values in the second data is greater than the threshold value. When the second ratio is not greater than the threshold value, the memory control circuit unit is further configured to perform the decoding operation according to the second data to generate a second decoded data, and output the second decoded data. When the second ratio is greater than the threshold value, the memory control circuit unit does not perform the decoding operation according to the second data.
In an embodiment of the present invention, before the operation of reading the first physical program unit of the first physical erase unit of the plurality of physical erase units to obtain the first data using the first read voltage of the plurality of read voltages, the memory control circuit unit is further configured to receive a write command from the host system to write a third data to the rewritable nonvolatile memory module. The memory control circuit unit is further configured to perform a scrambling operation on the third data according to the write command to generate scrambled data (scrambled data), wherein a third ratio of a fifth number of the first bit values to a sixth number of the second bit values in the scrambled data is not greater than the threshold value. The memory control circuit unit is also configured to write the scrambled data to the first physical programming unit.
The invention provides a decoding method, which is used for a rewritable nonvolatile memory module, the rewritable nonvolatile memory module is provided with a plurality of physical erasing units, each physical erasing unit in the plurality of physical erasing units is provided with a plurality of physical programming units, and the decoding method comprises the following steps: reading a first physical programming unit of a first physical erasing unit in the plurality of physical erasing units by using a first reading voltage in the plurality of reading voltages to obtain first data; judging whether a first ratio of a first number of first bit values to a second number of second bit values in the first data is larger than a threshold value or not; when the first proportion is not larger than the threshold value, performing a decoding operation according to the first data to generate first decoded data, and outputting the first decoded data; when the first ratio is greater than the threshold value, reading the first physical programming unit by using a second reading voltage of the plurality of reading voltages to obtain second data; judging whether a second ratio of a third number of the first bit values to a fourth number of the second bit values in the second data is greater than the threshold value; when the second proportion is not greater than the threshold value, performing the decoding operation according to the second data to generate second decoded data, and outputting the second decoded data; and when the second ratio is greater than the threshold value, not performing the decoding operation according to the second data.
Based on the above, the decoding method, the memory control circuit unit and the memory storage device of the present invention can quickly determine whether decoding failure of a piece of data is likely to occur when the piece of data is read out and not decoded, and directly retrieve another read voltage to perform a read operation when decoding failure is likely to occur. By the method, the execution time of the re-reading mechanism can be reduced, and the data reading efficiency is further improved.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention;
FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to another example embodiment of the invention;
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an example embodiment;
FIG. 6 is a schematic diagram of a memory cell array according to an example embodiment;
FIG. 7 is a graph showing statistical distribution of gate voltages corresponding to write data stored in a memory cell array according to an example embodiment;
FIG. 8 is a schematic diagram illustrating reading data from a memory cell according to an example embodiment;
FIG. 9 is a schematic diagram illustrating reading data from a memory cell according to another example embodiment;
FIG. 10 is an exemplary schematic diagram of a physical erase unit according to the present exemplary embodiment;
FIG. 11 is a schematic block diagram of a memory control circuit unit according to an example embodiment of the invention;
FIG. 12 is a schematic diagram of a multi-frame encoding according to an example embodiment of the invention;
FIG. 13 is a schematic diagram illustrating a re-read mechanism according to an example embodiment;
fig. 14 is a flowchart illustrating a decoding method according to an example embodiment.
Description of the reference numerals
10: memory storage device
11: host system
110: system bus
111: processor and method for controlling the same
112: random access memory
113: read-only memory
114: data transmission interface
12: input/output (I/O) device
20: motherboard
201: USB flash disk
202: memory card
203: solid state disk
204: wireless memory storage device
205: global positioning system module
206: network interface card
207: wireless transmission device
208: keyboard with keyboard body
209: screen panel
210: horn with horn body
32: SD card
33: CF card
34: embedded memory device
341: embedded multimedia card
342: embedded multi-chip packaging storage device
402: connection interface unit
404: memory control circuit unit
406: rewritable nonvolatile memory module
2202: memory cell array
2204: word line control circuit
2206: bit line control circuit
2208: line decoder
2210: data input/output buffer
2212: control circuit
502. C1-C8: memory cell
504: bit line
506: word line
508: common source line
512: select gate drain transistor
514: select gate source transistor
LSB: least significant bit
CSB: intermediate significant bits
MSB: most significant bits
VA, VA1, VB, VC, VD, VE, VF, VG, 1440 to 1444: reading voltage
1301. 1303, 1305, 1307, 1309: physical programming unit group
702: memory management circuit
704: host interface
706: memory interface
708: error checking and correcting circuit
710: buffer memory
712: power management circuit
801 (1) to 801 (r): position of
820: encoding data
810 (0) to 810 (E): physical programming unit
1410. 1420: distribution of
1430: region(s)
S1401: a step of receiving a write instruction to write the third data to the rewritable nonvolatile memory module from the host system
S1403: performing a scrambling operation on the third data according to the write instruction to generate scrambled data
S1405: writing the scrambled data to the first physical programming unit
S1407: reading the first physical programming unit using a first read voltage of the plurality of read voltages to obtain first data
S1409: judging whether the first ratio of the first number of the first bit values and the second number of the second bit values in the first data is larger than a threshold value
S1411: a step of performing a decoding operation based on the first data to generate first decoded data and outputting the first decoded data
S1413: reading the first physical programming unit using a second read voltage of the plurality of read voltages to obtain second data
S1415: judging whether the second ratio of the third number of the first bit values to the fourth number of the second bit values in the second data is larger than a threshold value
S1417: a step of performing a decoding operation based on the second data to generate second decoded data and outputting the second decoded data
S1419: step of not performing decoding operation according to the second data
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Memory storage devices are typically used with host systems so that the host system can write data to or read data from the memory storage device.
FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 are electrically connected to a system bus 110.
In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 through the system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.
In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through a wired or wireless manner via the data transmission interface 114. The memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (iBeacon) or the like based on a variety of wireless communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.
In an example embodiment, the host system referred to is any system that can cooperate with substantially a memory storage device to store data. Although the host system is described in the above exemplary embodiment as a computer system, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player or a tablet computer, and the memory storage device 30 may be a variety of nonvolatile memory storage devices such as an SD card 32, a CF card 33 or an embedded storage device 34. The embedded memory device 34 includes embedded memory devices of various types, such as an embedded multimedia card (eMMC) 341 and/or an embedded multi-chip package memory device (embedded Multi Chip Package, eMCP) 342, which directly electrically connects the memory module to the substrate of the host system.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable nonvolatile memory module 406.
In the present exemplary embodiment, the connection interface unit 402 is compatible with the serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may be a Flash Memory Card (MMC) interface standard, an embedded multimedia Memory Card (Embedded Multimedia Card, eMMC) interface standard, a Secure Digital (Universal Flash Storage, UFS) interface standard, an Ultra High Speed Flash-II (UHS-I) interface standard, a Memory Stick Flash (MS) interface standard, a Multi-Chip Package (Multi-Chip Package) interface standard, a multimedia Card (MMC) interface standard, an embedded multimedia Memory Card (Embedded Multimedia Card, eMMC) interface standard, a Flash Memory Card (Universal Flash Storage, UFS) interface standard, an embedded Flash Memory Chip Package (embedded Multi Chip Package, eMMC) interface standard, a Compact Flash Memory Card (Flash) interface standard, or other Flash drive-integrated standard, which are compatible with the parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in a single chip, or the connection interface unit 402 may be disposed off-chip with the memory control circuit unit 404.
The memory control circuit unit 404 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to the instructions of the host system 11.
The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a complex-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
The memory cells in the rewritable nonvolatile memory module 406 are arranged in an array. The memory cell array will be described below in terms of a two-dimensional array. However, it should be noted that the following exemplary embodiment is only one example of a memory cell array, and in other exemplary embodiments, the configuration of the memory cell array may be adjusted to meet the practical requirements.
FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an example embodiment. FIG. 6 is a schematic diagram of a memory cell array according to an example embodiment.
Referring to fig. 5 and 6, the rewritable nonvolatile memory module 406 includes a memory cell array 2202, a word line control circuit 2204, a bit line control circuit 2206, a column decoder 2208, a data input/output buffer 2210 and a control circuit 2212.
In the present example embodiment, the memory cell array 2202 may include a plurality of memory cells 502 for storing data, a plurality of select gate drain (select gate drain, SGD) transistors 512 and a plurality of select gate source (select gate source, SGS) transistors 514, and a plurality of bit lines 504, a plurality of word lines 506, and a common source line 508 (as shown in fig. 6) connecting such memory cells. Memory cells 502 are arranged in an array (or stacked in a three-dimensional fashion) at the intersections of bit lines 504 and word lines 506. When a write command or a read command is received from the memory control circuit unit 404, the control circuit 2212 controls the word line control circuit 2204, the bit line control circuit 2206, the row decoder 2208, the data input/output buffer 2210 to write data into the memory cell array 2202 or read data from the memory cell array 2202, wherein the word line control circuit 2204 is used for controlling the voltage applied to the word line 506, the bit line control circuit 2206 is used for controlling the voltage applied to the bit line 504, the row decoder 2208 selects the corresponding bit line according to the column address in the command, and the data input/output buffer 2210 is used for temporarily storing data.
The memory cells in the rewritable nonvolatile memory module 406 store multiple bits (bits) with a change in threshold voltage. Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This process of changing the threshold voltage is also referred to as "writing data to a memory cell" or "programming a memory cell". Each memory cell of the memory cell array 2202 has a plurality of memory states as the threshold voltage changes. And the memory cell can be judged to be in which memory state by reading the voltage, thereby obtaining the bit stored by the memory cell.
FIG. 7 is a graph showing a statistical distribution of gate voltages corresponding to write data stored in a memory cell array according to an example embodiment.
Referring to fig. 7, taking MLC NAND type flash memory as an example, each memory cell has 4 memory states along with different threshold voltages, and these memory states represent bits of "11", "10", "00", and "01", respectively. In other words, each memory state includes a least significant bit (Least Significant Bit, LSB) and a most significant bit (Most Significant Bit, MSB). In the present exemplary embodiment, the 1 st bit from the left side in the memory states (i.e., "11", "10", "00", and "01") is the LSB, and the 2 nd bit from the left side is the MSB. Thus, in this example embodiment, each memory cell may store 2 bits. It should be understood that the correspondence between the threshold voltages and the memory states shown in fig. 7 is only an example. In another exemplary embodiment of the present invention, the threshold voltage and the memory state may be arranged in the order of "11", "10", "01" and "00", or other arrangements as the threshold voltage is larger. Furthermore, in another exemplary embodiment, the 1 st bit from the left side may be defined as the MSB, and the 2 nd bit from the left side as the LSB.
In an example embodiment where one memory cell may store multiple bits (e.g., MLC or TLC NAND flash memory modules), physical program cells belonging to the same word line may be categorized into at least a lower physical program cell and an upper physical program cell. For example, in an MLC NAND flash memory module, the least significant bit (Least Significant Bit, LSB) of a memory cell is the lower physical program cell, and the most significant bit (MostSignificant Bit, MSB) of the memory cell is the upper physical program cell. In an exemplary embodiment, the lower physical programming unit is also referred to as a fast page (fast page), and the upper physical programming unit is also referred to as a slow page (slow page). In addition, in the TLC NAND flash memory module, the least significant bit (Least Significant Bit, LSB) of a memory cell belongs to the lower physical programming cell, the middle significant bit (Center Significant Bit, CSB) of the memory cell belongs to the middle physical programming cell, and the most significant bit (Most Significant Bit, MSB) of the memory cell belongs to the upper physical programming cell.
Fig. 8 is a schematic diagram showing reading data from a memory cell according to an exemplary embodiment, which is exemplified by MLC NAND type flash memory.
Referring to FIG. 8, the read operation of the memory cells of the memory cell array 2202 is performed by applying read voltages VA-VC to the control gates to identify the data stored by the memory cells by the conductive state of the memory cell channels. The verification bit (VA) is used to indicate whether the memory cell channel is conductive when the read voltage VA is applied; the verify bit (VC) is used to indicate whether the memory cell channel is conductive or not when the read voltage VC is applied; the Verify Bit (VB) is used to indicate whether the memory cell channel is conducting or not when the read voltage VB is applied. It is assumed here that the corresponding memory cell channel is turned on when the verification bit is "1", and that the corresponding memory cell channel is not turned on when the verification bit is "0". As shown in fig. 8, the stored bits (VA) to (VC) can be obtained by determining which storage state the memory cell is in.
Fig. 9 is a schematic diagram illustrating reading data from a memory cell according to another example embodiment.
Referring to fig. 9, taking a TLC NAND type flash memory as an example, each memory state includes a least significant bit LSB of the 1 st bit from the left, an intermediate significant bit (Center Significant Bit, CSB) of the 2 nd bit from the left, and a most significant bit MSB of the 3 rd bit from the left. In this example, the memory cell has 8 memory states (i.e., "111", "110", "100", "101", "001", "000", "010" and "011") according to different threshold voltages. By applying the read voltages VA through VG to the control gates, the bits stored by the memory cells can be identified.
It should be noted that the arrangement order of the 8 storage states in fig. 9 may be defined according to the design of the manufacturer, and is not limited to the arrangement manner of the present example.
In addition, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical program cells, and the physical program cells form a plurality of physical erase cells. Specifically, the memory cells on the same word line in FIG. 6 constitute one or more physical programming units. For example, if the rewritable nonvolatile memory module 406 is an MLC NAND type flash memory module, the memory cells at the intersections of the same word line and the plurality of bit lines form 2 physical program units, i.e., an upper physical program unit and a lower physical program unit. And an upper physical programming unit and a lower physical programming unit may be collectively referred to as a physical programming unit group. In particular, if the data to be read is located in a lower physical program unit of a group of physical program units, the read voltage VA shown in fig. 8 can be used to identify the value of each bit in the lower physical program unit. If the data to be read is located in an upper physical program unit of a physical program unit group, the read voltage VB and the read voltage VC shown in FIG. 8 can be used to identify the value of each bit in the upper physical program unit.
Alternatively, if the rewritable nonvolatile memory module 406 is a TLC NAND flash memory module, the memory cells at the intersections of the same word line and the bit lines form 3 physical program units, i.e., an upper physical program unit, a middle physical program unit, and a lower physical program unit. And an upper physical programming unit, a middle physical programming unit, and a lower physical programming unit may be collectively referred to as a physical programming unit group. In particular, if the data to be read is located in a lower physical program unit of a group of physical program units, the read voltage VA shown in fig. 9 can be used to identify the value of each bit in the lower physical program unit. If the data to be read is located in one of the physical program units of a physical program unit group, the read voltage VB and the read voltage VC shown in FIG. 9 can be used to identify the value of each bit in the physical program unit. If the data to be read is located in an upper physical program unit of a physical program unit group, the read voltage VD, the read voltage VE, the read voltage VF and the read voltage VG shown in fig. 9 can be used to identify the value of each bit in the upper physical program unit.
In the present exemplary embodiment, the physical programming unit is the minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit is a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, these physical programming units typically include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is for storing system data (e.g., error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erased cell is the minimum unit of erase. That is, each physical erased cell contains a minimum number of memory cells that are erased. For example, the physical erase unit is a physical block (block).
FIG. 10 is an exemplary schematic diagram of a physical erase unit according to the present exemplary embodiment.
Referring to FIG. 10, in the present exemplary embodiment, it is assumed that a physical erase unit is composed of a plurality of physical program unit groups, wherein each physical program unit group includes a lower physical program unit, a middle physical program unit and an upper physical program unit composed of a plurality of memory cells arranged on the same word line. For example, in a physical erase unit, the 0 th physical program unit belonging to the lower physical program unit, the 1 st physical program unit belonging to the middle physical program unit, and the 2 nd physical program unit belonging to the upper physical program unit are regarded as one physical program unit group. Similarly, the 3 rd, 4 th and 5 th physical programming units are considered as one physical programming unit group, and other physical programming units are also divided into a plurality of physical programming unit groups according to the method.
FIG. 11 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
Referring to FIG. 11, the memory control circuit unit 404 includes a memory management circuit 702, a host interface 704, a memory interface 706, and an error checking and correcting circuit 708.
The memory management circuit 702 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 702 has a plurality of control commands, and the control commands are executed to perform writing, reading and erasing operations of data while the memory storage device 10 is in operation. The operation of the memory management circuit 702 or any of the circuit elements included in the memory control circuit unit 404 is described as follows, which is equivalent to describing the operation of the memory control circuit unit 404.
In the present exemplary embodiment, the control instructions of the memory management circuit 702 are implemented in firmware. For example, the memory management circuit 702 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.
In another example embodiment, the control instructions of the memory management circuit 702 may also be stored in program code form in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area of the memory module dedicated to storing system data). In addition, the memory management circuit 702 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit 404 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 702. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.
Furthermore, in another example embodiment, the control instructions of the memory management circuit 702 may also be implemented in a hardware type. For example, the memory management circuit 702 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read instruction sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erase circuit is configured to issue an erase command sequence to the rewritable nonvolatile memory module 406 to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 406 to perform the corresponding write, read, erase, etc. In an example embodiment, the memory management circuitry 702 may also issue other types of sequences of instructions to the rewritable non-volatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 704 is electrically connected to the memory management circuit 702 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, the instructions and data transmitted by the host system 11 are transmitted to the memory management circuit 702 through the host interface 704. In the present exemplary embodiment, host interface 704 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 704 may also be compatible with PATA standards, IEEE 1394 standards, PCI Express standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.
The memory interface 706 is electrically connected to the memory management circuit 702 and is used to access the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format acceptable to the rewritable nonvolatile memory module 406 through the memory interface 706. Specifically, if the memory management circuit 702 is to access the rewritable nonvolatile memory module 406, the memory interface 706 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection procedures, etc.). These sequences of instructions are, for example, generated by memory management circuitry 702 and transferred to rewritable non-volatile memory module 406 through memory interface 706. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.
The error checking and correcting circuit 708 is electrically connected to the memory management circuit 702 and is used for performing an error checking and correcting procedure to ensure the correctness of the data. Specifically, when the memory management circuit 702 receives a write command from the host system 11, the error checking and correcting circuit 708 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 702 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 406. Then, when the memory management circuit 702 reads data from the rewritable nonvolatile memory module 406, it reads the error correction code and/or the error check code corresponding to the data at the same time, and the error check and correction circuit 708 performs an error check and correction procedure on the read data according to the error correction code and/or the error check code.
In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 710 and a power management circuit 712.
The buffer memory 710 is electrically connected to the memory management circuit 702 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 712 is electrically connected to the memory management circuit 702 and is used for controlling the power of the memory storage device 10.
In the present exemplary embodiment, the error checking and correction circuit 708 may perform single-frame (single-frame) encoding for data stored in the same physical programming unit, or may perform multi-frame (multi-frame) encoding for data stored in multiple physical programming units. The single frame coding and the multi-frame coding may employ at least one of coding algorithms such as low density parity check correction codes (low density parity code, LDPC), BCH codes, convolutional codes (convolutional code), or turbo codes (turbo codes), respectively. Alternatively, in an exemplary embodiment, the multi-frame encoding may also employ a Reed-solomon codes (RS codes) algorithm or a exclusive-or (XOR) algorithm. In addition, in another exemplary embodiment, more encoding algorithms not listed above may be used, and will not be described here. Depending on the encoding algorithm employed, the error checking and correction circuit 708 may encode the data to be protected to generate a corresponding error correction code and/or error checking code. For convenience of explanation, the error correction codes and/or error check codes generated by encoding will be collectively referred to as encoded data hereinafter.
Fig. 12 is a schematic diagram of a multi-frame encoding according to an example embodiment of the invention.
Referring to fig. 12, taking the example of encoding the data stored in the physical programming units 810 (0) to 810 (E) to generate the corresponding encoded data 820, at least a portion of the data stored in each of the physical programming units 810 (0) to 810 (E) can be regarded as a frame. In multi-frame encoding, the data in the physical programming units 810 (0) to 810 (E) is encoded based on the location of each bit (or byte). For example bit b located at position 801 (1) 11 、b 21 、…、b p1 Will be encoded as bit b in encoded data 820 o1 Bit b located at position 801 (2) 12 、b 22 、…、b p2 Will be encoded as bit b in encoded data 820 o2 The method comprises the steps of carrying out a first treatment on the surface of the Similarly, bit b at position 801 (r) 1r 、b 2r 、…、b pr Will be encoded as bit b in encoded data 820 or . The data read from the physical programming units 810 (0) through 810 (E) may then be decoded based on the encoded data 820 in an attempt to correct errors that may exist in the read data.
In addition, in another example embodiment of fig. 12, the data used to generate the encoded data 820 may also include redundancy bits (redundancy bits) corresponding to data bits (data bits) in the data stored by the physical programming units 810 (0) to 810 (E). Taking the data stored in the physical programming unit 810 (0) as an example, the redundancy bits are generated by, for example, single frame encoding the data bits stored in the physical programming unit 810 (0). In the present exemplary embodiment, it is assumed that when reading data in the physical programming unit 810 (0), the data read from the physical programming unit 810 (0) can be decoded by using redundant bits (e.g., encoded data encoded by a single frame) in the physical programming unit 810 (0) for error detection and correction. However, when decoding using the redundant bits in the physical programming unit 810 (0) fails (e.g., the number of erroneous bits of the data stored in the physical programming unit 810 (0) after decoding is greater than a threshold), a re-Read mechanism may be used to attempt to Read the correct data from the physical programming unit 810 (0). Details of the re-reading mechanism are described later. When correct data cannot be Read from the physical programming unit 810 (0) by a re-Read mechanism, the encoded data 820 and the data of the physical programming units 810 (1) to 810 (E) can be Read and decoded according to the encoded data 820 and the data of the physical programming units 810 (1) to 810 (E) to attempt to correct errors in the data stored in the physical programming unit 810 (0). That is, in the present exemplary embodiment, when decoding of encoded data generated using single frame encoding fails and reading of encoded data generated using a re-Read (Retry-Read) mechanism fails, decoding is performed using encoded data generated using multi-frame encoding.
In particular, FIG. 13 is a schematic diagram illustrating a re-reading mechanism according to an example embodiment.
Referring to fig. 13, here, for example, SLC flash memory is taken as an example, distribution 1410 and distribution 1420 are used to represent the memory states of a plurality of first memory cells, and distribution 1410 and distribution 1420 respectively represent different memory states. The first memory units may belong to the same physical programming unit or different physical programming units, and the present invention is not limited thereto. It is assumed herein that when a memory cell belongs to distribution 1410, bit "1" is stored in that memory cell; when a memory cell belongs to distribution 1420, this memory cell stores bit "0". When the memory management circuit 702 reads the memory cell with the read voltage 1440, the memory management circuit 702 obtains a verification bit indicating whether the memory cell is turned on. It is assumed here that the verify bit is "1" when the memory cell is turned on, and "0" when the memory cell is turned on, but the invention is not limited thereto. If the verification bit is "1", the memory management circuit 702 determines that the memory cell belongs to the distribution 1410, and vice versa is the distribution 1420. However, distribution 1410 overlaps with distribution 1420 in region 1430. That is, there are several memory cells that should belong to distribution 1410 but are identified as distribution 1420, and there are several memory cells that should belong to distribution 1420 but are identified as distribution 1410.
In this example embodiment, when the memory cells are to be read, the memory management circuit 702 selects a predetermined read voltage (e.g., the read voltage 1441) to read the memory cells to obtain the verification bits of the memory cells. The error checking and correction circuit 708 performs decoding operations based on the verification bits of the memory cells to generate a plurality of decoded bits, which may form a decoded data (also referred to as a codeword).
If decoding fails, it means that these memory cells store uncorrectable error bits. If the decoding fails, in the re-read scheme, the memory management circuit 702 re-retrieves another read voltage (e.g., the read voltage 1442) to read the first memory cells to re-retrieve the verification bits of the memory cells. The memory management circuit 702 performs the decoding operation according to the retrieved verification bits to retrieve another decoded data composed of a plurality of decoding bits. In an exemplary embodiment, the error checking and correcting circuit 708 determines whether the other decoded data is a valid codeword according to a syndrome corresponding to the other decoded data. If the other decoded data is not a valid codeword, the memory management circuit 702 determines that decoding has failed. If the number of times of re-fetching the read voltage does not exceed the preset number of times, the memory management circuit 702 re-fetches other fetch voltages (e.g., the read voltage 1443), and reads the memory cell according to the re-fetched read voltage 1443 to re-fetch the verification bit and perform the first decoding operation.
In other words, when there is an uncorrectable error bit, the verify bit of some memory cells is changed by retrieving the read voltage, thereby having the opportunity to change the decoding result of the decoding operation. Logically, the above-mentioned action of retrieving the read voltage is to flip (flip) bits in a codeword and re-decode the new codeword. In some cases, codewords that cannot be decoded before flipping (with uncorrectable error bits) may be decoded after flipping. Also, in an example embodiment, the memory management circuit 702 may attempt to decode several times until the number of attempts exceeds a predetermined number. However, the present invention is not limited to what the preset number of times is.
It should be noted that the example of SLC flash memory is illustrated in fig. 13, but the step of retrieving the read voltage may also be applied to MLC or TLC flash memory. As shown in fig. 8, changing the read voltage VA inverts the LSB of one memory cell, and changing the read voltage VB or VC inverts the MSB of one memory cell. Thus, changing the read voltage VA, VB or VC can change one codeword to another codeword. The result of changing the codeword is also applicable to the TLC flash memory of fig. 9. The invention is not limited to SLC, MLC or TLC flash memory.
It should be noted that, in the conventional re-reading mechanism, the memory management circuit 702 typically reads a piece of data and re-fetches another read voltage to perform a read operation when a decoding operation according to the piece of data fails. In other words, before another read voltage is obtained, two steps of "read" and "decode" are usually performed, and when the decode fails, another read voltage is obtained to perform the read operation. However, the more times the read voltage is retrieved, the more time it takes.
Based on the above, the present invention proposes a decoding method, which can quickly determine that a decoding failure may occur in a piece of data and directly retrieve another read voltage to perform a read operation when the piece of data is read and the piece of data is not decoded. In this way, the step of "decoding" in two steps that need to be performed before another read voltage is taken in the conventional re-read mechanism can be subtracted, thereby reducing the time of data reading and improving the efficiency of data reading.
Fig. 14 is a flowchart illustrating a decoding method according to an example embodiment.
Referring to fig. 14, in the present embodiment, when the host system 11 wants to write a piece of data (also referred to as a third data) into the rewritable nonvolatile memory module 406, the host system 11 can issue a write command. After that, the memory management circuit 702 receives a write command from the host system 11 to write the third data to the rewritable nonvolatile memory module 406 (step S1401). The memory management circuit 702 performs scrambling operation on the third data (e.g. inputs the third data to a scrambling circuit) according to the above-mentioned write command to generate scrambled data (step S1403), and writes the scrambled data to one of the physical programming units (also referred to as the first physical programming unit) in the rewritable nonvolatile memory module 406 (step S1405).
It should be noted that the "scrambling operation" is used to scramble (reprocess) the data to be written into the rewritable nonvolatile memory module 406. Specifically, in order to make the data written (or programmed) into the rewritable nonvolatile memory module 406 in an irregular and random state, the data is first subjected to a scrambling operation (e.g. editing, calculation or rearrangement) and then written, so that the data actually written into the physical programming unit is sufficiently random, and thus, the recognition error of the data due to uneven distribution, offset of read voltage or uneven resistance of bit lines is avoided. Wherein, the scrambled data generated by performing the scrambling operation on the third data is different from the third data, but the ratio of 0 to 1 in the scrambled data may be the same as or different from the third data. Similarly, during reading, since the data actually programmed into the physical programming unit is scrambled, the data read from the rewritable nonvolatile memory module 406 is also subjected to the scrambling operation to restore the original data.
In this embodiment, the number of bits (also referred to as the fifth number) with a bit value (also referred to as the first bit value) of 0 in the scrambled data is close to the number of bits (also referred to as the sixth number) with a bit value (also referred to as the second bit value) of 1. For example, in one embodiment, the ratio of the fifth number to the sixth number is one-to-one. In this embodiment, the ratio of the fifth number to the sixth number (also referred to as the third ratio) is not greater than a threshold value. In more detail, the third ratio is a quotient obtained by dividing a difference between the fifth number and the sixth number by a sum of the fifth number and the sixth number, and the third ratio may represent a percentage of the difference between the fifth number and the sixth number in the scrambled data. In the present exemplary embodiment, the threshold value is ten percent, however, the present invention is not limited to the actual value of the threshold value.
After writing to the first physical programming unit, the memory management circuitry 702 may perform a read operation on the first physical programming unit. In more detail, the memory management circuit 702 uses a first read voltage (e.g. the read voltage 1441) of the plurality of read voltages (e.g. the read voltages 1440-1444) to read the first physical programming unit to obtain a piece of data (also referred to as a first data) (step S1407). It should be noted that the first data may be the same as or different from the third data.
Next, the memory management circuit 702 determines whether the ratio (also referred to as a first ratio) of the number of bits (also referred to as a first number) with a bit value (i.e., a first bit value) of 0 to the number of bits (also referred to as a second number) with a bit value (i.e., a second bit value) of 1 in the first data is greater than a threshold value (step S1409). Similar to the aforementioned third ratio, the first ratio is a quotient obtained by dividing the difference between the first number and the second number by the sum of the first number and the second number. Wherein the sum of the first number and the second number may also be referred to as a first number. In the present exemplary embodiment, the threshold value used in step S1407 is ten percent, however, the present invention is not limited to the actual value of the threshold value in step S1407.
When the first ratio is not greater than the threshold, the memory management circuit 702 performs a decoding operation according to the first data to generate decoded data (also referred to as first decoded data), and outputs the first decoded data (step S1411). Note that the decoding operation in step S1411 is, for example, a decoding operation using an LDPC algorithm. In addition, before performing the decoding operation, the memory management circuit 702 may perform the inverse of the scrambling operation on the first data, and then perform the decoding operation.
When the first ratio is greater than the threshold value, it is indicated that the first data may fail in decoding. Therefore, the memory management circuit 702 may not perform the foregoing decoding operation according to the first data, but directly perform the re-reading mechanism to read the first physical programming unit to obtain the second data using the second read voltage (e.g., the read voltage 1442) of the plurality of read voltages (e.g., the read voltages 1440-1444) (step S1413). Similarly, the second data may be the same as or different from the aforementioned third data.
Then, the memory management circuit 702 determines whether the ratio (also referred to as a second ratio) of the number of bits (also referred to as a third number) with the bit value (i.e., the first bit value) being 0 to the number of bits (also referred to as a fourth number) with the bit value (i.e., the second bit value) being 1 in the second data is greater than a threshold value (step S1415). Similar to the aforementioned third ratio, the second ratio is a quotient obtained by dividing the difference between the third number and the fourth number by the sum of the third number and the fourth number. In the present exemplary embodiment, the threshold value used in step S1415 is ten percent, however, the present invention is not limited to the actual value of the threshold value in step S1415.
When the second ratio is not greater than the threshold, the memory management circuit 702 performs a decoding operation according to the second data to generate decoded data (also referred to as second decoded data), and outputs the second decoded data (step S1417). Note that the decoding operation in step S1417 is, for example, a decoding operation using an LDPC algorithm. In addition, before performing the decoding operation, the memory management circuit 702 may perform the inverse of the scrambling operation on the second data, for example, and then perform the decoding operation described above.
When the second ratio is greater than the threshold value, it means that the second data may fail in decoding. Accordingly, the memory management circuit 702 may not perform the foregoing decoding operation according to the second data (step S1419). Assuming that the number of times of re-fetching the read voltage has not reached the preset value, the memory management circuit 702 may again execute the re-fetch mechanism to re-fetch the first physical programming unit to fetch the data using one of the read voltages (e.g., the read voltage 1444) among the plurality of read voltages (e.g., the read voltages 1440-1444) and perform the determination of step S1409 (or step S1415) as described above. However, if the number of times of re-fetching the read voltage reaches the predetermined value, the memory management circuit 702 decodes the encoded data generated by the multi-frame encoding.
In summary, the decoding method, the memory control circuit unit and the memory storage device of the present invention can quickly determine whether decoding failure of a piece of data is likely to occur when the piece of data is read out and directly retrieve another read voltage to perform a read operation when decoding failure is likely to occur. By the method, the execution time of the re-reading mechanism can be reduced, and the data reading efficiency is further improved.
Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.

Claims (13)

1. A decoding method for a rewritable non-volatile memory module having a plurality of physical erase units, each physical erase unit of the plurality of physical erase units having a plurality of physical program units, the decoding method comprising:
reading a first physical programming unit of a first physical erasing unit in a plurality of physical erasing units by using a first reading voltage in the plurality of reading voltages to obtain first data;
Judging whether a first proportion of a first number of first bit values and a second number of second bit values in the first data is larger than a threshold value or not;
when the first proportion is not larger than the threshold value, decoding operation is carried out according to the first data to generate first decoded data, and the first decoded data is output; and
when the first ratio is greater than the threshold value, not performing the decoding operation according to the first data;
wherein the step of determining whether the first ratio of the first number of the first bit values and the second number of the second bit values in the first data is greater than the threshold value comprises:
calculating a difference between the first number and the second number;
when the quotient obtained by dividing the difference by the first numerical value is not larger than the threshold value, judging that the first ratio is not larger than the threshold value; and
when the quotient obtained by dividing the difference by the first value is greater than the threshold value, determining that the first ratio is greater than the threshold value,
wherein the first value is the sum of the first number and the second number.
2. The decoding method of claim 1, wherein the threshold is ten percent.
3. The decoding method of claim 2, wherein when the first ratio is greater than the threshold, the method further comprises:
reading the first physical programming unit using a second read voltage of the plurality of read voltages to obtain second data;
judging whether a second ratio of the third number of the first bit values to the fourth number of the second bit values in the second data is greater than the threshold value;
performing the decoding operation according to the second data to generate second decoded data and outputting the second decoded data when the second ratio is not greater than the threshold value; and
when the second ratio is greater than the threshold, the decoding operation is not performed according to the second data.
4. The decoding method of claim 1, wherein prior to the step of reading the first physical programming unit of the first physical erase unit of the plurality of physical erase units using the first read voltage of a plurality of read voltages to obtain the first data, the method further comprises:
receiving a write instruction from a host system to write third data to the rewritable nonvolatile memory module;
Performing a scrambling operation on the third data according to the write instruction to generate scrambled data, wherein a third ratio of the fifth number of the first bit values to the sixth number of the second bit values in the scrambled data is not greater than the threshold value; and
the scrambled data is written to the first physical programming unit.
5. A memory control circuit unit for a rewritable nonvolatile memory module having a plurality of physical erase units, each of the plurality of physical erase units having a plurality of physical program units, the memory control circuit unit comprising:
the host interface is used for being electrically connected to a host system;
a memory interface electrically connected to the rewritable non-volatile memory module;
a memory management circuit electrically connected to the host interface and the memory interface,
wherein the memory management circuit is used for reading a first physical programming unit of a first physical erasing unit in the plurality of physical erasing units by using a first reading voltage in the plurality of reading voltages to obtain first data,
Wherein the memory management circuit is further configured to determine whether a first ratio of a first number of first bit values to a second number of second bit values in the first data is greater than a threshold value,
the memory management circuit is further configured to perform a decoding operation according to the first data to generate first decoded data and output the first decoded data when the first ratio is not greater than the threshold value,
when the first ratio is greater than the threshold value, the memory management circuit does not perform the decoding operation according to the first data;
wherein in the operation of determining whether the first ratio of the first number of the first bit values and the second number of the second bit values in the first data is greater than the threshold value,
the memory management circuit is also configured to calculate a difference between the first number and the second number,
when the quotient obtained by dividing the difference by the first value is not greater than the threshold value, the memory management circuit is further configured to determine that the first ratio is not greater than the threshold value, and
when the quotient obtained by dividing the difference by the first value is greater than the threshold value, the memory management circuit is further configured to determine that the first ratio is greater than the threshold value,
Wherein the first value is the sum of the first number and the second number.
6. The memory control circuit unit of claim 5, wherein the threshold is ten percent.
7. The memory control circuit unit of claim 5, wherein when the first ratio is greater than the threshold value,
the memory management circuit is also configured to read the first physical programming unit using a second read voltage of the plurality of read voltages to obtain second data,
the memory management circuit is further configured to determine whether a second ratio of the third number of the first bit values to the fourth number of the second bit values in the second data is greater than the threshold value,
when the second ratio is not greater than the threshold value, the memory management circuit is further configured to perform the decoding operation according to the second data to generate second decoded data, and output the second decoded data, and
when the second ratio is greater than the threshold, the memory management circuit does not perform the decoding operation based on the second data.
8. The memory control circuit unit of claim 5, wherein prior to an operation of reading the first physical program unit of the first physical erase unit of the plurality of physical erase units using the first read voltage of the plurality of read voltages to obtain the first data,
The memory management circuit is also to receive a write instruction from the host system to write third data to the rewritable non-volatile memory module,
the memory management circuit is further configured to perform a scrambling operation on the third data according to the write instruction to generate scrambled data, wherein a third ratio of the fifth number of the first bit values to the sixth number of the second bit values in the scrambled data is not greater than the threshold value, and
the memory management circuit is also configured to write the scrambled data to the first physical programming unit.
9. A memory storage device, comprising:
the connection interface unit is used for being electrically connected to the host system;
a rewritable non-volatile memory module having a plurality of physical erase units, each of the plurality of physical erase units having a plurality of physical program units; and
a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is used for reading a first physical programming unit of a first physical erasing unit in the plurality of physical erasing units by using a first reading voltage in the plurality of reading voltages to obtain first data,
Wherein the memory control circuit unit is further configured to determine whether a first ratio of a first number of first bit values to a second number of second bit values in the first data is greater than a threshold value,
when the first proportion is not larger than the threshold value, the memory control circuit unit is further used for performing decoding operation according to the first data to generate first decoded data and outputting the first decoded data; and
when the first ratio is greater than the threshold value, wherein the memory control circuit unit does not perform the decoding operation according to the first data,
in determining whether the first ratio of the first number of the first bit values and the second number of the second bit values in the first data is greater than the threshold value,
the memory control circuit unit is also configured to calculate a difference between the first number and the second number,
when the quotient obtained by dividing the difference by the first value is not greater than the threshold value, the memory control circuit unit is further configured to determine that the first ratio is not greater than the threshold value, and
when the quotient obtained by dividing the difference by the first value is greater than the threshold value, the memory control circuit unit is further configured to determine that the first ratio is greater than the threshold value,
Wherein the first value is the sum of the first number and the second number.
10. The memory storage device of claim 9, wherein the threshold is ten percent.
11. The memory storage device of claim 9, wherein when the first ratio is greater than the threshold,
the memory control circuit unit is also configured to read the first physical programming unit using a second read voltage of the plurality of read voltages to obtain second data,
the memory control circuit unit is further configured to determine whether a second ratio of the third number of the first bit values to the fourth number of the second bit values in the second data is greater than the threshold value,
when the second ratio is not greater than the threshold value, the memory control circuit unit is further configured to perform the decoding operation according to the second data to generate second decoded data, and output the second decoded data, and
when the second ratio is greater than the threshold value, the memory control circuit unit does not perform the decoding operation according to the second data.
12. The memory storage device of claim 9, wherein prior to an operation of reading the first physical programming unit of the first physical erase unit of the plurality of physical erase units using the first read voltage of the plurality of read voltages to obtain the first data,
The memory control circuit unit is also configured to receive a write instruction from the host system to write third data to the rewritable nonvolatile memory module,
the memory control circuit unit is further configured to perform a scrambling operation on the third data according to the write instruction to generate scrambled data, wherein a third ratio of the fifth number of the first bit values to the sixth number of the second bit values in the scrambled data is not greater than the threshold value, and
the memory control circuit unit is also configured to write the scrambled data to the first physical programming unit.
13. A decoding method for a rewritable non-volatile memory module having a plurality of physical erase units, each physical erase unit of the plurality of physical erase units having a plurality of physical program units, the decoding method comprising:
reading a first physical programming unit of a first physical erasing unit in a plurality of physical erasing units by using a first reading voltage in the plurality of reading voltages to obtain first data;
judging whether a first proportion of a first number of first bit values and a second number of second bit values in the first data is larger than a threshold value or not;
When the first proportion is not larger than the threshold value, decoding operation is carried out according to the first data to generate first decoded data, and the first decoded data is output;
when the first ratio is greater than the threshold value, reading the first physical programming unit by using a second reading voltage in the plurality of reading voltages to obtain second data;
judging whether a second ratio of the third number of the first bit values to the fourth number of the second bit values in the second data is greater than the threshold value;
performing the decoding operation according to the second data to generate second decoded data and outputting the second decoded data when the second ratio is not greater than the threshold value; and
when the second ratio is greater than the threshold value, not performing the decoding operation according to the second data;
wherein the step of determining whether the first ratio of the first number of the first bit values and the second number of the second bit values in the first data is greater than the threshold value comprises:
calculating a difference between the first number and the second number;
When the quotient obtained by dividing the difference by the first numerical value is not larger than the threshold value, judging that the first ratio is not larger than the threshold value; and
when the quotient obtained by dividing the difference by the first value is greater than the threshold value, determining that the first ratio is greater than the threshold value,
wherein the first value is the sum of the first number and the second number.
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