CN113496752B

CN113496752B - Decoding method, memory storage device and memory control circuit unit

Info

Publication number: CN113496752B
Application number: CN202010264881.3A
Authority: CN
Inventors: 林玉祥
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2020-04-07
Filing date: 2020-04-07
Publication date: 2023-08-29
Anticipated expiration: 2040-04-07
Also published as: CN113496752A

Abstract

The invention provides a decoding method, a memory storage device and a memory control circuit unit. The method comprises the following steps: receiving a read instruction sequence, wherein the read instruction sequence is used for reading a plurality of bits from a plurality of storage units; calculating a first count value of a first value and a second count value of a second value in the plurality of bits; and adjusting decoding parameters corresponding to the plurality of bits to specific decoding parameters according to the first count value and the second count value, and performing a decoding operation according to the specific decoding parameters, wherein the adjusted decoding parameters affect the probability that the plurality of bits are regarded as erroneous bits in the decoding operation.

Description

Decoding method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a decoding technique, and more particularly, to a decoding method, a memory storage device, and a memory control circuit unit.

Background

Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, such that consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable multimedia devices.

Generally, in order to ensure the correctness of data stored in a rewritable nonvolatile memory module, some data is encoded before the data is stored in the rewritable nonvolatile memory module. The encoded data (including the original data and the error correction code) is stored in the rewritable nonvolatile memory module. The encoded data may then be read from the rewritable non-volatile memory module and decoded to correct errors that may exist therein. The error correction code may use, for example, an algebraic decoding algorithm, such as (BCH code), or a probabilistic decoding algorithm, such as a low density parity check code (low density parity code, LDPC). The low density parity check code is encoded and decoded using a sparse matrix (sparse matrix). Generally, an LDPC decoder decodes via unsatisfied check node (unsatisfied check node) information or log-likelihood ratio (LLR) in an iterative decoding operation. Therefore, how to obtain the appropriate LLR values to enhance the performance of LDPC decoding is an issue of interest to those skilled in the art.

Disclosure of Invention

The invention provides a decoding method, a memory storage device and a memory control circuit unit, which can calculate the distribution of a first value and a second value and adjust decoding parameters according to the average degree of the distribution, thereby improving the correction capability of decoding and the probability of decoding success so as to reduce decoding delay.

The invention provides a decoding method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of storage units, and the decoding method comprises the following steps: receiving a read instruction sequence, wherein the read instruction sequence is used for reading a plurality of bits from the plurality of storage units; calculating a first count value of a first value and a second count value of a second value in the plurality of bits; and adjusting decoding parameters corresponding to the plurality of bits to specific decoding parameters according to the first count value and the second count value, and performing a decoding operation according to the specific decoding parameters, wherein the adjusted decoding parameters affect the probability that the plurality of bits are regarded as erroneous bits in the decoding operation.

In an embodiment of the present invention, wherein the decoding parameters and the particular decoding parameters are log-likelihood ratios (Log Likelihood Ratio, LLRs).

In an embodiment of the present invention, an adjustment value for adjusting the decoding parameter to the specific decoding parameter is ±1 to 3.

In an embodiment of the present invention, the adjustment value for adjusting the decoding parameter to the specific decoding parameter is ±10-20% of the decoding parameter.

In an embodiment of the present invention, the decoding parameters include one or more positive decoding parameters and one or more negative decoding parameters, and in the step of adjusting the decoding parameters corresponding to the plurality of bits to the specific decoding parameters according to the first count value and the second count value, an adjustment value of the one or more positive decoding parameters is different from an adjustment value of the one or more negative decoding parameters.

In an embodiment of the present invention, the decoding parameters include one or more positive decoding parameters and one or more negative decoding parameters, and the adjusting values of the one or more positive decoding parameters are the same as the adjusting values of the one or more negative decoding parameters in the step of adjusting the decoding parameters corresponding to the plurality of bits to the specific decoding parameters according to the first count value and the second count value.

In an embodiment of the present invention, before the step of adjusting the decoding parameters corresponding to the plurality of bits to the specific decoding parameters according to the first count value and the second count value, the decoding method further includes: and adjusting a voltage level used for reading the plurality of bits from the plurality of memory cells to a second voltage level according to the first count value and the second count value.

In an embodiment of the present invention, the decoding operation is at least one of a hard bit decoding operation and a soft bit decoding operation.

The present invention provides a memory storage device comprising: the memory control circuit unit is connected with the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit. The connection interface unit is used for being coupled to a host system. The rewritable nonvolatile memory module includes a plurality of memory cells. The memory control circuit unit is coupled to the connection interface unit and the rewritable nonvolatile memory module, wherein the memory control circuit unit is configured to receive a read instruction sequence, wherein the read instruction sequence is configured to read a plurality of bits from the plurality of memory units. The memory control circuit unit is further configured to calculate a first count value of a first value and a second count value of a second value of the plurality of bits by a counter, and adjust decoding parameters corresponding to the plurality of bits to specific decoding parameters according to the first count value and the second count value, and perform a decoding operation according to the specific decoding parameters, wherein the adjusted decoding parameters affect a probability that the plurality of bits are regarded as erroneous bits in the decoding operation.

In an embodiment of the present invention, wherein the decoding parameter and the specific decoding parameter are log likelihood ratios.

In an embodiment of the present invention, the decoding parameters include one or more positive decoding parameters and one or more negative decoding parameters, and the memory control circuit unit adjusts the decoding parameters corresponding to the plurality of bits to the specific decoding parameters according to the first count value and the second count value, wherein an adjustment value of the one or more positive decoding parameters is different from an adjustment value of the one or more negative decoding parameters.

In an embodiment of the present invention, the decoding parameters include one or more positive decoding parameters and one or more negative decoding parameters, and the memory control circuit unit adjusts the decoding parameters corresponding to the plurality of bits to the specific decoding parameters according to the first count value and the second count value, wherein an adjustment value of the one or more positive decoding parameters is identical to an adjustment value of the one or more negative decoding parameters.

In an embodiment of the present invention, before the operation of adjusting the decoding parameters corresponding to the bits to the specific decoding parameters according to the first count value and the second count value, the memory control circuit unit is further configured to adjust a voltage level used to read the bits from the memory cells to a second voltage level according to the first count value and the second count value.

The present invention provides a memory control circuit unit for controlling a memory storage device including a rewritable nonvolatile memory module, and the memory control circuit unit includes: host interface, memory interface and memory management circuitry. The host interface is configured to be coupled to a host system. The memory interface is configured to be coupled to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of memory cells. The memory management circuit is coupled to the host interface and the memory interface, wherein the memory control circuit unit is configured to receive a read instruction sequence, wherein the read instruction sequence is configured to read a plurality of bits from the plurality of memory cells. The memory control circuit unit is further configured to calculate a first count value of a first value and a second count value of a second value of the plurality of bits by a counter, and adjust decoding parameters corresponding to the plurality of bits to specific decoding parameters according to the first count value and the second count value, and perform a decoding operation according to the specific decoding parameters, wherein the adjusted decoding parameters affect a probability that the plurality of bits are regarded as erroneous bits in the decoding operation.

Based on the above, the decoding method, the memory storage device and the memory control circuit unit provided by the invention can calculate the distribution of the first value and the second value and judge whether the distribution is average. The memory control circuit unit may adjust the decoding parameter corresponding to the bit to a specific decoding parameter according to the average degree of the distribution, and execute the decoding operation again according to the value of the bit and the specific decoding parameter to attempt to obtain the successfully decoded codeword. By the method, the correction capability of decoding can be improved, the probability of decoding success can be improved, and decoding delay can be reduced.

In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another example embodiment of the invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an example embodiment;

FIG. 6 is a schematic diagram of a memory cell array according to an example embodiment;

FIG. 7 is a graph showing statistical distribution of gate voltages corresponding to write data stored in a memory cell array according to an example embodiment;

FIG. 8 is a schematic diagram of a programmed memory cell according to an example embodiment;

FIG. 9 is a schematic diagram illustrating reading data from a memory cell according to an example embodiment;

FIG. 10 is a schematic diagram illustrating reading data from a memory cell according to another example embodiment;

FIG. 11 is an exemplary schematic diagram of a memory cell memory architecture and a physical erase unit according to the present exemplary embodiment;

FIG. 12 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;

FIG. 13 is a schematic block diagram of a memory control circuit unit according to an example embodiment;

FIG. 14 is a schematic diagram illustrating hard bit pattern decoding according to an example embodiment;

FIG. 15 is a schematic diagram illustrating soft bit pattern decoding according to an example embodiment;

FIG. 16 is an example illustrating decoding initial values according to an example embodiment;

fig. 17 is a flowchart illustrating a decoding method according to an example embodiment.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Memory storage devices are typically used with host systems so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 are all coupled to a system bus 110.

In the present exemplary embodiment, host system 11 is coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, host system 11 is coupled to I/O device 12 via system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be coupled to the memory storage device 10 via a wired or wireless connection via the data transmission interface 114. The memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (iBeacon) or the like based on a variety of wireless communication technologies. In addition, the motherboard 20 may also be coupled to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, the host system referred to is any system that can cooperate with substantially a memory storage device to store data. Although the host system is described in the above exemplary embodiment as a computer system, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player or a tablet computer, and the memory storage device 30 may be a variety of nonvolatile memory storage devices such as an SD card 32, a CF card 33 or an embedded storage device 34. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (eMMC) 341 and/or an embedded multi-chip package storage device (embedded Multi Chip Package, eMCP) 342, which directly couple the memory module to a substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable nonvolatile memory module 406.

In the present exemplary embodiment, the connection interface unit 402 is compatible with the serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) standard. It must be understood, however, that the present invention is not limited thereto, and the connection interface unit 402 may also be a device that conforms to the parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, the institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, the peripheral component interconnect Express (Peripheral Component Interconnect Express, PCI Express) standard, the universal serial bus (Universal Serial Bus, USB) standard, the Secure Digital (SD) interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed second generation (Ultra High Speed-II, UHS-II) interface standard, memory Stick (MS) interface standard, multi-Chip Package (MMC) interface standard, multimedia Memory Card (MMC) interface standard, embedded multimedia Memory Card (Embedded Multimedia Card, eMMC) interface standard, universal Flash Memory (Universal Flash Storage, UFS) interface standard, embedded Multi-Chip Package (embedded Multi Chip Package, eMCP) interface standard, compact Flash (CF) interface standard, integrated drive electronics (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in a single chip, or the connection interface unit 402 may be disposed off-chip with the memory control circuit unit 404.

The memory control circuit unit 404 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 406 is coupled to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a complex-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

The memory cells in the rewritable nonvolatile memory module 406 are arranged in an array. The memory cell array will be described below in terms of a two-dimensional array. However, it should be noted that the following exemplary embodiment is only one example of a memory cell array, and in other exemplary embodiments, the configuration of the memory cell array may be adjusted to meet the practical requirements.

FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an example embodiment. FIG. 6 is a schematic diagram of a memory cell array according to an example embodiment.

Referring to fig. 5 and 6, the rewritable nonvolatile memory module 406 includes a memory cell array 2202, a word line control circuit 2204, a bit line control circuit 2206, a column decoder 2208, a data input/output buffer 2210 and a control circuit 2212.

In the present example embodiment, the memory cell array 2202 may include a plurality of memory cells 502 for storing data, a plurality of select gate drain (select gate drain, SGD) transistors 512 and a plurality of select gate source (select gate source, SGS) transistors 514, and a plurality of bit lines 504, a plurality of word lines 506, and a common source line 508 (as shown in fig. 6) connecting such memory cells. Memory cells 502 are arranged in an array (or stacked in a three-dimensional fashion) at the intersections of bit lines 504 and word lines 506. When a write command or a read command is received from the memory control circuit unit 404, the control circuit 2212 controls the word line control circuit 2204, the bit line control circuit 2206, the row decoder 2208, the data input/output buffer 2210 to write data into the memory cell array 2202 or read data from the memory cell array 2202, wherein the word line control circuit 2204 is used for controlling the voltage applied to the word line 506, the bit line control circuit 2206 is used for controlling the voltage applied to the bit line 504, the row decoder 2208 selects the corresponding bit line according to the column address in the command, and the data input/output buffer 2210 is used for temporarily storing data.

The memory cells in the rewritable nonvolatile memory module 406 store multiple bits (bits) with a change in threshold voltage. Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This process of changing the threshold voltage is also referred to as "writing data to a memory cell" or "programming a memory cell". Each memory cell of the memory cell array 2202 has a plurality of memory states as the threshold voltage changes. And the memory cell can be judged to be in which memory state by reading the voltage, thereby obtaining the bit stored by the memory cell.

FIG. 7 is a graph showing a statistical distribution of gate voltages corresponding to write data stored in a memory cell array according to an example embodiment.

Referring to fig. 7, taking MLC NAND type flash memory as an example, each memory cell has 4 memory states along with different threshold voltages, and these memory states represent bits of "11", "10", "00", and "01", respectively. In other words, each memory state includes a least significant bit (Least Significant Bit, LSB) and a most significant bit (MostSignificant Bit, MSB). In the present exemplary embodiment, the 1 st bit from the left side in the memory states (i.e., "11", "10", "00", and "01") is the LSB, and the 2 nd bit from the left side is the MSB. Thus, in this example embodiment, each memory cell may store 2 bits. It should be understood that the correspondence between the threshold voltages and the memory states shown in fig. 8 is only an example. In another exemplary embodiment of the present invention, the threshold voltage and the memory state may be arranged in the order of "11", "10", "00", and "01", or other arrangements as the threshold voltage is larger. In addition, in another example, the 1 st bit from the left side may be defined as the MSB, and the 2 nd bit from the left side as the LSB.

FIG. 8 is a schematic diagram of a programmable memory cell according to an example embodiment.

Referring to FIG. 8, in the exemplary embodiment, programming of the memory cell is accomplished by a pulse write/verify threshold voltage method. Specifically, when data is to be written into the memory cell, the memory control circuit unit 404 sets an initial write voltage and a write pulse time, and instructs the control circuit 2212 of the rewritable nonvolatile memory module 406 to program the memory cell with the set initial write voltage and write pulse time for writing data. Then, the memory control circuit unit 404 applies a verification voltage to the control gate to determine whether the memory cell is turned on, and further determine whether the memory cell is in a correct memory state (has a correct threshold voltage). If the memory cell is not programmed to the correct memory state, the memory control circuit 404 instructs the control circuit 2212 to use the currently applied write voltage plus an Incremental step-pulse-pulse programming (ISPP) adjustment value as a new write voltage and to program the memory cell again according to the new write voltage and the write pulse time. Otherwise, if the memory cell has been programmed to the correct memory state, it indicates that the data has been correctly written into the memory cell. For example, the initial write Voltage is set to 16 volts (V), the write pulse time is set to 18 microseconds (μs) and the incremental step pulse program adjustment value is set to 0.6V, but the present invention is not limited thereto.

Fig. 9 is a schematic diagram showing reading data from a memory cell according to an exemplary embodiment, which is exemplified by MLC NAND type flash memory.

Referring to fig. 9, the read operation of the memory cells of the memory cell array 2202 is performed by applying a read voltage to the control gate, and identifying the data stored in the memory cells by the conductive state of the memory cells. The verification bit (VA) is used to indicate whether the memory cell is turned on when the read voltage VA is applied; a verify bit (VC) is used to indicate whether the memory cell is turned on when the read voltage VC is applied; the Verify Bit (VB) is used to indicate whether the memory cell is turned on when the read voltage VB is applied. It is assumed here that a verify bit of "1" indicates that the corresponding memory cell is on, and that a verify bit of "0" indicates that the corresponding memory cell is not on. As shown in fig. 9, the stored bits (VA) to (VC) can be obtained by determining which storage state the memory cell is in.

Fig. 10 is a schematic diagram illustrating reading data from a memory cell according to another example embodiment.

Referring to fig. 10, taking a TLC NAND type flash memory as an example, each memory state includes a least significant bit LSB of a 1 st bit from the left, an intermediate significant bit (Center Significant Bit, CSB) of a 2 nd bit from the left, and a most significant bit MSB of a 3 rd bit from the left. In this example, the memory cell has 8 memory states (i.e., "111", "110", "100", "101", "001", "000", "010" and "011") according to different threshold voltages. By applying the read voltages VA through VG to the control gates, the bits stored by the memory cells can be identified.

It should be noted that, taking an MLC NAND type flash memory as an example, several memory cells arranged on the same word line may constitute 2 physical program cells, where the physical program cells constituted by LSBs of the memory cells are referred to as lower physical program cells, and the physical program cells constituted by MSBs of the memory cells are referred to as upper physical program cells. Taking TLC NAND type flash memory as an example, several memory cells arranged on the same word line may constitute 3 physical programming cells, wherein the physical programming cells constituted by LSBs of the memory cells are referred to as lower physical programming cells, the physical programming cells constituted by CSBs of the memory cells are referred to as middle physical programming cells, and the physical programming cells constituted by MSBs of the memory cells are referred to as upper physical programming cells.

FIG. 11 is a schematic diagram of an exemplary memory cell memory architecture and a physical erase unit according to the present exemplary embodiment.

Referring to FIG. 11, taking a TLC NAND type flash memory as an example, one physical erasing unit is composed of a plurality of physical programming unit groups, wherein each physical programming unit group comprises a lower physical programming unit, a middle physical programming unit and an upper physical programming unit composed of a plurality of memory cells arranged on the same word line. For example, in the physical erase unit, the 0 th physical program unit belonging to the lower physical program unit, the 1 st physical program unit belonging to the middle physical program unit, and the 2 nd physical program unit belonging to the upper physical program unit are regarded as one physical program unit group. Similarly, the 3 rd, 4 th and 5 th physical programming units are considered as a physical programming unit group, and other physical programming units are also divided into a plurality of physical programming unit groups according to the method. That is, in the example embodiment of fig. 11, there are 258 physical program units in total, and the physical erase unit of fig. 11 can be divided into 86 physical program unit groups in total, because the lower physical program unit, the middle physical program unit and the upper physical program unit, which are composed of a plurality of memory cells arranged on the same word line, form one physical program unit group. However, it should be noted that the present invention is not limited to the number of the physical program units or the physical program unit groups in the physical erase unit.

FIG. 12 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention.

Referring to FIG. 12, the memory cells 502 of the rewritable nonvolatile memory module 406 form a plurality of physical program units, and the physical program units form a plurality of physical erase units 400 (0) to 400 (N). Specifically, memory cells on the same word line constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into lower physical programming units and upper physical programming units. For example, the LSB of each memory cell is that belonging to the lower physical programming cell, and the MSB of each memory cell is that belonging to the upper physical programming cell. In this exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit is a physical page or a physical sector (sector). If the physical programming units are physical pages, each physical programming unit typically includes a data bit region and a redundancy bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., error correction codes). In the present exemplary embodiment, each data bit zone includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical fans, and the present invention is not limited to the size and number of physical fans. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks.

FIG. 13 is a schematic block diagram of a memory control circuit unit according to an example embodiment. It should be understood that the structure of the memory control circuit unit shown in fig. 13 is only an example, and the invention is not limited thereto.

Referring to fig. 13, the memory control circuit unit 404 includes a memory management circuit 702, a host interface 704, a memory interface 706, and an error checking and correcting circuit 708.

The memory management circuit 702 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 702 has a plurality of control commands, and the control commands are executed to perform writing, reading and erasing operations of data while the memory storage device 10 is in operation. The operation of the memory management circuit 702 or any of the circuit elements included in the memory control circuit unit 404 is described as follows, which is equivalent to describing the operation of the memory control circuit unit 404.

In the present exemplary embodiment, the control instructions of the memory management circuit 702 are implemented in firmware. For example, the memory management circuit 702 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In another example embodiment, the control instructions of the memory management circuit 702 may also be stored in code form in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area of the memory module dedicated to storing system data). In addition, the memory management circuit 702 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit 404 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 702. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

Furthermore, in another example embodiment, the control instructions of the memory management circuit 702 may also be implemented in a hardware type. For example, the memory management circuit 702 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read instruction sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erase circuit is configured to issue an erase command sequence to the rewritable nonvolatile memory module 406 to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, read command sequence, and erase command sequence may each include one or more codes or command codes and are used to instruct the rewritable nonvolatile memory module 406 to perform corresponding writing, reading, and erasing operations. In an example embodiment, the memory management circuitry 702 may also issue other types of sequences of instructions to the rewritable non-volatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 704 is coupled to the memory management circuit 702 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, the instructions and data transmitted by the host system 11 are transmitted to the memory management circuit 702 through the host interface 704. In the present exemplary embodiment, host interface 704 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 704 may also be compatible with PATA standards, IEEE 1394 standards, PCI Express standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 706 is coupled to the memory management circuit 702 and is used to access the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format acceptable to the rewritable nonvolatile memory module 406 through the memory interface 706. Specifically, if the memory management circuit 702 is to access the rewritable nonvolatile memory module 406, the memory interface 706 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection procedures, etc.). These sequences of instructions are, for example, generated by memory management circuitry 702 and transferred to rewritable non-volatile memory module 406 through memory interface 706. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction codes or codes. For example, the read instruction sequence may include information such as a read identification code and a memory address.

The error checking and correction circuit 708 is coupled to the memory management circuit 702 and is used for performing an error checking and correction procedure to ensure the correctness of the data. Specifically, when the memory management circuit 702 receives a write command from the host system 11, the error checking and correcting circuit 708 generates a corresponding error correction code (error correcting code, ECC code) or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 702 writes the data corresponding to the write command and the corresponding error correction code or error checking code into the rewritable nonvolatile memory module 406. Then, when the memory management circuit 702 reads data from the rewritable nonvolatile memory module 406, it reads the error correction code or the error check code corresponding to the data at the same time, and the error check and correction circuit 708 performs an error check and correction procedure on the read data according to the error correction code or the error check code.

In an exemplary embodiment of the present invention, the memory control circuit unit 404 further includes a buffer memory 710 and a power management circuit 712. The buffer memory 710 is coupled to the memory management circuit 702 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 712 is coupled to the memory management circuit 702 and is used to control the power of the memory storage device 10.

In an example embodiment of the invention, the memory control circuit unit 404 further includes a counter 714. The counter 714 is coupled to the memory management circuit 702 and is used to count the read data from the rewritable nonvolatile memory module 406.

Fig. 14 is a diagram illustrating hard bit pattern decoding according to an example embodiment.

Referring to fig. 14, here, for example, SLC flash memory is taken as an example, distribution 1410 and distribution 1420 are used to represent the memory states of a plurality of memory cells, and distribution 1410 and distribution 1420 respectively represent different memory states. The memory units may belong to the same physical programming unit or different physical programming units, and the invention is not limited thereto. It is assumed herein that when a memory cell belongs to distribution 1410, bit "1" is stored in that memory cell; when a memory cell belongs to distribution 1420, this memory cell stores bit "0". When the memory management circuit 702 reads the memory cell with the read voltage 1440, the memory management circuit 702 obtains a verification bit indicating whether the memory cell is turned on. It is assumed here that the verify bit is "1" when the memory cell is turned on, and "0" when the memory cell is turned on, but the invention is not limited thereto. If the verification bit is "1", the memory management circuit 702 determines that the memory cell belongs to the distribution 1410, and vice versa is the distribution 1420. However, distribution 1410 overlaps with distribution 1420 in region 1430. That is, there are several memory cells that should belong to distribution 1410 but are identified as distribution 1420, and there are several memory cells that should belong to distribution 1420 but are identified as distribution 1410.

In this example embodiment, when the memory cells are to be read, the memory management circuit 702 selects a read voltage (e.g., the read voltage 1441) to read the memory cells to obtain the verification bits of the memory cells. The error checking and correction circuit 708 performs a decoding operation including a probability decoding algorithm based on the verification bits of the memory cells to generate a plurality of decoded bits, and the decoded bits may form a codeword.

In the present exemplary embodiment, the probability decoding algorithm uses a symbol (symbol) as a candidate, and the information input in the decoding process or the numerical value of the intermediate operation process is represented by the probability value of the candidates or the ratio of the probabilities between the candidates, so as to determine which candidate is the most likely candidate. For example, if a symbol has two candidates (bits 0 and 1), the probability decoding algorithm calculates the most likely candidate according to the probability of occurrence of 0 or 1, respectively, or calculates the most likely candidate according to the ratio of probabilities between 0 and 1. If N candidates are possible, for example, in Finite fields (finish fields) with values of 0 to N-1 (N is a positive integer, each candidate represents a plurality of bits), the probability decoding algorithm calculates the probabilities of the N candidates to determine the most likely candidate, or calculates the relative probability ratio using the probability of one of the values as the denominator to determine the most likely candidate. In an exemplary embodiment, the ratio of the probabilities may also be expressed in logarithmic form.

In the present example embodiment, the probability decoding algorithm may be a convolutional code (convolutional code), a turbo code (turbo code), a low-density parity-check code (low-density parity-check code), or other algorithm with probability decoding features. For example, in convolutional codes and turbo codes, a finite state machine (finite state machine) may be used to encode and decode, and in this example embodiment, the most likely states are calculated based on the validation bits, thereby generating decoded bits. The low density parity check code will be described below as an example.

If a low density parity check code is used, the memory management circuit 702 also obtains the decoding initial value of each memory cell according to each verification bit when performing the decoding operation according to the verification bit. For example, if the verification bit is "1", the memory management circuit 702 sets the decoding initial value of the corresponding memory cell to n; if the verification bit is "0", the decoding initial value is-n. Where n is a positive number, but the invention is not limited to what the value of the positive integer n is. In one embodiment, n is, for example, 8.

The error checking and correction circuit 708 performs iterative decoding of the low density parity check algorithm based on the decoding initial values to generate a codeword comprising a plurality of decoded bits. In iterative decoding, the decoding initial values are continuously updated to represent a probability value, which is also referred to as reliability or confidence (belief). The updated decoding initial value is converted into a plurality of decoding bits, and the error checking and correcting circuit 708 regards the decoding bits as a vector and multiplies the vector by a matrix of modulo 2 (module 2) of a parity-check matrix of a low density parity-check algorithm to obtain a plurality of syndromes. These syndromes can be used to determine whether the codeword made up of decoded bits is a valid codeword. If the codeword of decoded bits is a valid codeword, iterative decoding is stopped and error checking and correction circuit 708 outputs the codeword of decoded bits. If the decoded bits constitute an invalid codeword, the decoded initial value is continued to be updated and new decoded bits are generated for the next iteration. When the number of iterations reaches a preset number of iterations, iterative decoding is stopped. The error checking and correction circuit 708 uses the decoded bits from the last iteration to determine whether the decoding was successful. For example, if the decoding bits generated by the last iteration are determined to constitute a valid codeword according to the syndrome, then the decoding is successful; if the first decoded bit constitutes an invalid codeword, it indicates decoding failure.

In another example embodiment, the decoding operation includes probability decoding algorithms including convolutional codes and turbo codes, and further error correction codes. For example, convolutional codes and turbo codes may be used with parity codes of any algorithm. After the decoding portion of the convolutional code or turbo code is performed in the decoding operation, the parity code may be used to determine whether the codeword formed by the generated decoding bits is a valid codeword, thereby determining whether the decoding is successful.

Regardless of the error correction code used, if decoding fails, it means that these memory cells store uncorrectable error bits. If the decoding fails, the memory management circuit 702 retrieves another read voltage (e.g., the read voltage 1442) to read the memory cells to retrieve the verification bits of the memory cells. The memory management circuit 702 performs the decoding operation described above based on the retrieved verification bits to retrieve another codeword composed of a plurality of decoded bits. In an exemplary embodiment, the error checking and correcting circuit 708 determines whether the other codeword is a valid codeword according to a syndrome corresponding to the other codeword. If the other codeword is not a valid codeword, the memory management circuit 702 determines that decoding has failed. If the number of times of re-fetching the read voltage does not exceed the preset number of times, the memory management circuit 702 re-fetches other fetch voltages (e.g., the read voltage 1443), and reads the memory cell according to the re-fetched read voltage 1443 to re-fetch the verification bit and perform the decoding operation.

In other words, when there are uncorrectable error bits, by retrieving the read voltage, the verification bits of some memory cells are changed, thereby changing a plurality of probability values in the probability decoding algorithm, and further having the opportunity to change the decoding result of the decoding operation. Logically, the above-mentioned action of retrieving the read voltage is to flip (flip) bits in a codeword and re-decode the new codeword. In some cases, codewords that cannot be decoded before flipping (with uncorrectable error bits) may be decoded after flipping. Also, in an example embodiment, the memory management circuit 702 may attempt to decode several times until the number of attempts exceeds a predetermined number. However, the present invention is not limited to what the preset number of times is.

It should be noted that the example of SLC flash memory is illustrated in fig. 14, but the step of retrieving the read voltage may also be applied to MLC or TLC flash memory. As shown in fig. 9, changing the read voltage VA inverts the LSB of one memory cell, and changing the read voltage VB or VC inverts the MSB of one memory cell. Thus, changing the read voltage VA, VB or VC can change one codeword to another codeword. The result of changing the codeword is also applicable to the TLC flash memory of fig. 10. The invention is not limited to SLC, MLC or TLC flash memory.

In the example embodiment of fig. 14, the decoding initial value of the memory cell is divided into two values (e.g., n and-n) according to one verification bit. The iterative decoding performed according to the two values is also called iterative decoding of a hard bit pattern (hard bit mode) (also called hard bit decoding operation). However, the above-described step of changing the read voltage may also be applied to iterative decoding (also referred to as soft bit decoding operation) of a soft bit pattern (soft bit mode), in which the decoding initial value of each memory cell is determined according to a plurality of verification bits. It is noted that either the hard bit mode or the soft bit mode, the probability values of the bits are calculated in iterative decoding and thus belong to the probability decoding algorithm.

Fig. 15 is a diagram illustrating soft bit pattern decoding according to an example embodiment.

As described above, after the read voltage is applied to the control gate of the memory cell, the verification bit obtained by the memory management circuit 702 is either "0" or "1" depending on whether the memory cell is turned on. Here, it is assumed that the corresponding verify bit is "0" if the memory cell is not turned on, and "1" if the memory cell is not turned on. In FIG. 15, the memory management circuit 702 applies the read voltages V1-V5 to the memory cells to obtain 5 verification bits. Specifically, the read voltage V1 corresponds to the verification bit b1; the read voltage V2 corresponds to the verification bit b2; the read voltage V3 corresponds to the verification bit b3; the read voltage V4 corresponds to the verification bit b4; the read voltage V5 corresponds to the verification bit b5. If the threshold voltage of a memory cell is in the interval 1501, the verification bits obtained by the memory management circuit 702 from the verification bit b1 to the verification bit b5 are "11111"; if the threshold voltage of the memory cell is in the interval 1502, the verify bit is "01111"; if the threshold voltage of the memory cell is in the interval 1503, the verify bit is "00111"; if the threshold voltage of the memory cell is within the interval 1504, the verify bit is "00011"; if the threshold voltage of the memory cell is in the interval 1505, the verify bit is "00001"; if the threshold voltage of the memory cell is in the interval 1506, the verify bit is "00000".

In this example embodiment, one of the read voltages V1-V5 is set to a sign read voltage. The sign read voltage is used to determine the sign of the decoding initial value. For example, if the read voltage V3 is a sign read voltage, the decoding initial values corresponding to the sections 1501 to 1503 are smaller than 0, and the decoding initial values corresponding to the sections 1504 to 1506 are larger than 0. Further, in each section, the probability that the memory cell belongs to the distribution 1510 and the probability that the memory cell belongs to the distribution 1520 may be calculated in advance. From these two probabilities, a log-likelihood ratio (Log Likelihood Ratio, LLR) can be calculated, which can be used to determine the absolute value of the decoding initial value. Therefore, the memory management circuit 702 obtains the decoding initial value of the memory cell in the soft bit mode according to the sign reading voltage and the verification bits b1 to b 5. For example, the decoding initial values corresponding to the sections 1501 to 1503 may be-8, -4, and-3, respectively, and the decoding initial values corresponding to the sections 1504 to 1506 may be 3, 4, and 8, respectively. In an exemplary embodiment, the decoding initial values corresponding to the respective intervals may be calculated in advance and stored in a lookup table. The memory management circuit 702 may input the verification bits b1 to b5 into the lookup table, thereby obtaining the corresponding decoding initial values. In other words, the implementation upper memory management circuit 702 may also obtain the decoding initial value of the memory cell in the soft bit mode based on the verification bits b1 to b5 without referring to the sign read voltage. In addition, if different sign read voltages are set, the memory management circuit 702 may use different look-up tables.

After the memory management circuit 702 obtains the decoding initial value, the error checking and correcting circuit 708 performs iterative decoding on the decoding initial value to obtain a codeword composed of a plurality of decoding bits, and uses the codeword composed of the plurality of decoding bits to determine whether the decoding is successful. If the decoding fails, the memory management circuit 702 can retrieve another read voltage.

After another read voltage is retrieved, the log likelihood ratio corresponding to each interval is changed, so the memory management circuit 702 uses a different look-up table to obtain the decoding initial value. Logically, the read voltage is changed to flip a number of bits in a codeword and to give a different decoding initial value (change value size or sign) so that a codeword that cannot be decoded before the change (with uncorrectable erroneous bits) can possibly be decoded after the change.

In the example embodiment of fig. 15, the decoding initial value of one soft bit pattern decoding (also referred to as soft bit decoding operation) is determined by 5 verification bits (read voltages). However, in other exemplary embodiments, the decoding initial value of a soft bit pattern decoding may be determined by a greater or lesser number of verification bits, and the invention is not limited thereto.

In general, when the NAND type flash memory is operated, data to be written into the rewritable nonvolatile memory module 406 is disturbed (inverted) by a data randomizer (not shown) and data read from the rewritable nonvolatile memory module 406 is restored (or "anti-disturbed") to average the distribution of 0 and 1. Specifically, in order to make the data programmed into the rewritable nonvolatile memory module 406 in an irregular random state, the data is first subjected to a data randomization process (e.g. editing, calculating or rearrangement) and then written, so that the data actually programmed into the physical programming unit is disordered enough to avoid the recognition error of the data caused by uneven distribution, uneven read voltage offset or uneven bit line resistance, etc., wherein the new data subjected to the randomization process is different from the original data, but the ratio of 0 to 1 in the new data may be the same as or different from the original data. Similarly, since the data actually programmed into the physical programming unit has been scrambled, the data read from the rewritable nonvolatile memory module 406 is also first restored to the original data by the data randomizing circuit.

In an exemplary embodiment, the data to be stored may be encoded by performing an encoding process by the error checking and correction circuit 708, and then performing a scrambling process on the encoded data by the data randomizing circuit. However, in another exemplary embodiment, the data to be stored may be scrambled by the data randomizing circuit to generate scrambled data, and then the error checking and correcting circuit 708 may encode the scrambled data. In addition, the data randomization circuit may be implemented separately from the error checking and correction circuit 708, or may be implemented in the error checking and correction circuit 708.

However, the rewritable nonvolatile memory module 406 changes the memory state with time and the usage status of the Program/Erase Cycle (P/E Cycle), the data retention (data retention), the temperature, the read count (read count) or the read voltage (read level), for example, the average of 0 and 1 is not even. Therefore, the decoding method according to the present invention can find the 0 and 1 distribution states in the data after the data is read out from the rewritable nonvolatile memory module 406, and adjust the log likelihood ratio (also referred to as the decoding parameter) corresponding to the data to a specific value according to the 0 and 1 distribution states, and decode the read data according to the decoding initial value corresponding to the adjusted log likelihood ratio. In particular, the log-likelihood ratio corresponding to the current memory state can be obtained by adjusting the log-likelihood ratio corresponding to the data to a specific value, and the probability of decoding success can be improved.

The operation of the memory control circuit unit 404 is described below as the operation of the memory management circuit 702.

In the present exemplary embodiment, the read command sequence received by the memory control circuit 404 is used to read bits from the memory cells. Specifically, the memory control circuit unit 404 reads bits from the memory unit after receiving the read command sequence. The read bits may be identified as either a first value or a second value. Here, the bit is "1" or "0", and in the present exemplary embodiment, "1" is referred to as a first value and "0" is referred to as a second value, but the present invention is not limited thereto. In another example embodiment, "1" may also be referred to as a second value, and "0" may also be referred to as a first value.

Next, the memory control circuit unit 404 calculates a first count value of a first value and a second count value of a second value in the read bits. Specifically, the memory control circuit unit 404 calculates the number of bits belonging to the first value (i.e., the first count value) and the number of bits belonging to the second value (i.e., the second count value) among the read bits by the counter 714.

Finally, the memory control circuit unit 404 may adjust the decoding parameters corresponding to the bits to specific decoding parameters according to the first count value and the second count value, and perform the decoding operation according to the specific decoding parameters. Wherein the adjusted decoding parameters affect the probability that each bit is considered an erroneous bit in the decoding operation. In general, the less evenly the distribution of 0 s and 1 s in the read data to be decoded, the less reliable the state of the memory. Thus, in the present exemplary embodiment, the memory control circuit unit 404 may adjust the decoding parameters corresponding to the bits by calculating the difference between the first count value and the second count value.

Specifically, if the difference between the first count value and the second count value is greater than 0, it means that the number of bits belonging to the first value is greater than the number of bits belonging to the second value in the read bits. This means that the number of 0 to 1 errors is greater than the number of 1 to 0 errors in the read bits, the first count value may contain more erroneous bits and be less reliable, and the second count value may contain fewer erroneous bits and be reliable. The memory control circuit unit 404 decreases the decoding parameter corresponding to the first value and/or increases the decoding parameter corresponding to the second value. On the other hand, if the difference between the first count value and the second count value is smaller than 0, it means that the number of bits belonging to the first value is smaller than the number of bits belonging to the second value in the read bits. This means that the number of 1 s to 0 s is greater than the number of 0 s to 1 s in the read bits, the first count value may contain fewer erroneous bits and be reliable, and the second count value may contain more erroneous bits and be less reliable. The memory control circuit unit 404 increases the decoding parameter corresponding to the first value and/or decreases the decoding parameter corresponding to the second value. Here, the memory control circuit unit 404 may adjust only the decoding parameters corresponding to at least one of the first value and the second value, or may simultaneously adjust the decoding parameters corresponding to the first value and the second value, which is not limited in this disclosure.

The present exemplary embodiment may further determine the size of the decoding parameter corresponding to the first value or the second value by using a predetermined threshold. In the present exemplary embodiment, the memory control circuit unit 404 calculates an absolute value of a difference between the first count value and the second count value, and if the absolute value of the difference is greater than the first threshold, the memory control circuit unit 404 adjusts the decoding parameter corresponding to the bit to a specific decoding parameter according to the first adjustment value. The preset threshold for determining the adjusted log likelihood ratio may be one or more, and the invention is not limited in this regard. In another embodiment, if the absolute value of the difference between the first count value and the second count value is greater than the second threshold, the memory control circuit unit 404 adjusts the decoding parameter corresponding to the bit to a specific decoding parameter according to the second adjustment value. In the present exemplary embodiment, the second threshold is greater than the first threshold, and the second adjustment value is greater than the first adjustment value.

In the present exemplary embodiment, the adjustment value for adjusting the decoding parameter to a specific decoding parameter is, for example, ±1 to 3. In another exemplary embodiment, the adjustment value for adjusting the decoding parameter to a specific decoding parameter is, for example, ±10 to 20% of the decoding parameter. The invention is not limited to the adjustment value here. The above decoding parameters, preset threshold values and adjustment values can be obtained through experiments in advance and stored in a specific area of the rewritable nonvolatile memory module 406, which is not limited in this disclosure.

In the present exemplary embodiment, the decoding parameters may include one or more positive decoding parameters and one or more negative decoding parameters, and the adjustment values for adjusting the positive decoding parameters and the adjustment values for adjusting the negative decoding parameters may be the same or different.

In the present exemplary embodiment, the decoding operation may be a hard bit decoding operation or a soft bit decoding operation. The following describes embodiments for adjusting log likelihood ratios in hard bit decoding operations and soft bit decoding operations, respectively.

Fig. 16 is an example illustrating decoding initial values according to an example embodiment. The log likelihood ratio may be used to determine the absolute value of the decoding initial value in the hard bit decoding operation, and the decoding initial value corresponding to the memory unit is divided into two values (e.g., n and-n) according to a verification bit (e.g., "1" or "0"), and the decoding initial value is calculated in advance and stored in a lookup table. Referring to fig. 16, assuming that the log-likelihood ratio is 10, the decoding initial value llr_h1 corresponds to the decoding initial value of the verification bit "1" being-10, and the decoding initial value corresponding to the verification bit "0" being +10.

First, the memory control circuit unit 404 reads bits from the memory unit after receiving the read command sequence, and the read bits can be identified as 0 or 1. Next, the memory control circuit unit 404 calculates the number of bits belonging to 0 (i.e., the first count value) and the number of bits belonging to 1 (i.e., the second count value) among the read bits by the counter 714, and determines whether the absolute value of the difference between the first count value and the second count value is greater than the first threshold. In the present exemplary embodiment, the absolute value of the difference between the first count value and the second count value is greater than the first threshold (e.g., 100), so the memory control circuit unit 404 adjusts the log likelihood ratio according to the first adjustment value (e.g., ±1).

Referring to fig. 16, the memory control circuit unit 404 adjusts the decoding initial value llr_h1 corresponding to the bit to the decoding initial value llr_h2. In this embodiment, the difference between the first count value and the second count value is greater than 0, which means that the first count value may contain more error bits and is less reliable, and the second count value may contain fewer error bits and is reliable. The memory control circuit unit 404 therefore decrements the log likelihood ratio 10 corresponding to the verification bit "1" by 1 to adjust the decoding initial value to-9, and increments the log likelihood ratio 10 corresponding to the verification bit "0" by 1 to adjust the decoding initial value to +11, as shown in fig. 16. After the memory control circuit unit 404 obtains the adjusted log likelihood ratio and the corresponding decoding initial value, the error checking and correcting circuit 708 performs iterative decoding according to the decoding initial value to obtain a codeword composed of a plurality of decoding bits, and uses the codeword composed of the plurality of decoding bits to determine whether the decoding is successful. It should be noted that those skilled in the art should know how to perform iterative decoding according to log likelihood ratios, and therefore, the description thereof is omitted here.

In the soft bit decoding operation, it is assumed that the log-likelihood ratio corresponding to the sections 1601, 1606 calculated in advance is 7, the log-likelihood ratio corresponding to the sections 1602, 1605 is 4, and the log-likelihood ratio corresponding to the sections 1603, 1604 is 1. The memory control circuit unit 404 obtains the decoding initial values LLR_S1 of the memory unit in the soft bit mode according to the sign reading voltage V3 and the verification bit, wherein the decoding initial values corresponding to the sections 1601-1603 are-7, -4 and-1, and the decoding initial values corresponding to the sections 1604-1606 are +1, +4 and +7.

First, the memory control circuit unit 404 reads bits from the memory unit after receiving the read command sequence, and the read bits can be identified as 0 or 1. Next, the memory control circuit unit 404 calculates the number of bits belonging to 0 (i.e., a first count value) and the number of bits belonging to 1 (i.e., a second count value) among the read bits by the counter 714, and determines whether the absolute value of the difference between the first count value and the second count value is greater than the first threshold or the second threshold. If the absolute value of the difference is greater than the first threshold but less than the second threshold, the memory control circuit unit 404 adjusts the log likelihood ratio according to the first adjustment value. If the absolute value of the difference is greater than the second threshold, the memory control circuit unit 404 adjusts the log likelihood ratio according to the second adjustment value.

In the present exemplary embodiment, the difference between the first count value and the second count value is greater than the second threshold (e.g., 300), so the memory control circuit unit 404 adjusts the log likelihood ratio according to the second adjustment value (e.g., ±2). Referring to fig. 16, the memory control circuit unit 404 adjusts the decoding initial value llr_s1 corresponding to the bit to the decoding initial value llr_s2. In this embodiment, the difference between the first count value and the second count value is greater than 0, which means that the first count value may contain more error bits and is less reliable, and the second count value may contain fewer error bits and is reliable. Therefore, the memory control circuit unit 404 decreases the log likelihood ratio 7 of the corresponding section 1601 by 2 to adjust to the decoding initial value of-5, decreases the log likelihood ratio 4 of the corresponding section 1602 by 2 to adjust to the decoding initial value of-6, decreases the log likelihood ratio 1 of the corresponding section 1603 by 2, and maintains the decoding initial value of-1 or adjusts to +1, increases the log likelihood ratio 1 of the corresponding section 1604 by 2 to adjust to the decoding initial value of +3, increases the log likelihood ratio 4 of the corresponding section 1605 by 2 to adjust to the decoding initial value of +6, and increases the log likelihood ratio 4 of the corresponding section 1606 by 2 to adjust to the decoding initial value of +9. In the present embodiment, the decoding initial values of the sections 1601 to 1603 are adjusted to +1 at the highest when they are adjusted to positive values, and the decoding initial values of the sections 1604 to 1606 are adjusted to-1 at the lowest when they are adjusted to negative values, and the present invention is not limited thereto. After the memory control circuit unit 404 obtains the adjusted log likelihood ratio and the corresponding decoding initial value, the error checking and correcting circuit 708 performs iterative decoding according to the decoding initial value to obtain a codeword composed of a plurality of decoding bits, and uses the codeword composed of the plurality of decoding bits to determine whether the decoding is successful. It should be noted that those skilled in the art should know how to perform iterative decoding according to log likelihood ratios, and therefore, the description thereof is omitted here.

Based on the above, the memory control circuit unit 404 can adjust the log likelihood ratio used for decoding according to the read bits to obtain the corresponding decoding initial value after each time reading the data according to the read command sequence (e.g. receiving a new read command sequence and re-obtaining another read voltage), so as to increase the probability of decoding success.

In another example embodiment, the memory control circuit unit 404 may also adjust a voltage level used to read bits from the memory cells to a second voltage level according to the first count value and the second count value. And after being adjusted to the second voltage level, performing the decoding operation provided by the invention. Specifically, the memory control circuit unit 404 reads bits from the memory unit after receiving the read command sequence. The read bits may be identified as either a first value or a second value. Then, the memory control circuit unit 404 calculates a first count value of a first value and a second count value of a second value in the read bits, and adjusts the voltage level for reading the bits from the memory cells to a second voltage level by calculating a difference between the first count value and the second count value.

For example, if the read voltage V3 is applied to the control gate of the memory cell, the read bits include a difference between the first count value and the second count value greater than 0, which indicates that the number of bits belonging to the first value is greater than the number of bits belonging to the second value. This means that the number of 0 to 1 errors is greater than the number of 1 to 0 errors in the read bits, the first count value may contain more erroneous bits and be less reliable, and the second count value may contain fewer erroneous bits and be reliable. The memory control circuit unit 404 thus regulates down the read voltage. On the other hand, if the difference between the first count value and the second count value is smaller than 0, it means that the number of bits belonging to the first value is smaller than the number of bits belonging to the second value in the read bits. This means that the number of 1 s to 0 s is greater than the number of 0 s to 1 s in the read bits, the first count value may contain fewer erroneous bits and be reliable, and the second count value may contain more erroneous bits and be less reliable. The memory control circuit unit 404 thus adjusts the read voltage up. The adjustment value for adjusting the read voltage may be obtained through experiments in advance and stored in a specific area of the rewritable nonvolatile memory module 406, which is not limited in this regard.

Fig. 17 is a flowchart illustrating a decoding method according to an example embodiment. In step S1702, a read instruction sequence is received, wherein the read instruction sequence is configured to read a plurality of bits from the plurality of memory cells. In step S1704, a first count value of a first value and a second count value of a second value of the plurality of bits are calculated. In step S1706, the decoding parameters corresponding to the plurality of bits are adjusted to specific decoding parameters according to the first count value and the second count value, and a decoding operation is performed according to the specific decoding parameters.

It should be noted that each step in fig. 17 may be implemented as a plurality of codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 17 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.

In summary, the decoding method, the memory storage device and the memory control circuit unit provided by the invention can calculate the distribution of the first value and the second value and judge whether the distribution is even. The memory control circuit unit may adjust the decoding parameter corresponding to the bit to a specific decoding parameter according to the average degree of the distribution, and execute the decoding operation again according to the value of the bit and the specific decoding parameter to attempt to obtain the successfully decoded codeword. By the method, the correction capability of decoding can be improved, the probability of decoding success can be improved, and decoding delay can be reduced.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A decoding method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, the decoding method comprising:

receiving a read instruction sequence, wherein the read instruction sequence is used for reading a plurality of bits from the plurality of storage units;

calculating a first count value of a first value and a second count value of a second value in the plurality of bits; and

adjusting decoding parameters corresponding to the plurality of bits to specific decoding parameters according to the first count value and the second count value, including:

in response to the difference between the first count value and the second count value being greater than a predetermined value, decreasing the decoding parameter corresponding to the first value or increasing the decoding parameter corresponding to the second value, and

In response to the difference between the first count value and the second count value being less than the predetermined value, increasing the decoding parameter corresponding to the first value or decreasing the decoding parameter corresponding to the second value,

and performing a decoding operation according to the particular decoding parameter, wherein the adjusted decoding parameter affects the probability that the plurality of bits are considered erroneous bits in the decoding operation.

2. The decoding method of claim 1, wherein the decoding parameter and the particular decoding parameter are log-likelihood ratios.

3. The decoding method according to claim 1, wherein an adjustment value for adjusting the decoding parameter to the specific decoding parameter is ±1 to 3.

4. The decoding method of claim 1, wherein the adjustment value for adjusting the decoding parameter to the specific decoding parameter is ±10-20% of the decoding parameter.

5. The decoding method according to claim 1, wherein the decoding parameters include one or more positive decoding parameters and one or more negative decoding parameters, and in the step of adjusting the decoding parameters corresponding to the plurality of bits to the specific decoding parameters according to the first count value and the second count value, adjustment values of the one or more positive decoding parameters are different from adjustment values of the one or more negative decoding parameters.

6. The decoding method according to claim 1, wherein the decoding parameters include one or more positive decoding parameters and one or more negative decoding parameters, and in the step of adjusting the decoding parameters corresponding to the plurality of bits to the specific decoding parameters according to the first count value and the second count value, an adjustment value of the one or more positive decoding parameters is identical to an adjustment value of the one or more negative decoding parameters.

7. The decoding method according to claim 1, wherein before the step of adjusting the decoding parameters corresponding to the plurality of bits to the specific decoding parameters according to the first count value and the second count value, the decoding method further comprises:

and adjusting the voltage level used for reading the bits from the memory cells to a second voltage level according to the first count value and the second count value.

8. The decoding method of claim 1, wherein the decoding operation is at least one of a hard bit decoding operation and a soft bit decoding operation.

9. A memory storage device, comprising:

the connection interface unit is used for being coupled to the host system;

A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells; and

a memory control circuit unit coupled to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to receive a sequence of read instructions, wherein the sequence of read instructions is configured to read a plurality of bits from the plurality of memory cells,

the memory control circuit unit is also used for calculating a first count value of a first value and a second count value of a second value in the plurality of bits through a counter, and

the memory control circuit unit is also configured to adjust decoding parameters corresponding to the plurality of bits to specific decoding parameters according to the first count value and the second count value, including:

10. The memory storage device of claim 9, wherein the decoding parameter and the particular decoding parameter are log-likelihood ratios.

11. The memory storage device of claim 9, wherein an adjustment value for adjusting the decoding parameter to the particular decoding parameter is ±1-3.

12. The memory storage device of claim 9, wherein an adjustment value for adjusting the decoding parameter to the particular decoding parameter is ±10-20% of the decoding parameter.

13. The memory storage device of claim 9, wherein the decoding parameters comprise one or more positive decoding parameters and one or more negative decoding parameters, and

in the operation of the memory control circuit unit adjusting the decoding parameters corresponding to the plurality of bits to the specific decoding parameters according to the first count value and the second count value, the adjustment values of the one or more positive decoding parameters are different from the adjustment values of the one or more negative decoding parameters.

14. The memory storage device of claim 9, wherein the decoding parameters comprise one or more positive decoding parameters and one or more negative decoding parameters, and

in the operation of the memory control circuit unit adjusting the decoding parameters corresponding to the plurality of bits to the specific decoding parameters according to the first count value and the second count value, the adjustment value of the one or more positive decoding parameters is identical to the adjustment value of the one or more negative decoding parameters.

15. The memory storage device of claim 9, wherein the memory control circuit unit is further configured to adjust a voltage level used to read the plurality of bits from the plurality of memory cells to a second voltage level based on the first count value and the second count value prior to an operation of adjusting the decoding parameters corresponding to the plurality of bits to the particular decoding parameters based on the first count value and the second count value.

16. The memory storage device of claim 9, wherein the decoding operation is at least one of a hard bit decoding operation and a soft bit decoding operation.

17. A memory control circuit unit for controlling a memory storage device including a rewritable nonvolatile memory module, and comprising:

A host interface for coupling to a host system;

a memory interface for coupling to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells; and

a memory management circuit coupled to the host interface and the memory interface,

18. The memory control circuit unit of claim 17, wherein the decoding parameter and the particular decoding parameter are log likelihood ratios.

19. The memory control circuit unit of claim 17, wherein an adjustment value for adjusting the decoding parameter to the specific decoding parameter is ±1-3.

20. The memory control circuit unit of claim 17, wherein an adjustment value for adjusting the decoding parameter to the particular decoding parameter is ±10-20% of the decoding parameter.

21. The memory control circuit unit of claim 17, wherein the decoding parameters comprise one or more positive decoding parameters and one or more negative decoding parameters, and

22. The memory control circuit unit of claim 17, wherein the decoding parameters comprise one or more positive decoding parameters and one or more negative decoding parameters, and

23. The memory control circuit unit of claim 17, wherein prior to operation of adjusting the decoding parameters corresponding to the plurality of bits to the particular decoding parameters according to the first count value and the second count value, the memory control circuit unit is further configured to adjust a voltage level used to read the plurality of bits from the plurality of memory cells to a second voltage level according to the first count value and the second count value.

24. The memory control circuit unit of claim 17, wherein the decoding operation is at least one of a hard bit decoding operation and a soft bit decoding operation.