TWI514404B - Method, memory controller and system for reading data stored in flash memory - Google Patents

Description

Method, memory controller and system for reading data stored in flash memory

The invention relates to reading data stored in a flash memory, in particular to a bit sequence read by referring to a memory cell of a flash memory. A method and a memory controller for reading data stored in a flash memory by binary digit distribution characteristic.

Flash memory can be stored electronically by erase and write/program, and is widely used in memory cards, solid-state drives and Portable multimedia player and more. Since the flash memory system is non-volatile memory, no additional power is required to maintain the information stored in the flash memory. In addition, the flash memory can provide fast data reading and better. The ability to withstand shocks, and these characteristics also explain why flash memory is so popular.

The flash memory can be divided into a NOR type flash memory and a NAND type flash memory. For NAND type flash memory, it has a shorter erasing and writing time and requires less wafer area per memory cell, so NAND type flash memory is compared to NOR type flash memory. Experience allows for higher storage densities and lower cost per storage location. In general, a flash memory system stores data in the form of a memory cell array, and the memory cells are implemented by a floating-gate transistor, and each memory cell is permeable. Appropriately controlling the number of charges on the floating gate of the floating gate transistor to set a required threshold voltage for turning on the memory cell implemented by the floating gate transistor, thereby storing information or a bit of a single bit Above the information, when one or more predetermined control gate voltages are applied to the control gate of the floating gate transistor, the conduction state of the floating gate transistor indicates the floating gate One or more binary digits stored in the crystal.

However, due to certain factors, the number of originally stored charges in the flash memory cell may be affected/disturbed. For example, the interference present in the flash memory may come from write disturb (write/program Disturbance, read disturbance, and/or retention disturbance. For example, a NAND-type flash memory having memory cells each storing information of one bit or more, a physical memory page contains a plurality of logical memory pages, and each logic Memory paging uses one or more control gate voltages for reading. For example, for a flash memory cell for storing information of 3 bits, the flash memory cell has 8 states corresponding to different numbers of charges (ie, different threshold voltages). One of the charge levels, however, due to the number of write/erase counts (program/erase count, P/E count) and/or retention time, in the flash memory cell. The threshold voltage distribution of the memory cell will change. Therefore, using the original control gate voltage setting (ie, threshold voltage setting) to read the information stored in the memory unit may be because The changed critical pressure distribution is not able to correctly obtain the stored information.

Using different control gate voltage settings to read flash memory may have a higher chance of getting the correct stored information. However, storing all the information obtained with different control gate voltage settings may require more memory space. In addition, using different control gate voltage settings to read flash memory can result in longer read times and, therefore, requires a more efficient read or decode program.

Accordingly, it is an object of the present invention to provide a method, memory controller and apparatus for reading data stored in a flash memory to solve the above problems. A method, a memory controller, and a device for reading data stored in a flash memory.

According to an embodiment of the invention, a method for reading data stored in a flash memory is disclosed, the method comprising: controlling the flash memory to be a first memory of the flash memory Paging performing a read operation; obtaining a first codeword of one of the first memory pages; obtaining a first set of similarity ratios of the first codeword according to a first approximate ratio corresponding rule; A set of similarity is compared with the corresponding value for an error correction operation; if the error correction operation indication is uncorrectable according to the first set of similarity ratio corresponding values, the first one is obtained according to a second approximate ratio corresponding rule The second group of codewords is similar to the corresponding value; and the error correction operation is performed according to the second group of similarity ratio corresponding values.

According to another embodiment of the present invention, a memory controller for reading data stored in a flash memory is disclosed. The memory controller includes: a control logic circuit for controlling the flash memory. Performing a read operation on the first memory page of the flash memory to obtain a first codeword of the first memory page; a similar ratio corresponding unit for corresponding to a first approximate ratio The rule obtains a first set of similarity ratio corresponding values of the first codeword; and a decoding circuit, configured to perform an error correction operation according to the first set of similarity ratio corresponding values, wherein if the first set is similar When the error correction operation result indicates an uncorrectable result than the corresponding value, the approximation is used to obtain a second group approximation ratio of the first codeword according to a second approximation ratio corresponding rule. Corresponding values, and the decoding circuit is further configured to perform the error correction operation according to the second set of similarity ratio corresponding values.

According to another embodiment of the present invention, a memory system for reading data stored in a flash memory is disclosed. The memory system includes: a control logic circuit for controlling the flash memory to One of the first memory banks of the flash memory performs a read operation to obtain one of the first memory words of the first memory page; a similar ratio corresponding unit for obtaining the first analog ratio corresponding rule One of the first codewords is similar to the corresponding value; and a decoding circuit is configured to perform an error correction operation according to the first set of similarity ratio corresponding values, wherein the corresponding value according to the first set of similarity ratios When the error correction operation indicates a result of the uncorrectable operation, the approximate ratio is used to obtain the second set of similarity ratio values of the first codeword according to a second approximate ratio corresponding rule. The decoding circuit is further configured to perform the error correction operation according to the second set of similarity ratio corresponding values.

Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the differences in the functions of the elements as the basis for the distinction. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is electrically connected to a second device, it means that the first device can be directly connected to the second device or indirectly connected to the second device through other devices or connection means.

Please note that reading a plurality of bits stored in the memory unit in the physical memory page of the NAND type flash memory is only an embodiment to illustrate the technical features of the present invention, however, regardless of the flash memory. The body is a NAND type flash memory or has other types of flash memory (such as NOR type flash memory), as long as the binary digits obtained from different reading operations are encoded into code words for error. Corrective operation is in accordance with the spirit of the present invention.

Please refer to FIG. 1 , which is a schematic diagram of a first embodiment of a memory system of the present invention. The memory system 1000 includes a flash memory 1100 and a memory controller 1200. In this embodiment, the flash memory 1100 may include a plurality of physical memory pages P_0, P_1, P_2, . .., P_N NAND type flash memory, wherein each of the physical memory pages P_0 to P_N includes a plurality of memory cells (eg, floating gate transistors) 1110, for example, To be read, one of the target entity memory pages P_0 includes memory cells M_0 to M_K. In order to read the data stored in the memory cells M_0 to M_K of the target physical memory page P_0, the control gate voltages VG_0 to VG_N should be appropriately set. For example, the control gate voltages VG_0 to VG_N should be appropriately set. It is ensured that all the memory cells (floating gate memory) 103 in the physical memory pages P_1 to P_N are in an on state. If each memory unit 103 is used to store N bits (for example, a least significant bit (LSB), a central significant bit (CSB), and a most significant bit (most significant) Bit, MSB) 3 bits, the flash memory 102 sets the control gate voltage VG_0 to (2 ^N -1) voltage levels to identify each memory in the target entity memory page P_0 N bits of the volume unit 103.

Please refer to FIG. 2, which is a schematic diagram of the first threshold voltage distribution of the physical memory page P_0 to be read. The memory cells M_0 to M_K of the physical memory page P_0 may include a floating gate that is programmed to have a charge level L0 (ie, (MSB, CSB, LSB) = (1, 1, 1)) The memory cell having a floating gate is programmed into a memory cell having a charge level L1 (ie, (MSB, CSB, LSB) = (0, 1, 1)), having a floating gate is programmed into A memory cell having a charge level L2 (ie, (MSB, CSB, LSB) = (0, 0, 1)) having a floating gate is programmed to have a charge level L3 (ie, (MSB, CSB, A memory cell of LSB)=(1,0,1)), having a floating gate that is programmed to have a charge level L4 (ie, (MSB, CSB, LSB) = (1, 0, 0)) a body unit having a floating gate programmed into a memory cell having a charge level L5 (ie, (MSB, CSB, LSB) = (0, 0, 0)), having a floating gate is programmed to have a charge The memory cell of level L6 (ie (MSB, CSB, LSB) = (0, 1, 0)) and having a floating gate are programmed to have a charge level L7 (ie (MSB, CSB, LSB)) =(1,1,0)) memory unit.

In order to identify the least significant bits of the memory cells M_0 to M_K, the flash memory 102 sets the control gate voltage VG_0 to the threshold voltage VT_4 shown in FIG. 2, and then, each memory in the physical memory page P_0. The conduction state of the body unit indicates that the least significant bit of the memory unit has "0" or "1". In this embodiment, when a memory cell in the physical memory page P_0 is turned on by the threshold voltage VT_4 applied to its control gate, the flash memory 1100 outputs a second representing its least significant bit. The carry number "1"; otherwise, the flash memory 1100 will output another binary digit "0" representing its least significant bit.

In order to identify the intermediate effective bits of the memory cells M_0 to M_K, the flash memory 1100 sets the control gate voltage VG_0 to the threshold voltages VT_2 and VT_6 shown in FIG. 2, respectively, and the physical memory page P_0. The conduction state of each of the memory cells indicates that the intermediate effective bit of the memory cell is "0" or "1". In this embodiment, when a memory cell is turned on by any one of the threshold voltages VT_2 and VT_6 applied to its control gate, the flash memory 1100 outputs a second representing the middle effective bit. Carry number "1"; flash memory 102 when the memory cell is not turned on by the threshold voltage VT_2 applied to its control gate, but is applied to the threshold voltage VT_6 of its control gate. A binary digit "0" representing the middle effective bit will be output; and when the memory cell is turned on except for the threshold voltage VT_2 which is not applied to its control gate, it will not be applied to its control gate. When the threshold voltage VT_6 is turned on, the flash memory 1100 will output a binary digit "1" representing the middle significant bit.

In order to identify the most significant bits of the memory cells M_0 to M_K, the flash memory 1100 sets the control gate voltage VG_0 to the threshold voltages VT_1, VT_3, VT_5, and VT_7 shown in FIG. 2, respectively. The conduction state of each memory cell in the memory page P_0 indicates that the most significant bit of the memory cell has "0" or "1". In this embodiment, when a memory cell is turned on by any of the threshold voltages VT_1, VT_3, VT_5, and VT_7 applied to its control gate, the flash memory 1100 will output the most significant bit. A binary digit "1" of the element; when the memory cell is not turned on by the threshold voltage VT_1 applied to its control gate, but is applied to the threshold voltages VT_3, VT_5 and VT_7 of its control gate When any one of them is turned on, the flash memory 1100 will output a binary digit "0" representing its most significant bit; when the memory cell is not applied to its control gate threshold voltages VT_1 and VT_3 When any one of them is turned on, but is turned on by any one of the threshold voltages VT_5 and VT_7 applied to its control gate, the flash memory 1100 will output a binary digit representing its most significant bit. "1"; when the memory cell is not turned on by any one of the threshold voltages VT_1, VT_3, and VT_5 applied to its control gate, but is applied to the threshold voltage VT_7 of its control gate to be turned on , flash The memory 1100 will output a binary digit "0" representing its most significant bit; and any of the threshold voltages VT_1, VT_3, VT_5, and VT_7 when the memory cell is not applied to its control gate. When turned on, the flash memory 1100 will output a binary digit "1" representing its most significant bit.

However, the threshold voltage distribution shown in Figure 2 may change to another threshold voltage distribution due to certain factors (such as the number of writes/reads and/or the increase in data retention time), for example, corresponding The distribution of circular protrusions to each charge level may be broadened and/or offset. Please refer to FIG. 3, which is a schematic diagram of a second threshold voltage distribution of the physical memory page P_0 to be read. As can be seen from Fig. 3, the threshold voltage distribution is different from the threshold voltage distribution shown in Fig. 2. Setting the control gate voltage VG_0 to the above-mentioned threshold voltages VT_1 to VT_7 will not correctly obtain the least significant bit, the intermediate effective bit and the most significant bit of the memory cells M_0 to M_K of the target physical memory page P_0. It is said that when the memory cells M_0 to M_K have the threshold voltage distribution shown in FIG. 3, the new threshold voltages VT_1' to VT_7' should be used in order to correctly obtain the stored information, otherwise, applied to the memory unit. The error correction code (ECC) operation of the codeword read by M_0~M_K cannot be successfully run because of an uncorrectable error in the codeword. In the present embodiment, the memory controller 1200 is designed to adaptively perform soft decoding on the code words read by the memory cells M_0 to M_K to enhance the decoding capability. Details are detailed later.

Please refer to Figure 1 again. The memory controller 104 is for controlling access (read/write) of the flash memory 102, and includes, but is not limited to, a control logic circuit 1210 and an error correction circuit (ECC circuit having An error correction decoder 1222, an error correction encoder 1229, and a threshold voltage tracking unit 1230). Please note that FIG. 1 only shows elements related to the technical features of the present invention, that is, the memory controller 104 may also include additional components to support other functions. In general, when a read request for the data stored in the memory cells M_0 to M_K in the target physical memory page P_0 is received, the control logic circuit 1210 controls the flash as it should read the request. The memory 1100 reads the requested data, and then, when the flash memory 102 successfully recognizes all the bits stored in each of the memory cells M_0 to M_K, the memory is included. The read information of the identified bit of the body cells M_0 to M_K is received by the receiving circuit 1210. As is known to those skilled in the art, a portion of the memory unit located in a physical memory page is used to store error correction information (e.g., an error correction code (ECC code)). Therefore, the error correction circuit 1220 is used. An error correction operation is performed on the read information (for example, a codeword) read by the flash memory 1100. In the present embodiment, the error correction circuit 1220 includes an error correction decoder (ECC decoder) 1222 and an error correction encoder (ECC corrector) 1229. The error correction decoder 1222 is used to check the correctness of the read information to thereby detect the presence of any error bits. The error correction decoder 1222 is also used to correct the error bits found in the checked read information. However, when the number of error bits actually present in the read information exceeds the error correction decoder 1222 has a way to follow When hard decoding (e.g., BCH (Bose-Chaudhuri-Hocquenghem mode)) corrects the maximum number of error bits, the error correction decoder 1222 instructs the control logic circuit 1210 to read the information containing an uncorrectable error. As such, the control logic circuit 1210 will initiate a soft read mechanism to obtain soft information that can be used by the ECC decoder 1222 to perform a soft decoding mechanism. The threshold voltage tracking unit 1230 is configured to determine the threshold voltage moving direction and determine an optimal threshold voltage by comparing the readout information. Details are detailed later.

In this embodiment, the error correction decoder 1222 can be implemented by a low density parity-check (LDPC) decoder, and the control logic circuit 1210 controls the flash memory 1100 to provide an LDPC decoder. Decoded soft information, so under the control of the control logic circuit 1210, the flash memory 1100 outputs a plurality of binary digits as soft bits read by the respective memory cells M_0 to M_K. (soft bit). Further, when the reading of the least significant bit data, the reading of the intermediate valid bit data, or the reading of the most significant bit data is performed, the control logic circuit 1210 is configured to control the flash memory 1100 to target the target. Each of the memory cells M_0 to M_K of the physical memory page performs a plurality of read operations (for example, seven read operations).

Please refer to FIG. 4, which is a schematic diagram of the least significant bit read operation of reading a soft bit (ie, a soft information value) from one of the memory cells of the flash memory 1100. According to the example of the threshold voltage distribution shown in FIGS. 2 and 3, a memory cell having any one of the charge levels L0 to L3 will store LSB=1 and have a charge level L4~L7. Any one of the charge level memory cells will store LSB=0. In this embodiment, the control unit 1210 determines an initial control gate voltage V _LSB and a voltage spacing D, and then controls the flash memory 1100 for each memory cell in the memory cells M_0 M M_K. Perform 7 read operations, and based on the voltage adjusting order OD1, the flash memory 1100 will sequentially follow V _LSB , V _LSB +D , V _LSB -D , V _LSB +2D , V _LSB -2D , V _LSB +3D, V _LSB -3D to set the control gate voltage VG_0, therefore, due to the applied gate control voltages V _LSB , V _LSB +D , V _LSB -D , V _LSB +2D , V _LSB -2D For the sake of V _LSB +3D and V _LSB -3D, each bit sequence in the bit sequence BS_0~BS_M will get 7 bits in sequence. Please note that each bit sequence in the bit sequence BS_0~BS_M is used as a soft bit, which represents the soft information read by a memory cell and is obtained by the initial control gate voltage V _LSB . The binary digit can be used as a sign bit (ie, a hard bit value). The read operation performed using the initial control gate voltage V _LSB can be regarded as a general read operation. The read operations using the control gate voltages V _LSB +D, V _LSB -D, V _LSB +2D, V _LSB -2D, V _LSB +3D, V _LSB -3D can be regarded as reread operations 1~6 respectively. .

In this embodiment, each bit sequence has one of eight possible binary digital combinations BS1~BS8. When the charge currently stored in the floating gate of the memory cell is such that the threshold voltage of the memory cell is higher than V _LSB +3D, the bit sequence read from the memory cell will have a binary digital combination BS8=""0000000"; when the charge currently stored in the floating gate of the memory cell is such that the threshold voltage of the memory cell is between V _LSB +2D and V _LSB +3D, the bit sequence read from the memory cell Will have a binary digit combination BS7 = "0000010"; when the charge currently stored in the floating gate of the memory cell is such that the threshold voltage of the memory cell is between V _LSB +D and V _LSB +2D, then from memory The bit sequence read by the body unit will have a binary number combination BS6 = "0001010"; when the charge currently stored in the floating gate of the memory cell is such that the threshold voltage of the memory cell is between V _LSB and V _LSB Between +D, the bit sequence read from the memory unit will have a binary number combination BS5 = "0101010"; when the charge currently stored in the floating gate of the memory cell causes the criticality of the memory cell Electricity Below V _LSB -3D, the memory unit from the read out bit sequences will have a combination of binary digits BS1 = "1111111"; if the current charges stored in the floating gate memory cell of the memory cell such that The threshold voltage is between V _LSB -2D and V _LSB -3D, then the bit sequence read from the memory unit will have a binary digit combination BS2 = "1111110"; when currently stored in the memory unit The charge of the floating gate is such that the threshold voltage of the memory cell is between V _LSB -D and V _LSB -2D, then the bit sequence read from the memory cell will have a binary digital combination BS3 = "1111010"; and when the charge currently stored in the floating gate of the memory cell is such that the threshold voltage of the memory cell is between V _LSB and V _LSB -D, the sequence of bits read from the memory cell will There will be a binary digit combination BS4 = "1101010".

When all the binary digits in a bit sequence are "1", this represents that the corresponding memory cell has a charge level L0, L1, L2 or L3, and the reliability of LSB=1 is high. . On the other hand, when all the binary digits in a bit sequence are "0", this represents that the corresponding memory cell has a charge level L5, L6, L7 or L8, and the reliability of LSB=0 is very high. high. However, when a bit sequence has different binary digits "0" and "1" mixed, this represents that the corresponding memory cell has a charge level L3 or L4, since the threshold voltage of the corresponding memory cell is Between V _LSB -3D and V _LSB +3D, the reliability of LSB=1/LSB=0 will be lower due to the higher error rate. For example, the memory unit that originally stored LSB=0 will have The amount of charge corresponding to the charge level L4 is stored such that the threshold voltage is higher than V _LSB +3D, however, as the number of write/erase times or data retention time increases, the amount of stored charge changes. It is possible that the threshold voltage is lower than V _LSB ; similarly, the memory cell that originally stores LSB=1 will have a charge storage amount corresponding to the charge level L3 such that the threshold voltage is lower than V _LSB -3D compared to hard decoding. The reliability present in the soft information value will increase the probability of decoding correctly when performing soft decoding. However, the soft information value includes a plurality of binary digits obtained in the normal reading operation and subsequent re-reading operations 1 to 6, as described above for the seven binary digits. In order to perform soft decoding, the error correction decoder 1222 must fetch and store the complete soft information value. Therefore, the error correction decoder 1222 requires a large amount of storage space to store the complete soft information value. This will increase wafer area and cost.

To reduce storage space, the binary digits obtained from the read operation can be encoded as a shorter codeword before being stored or decoded. Referring to FIG. 1, as described above, the error correction circuit 1220 is for performing an error correction operation on the read information obtained from the flash memory 1100. The error correction decoder 1222 is used to check the correctness of the read information. In addition, the error correction decoder 1222 further includes an encoder 1223, a storage device 1227, and a decoding unit 1228. The encoder 1223 is configured to generate a shorter codeword representing the binary digit based on the binary digits read from the flash memory 1100. The storage device 1227 is configured to store the codeword generated by the encoder and provide the stored codeword to the decoding unit 1228. Decoding unit 1228 is operative to perform an error correction operation on the codeword. Details are detailed later.

In one embodiment, the control logic circuit 1210 controls the flash memory 1100 to perform a read operation on the memory cell unit, such as the memory cell unit M_0~MK of the physical memory page P_0, according to the initial control gate voltage V _{LSB .} Identify the least significant bits of the memory cell unit M_0~MK. The read operation in accordance with the initial control gate voltage V _LSB can be regarded as a general read operation. The flash memory 1100 provides a page of binary digits including a data portion, a spare portion, and at least one parity portion to the control logic circuit 1210. Control logic circuit 1210 transmits its received binary digits to error correction circuit 1220. In an embodiment, the error correction circuit 1220 divides the received binary digits into two parts. The first part contains the data part and its corresponding check code part. The second part contains the spare part and its corresponding check code part. The error correction circuit 1220 performs a soft decode operation on the first portion and a hard decode operation on the second portion. This is illustrative and not a limitation of the invention. It is within the scope of the present invention to perform either soft decoding or hard decoding operations on any of the two-digit digits of the page. In this embodiment, encoder 1223 generates a codeword based on the binary digits of the first portion. Details are detailed later.

Please refer to FIG. 5 and FIG. 6. FIG. 5 is a block diagram of the encoder 1223 of FIG. Figure 6 is a diagram illustrating the encoding of binary digits read from a flash memory cell. The encoder 1223 includes a comparison unit 1224 and a determination unit 1225. Figure 5 only shows the components associated with the technical features of the present invention, i.e., the encoder 1223 may also include additional components to support other functions. The comparison unit 1223 is for comparing the binary digits of the first portion sent from the control logic circuit with the positive and negative bits stored in the storage device 1227. When reading a target physical memory page (eg, physical memory page P_0), control logic circuit 1210 controls flash memory 1210 to _store memory cell units in accordance with an initial control gate voltage VLSB (eg, physical memory page P_0) The memory cells M_0~M_K) perform a read operation to identify the least significant bits of the memory cells M_0~M_K. As shown in FIG. 6, the binary digit of the first portion of the physical memory page is transmitted to the encoder 1223. Please note that each of the binary digits represents a hard bit (hard information) of the least significant bit of the memory cell unit of the physical memory page P_0. . For example, the leftmost digit of the binary digits is "1", and the hard bit of the least significant bit of the memory cell M_0 representing the physical memory page P_0 is "1". The binary digits "1" next to the leftmost binary digits of the binary digits represent "1" as the hardest digit of the least significant digit of the memory cell M_1 of the physical memory page P_0. analogy. Since the binary digits of the first part are obtained by reading the memory cell units according to the initial control gate voltage, the binary digits can be regarded as the sign bits of the memory cells. Accordingly, the encoder 1223 generates (and sets) a high-intensity bit of "1" and a low-intensity bit of "1" to represent the positive and negative bit "1" having the highest reliability. In other words, the memory cell M_0 is assumed to be "1" and has the highest reliability. In addition, the code word "111" including the hard bit "1" and the soft bit (also referred to as soft information) "11" is used to represent the information stored in the memory unit M_0. The codewords used to represent other memory cells are also performed in a similar manner. Next, the first part of the binary digit code word is transmitted to the storage device 1227. Next, storage device 1227 provides the codeword to decoding unit 1228 to perform an error correction operation. In an embodiment, the decoding unit 1228 performs an error correction hard decode according to the codeword. In another embodiment, the decoding unit 1228 performs an error correction hard decoding according to the sign bit. The error correction operation indicates that the codeword is correct or correctable (in other words, the error corrects the hard decoding to indicate a correctable result), then the error correction circuit 1220 notifies the control logic circuit 1210 of the result and provides the correct data to the control logic circuit. 1210. If the error correction operation indicates that the codeword (or the sign bit) is uncorrectable (in other words, the error corrects the hard decoding to indicate a non-correctable result), the error correction circuit 1220 notifies the control logic circuit 1210 of the result, and the control logic circuit The 1210 control flash memory 1100 performs a reread operation (D is a predetermined voltage interval) on the memory cell unit in accordance with the control gate voltage V _LSB +D. Details are detailed later.

Please refer to FIG. 7. FIG. 7 is a diagram illustrating the encoding of the binary digits read from the flash memory unit to obtain the correct data. When reading a target physical memory page (eg, physical memory page P_0), control logic circuit 1210 controls flash memory 1100 to store memory cells in accordance with second control gate voltage V _LSB +D (eg, physical memory) The memory cells M_0 to M_K of the body page P_0 perform a read operation to interpret the least significant bits of the memory cells M_0 to M_K. This rereading operation can be considered as the first rereading operation. As shown in FIG. 7, the binary digit of the first portion of the physical memory page is sent to the encoding unit 1223. Please note that each of these binary digits represents a soft bit of the least significant bit of one of the memory cells of a physical memory page P_0. For example, the leftmost digit of the binary digits is "1", and the soft bit of the least significant bit of the memory cell M_0 representing the physical memory page P_0 is "1". The binary digits next to the leftmost binary digits of the binary digits are “0”, and the soft bit system representing the least significant bit of the memory cell M_1 of the physical memory page P_0 is “0”. analogy. Please note that the binary digits (rereading data) shown in Figure 7 may not be exactly the same as the sign digits. Because the control gate voltage system V _LSB +D is used for the first reread operation, the memory _whose threshold voltage falls in V _LSB and V _LSB +D is read by using the gate control voltages V _LSB and V _LSB +D . The unit will get different results. For example, the sign of the least significant bit of the memory cell M_1 obtained by controlling the gate voltage V _LSB is “0”, and the minimum of the memory cell M_1 obtained according to the control gate voltage V _LSB +D is obtained. The soft bit of the valid bit is "1". Therefore, the encoder 1223 needs to update the reliability of the codeword of the least significant bit of the memory unit M_1. Details are detailed later.

The reread data (binary digits) obtained in accordance with the control gate voltage V _LSB +D is sent to the comparison unit 1224. Comparison unit 1224 accesses the sign bit stored in storage device 1227 and compares the sign bit with the reread data to update the code word. If the sign bit is the same as its corresponding reread data (binary number), the comparing unit 1224 indicates the result to the judging unit 1225. The judging unit 1225 determines that the reliability of the sign bit is to be maintained. In other words, the codeword used to express the corresponding memory unit is not changed. If the sign bit is not the same as its corresponding reread data (binary number), the comparing unit 1224 indicates the result to the judging unit 1225. The determining unit 1225 determines that the reliability of the sign bit is to be updated to a minimum reliability. In other words, the codeword used to express the corresponding memory unit is changed. For example, the sign of the least significant bit of the memory cell M_1 obtained by controlling the gate voltage V _LSB is “0”, and the minimum of the memory cell M_1 obtained according to the control gate voltage V _LSB +D is obtained. The soft bit of the valid bit is "1". Accordingly, the judging unit 1225 determines that a high-intensity bit "0" and a low-intensity bit "0"" to represent the sign bit "1" have the lowest reliability. In other words, the least significant bit of the memory cell M_1 is updated to have a minimum reliability of "0". Further, the code word "000" including the hard bit "0" and the soft bit "00" is used to represent the least significant bit of the memory cell M_1. The codewords used to express other memory cells are also performed in a similar manner. Then, the updated first part of the binary digit code word is sent to the storage device 1227 for updating the original code word. Next, the storage device 1227 provides the updated codeword to the decoding unit 1228 to perform an error correction operation. In an embodiment, the decoding unit 1228 performs an error correction soft decode according to the updated codeword. Please note that the updated codeword is compared by the control gate and the voltage V _LSB +D. The obtained reread data (binary digits) and the positive and negative bits obtained from the control gate and voltage V _LSB are obtained. In other words, error correction soft decoding is performed based on the sign bit and the reread data (binary number). If the error correction operation indicates that the updated codeword is correct or correctable (in other words, the error correction soft decode indicates a correctable result), the error correction circuit 1220 notifies the control logic circuit 1210 of the result and provides the correct material to Control logic circuit 1210. If the error correction operation indicates that the updated codeword is not correctable (in other words, the error correction soft decode indicates an uncorrectable result), the error correction circuit 1220 notifies the control logic circuit 1210 of the result, and the control logic circuit 1210 controls the flash memory. 1100 performs a reread operation on the memory cell unit in accordance with the control gate voltage V _LSB -D (D is a predetermined voltage interval). The rereading operation performed on the memory cell unit in accordance with the control gate voltage V _LSB -D can be regarded as the second rereading operation. Please note that the voltage interval between the normal read operation and the first reread operation is the same as the voltage interval between the normal read operation and the second reread operation. Therefore, the rules for updating the reliability of the codeword should be similar, and the details of generating and storing the codeword according to the reread data obtained by the second reread operation are omitted here. If the error correction operation indicates that the updated codeword resulting from the second reread operation is correct or correctable (in other words, the error correction soft decode indicates a correctable result), the error correction circuit 1220 notifies the control logic circuit 1210 of the result. The correct information is provided to control logic circuit 1210. If the error correction operation indicates that the updated codeword resulting from the second reread operation is not correctable (in other words, the error correction soft decode indicates an uncorrectable result), the error correction circuit 1220 notifies the control logic circuit 1210 of the result, and the control logic The circuit 1210 controls the flash memory 1100 to perform a reread operation (D is a predetermined voltage interval) on the memory cell unit in accordance with the control gate voltage V _LSB + 2D. The rereading operation performed on the memory cell unit in accordance with the control gate voltage V _LSB +2D can be regarded as the third rereading operation. In addition, by comparing the binary digits obtained from the normal read operation and the first reread operation, the bit changes of the second digit of the first part in the normal read operation and the first reread operation can be obtained (bit). The total number of floppings, and can be recorded as the number of bits BF1. Similarly, by comparing the binary digits obtained from the normal read operation and the second reread operation, the total number of bit changes in the first part of the second part of the normal read operation and the second reread operation can be obtained, and This is recorded as the bit change number BF2. The bit change numbers BF1 and BF2 can be used to track an optimal threshold voltage. Details are detailed later.

Please refer to FIG. 8. FIG. 8 is a diagram illustrating the encoding of the binary digits read from the flash memory unit to obtain the correct data. When reading a target physical memory page (eg, physical memory page P_0), control logic circuit 1210 controls flash memory 1100 to memory cells in accordance with third control gate voltage V _LSB + 2D (eg, physical memory) The memory cells M_0 to M_K of the body page P_0 perform a read operation to interpret the least significant bits of the memory cells M_0 to M_K. This rereading operation can be considered as the third rereading operation. As shown in FIG. 8, the binary digit of the first portion of the physical memory page is sent to the encoding unit 1223. Please note that each of these binary digits represents a soft bit of the least significant bit of one of the memory cells of a physical memory page P_0. For example, the leftmost digit of the binary digits is "0", which represents the soft bit of the least significant bit of the memory cell M_0 of the physical memory page P_0. Please note that the binary digits (rereading data) shown in Figure 8 may not be exactly the same as the positive and negative digits. Because the control gate voltage system V _LSB +2D is used for the third reread operation, the memory _whose threshold voltage falls in V _LSB and V _LSB +2D is read using the gate control voltages V _LSB and V _LSB +2D . The unit will get different results. For example, the sign of the least significant bit of the memory cell M_0 obtained by controlling the gate voltage V _LSB is “0”, and the minimum of the memory cell M_0 obtained according to the control gate voltage V _LSB +2D is obtained. The soft bit of the valid bit is "1". Therefore, the encoder 1223 needs to update the reliability of the codeword of the least significant bit of the memory unit M_0. Details are detailed later.

The reread data (binary digits) obtained in accordance with the control gate voltage V _LSB + 2D is sent to the comparison unit 1224. Comparison unit 1224 accesses the sign bit stored in storage device 1227 and compares the sign bit with the reread data to update the code word. Please note that some binary digits may differ from the corresponding positive and negative digits in the first reread operation and the second reread operation. The reliability of these binary digits will no longer be updated. Comparison unit 1224 can ignore the binary digits. The determining unit 1225 maintains the reliability of the updated codeword. In other words, when the high-intensity bit and the low-intensity bit have been updated, the judging unit 1225 maintains the values of the high-intensity bit and the low-intensity bit. If the sign bit is not the same as its corresponding reread data (binary number), the comparing unit 1224 indicates the result to the judging unit 1225. The judging unit 1225 determines that the reliability of the sign bit is to be maintained. In other words, the code word used to express the corresponding memory unit does not change. If the sign bit is not the same as its corresponding reread data (binary number), the comparing unit 1224 indicates the result to the judging unit 1225. The determining unit 1225 determines that the reliability of the sign bit is to be updated to a higher reliability. In other words, the codeword used to express the corresponding memory unit is changed. For example, the sign of the least significant bit of the memory cell M_0 obtained by controlling the gate voltage V _LSB is “0”, and the minimum of the memory cell M_0 obtained according to the control gate voltage V _LSB +2D is obtained. The soft bit of the valid bit is "1". Accordingly, the judging unit 1225 determines that a high-intensity bit "0" and a low-intensity bit "1" to represent the sign bit "1" have higher reliability. In other words, the least significant bit of the memory cell M_0 is updated to have a higher reliability of "0". Further, the code word "001" including the hard bit "0" and the soft bit "01" is used to represent the least significant bit of the memory cell M_0. The codewords used to express other memory cells are also performed in a similar manner. Then, the updated first part of the binary digit code word is sent to the storage device 1227 for updating the original code word. Next, the storage device 1227 provides the updated codeword to the decoding unit 1228 to perform an error correction operation. In an embodiment, decoding unit 1228 performs an error correction soft decoding in accordance with the updated codeword. Please note that the updated codeword is obtained by comparing the reread data (binary digits) obtained from the gate and voltage V _LSB +2D and the sign bits obtained from the gate and voltage V _LSB . In other words, error correction soft decoding is performed based on the sign bit and the reread data (binary number). If the error correction operation indicates that the updated codeword is correct or correctable (in other words, the error correction soft decode indicates a correctable result), the error correction circuit 1220 notifies the control logic circuit 1210 of the result and provides the correct material to Control logic circuit 1210. If the error correction operation indicates that the updated codeword is not correctable (in other words, the error correction soft decode indicates an uncorrectable result), the error correction circuit 1220 notifies the control logic circuit 1210 of the result, and the control logic circuit 1210 controls the flash memory. 1100 performs a reread operation on the memory cell unit in accordance with the control gate voltage V _LSB -2D (D is a predetermined voltage interval). Details are detailed later.

The rereading operation performed on the memory cell unit in accordance with the control gate voltage V _LSB -2D can be regarded as the fourth reread operation. Please note that the voltage interval between the normal read operation and the third read operation is the same as the voltage interval between the normal read operation and the fourth read operation. Therefore, the rules for updating the reliability of codewords should be similar, and the details of generating and storing codewords according to the reread data obtained by the fourth reread operation are omitted here. If the error correction operation indicates that the updated codeword resulting from the fourth reread operation is correct or correctable (in other words, the error correction soft decode indicates a correctable result), the error correction circuit 1220 notifies the control logic circuit 1210 of the result. The correct information is provided to control logic circuit 1210. If the error correction operation indicates that the updated codeword resulting from the fourth reread operation is not correctable (in other words, the error correction soft decode indicates an uncorrectable result), the error correction circuit 1220 notifies the control logic circuit 1210 of the result, and the control logic The circuit 1210 controls the flash memory 1100 to perform a reread operation on the memory cell unit in accordance with the control gate voltage V _LSB +3D. The rereading operation performed on the memory cell unit in accordance with the control gate voltage V _LSB +3D can be regarded as the fifth reread operation. In addition, by comparing the binary digits obtained from the normal read operation and the third reread operation, the bit change of the second digit of the first part in the normal read operation and the third reread operation can be obtained. The total number of (bit flopping), and it can be recorded as the bit change number BF3. Similarly, by comparing the binary digits obtained from the normal read operation and the fourth reread operation, the total number of bit changes in the first part of the second part of the normal read operation and the fourth reread operation can be obtained, and This is recorded as the bit change number BF4. Bit change numbers BF3 and BF4 can be used to track an optimal threshold voltage. Details are detailed later.

Please refer to FIG. 9. FIG. 9 is a schematic diagram showing the encoding of the binary digits read from the flash memory unit to obtain the correct data. When reading a target physical memory page (eg, physical memory page P_0), control logic circuit 1210 controls flash memory 1100 to memory cells in accordance with fifth control gate voltage V _LSB +5D (eg, physical memory) The memory cells M_0 to M_K of the body page P_0 perform a read operation to interpret the least significant bits of the memory cells M_0 to M_K. This rereading operation can be considered as the fifth rereading operation. As shown in FIG. 9, the binary digit of the first portion of the physical memory page is sent to the encoding unit 1223. Please note that each of these binary digits represents a soft bit of the least significant bit of one of the memory cells of a physical memory page P_0. For example, the rightmost binary digit of the binary digits is "0", which represents the soft bit of the least significant bit of the memory cell M_0 of the physical memory page P_0. Please note that the binary digits (rereading data) shown in Figure 9 may not be exactly the same as the plus and minus digits. Because the control gate voltage system V _LSB +3D is used for the fifth reread operation, the memory _whose threshold voltage falls in V _LSB and V _LSB +3D is read using the gate control voltages V _LSB and V _LSB +3D . The unit will get different results. For example, according to the positive and negative bit line "1" of the least significant bit of the memory cell M_K obtained by controlling the gate voltage V _LSB , the minimum of the memory cell M_0 obtained according to the control gate voltage V _LSB +3D The soft bit of the valid bit is "1". Therefore, the encoder 1223 needs to update the reliability of the codeword of the least significant bit of the memory unit M_K. Details are detailed later.

The reread data (binary digits) obtained in accordance with the control gate voltage V _LSB +3D is sent to the comparison unit 1224. Comparison unit 1224 accesses the sign bit stored in storage device 1227 and compares the sign bit with the reread data to update the code word. Please note that some binary digits may differ from their corresponding sign digits in the first, second, third, and fourth reread operations. The reliability of these binary digits will no longer be updated. Comparison unit 1224 can ignore the binary digits. The determining unit 1225 maintains the reliability of the updated codeword. In other words, when the high-intensity bit and the low-intensity bit have been updated, the judging unit 1225 maintains the values of the high-intensity bit and the low-intensity bit. If the sign bit is the same as its corresponding reread data (binary number), the comparing unit 1224 indicates the result to the judging unit 1225. In other words, the code word used to express the corresponding memory unit does not change. If the sign bit is not the same as its corresponding reread data (binary number), the comparing unit 1224 indicates the result to the judging unit 1225. The determining unit 1225 determines that the reliability of the sign bit is to be updated to a higher reliability. In other words, the codeword used to express the corresponding memory unit is changed. For example, the sign of the least significant bit of the memory cell M_K obtained by controlling the gate voltage V _LSB is “0”, and the minimum of the memory cell M_K obtained according to the control gate voltage V _LSB +3D . The soft bit of the valid bit is "1". Accordingly, the judging unit 1225 determines that a high-intensity bit "1" and a low-intensity bit "0" to represent the sign bit "1" have a higher reliability. In other words, the least significant bit of the memory unit M_K is updated to have a higher reliability of "0". Further, the code word "010" including the hard bit "0" and the soft bit "10" is used to represent the least significant bit of the memory cell M_K. The codewords used to express other memory cells are also performed in a similar manner. Then, the updated first part of the binary digit code word is sent to the storage device 1227 for updating the original code word. Next, the storage device 1227 provides the updated codeword to the decoding unit 1228 to perform an error correction operation. In an embodiment, decoding unit 1228 performs an error correction soft decoding in accordance with the updated codeword. Please note that the updated codeword is obtained by comparing the reread data (binary digits) obtained from the control gate and voltage V _LSB +3D and the sign bits obtained from the control gate and voltage V _LSB . In other words, error correction soft decoding is performed based on the sign bit and the reread data (binary number). If the error correction operation indicates that the updated codeword is correct or correctable (in other words, the error correction soft decode indicates a correctable result), the error correction circuit 1220 notifies the control logic circuit 1210 of the result and provides the correct material to Control logic circuit 1210. If the error correction operation indicates that the updated codeword is not correctable (in other words, the error correction soft decode indicates an uncorrectable result), the error correction circuit 1220 notifies the control logic circuit 1210 of the result, and the control logic circuit 1210 controls the flash memory. The 1100 performs a reread operation on the memory cell unit in accordance with the control gate voltage V _LSB -3D. Details are detailed later.

The rereading operation performed on the memory cell unit in accordance with the control gate voltage V _LSB -3D can be regarded as the sixth reread operation. Please note that the voltage interval between the normal read operation and the fifth reread operation is the same as the voltage interval between the normal read operation and the sixth read operation. Therefore, the rules for updating the reliability of the codeword should be similar, and the details of generating and storing the codeword according to the reread data obtained by the sixth reread operation are omitted here. If the error correction operation indicates that the updated codeword resulting from the sixth reread operation is correct or correctable (in other words, the error correction soft decode indicates a correctable result), the error correction circuit 1220 notifies the control logic circuit 1210 of the result. The correct information is provided to control logic circuit 1210. If the error correction operation indicates that the updated codeword resulting from the sixth reread operation is not correctable (in other words, the error correction soft decode indicates an uncorrectable result), the error correction circuit 1220 notifies the control logic circuit 1210 of the result, and the control logic The circuit 1210 controls the flash memory 1100 to perform a reread operation on the memory cell unit in accordance with the control gate voltage V _LSB +4D. The rereading operation performed on the memory cell unit in accordance with the control gate voltage V _LSB +4D can be regarded as the seventh reread operation. Alternatively, if the error correction operation indicates that the updated codeword obtained from the sixth reread operation cannot be corrected (in other words, the data stored in the memory unit cannot be correctly obtained), the error correction circuit 1220 notifies the control logic circuit 1210 of the result. And the control logic circuit 1210 determines that the reading of the target entity memory page P_0 fails, and returns the read failure to a host. The number of reading operations can be arbitrarily determined, which is not a limitation of the present invention. In addition, by comparing the binary digits obtained from the normal read operation and the fifth reread operation, the bit change of the second carry digit of the first part in the normal read operation and the fifth reread operation can be obtained (bit). The total number of floppings, and can be recorded as the number of bit changes BF5. Similarly, by comparing the binary digits obtained from the normal read operation and the sixth reread operation, the total number of bit changes in the first part of the second part of the normal read operation and the sixth reread operation can be obtained, and This is recorded as the bit change number BF6. The bit variation BF5 and BF6 can be used to track an optimal threshold voltage.

Please refer to FIG. 10, which is a schematic diagram showing the correspondence between codewords and memory cells. For example, when receiving a hard bit of one of the memory cells obtained according to the initial control gate voltage VLSB, the encoder 1223 regards the hard bit as the sign bit of the least significant bit of the memory cell and It is preset that the sign bit has the highest reliability, for example, the code word "011" represents a very strong "0", and the code word "111" represents a very strong "1". However, in the first reread operation, the memory cell with a threshold voltage between V _LSB and V _LSB +D will be mapped to a very weak "0" and encoded as "000". In the second reread operation, the memory cell with a threshold voltage between V _LSB and V _LSB -D will be mapped to a very weak "1" and encoded as "100". In the third reread operation, the memory cell with a threshold voltage between V _LSB +D and V _LSB +2D will be mapped to a weak "0" and encoded as "001". In the fourth reread operation, the memory cell with a threshold voltage between V _LSB -D and V _LSB -2D will be mapped to a weak "1" and encoded as "101". In the fifth reread operation, the memory cell with a threshold voltage between V _LSB +2D and V _LSB +3D will be corresponding to a strong "0" and encoded as "010". In the sixth reread operation, the memory cell with a threshold voltage between V _LSB -2D and V _LSB -3D will be mapped to a weak "1" and encoded as "110". Please note that the correspondence between the codeword and the threshold voltage can be arbitrarily determined as long as the reliability of the (hard bit) of the sign bit can be identified by different code words. In addition, the codeword has a codeword length of three bits, which is shorter than a binary number (string) obtained by a memory cell in the normal read operation and the first to sixth read operations. For example, the threshold voltage of a memory cell is between V _LSB +2D and V _LSB +3D. The binary digit "0000000" (binary digit combination BS8) of the least significant bit of the memory unit obtained in the normal read operation and the first to sixth read operations. The binary digit contains seven bits, which are longer than the codeword length of the codeword. If the error correction decoder 1222 needs to store all seven bits in order to perform the error correction operation, instead of only storing three bits, the error correction decoder requires more memory space. Therefore, encoding the binary codewords obtained in different read operations into shorter codewords can reduce the memory space, and the cost can also be reduced.

In another embodiment, if the error correction operation indicates that the updated codeword obtained in the sixth reread operation cannot be corrected (in other words, the data stored in the memory unit cannot be correctly obtained), the decoding unit 1228 starts the approximate ratio. (LLR, log-likelihood ratio) training program to adjust the LLR mapping rule to perform error correction soft decoding. Please refer to FIG. 11 and FIG. 11 for explaining a block diagram of the decoding unit 1228. The decoding unit 1228 includes an approximate ratio training unit 12280, an analogy ratio corresponding unit 12282, and a decoding circuit 12284. Please note that only the technical features related to the present invention are shown in FIG. That is, decoding unit 1228 can include other components for performing other functions. Since the sixth re-read operation cannot obtain the correct data, the analogy used to map the updated codeword to the approximate ratio should be adjusted. Details are detailed later.

The updated codeword of the target entity memory page (eg, physical memory page P_0) is obtained during the sixth reread operation. The approximate ratio matching unit 12282 associates the updated codewords of the target entity memory pages into a set of first approximate ratio corresponding values according to a predetermined approximate ratio correspondence rule. For example, each code word used to express each memory unit corresponds to a specific approximate ratio corresponding value. The first set of approximate ratios are provided to the decoding circuit 12284. The decoding circuit 12284 performs an error correction operation according to the first set of similarity ratio corresponding values. If the error correction operation indication according to the first group approximate ratio corresponding value is a result of the uncorrectable, the training unit 12280 collects a correctable error correction unit code word of the flash memory 1100 and may The corrected error corrects the statistical characteristics of the correct data for the unit's codeword. For example, the target entity memory page contains 8 segments, and the segments are an error correction unit. Of the eight segments, the first segment S0 is not correctable, while the other segments are correctable. The codeword of the second segment S1 is obtained from the codeword of the target memory page by the training unit 12280. The second segment S1 is adjacent to the first segment S1 and includes x memory cells. Among the x memory cells, n0 memory cells are coded as codeword "000", n1 memory cells are coded as codeword "001"... and there are n7 memory cell codes. For the code word "111". After the error correction operation is performed on the second segment S1, the correct data of the second segment S1 can be correctly obtained. For those memory cells encoded as "000", there are A0 memory cells that are correctly decoded to 1, and A0 memory cells are correctly decoded to zero. Therefore, the approximate ratio of the codeword "000" should be constructed as log(A0/B0). The approximate ratio of the code word "001", the code word "010", and the code word "111" can also be similarly obtained. The correspondence between the codeword and the approximate ratio of the corresponding values obtained from the statistical features collected by the codeword of the second segment S1 and the correct data of the second segment S1 can be regarded as an adjusted approximation ratio corresponding rule. The adjusted approximate ratio can be compared with the corresponding rule to construct an approximate ratio correspondence table. Since the second segment S1 can be corrected, the adjusted approximation ratio corresponding rule obtained from the second segment S1 may indicate an approximation ratio corresponding rule that is more appropriate than the predetermined rule.

The adjusted approximate ratio correspondence rule may be provided to the approximate ratio corresponding unit 12282. In this way, the approximate ratio ratio unit 12282 corresponds the codeword of the target entity memory page obtained from the sixth reread operation to the second group approximate ratio corresponding value according to the adjusted approximate ratio correspondence rule. The second set of similarity ratios is provided to the decoding circuit 12284. The decoding circuit 12284 performs an error correction operation (eg, error correction soft decoding operation) according to the second set of similarity ratio corresponding values. If the error corrects the operational indication to a corrected result, the adjusted likelihood ratio corresponding value can be used to decode the next physical memory page. For example, the control logic circuit 1210 controls the flash memory 1100 to perform another read operation on the other physical memory page of the flash memory 1100 (for example, the physical memory page P_1), and obtain the code of another entity memory page. word. The approximate ratio unit 12282 obtains a set of similar ratios of the codewords according to the adjusted approximate ratio correspondence rule. The decoding circuit 12284 performs an error correction operation on the set of similarity ratio corresponding values.

Please note that the adjusted appearance is obtained in a different way than the corresponding rules. For example, the adjusted likelihood ratio can be obtained by translating the codewords of other sections (eg, sections S2, S3, ..., and S7) and the statistical characteristics of the correct data of the other sections. In addition, the adjusted likelihood ratio correspondence rule may be obtained by using other codewords that can correct the physical memory page (for example, the physical memory page P_N) and the statistical characteristics of the correct data of the correctable entity memory page. The correctable physical memory page can be physically adjacent to the target entity memory page. Finding the adjusted approximation is similar to the details of the corresponding rule. Therefore, the description will be omitted for brevity.

Please refer to FIG. 12, which is a flowchart illustrating a procedure for reading data stored in a flash memory. In step 200, the control logic circuit 1210 controls the flash memory 1100 to perform a general read operation on the memory unit of a target physical memory page according to the initial threshold voltage V _LSB to obtain a first binary digit of the page. Represents the least significant bits of each memory unit. In step 202, error correction decoder 1222 performs error correction hard decoding in accordance with the first binary digit of the page. If the error correction hard decode indicates a correctable result, proceed to step 214 to read the next physical memory page. In step 204, if the error correction hard decoding indicates a result that cannot be corrected, the control logic circuit 1210 controls the memory of the flash memory 1100 to page the target entity memory according to the initial threshold voltages V _LSB +D and V _LSB -D . The unit performs the first and second reread operations to obtain the second binary digits of the two pages for respectively representing the least significant bits of the respective memory unit. The error correction decoder 1222 performs error correction soft decoding based on the codeword obtained by encoding the first binary digit and the second binary digit. If the error correction soft decode indicates a correctable result, then step 212 is entered to perform a threshold voltage tracking procedure. Details are detailed later. Step 206, if the error correction soft decoding indicates a result of the uncorrectable, the control logic circuit 1210 controls the flash memory 1100 to perform the memory unit of the target physical memory page according to the initial threshold voltages V _LSB +2D and V _LSB -2D. The third and fourth reread operations operate to obtain the third binary digits of the two pages to represent the least significant bits of the respective memory cells. The error correction decoder 1222 performs error correction soft decoding based on the code words obtained by encoding the first binary digit, the second binary digit, and the third binary digit. If the error correction soft decode indicates a correctable result, then step 212 is entered to perform a threshold voltage tracking procedure. In step 208, if the error correction soft decoding indicates a result of the uncorrectable, the control logic circuit 1210 controls the flash memory 1100 to perform the memory unit of the target physical memory page according to the initial threshold voltages V _LSB +3D and V _LSB -3D. The fifth and sixth reread operations operate to obtain the fourth binary digits of the two pages for respectively representing the least significant bits of the respective memory cells. The error correction decoder 1222 performs error correction soft decoding based on the code words obtained by encoding the first binary digit, the second binary digit, the third binary digit, and the fourth binary digit. If the error correction soft decode indicates a correctable result, then step 212 is entered to perform a threshold voltage tracking procedure. If the error correction in step 210 indicates a non-correctable result, the LLR training stage is entered, and the details of the training phase are detailed in Figure 11 and the related description. Therefore, the details are omitted here for brevity.

Please refer to Fig. 13, which is a schematic diagram showing the threshold voltage distribution of the target entity memory page. The threshold voltage distribution of the standard physical memory page is derived from different reread operations. For example, the number of memory cells having a threshold voltage between V _LSB and V _LSB +D is X1. The number X1 is equal to the number of bit changes BF1. As mentioned above, the bit change number BF1 is obtained by comparing the binary read numbers obtained by the general read operation and the first reread operation. Similarly, the number of memory cells whose threshold voltage is between V _LSB and V _LSB -D is X2. The number X2 is equal to the number of bit changes BF2. The number of memory cells whose threshold voltage is between V _LSB +D and V _LSB +2D is X3. The number X3 is equal to the bit change number BF3 minus the bit change number BF1. Similarly, the number of memory cells having a threshold voltage between V _LSB -D and V _LSB -2D is X4. The number X4 is equal to the bit change number BF4 minus the bit change number BF2. Further, the number of memory cells whose threshold voltage is between V _LSB +2D and V _LSB +3D is X5. The number X5 is equal to the bit change number BF5 minus the bit change number BF3 and the bit change number BF1. Similarly, the number of memory cells whose threshold voltage is between V _LSB -2D and V _LSB -3D is X6. The number X6 is equal to the bit change number BF6 minus the bit change number BF2 and the bit change number BF4. The threshold voltage tracking unit 1230 finds the numbers X1 to X6, and determines a threshold voltage moving direction SD according to the numbers X1 to X6. Since the number X1 is greater than the number X2, a preferred threshold voltage may move to a lower voltage than _VLSB . In addition, the preferred threshold voltage may fall at V _LSB -D because the number X2 is relatively small compared to the X4 system. Please note that after the preferred threshold voltage (eg, V _LSB -D) is found, the control logic 1210 can use the preferred voltage as the initial threshold voltage for reading a physical memory page below the flash memory circuit 1100. (Control gate voltage).

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

1000. . . Memory system

1100. . . Flash memory

1110. . . Memory unit

1200. . . Memory controller

1210. . . Control logic

1220. . . Error correction circuit

1222. . . Error correction decoder

1223. . . Encoder

1224. . . Comparison unit

1225. . . Judging unit

1227. . . Storage device

1228. . . Decoding unit

1229. . . Error correction encoder

12280. . . Proportional ratio training unit

12282. . . Approximate ratio

12284. . . Decoding circuit

200~214. . . step

Figure 1 is a schematic illustration of a first embodiment of a memory system of the present invention.

Figure 2 is a schematic diagram of the first threshold voltage distribution of the physical memory page P_0 to be read.

Figure 3 is a schematic illustration of a second threshold voltage distribution of the physical memory page P_0 to be read.

FIG. 4 is a schematic diagram of the least significant bit read operation of reading a soft bit from one of the memory cells of the flash memory 1100.

Figure 5 is a block diagram of the encoder 1223 of Figure 1.

Figure 6 is a diagram illustrating the encoding of binary digits read from a flash memory cell.

Figure 7 is a diagram illustrating the encoding of the binary digits read from the flash memory unit to obtain the correct data.

Figure 8 is a diagram illustrating the encoding of binary digits read from a flash memory cell to obtain correct data.

Figure 9 is a diagram illustrating the encoding of binary digits read from a flash memory cell to obtain correct data.

Figure 10 is a diagram showing the correspondence between codewords and memory cells.

Figure 11 is a block diagram showing the decoding unit 1228.

Figure 12 is a flow chart showing the procedure for reading data stored in the flash memory.

Figure 13 is a schematic diagram showing the threshold voltage distribution of the target entity memory page.

1228. . . Decoding unit

12280. . . Proportional ratio training unit

12282. . . Approximate ratio

12284. . . Decoding circuit

Claims (20)

A method for reading data stored in a flash memory, the method comprising: controlling the flash memory to perform a read operation on a first memory page of the flash memory; obtaining the first a first codeword of the memory page; obtaining a first set of similarity ratios of the first codeword according to a first generality ratio matching rule; performing an error correction according to the first set of similarity ratio corresponding values If the error correction operation indication is uncorrectable according to the first set of similarity ratio corresponding values, obtaining a second set of similarity ratios of the first codeword according to a second approximate ratio corresponding rule a value; and the error correction operation is performed according to the second set of similarity ratio corresponding values. The method for reading data stored in a flash memory as described in claim 1, wherein the second similarity ratio is obtained by collecting a second codeword of the flash memory. The statistical characteristics of one of the correct data of the flash memory are obtained. The method for reading data stored in a flash memory as described in claim 2, wherein the second approximate ratio correspondence rule is configured to collect a portion of the first codeword and the first code A statistical feature of one of the correct data for that part of the word. The method for reading data stored in a flash memory according to claim 3, wherein the error correction operation according to the first set of similarity ratios indicates that the first memory page is One of the first sections is not correctable, and the second section adjacent to the first section is Preferably, the second likelihood ratio corresponding rule is obtained by collecting a statistical feature of the second codeword of the second segment and the correct data of the second segment. The method for reading data stored in a flash memory according to claim 3, wherein the error correction operation according to the first set of similarity ratios indicates that the first memory page is One of the first segments is uncorrectable, and the other segments of the first segment are correctable, and the second likelihood ratio corresponding rule is obtained by collecting the second codeword of the second segment and the other region The statistical characteristics of one of the correct data of the paragraph were obtained. The method for reading data stored in a flash memory as described in claim 2, wherein the second likelihood ratio corresponding rule is collected by collecting a second memory adjacent to the first memory page. The second codeword of one of the body pages is obtained from one of the correct data of the second memory page. The method for reading data stored in a flash memory according to claim 1, wherein the second similarity ratio is obtained by: obtaining a first from the flash memory a second codeword; performing the error correction operation on the second codeword; obtaining the correct data of the second codeword; and collecting the statistical data and the statistical feature of the second codeword to obtain the second approximate ratio corresponding rule. The method for reading data stored in a flash memory according to claim 1, wherein the method further comprises: controlling the flash memory to page through a third memory of the flash memory. Performing the read operation; Obtaining a third codeword of the third memory page; obtaining a third group approximate ratio corresponding value of the third codeword according to the second approximate ratio correspondence rule; and corresponding to the third group approximate ratio The value is corrected for this error to work. A memory controller for reading data stored in a flash memory, the memory controller comprising: a control logic circuit for controlling the flash memory to be one of the flash memory The memory page performs a read operation to obtain one of the first code words of the first memory page; a similar ratio corresponding unit, configured to obtain one of the first code words according to a first approximate ratio corresponding rule The group approximates the corresponding value; and a decoding circuit is configured to perform an error correction operation according to the first set of similarity ratio corresponding values; wherein the error correction operation indication is performed according to the first set of similarity ratio corresponding values When the result is corrected, the similarity is used to obtain a second set of similarity ratios of the first codeword according to a second generalized ratio corresponding rule, and the decoding circuit is further used for The error correction operation is performed according to the second set of similarity ratio corresponding values. The memory controller for reading data stored in a flash memory according to claim 9 of the patent application, the memory controller further comprising: a similar ratio training unit for collecting the flash memory One of the second codewords and one of the correct data of the flash memory is statistically characterized to obtain the second approximate ratio correspondence rule. For reading and storing as described in item 10 of the patent application scope a memory controller of data of a flash memory, wherein the overview is used to collect a statistical feature of the correct data of the portion of the first codeword and the portion of the first codeword to obtain the statistical component The second is similar to the corresponding rule. The memory controller for reading data stored in a flash memory according to claim 11, wherein the error correction operation according to the first set of similarity ratios indicates that the first One of the first sections of the memory page is uncorrectable, and the second section adjacent to one of the first sections can be corrected, which is more useful than the training unit for collecting one of the second sections. The second code word and one of the correct data of the second segment are statistically characterized to obtain the second approximation ratio correspondence rule. The memory controller for reading data stored in a flash memory according to claim 11, wherein the error correction operation according to the first set of similarity ratios indicates that the first One of the first pages of the memory page is not correctable, and the other segments of the first segment can be corrected, which is more useful than the training unit for collecting the second codeword of the other segment and the One of the correct data of the other sections is statistically characterized to obtain the second approximate ratio correspondence rule. The memory controller for reading data stored in a flash memory according to claim 10, wherein the analogy training unit is used for collecting adjacent first memory partitions. A second memory word of one of the second memory pages and one of the correct data of the second memory page are statistically obtained to obtain the second approximate ratio correspondence rule. a memory controller for reading data stored in a flash memory as described in claim 9 of the patent application, wherein The control logic circuit is further configured to obtain a second codeword from the flash memory; the decoding circuit is further configured to perform the error correction operation on the second codeword to obtain the correct data of the second codeword; And the approximation is used to collect the statistical data and the statistical feature of the second codeword to obtain the second approximate ratio corresponding rule. The memory controller for reading data stored in a flash memory, as described in claim 9, wherein the control logic circuit is further configured to control the flash memory to the flash memory. The third memory page performs the reading operation to obtain one of the third memory pages of the third memory page; the similarity is more than the corresponding unit system for obtaining the third according to the second likelihood ratio corresponding rule The third group of codewords is similar to the corresponding value; and the decoding circuit is further used to perform the error correction operation on the third group of similarity ratio corresponding values. A memory system for reading data stored in a flash memory, the memory system comprising: a control logic circuit for controlling the first memory of the flash memory to the flash memory Paging performing a read operation to obtain a first codeword of one of the first memory pages; a similarity ratio corresponding unit for obtaining a first group of the first codeword according to a first approximate ratio correspondence rule a similarity value; and a decoding circuit for performing an error correction operation according to the first set of similarity ratio corresponding values; wherein the error correction is performed according to the first set of similarity ratio corresponding values When the result of the uncorrectable indication is used, the approximate ratio is used to obtain the second set of similarity ratios of the first codeword according to a second approximate ratio corresponding rule, and the decoding circuit is used. The system is further configured to perform the error correction operation according to the second set of similarity ratio corresponding values. For example, in the memory system for reading data stored in a flash memory, the memory system further includes: a similar ratio training unit for collecting the second of the flash memory. The codeword and one of the correct data of the flash memory are statistically characterized to obtain the second approximate ratio correspondence rule. For example, in claim 18, the memory system for reading data stored in a flash memory, wherein the approximation is used to collect a portion of the first codeword and the first codeword more than the training unit One of the correct data of the portion is statistically characterized to obtain the second approximate ratio correspondence rule. For example, in claim 19, the memory system for reading data stored in a flash memory, wherein the error correction operation according to the first set of similarity ratios indicates that the first memory page is A first segment is uncorrectable, and a second segment adjacent to the first segment can be corrected, the approximation being used to collect the second codeword of the second segment more than the training unit One of the correct data of the second segment is statistically characterized to obtain the second approximation ratio corresponding rule.