CN110060723B

CN110060723B - Memory control device and memory control method

Info

Publication number: CN110060723B
Application number: CN201810046188.1A
Authority: CN
Inventors: 谢易霖; 萧景隆; 陈政宇; 林旺圣
Original assignee: Hefei Peirui Microelectronics Co ltd
Current assignee: Hefei Peirui Microelectronics Co ltd
Priority date: 2018-01-17
Filing date: 2018-01-17
Publication date: 2021-03-12
Anticipated expiration: 2038-01-17
Also published as: CN110060723A

Abstract

A memory control device includes a memory and a controller. The memory includes a plurality of memory blocks. The controller is coupled to the memory and is used for selecting a first memory block of the memory blocks and writing data into the first memory block. When the memory control device is turned off and operates again, the controller is further used for reading the voltage value distribution of the first memory block to determine the turn-off period, and determining the reference time according to the turn-off period and the initial time. The voltage distribution of the first memory block corresponds to data.

Description

Memory control device and memory control method

Technical Field

The present disclosure relates to memory technologies, and more particularly, to a memory control apparatus and a memory control method.

Background

Due to the NAND flash memory (NAND flash memory) process, data stored inside the memory may be in error due to the long time no power is connected. However, in the case of power-off, the controller controlling the operation of the memory cannot record the time information without reference to the clock, and thus cannot know the off-period of the memory. If a Real Time Clock (RTC) circuit is integrated or an external RTC circuit is used, the cost and the additional Standby power (Standby power) are increased.

Disclosure of Invention

One aspect of the present disclosure is a memory control device that includes a memory and a controller. The memory includes a plurality of memory blocks. The controller is coupled to the memory and is used for selecting a first memory block of the memory blocks and writing data into the first memory block. When the memory control device is turned off and operates again, the controller is further used for reading the voltage value distribution of the first memory block to determine the turn-off period, and determining the reference time according to the turn-off period and the initial time. The voltage distribution of the first memory block corresponds to data.

Another aspect of the present disclosure is a memory control method for a memory control device. The memory control method comprises the following steps. A first bank of a plurality of banks in the memory is selected by the controller and data is written into the first bank. When the memory control device is shut down and operates again, the voltage value distribution of the first memory block corresponding to the data is read by the controller to determine a shut-down period, and the reference time is determined according to the shut-down period and the initial time.

In summary, the controller can determine the turn-off period and the current reference time of the memory control device according to the voltage distribution of the selected first memory block without integrating additional circuits or external circuits.

Drawings

In order to make the aforementioned and other objects, features, advantages and embodiments of the present invention comprehensible, the following description is made with reference to the accompanying drawings:

FIG. 1 is a diagram illustrating a memory control device according to an embodiment of the present disclosure;

FIG. 2 is a flow chart illustrating a memory control method according to an embodiment of the disclosure;

FIG. 3 is a flow chart illustrating a memory control method according to an embodiment of the disclosure;

FIG. 4 is a diagram illustrating a voltage distribution of a first memory block according to an embodiment of the present disclosure; and

fig. 5 is a schematic diagram illustrating a voltage value distribution of the first memory block according to an embodiment of the disclosure.

[ notation ] to show

100: memory control device

110: memory body

120: controller

B1-Bn: memory block

200: memory control method

S201 to S204: step (ii) of

300: memory control method

S301 to S306: step (ii) of

D1, D2: distribution of voltage values

V1, V2: voltage of

Δ V: voltage difference

Detailed Description

The following disclosure provides many different embodiments or illustrations for implementing features of the invention. The present disclosure may repeat reference numerals and/or letters in the various examples, which repeat reference numerals and/or letters in the various figures are used for simplicity and clarity of illustration and do not in themselves designate relationships between the various embodiments and/or configurations in the following discussion.

As used herein, coupled or connected means that two or more elements are in direct physical or electrical contact with each other or in indirect physical or electrical contact with each other, and coupled or connected means that two or more elements are in operation or act with each other.

Please refer to fig. 1 and fig. 2. FIG. 1 is a diagram illustrating a memory control device 100 according to an embodiment of the present disclosure. FIG. 2 is a flow chart illustrating a memory control method 200 according to an embodiment of the disclosure. The memory control method 200 has a plurality of steps S201-S204, which can be applied to the memory control apparatus 100 shown in FIG. 1. It will be appreciated by those skilled in the art that the steps in the above embodiments, except where specifically indicated by their order, may be performed in any order, even simultaneously or in part simultaneously, as desired. The memory control device 100 includes a memory 110 and a controller 120. The Memory 110 includes a plurality of Memory blocks (Memory blocks) B1-Bn, each of the Memory blocks B1-Bn includes a plurality of Memory cells (cells). The memory 110 is coupled to the controller 120. In one embodiment, the memory 110 may be a NAND flash memory (NAND flash memory).

In step S201, the controller 120 selects one of the banks B1-Bn and writes data into the selected bank. For example, controller 120 selects bank B1 and writes the data to bank B1. It should be noted that the data written into the bank B1 may have a specific data type, so that the memory cells in the bank B1 are raised to a specific voltage (i.e., the voltage distribution is D1, as shown in fig. 4).

Alternatively, in another embodiment, the controller 120 may select one or more other banks for writing data, not limited to bank B1.

In an embodiment, the memory control device 100 can be applied to a Solid State Disk (SSD), and the controller 120 can be a controller of the SSD. The controller 120 writes data into the bank B1 during an initialization process of the solid state disk, and receives an initial time from an external device (e.g., a connected initialization system), and the controller 120 records the initial time in the memory 110.

In step S202, the memory control device 100 is turned off and re-operated. For example, the solid state disk using the memory control apparatus 100 may be disconnected from the system (e.g., a computer) and reconnected to the system after a period of time. In other words, the memory controller 100 also goes through the process of shutting down (i.e. disconnecting from the system) and re-operating (i.e. reconnecting to the system) in the above process.

In step S203, when the memory control device 100 is re-operated, the controller 120 can read the voltage distribution of the bank B1 to determine the turn-off period (i.e., the time difference between the previous operation and the current operation) of the memory control device 100. It should be noted that the data written into the memory block B1 in step S201 may have a voltage value decreasing after a period of shutdown, and the voltage value distribution changes in association with the shutdown period of the memory control apparatus 100.

For example, as shown in FIG. 5, the voltage distribution of the memory block B1 is changed from the voltage distribution D1 to the voltage distribution D2, and the voltages of the memory cells of the memory block B1 are decreased from V1 to V2 (i.e., the voltage difference Δ V is decreased). The controller 120 determines the turn-off period of the memory control device 100 according to the read voltage distribution of the bank B1. For example, the controller 120 can calculate the shutdown period of the memory control device 100 through an algorithm according to the voltage distribution of the memory block B1. For another example, the controller 120 can determine the shutdown period of the memory control apparatus 100 through a lookup table according to the voltage distribution of the memory block B1.

In step S204, the controller 120 determines a reference time according to the off period and the initial time. It should be noted that, according to the initial time received by the initialization program and the determined shutdown period, the controller 120 may calculate the current reference date (i.e., the reference time) of the solid state disk. It should be noted that, in the case that the memory control device 100 is turned off for multiple times, the controller 120 may repeat steps S202 to S204 to determine each turn-off period of the memory control device 100, and superimpose all turn-off periods according to the initial time to calculate the current reference date (i.e., the reference time) of the memory control device 100.

Thus, without the need to integrate additional circuits or external circuits, the controller 120 can determine the turn-off period and the current reference time of the memory control device 100 according to the voltage distribution of the selected bank B1.

In one embodiment, the controller 120 is further configured to determine whether to erase the memory block and write data into the memory block B1 according to the off period and the time threshold. Referring to fig. 3, fig. 3 is a flowchart illustrating a memory control method 300 according to an embodiment of the disclosure. The memory control method 300 has a plurality of steps S301-S306, which can be applied to the memory control apparatus 100 shown in FIG. 1. It will be appreciated by those skilled in the art that the steps in the above embodiments, except where specifically indicated by their order, may be performed in any order, even simultaneously or in part simultaneously, as desired.

In step S301, the controller 120 writes the data into the bank B1 and records the initial time in the memory 110. As described above, for example, the controller 120 can write data into the bank B1 in the initialization process of the solid state disk, and record the initial time in the memory 110.

Steps S302 to S304 are similar to steps S202 to S204, and the description will not be repeated here.

In step S305, the controller 120 determines whether the closing period is greater than a time threshold (which may be designed according to actual requirements).

When the controller 120 determines in step S305 that the off period is greater than the time threshold, the controller 120 erases the memory block B1 and writes data into the memory block B1 (step S306). It should be noted that if the controller 120 determines that the off period is greater than the time threshold, it indicates that the voltage level of the data written into the bank B1 may have dropped too low to accurately determine the off period. Therefore, the controller 120 can erase the data with the voltage value too low in the memory block B1 and rewrite the data into the memory block B1 for the accurate determination of the off period in steps S302-S303.

On the contrary, when the controller 120 determines in step S305 that the shutdown period is not greater than the time threshold, it indicates that the data written into the bank B1 can still be used to accurately determine the shutdown period in steps S302 to S303.

In this way, the controller 120 can accurately determine the current reference time of the solid state disk to which the memory control apparatus 100 is applied through the timely updated data bank B1.

Alternatively, in another embodiment, the controller 120 may select a plurality of banks among the banks B1-Bn in step S301 and write data into the selected plurality of banks. For example, the controller 120 may select eight banks among the banks B1-Bn in step S301 and write data into the selected eight banks. After each time the memory control device 100 is turned off and re-operated (step S302), the controller 120 erases one of the eight memory blocks in step S303, writes data into the erased memory block, and reads the voltage value distribution of the other memory blocks among the eight memory blocks to determine the off period of the memory control device 100.

It should be noted that the controller 120 can calculate the calculated value (e.g., the average value of the off periods) of the off periods according to the off periods corresponding to the voltage value distributions of the other memory blocks among the eight memory blocks, as the off periods of the memory control apparatus 100. Thus, the memory controller 100 can ensure that at least one bank can be used to accurately determine the off period during each re-operation.

In one embodiment, the controller 120 is further configured to determine whether to perform a maintenance operation on the memory 110 according to the shutdown period. For example, when the controller 120 determines that the shutdown period is greater than a predetermined value (e.g., one year, but the disclosure is not limited thereto), the controller 120 may perform a maintenance operation (e.g., data movement, recharging, etc.) on the memory to prolong the life of the memory.

In summary, without integrating additional circuits or external circuits, the controller 120 can determine the turn-off period and the current reference time of the memory control apparatus 100 according to the voltage distribution of the selected bank B1.

Although the present disclosure has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure should be limited only by the terms of the appended claims.

Claims

1. A memory control device includes:

a memory including a plurality of memory blocks; and

a controller coupled to the memory for selecting a first bank of the banks and writing a data into the first bank,

when the memory control device is turned off and operates again, the controller is further used for reading the voltage value distribution of the first memory block to obtain a reduced voltage difference according to the change of the voltage value distribution so as to determine a turn-off period, and determining a reference time according to the turn-off period and an initial time, wherein the voltage value distribution of the first memory block corresponds to the data.

2. The memory control device of claim 1, wherein the controller is further configured to determine whether to erase the first memory block and write the data into the first memory block according to the turn-off period and a time threshold.

3. The memory control device of claim 1, wherein the controller is further configured to determine whether to perform a maintenance operation on the memory according to the shutdown period.

4. The memory control device of claim 1, wherein the controller is further configured to calculate the reference time by adding the off period to the initial time.

5. The memory control device of claim 1, wherein the controller is further configured to record the initial time in the memory when the data is written into the first bank.

6. A memory control method for a memory control device, the memory control method comprising:

selecting a first memory block of a plurality of memory blocks in a memory by a controller, and writing data into the first memory block;

when the memory control device is turned off and operates again, the controller reads the voltage value distribution of the first memory block corresponding to the data to obtain a reduced voltage difference according to the change of the voltage value distribution so as to determine a turn-off period, and determines a reference time according to the turn-off period and an initial time.

7. The method of claim 6, further comprising:

determining whether to erase the first memory block and write the data into the first memory block by the controller according to the turn-off period and a time threshold.

8. The method of claim 6, further comprising:

the controller determines whether to perform a maintenance operation on the memory according to the reference time.

9. The method of claim 6, wherein determining the reference time according to the turn-off period and the initial time comprises:

the controller is used for adding the closing period and the initial time to calculate the reference time.

10. The method of claim 6, further comprising:

when the data is written into the first memory block, the controller records the initial time in the memory.