TW201447577A - Data writing method, memory controller and memory storage apparatus - Google Patents

Abstract

A data writing method for a writeable non-volatile memory module is provided. The method includes receiving a write command and data corresponding to the write command from a host system and temper temporarily storing the data into a buffer memory, wherein the data includes a plurality of sub-data streams. The method includes still includes transmitting the sub-data streams into the writeable non-volatile memory module, thereby writing the sub-data streams into at least one physical erasing unit of the non-volatile memory module. The method further includes generating parity information based on at least a portion of the sub-data streams; storing the parity information into the buffer memory and deleting the sub-data streams from the buffer memory. Accordingly, the method can effectively utilize the storage space of the buffer memory.

Description

Data writing method, memory controller and memory storage device

The present invention relates to a data writing method for a rewritable non-volatile memory and a memory controller and a memory storage device using the same.

Digital cameras, mobile phones and MP3s have grown very rapidly in recent years, prompting consumers to increase their demand for storage media. Because rewritable non-volatile memory has the characteristics of non-volatile data, low power consumption, small size, no mechanical structure and fast reading and writing speed, it is most suitable for portable electronic products, such as Mobile phones, personal digital assistants, and notebook computers. Therefore, in recent years, the flash memory industry has become a very popular part of the electronics industry.

Traditionally, the flash memory controller of the flash memory storage device is configured with a buffer memory, and when receiving a write command and multiple data from the host system, the flash memory controller first temporarily stores the data. Stored in the buffer memory, and then sequentially write the data to the corresponding entity page according to the order of the physical page. However, physical pages on the same character line have a coupling relationship with each other, so if A stylized error occurs on one of the entity pages, and the data on another entity page that is coupled to the physical page may be lost. For example, one physical block includes a plurality of physical page groups, and each physical page group includes a lower entity page and an upper entity page. When a physical stylization error occurs on the physical page of a physical page group, the data on the physical page may also be lost. In particular, according to the stylized order of the physical pages specified by the flash memory, it is possible to program a plurality of upper physical pages after serializing a plurality of lower physical pages. Therefore, after executing a write command (hereinafter referred to as a first write command), a transient in which only the lower physical page of the physical page group is written to the data is frequently generated, and in some of the physical page groups The upper physical page may be written to the data after executing the next write instruction (hereinafter referred to as the second write instruction). In this example, if a stylized error occurs when the second write command is executed to write the data to the physical page, the data written to the next physical page by executing the first write command may also be lost. In order to avoid data loss, the flash memory controller will retain this data in the buffer memory until it is ensured that the data will not be lost due to the stylization of other physical pages. Therefore, the existing flash memory storage system needs to be equipped with a large-capacity buffer memory, so that the volume of the flash memory storage system cannot be reduced, and the manufacturing cost is increased. In particular, in a memory storage system in which a plurality of flash memory dies are arranged, more buffer memory capacity is required to temporarily store data written by such host systems.

The invention provides a resource for a rewritable non-volatile memory module The material writing method, the memory controller and the memory storage device can reduce the buffer memory space required when executing the write command while avoiding data loss.

An exemplary embodiment of the present invention provides a data writing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has at least one memory die, the at least one memory The die includes a plurality of physical erase units, each of the physical erase units including a plurality of physical stylized units. The method for writing data includes: receiving, from a host system, a first write command and a first data corresponding to the write command, and temporarily storing the first data in a buffer memory, wherein the first data includes multiple sub-data strings . The data writing method further includes transmitting the sub-data strings from the buffer memory to the rewritable non-volatile memory module to write the sub-data strings to the at least one first physical erasing unit; At least a portion of the sub-data strings of the sub-data strings are used to generate the co-located information; and the same-bit information is stored in the buffer memory and the first data is removed from the buffer memory.

In an exemplary embodiment of the present invention, the step of generating the parity information according to at least a part of the sub-data strings of the sub-data strings includes: generating the co-located information according to all the sub-data strings.

In an exemplary embodiment of the present invention, the physical stylization unit of each of the physical erasing units includes a plurality of lower physical stylized units and a plurality of upper physical stylized units, and the speed of writing data to the lower physical stylizing unit Faster than writing data to the upper stylized unit. And the step of generating the above-mentioned information according to at least a part of the sub-data strings of the sub-data strings includes: identifying at least one of the first sub-data strings according to the entity stylizing unit storing the sub-data strings Subdata string And generating the parity information according to the at least one first sub-data string, wherein the at least one first sub-data string is stored in the at least one first lower physical stylized unit among the lower physical stylized units and corresponds to the at least At least one of the first upper physical stylized units of a first lower entity stylized unit does not store data.

In an exemplary embodiment of the present invention, the data writing method further includes: receiving the second information from the host system after storing the parity information in the buffer memory and removing the first data from the buffer memory. The write command and the second data corresponding to the second write command.

In an exemplary embodiment of the present invention, the data writing method further includes: determining whether a stylization error occurs when the second data is written into the at least one first physical erasing unit from the buffer memory; and When a stylization error occurs, at least a portion of the sub-data strings stored in the at least one first entity erasing unit are decoded using the parity information stored in the buffer memory to correct at least one of the at least one sub-data string. string.

In an exemplary embodiment of the present invention, the data writing method further includes: if the stylization error does not occur when the second data is written into the first entity erasing unit from the buffer memory, the buffer memory Remove the above information from the body.

In an exemplary embodiment of the present invention, the data writing method further includes: generating another parity information according to at least a portion of the second data; and storing the another parity information in the buffer memory and deleting the second data.

In an exemplary embodiment of the present invention, the sub-data strings are transferred from the buffer memory to the rewritable non-volatile memory module to write the sub-files. The step of the data string to the at least one first entity erasing unit of the physical erasing units includes: generating a plurality of error checking and correcting codes for the sub-data strings respectively; and respectively separating the sub-data strings The error check and correction code corresponding to the sub-data strings are transmitted to the rewritable non-volatile memory module to write the sub-data strings and the error check and correction codes respectively corresponding to the sub-data strings to the above At least one first entity erases the entity in the stylized unit.

In an exemplary embodiment of the present invention, the step of generating the parity information according to at least a part of the sub-data strings of the sub-data strings includes: writing each one of the sub-data strings into each of the sub-data strings. When the first entity erases the unit, the parity information is generated according to one of the sub-data strings and the previous parity information.

In addition, an exemplary embodiment of the present invention provides a memory controller for controlling a rewritable non-volatile memory module. The memory controller includes a host interface, a memory interface, a buffer memory, a parity information encoding and decoding circuit, and a memory management circuit. The host interface is coupled to the host system. The memory interface is coupled to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has at least one memory die, and the memory die includes a plurality of physical erase electrodes Unit, each entity erasing unit includes a plurality of entity stylizing units. The memory management circuit is coupled to the host interface, the memory interface, the buffer memory, and the parity information encoding and decoding circuit. The memory management circuit is configured to receive the first write command and the first data corresponding to the write command from the host system and temporarily store the first data into the buffer memory, wherein the first data includes a plurality of sub-data strings. In addition, the memory management circuit is further configured to transfer the sub-data strings from the buffer memory to the rewritable non-swing The boot memory module writes the sub-data strings to at least one of the first physical erase units of the physical erase units. In addition, the parity information encoding and decoding circuit is configured to generate the parity information according to at least a part of the sub-data strings of the sub-data strings, and the memory management circuit is further configured to store the parity information in the buffer memory and the buffer memory. The first data is removed from the body.

In an exemplary embodiment of the present invention, in the operation of generating the parity information according to at least a part of the sub-data strings of the sub-data strings, the co-located information encoding and decoding circuit generates the co-located according to all the sub-data strings. News.

In an exemplary embodiment of the present invention, the physical stylization unit of each of the physical erasing units includes a plurality of lower physical stylized units and a plurality of upper physical stylized units, and the speed of writing data to the lower physical stylizing unit Faster than writing data to the upper stylized unit. And, in the operation of generating the above-mentioned information according to at least a part of the sub-data strings, the memory management circuit identifies the sub-data strings according to the entity stylizing unit storing the sub-data strings. At least a first sub-data string and a parity information encoding and decoding circuit generates co-located information according to the first sub-data string, wherein the first sub-data string is stored in at least one first lower physical stylized unit among the lower physical stylized units And at least one first upper physical stylized unit corresponding to the at least one first lower entity stylized unit does not store data.

In an exemplary embodiment of the present invention, the memory management path is further configured to receive the second write from the host system after storing the parity information in the buffer memory and removing the first data from the buffer memory. The input instruction and the second data corresponding to the second write command.

In an exemplary embodiment of the present invention, the memory management circuit generates another parity information according to at least a portion of the second data and stores the other parity information in the buffer memory and deletes the second data.

In an exemplary embodiment of the present invention, in the operation of generating the parity information according to at least a part of the sub-data strings of the sub-data strings, each of the sub-data strings is written. When entering the first entity erasing unit, the above-mentioned parity information encoding and decoding circuit generates the parity information according to the one of the sub-data strings and the previous parity information.

Furthermore, an exemplary embodiment of the present invention provides a memory storage device including a connector, a rewritable non-volatile memory module, and a memory controller. The connector is for coupling to the host system. The rewritable non-volatile memory module has at least one memory die, the at least one memory die includes a plurality of physical erase units, and each physical erase unit includes a plurality of physical stylization units. The memory controller has a buffer memory and is coupled to the connector and the rewritable non-volatile memory module. The memory controller is configured to receive the first write command and the first data corresponding to the write command from the host system and temporarily store the first data into the buffer memory, wherein the first data includes a plurality of sub-data strings. In addition, the memory controller is further configured to transfer the sub-data strings from the buffer memory to the rewritable non-volatile memory module to write the sub-data strings to at least one of the physical erasing units. A first entity is erased in the unit. In addition, the memory controller is configured to generate the parity information according to at least a part of the sub-data strings of the sub-data strings, and store the co-located information in the buffer memory and remove the first data from the buffer memory.

In an exemplary embodiment of the present invention, in the foregoing operation of generating the parity information according to at least a part of the sub-data strings of the sub-data strings, the memory controller generates the co-located information according to all the sub-data strings.

In an exemplary embodiment of the present invention, the physical stylization unit of each of the physical erasing units includes a plurality of lower physical stylized units and a plurality of upper physical stylized units, and the speed of writing data to the lower physical stylizing unit Faster than writing data to the upper stylized unit. And, in the operation of generating the above-mentioned information according to at least a part of the sub-data strings of the sub-data strings, the memory controller identifies the sub-data strings according to the entity stylizing unit storing the sub-data strings. And generating at least one first sub-data string according to the first sub-data string, wherein the first sub-data string is stored in at least one first lower physical stylized unit among the lower physical stylized units and corresponds to the at least one At least one of the first upper stylized units of the entity stylized unit does not store data.

In an exemplary embodiment of the present invention, the memory controller is further configured to receive the second write from the host system after storing the parity information in the buffer memory and removing the first data from the buffer memory. The input instruction and the second data corresponding to the second write command.

In an exemplary embodiment of the invention, the memory controller is further configured to determine whether a stylization error occurs when the second data is written into the first physical erasing unit from the buffer memory. In the event of a stylization error, the memory controller uses the parity information stored in the buffer memory to decode at least a portion of the sub-data strings stored in the at least one first physical erasing unit to correct the at least one portion. At least one error substring in the data string.

In an exemplary embodiment of the present invention, if no stylization error occurs when the second data is written into the first physical erasing unit from the buffer memory, the memory controller is further used from the buffer memory. Remove the above information.

In an exemplary embodiment of the present invention, the memory controller generates another parity information according to at least a portion of the second data and stores the other parity information in the buffer memory and deletes the second data.

In an exemplary embodiment of the present invention, the memory controller is further configured to generate a plurality of error check and correction codes for the sub-data strings respectively. And transferring the sub-data strings from the buffer memory to the rewritable non-volatile memory module to write the sub-data strings to at least one of the physical erasing units In the operation of the unit, the memory controller transmits the sub-data strings and the error check and correction codes respectively corresponding to the sub-data strings to the rewritable non-volatile memory module to write the sub-data modules. The data string and the error check and correction code respectively corresponding to the sub-data strings are respectively added to the entity stylizing unit of the at least one first entity erasing unit.

In an exemplary embodiment of the present invention, in the operation of generating the parity information according to at least a part of the sub-data strings of the sub-data strings, each of the sub-data strings is written. When entering the first physical erasing unit, the memory controller generates the parity information according to the one of the sub-data strings and the previous parity information.

Based on the above, the data writing method and the memory control of the exemplary embodiment The memory and memory storage device can perform write instructions while using less buffer memory space while ensuring the correctness of the data.

The above described features and advantages of the invention will be apparent from the following description.

1000‧‧‧Host system

1100‧‧‧ computer

1102‧‧‧Microprocessor

1104‧‧‧ Random access memory

1106‧‧‧Input/output devices

1108‧‧‧System Bus

1110‧‧‧Data transmission interface

1202‧‧‧ Mouse

1204‧‧‧ keyboard

1206‧‧‧ display

1208‧‧‧Printer

1212‧‧‧USB flash drive

1214‧‧‧ memory card

1216‧‧‧ Solid State Drive

1310‧‧‧ digital camera

1312‧‧‧SD card

1314‧‧‧MMC card

1316‧‧‧ Memory Stick

1318‧‧‧CF card

1320‧‧‧Embedded storage device

100‧‧‧ memory storage device

102‧‧‧Connector

104‧‧‧ memory controller

106‧‧‧Reusable non-volatile memory module

202‧‧‧Memory Management Circuit

204‧‧‧Host interface

206‧‧‧ memory interface

208‧‧‧buffer memory

210‧‧‧Error checking and correction circuit

212‧‧‧Same Information Encoding and Decoding Circuit

252‧‧‧ memory cell array

254‧‧‧Control circuit

256‧‧‧Data input/output buffer

256a‧‧‧ first buffer

256b‧‧‧second buffer zone

304(0)~304(R)‧‧‧ physical erasing unit

701(0)~701(255)‧‧‧ entity stylized unit

400‧‧‧ memory grain

402‧‧‧Information area

404‧‧‧ spare area

406‧‧‧System Area

408‧‧‧Replaced area

LBA(0)~LBA(H)‧‧‧ logical address

DATA1, DATA2‧‧‧ data

P1, P2‧‧‧Information

SDATA1, SDATA2, SDATA3, SDATA4, SDATA5, SDATA6, SDAT7, SDATA8, SDATA9, SDATA10, SDATA11, SDATA12‧‧‧ sub-data strings

ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8, ECC9, ECC10, ECC11, ECC12‧‧‧ Error checking and correction code

S1601, S1603, S1605, S1607, S1609, S1611, S1613‧‧‧ steps of data writing method

FIG. 1 illustrates a host system and a memory storage device according to an exemplary embodiment.

2 is a schematic diagram of a computer, an input/output device, and a memory storage device according to an exemplary embodiment.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment.

FIG. 4 is a schematic block diagram of a memory storage device according to an embodiment of the present invention.

FIG. 5 is a schematic block diagram of a memory controller according to an exemplary embodiment.

FIG. 6 is a schematic diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the invention.

FIG. 7 is a schematic diagram of a layout of an entity stylizing unit in a physical erasing unit according to an exemplary embodiment of the invention.

8 and FIG. 9 are diagrams illustrating management of rewritable non-swings according to an exemplary embodiment. A schematic diagram of an example of a hair memory module.

10-12 are examples of writing data to a physical stylized unit according to an exemplary embodiment of the invention.

13-15 are another example of writing data to a physical stylization unit according to an exemplary embodiment of the invention.

FIG. 16 is a flow chart of data writing according to an exemplary embodiment.

In general, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and controller (also referred to as a control circuit). Typically, the memory storage device is used with a host system to enable the host system to write data to or read data from the memory storage device.

FIG. 1 illustrates a host system and a memory storage device according to an exemplary embodiment.

Referring to FIG. 1, the host system 1000 generally includes a computer 1100 and an input/output (I/O) device 1106. The computer 1100 includes a microprocessor 1102, a random access memory (RAM) 1104, a system bus 1108, and a data transmission interface 1110. The input/output device 1106 includes a mouse 1202, a keyboard 1204, a display 1206, and a printer 1252 as shown in FIG. It must be understood that the device shown in FIG. 2 is not limited to the input/output device 1106, and the input/output device 1106 may further include other devices.

In the embodiment of the present invention, the memory storage device 100 transmits data through The interface 1110 is coupled to other components of the host system 1000. The data can be written to or read from the memory storage device 100 by the operation of the microprocessor 1102, the random access memory 1104, and the input/output device 1106. For example, the memory storage device 100 may be a rewritable non-volatile memory storage device such as a flash drive 1212, a memory card 1214, or a solid state drive (SSD) 1216 as shown in FIG. 2.

In general, host system 1000 is any system that can substantially cooperate with memory storage device 100 to store data. Although in the present exemplary embodiment, the host system 1000 is illustrated by a computer system, in another exemplary embodiment of the present invention, the host system 1000 may be a digital camera, a video camera, a communication device, an audio player, or a video player. And other systems. For example, when the host system is a digital camera (camera) 1310, the rewritable non-volatile memory storage device uses the SD card 1312, the MMC card 1314, the memory stick 1316, the CF card 1318 or Embedded storage device 1320 (shown in Figure 3). The embedded storage device 1320 includes an embedded multimedia card (Embedded MMC, eMMC). It is worth mentioning that the embedded multimedia card is directly coupled to the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an embodiment of the present invention.

Referring to FIG. 4, the memory storage device 100 includes a connector 102, a memory controller 104, and a rewritable non-volatile memory module 106.

In the present exemplary embodiment, the connector 102 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must It is to be understood that the present invention is not limited thereto, and the connector 102 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, and the high-speed periphery. Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (USB) standard, Secure Digital (SD) interface standard, Ultra High Speed-I (UHS-) I) Interface standard, Ultra High Speed II (UHS-II) interface standard, Memory Stick (MS) interface standard, Multi Media Card (MMC) interface standard, intrusive Embedded Memory Card (eMMC) interface standard, Universal Flash Storage (UFS) interface standard, Compact Flash (CF) interface standard, Integrated drive electronics interface (Integrated Device Electronics, IDE) standard or other suitable standard.

The memory controller 104 is configured to execute a plurality of logic gates or control commands implemented in a hard type or a firmware type, and perform data in the rewritable non-volatile memory module 106 according to instructions of the host system 1000. Write, read, and erase operations.

The rewritable non-volatile memory module 106 is coupled to the memory controller 104 and is used to store data written by the host system 1000.

FIG. 5 is a schematic block diagram of a memory controller according to an exemplary embodiment. It should be understood that the structure of the memory controller shown in FIG. 5 is merely an example, and the present invention is not limited thereto.

Referring to FIG. 5, the memory controller 104 includes a memory management circuit 202, a host interface 204, a memory interface 206, a buffer memory 208, an error checking and correction circuit 210, and a parity information encoding and decoding circuit 212.

The memory management circuit 202 is used to control the overall operation of the memory controller 104. Specifically, the memory management circuit 202 has a plurality of control commands, and when the memory storage device 100 operates, such control commands are executed to perform operations such as writing, reading, and erasing data.

In the present exemplary embodiment, the control instructions of the memory management circuit 202 are implemented in a firmware version. For example, the memory management circuit 202 has a microprocessor unit (not shown) and a read-only memory (not shown), and such control instructions are programmed into the read-only memory. When the memory storage device 100 is in operation, such control commands are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment of the present invention, the control command of the memory management circuit 202 can also be stored in a specific area of the rewritable non-volatile memory module 106 (for example, the memory module is dedicated to storage). In the system area of the system data). In addition, the memory management circuit 202 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a drive code, and when the memory controller 104 is enabled, the microprocessor unit executes the drive code segment to store the rewritable non-volatile memory module 106. The control command is loaded into the random access memory of the memory management circuit 202. After that, the microprocessor unit will run these control commands to perform data writing, reading and erasing operations.

In addition, in another exemplary embodiment of the present invention, the control command of the memory management circuit 202 can also be implemented in a hardware format. For example, the memory management circuit 202 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is configured to manage the physical erasing unit of the rewritable non-volatile memory module 106; the memory writing circuit is configured to issue a write command to the rewritable non-volatile memory module 106. Writing data to the rewritable non-volatile memory module 106; the memory reading circuit for issuing read commands to the rewritable non-volatile memory module 106 for rewritable non-volatile memory The body module 106 reads the data; the memory erasing circuit is used to issue an erase command to the rewritable non-volatile memory module 106 to erase the data from the rewritable non-volatile memory module 106. The data processing circuit is configured to process data to be written to the rewritable non-volatile memory module 106 and data read from the rewritable non-volatile memory module 106.

The host interface 204 is coupled to the memory management circuit 202 and is configured to receive and identify instructions and data transmitted by the host system 1000. That is to say, the instructions and data transmitted by the host system 1000 are transmitted to the memory management circuit 202 through the host interface 204. In the present exemplary embodiment, host interface 204 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 204 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I interface standard, and the UHS-II interface standard. MS standard, MMC standard, eMMC interface standard, UFS interface standard, CF standard, IDE standard or other suitable data transmission standard.

The memory interface 206 is coupled to the memory management circuit 202 and is used to access the rewritable non-volatile memory module 106. That is, the data to be written to the rewritable non-volatile memory module 106 is converted to a format acceptable to the rewritable non-volatile memory module 106 via the memory interface 206.

The buffer memory 208 is coupled to the memory management circuit 202 and is used to temporarily store data and instructions from the host system 1000 or data from the rewritable non-volatile memory module 106.

The error checking and correction circuit 210 is coupled to the memory management circuit 202 and is used to perform error checking and correction procedures to ensure the correctness of the data. In the present exemplary embodiment, when the memory management circuit 202 receives a write command from the host system 1000, the error check and correction circuit 210 generates a corresponding error check and correction code (Error) for the data corresponding to the write command. Checking and Correcting Code (ECC Code), and the memory management circuit 202 writes the data corresponding to the write command and the corresponding error check and correction code into the rewritable non-volatile memory module 106. Then, when the memory management circuit 202 reads the data from the rewritable non-volatile memory module 106, the error check and correction code corresponding to the data is simultaneously read, and the error check and correction circuit 210 according to the error. Check and calibration code Perform error checking and calibration procedures on the data read. In particular, error checking and correction circuit 210 will be designed to correct a number of error bits (hereinafter referred to as the maximum number of correctable error bits). For example, the maximum number of correctable error bits is 24. If it is issued When the number of error bits generated by the read data is not more than 24, the error check and correction circuit 210 can correct the error bit back to the correct value based on the error check and the correction code. Conversely, the error checking and correction circuit 210 will report an error correction failure and the memory management circuit 202 will transmit a message indicating that the data has been lost to the host system 1000.

The collocation information encoding and decoding circuit 212 is coupled to the memory management circuit 202 and configured to temporarily store a plurality of data to be written to the plurality of physical stylizing units in the buffer memory 208 according to the indication of the memory management circuit 202 ( That is, the data that the host system 1000 wants to write) to generate the parity information. In addition, the parity information encoding and decoding circuit 212 can also decode the data stored in the plurality of entity stylizing units with the parity information according to the instruction of the memory management circuit 202 to correct the error data in the data. That is, if an error message occurs in the data on one of the entity stylized units of the entity stylized units, the parity information encoding and decoding circuit 212 can decode the entity stylized units according to the generated parity information. Information to correct the error data. Here, the co-located information generated by the parity information encoding and decoding circuit 212 may be a parity checking code, a channel coding, or the like. For example, a hamming code, a low density parity check code (LDPC code), a turbo code, or a Reed-solomon code (RS code). For example, if the ratio of the length of the data to the information of the same information is m:n, it means that the m-pen data will correspond to n pen-like information, where m and n are positive integers and the error data can be obtained if the number of data errors is less than n. Corrected by the same information. In general, a positive integer m will Greater than a positive integer n, but the invention is not limited thereto. Moreover, the present invention does not limit the values of the positive integer m and the positive integer n.

FIG. 6 is a schematic diagram of a rewritable non-volatile memory module 106 according to an exemplary embodiment of the invention.

The rewritable non-volatile memory module 106 includes a memory die 400. The memory die 400 includes a memory cell array 252, a control circuit 254, and a data input/output buffer 256.

Memory cell array 252 includes physical erase units 304(0)-304(R). Each physical erasing unit has at least one physical stylized unit, and the physical stylized units belonging to the same physical erasing unit can be independently written and erased simultaneously. For example, each physical erase unit is composed of 128 physical stylized units. However, it must be understood that the present invention is not limited thereto, and each physical erasing unit may also be composed of 64 physical stylized units, 256 physical stylized units, or any other physical stylized units.

In more detail, the physical erase unit is the smallest unit of erase. That is, each physical erase unit contains one of the smallest number of erased memory cells. The entity stylized unit is the smallest unit that is stylized. That is, the entity stylized unit is the smallest unit that writes data.

Specifically, NAND-type flash memory can be classified into single-level storage unit (SLC) NAND-type flash memory, multi-level storage unit (Multi Level) according to the number of bits that can be stored in each memory cell. Cell, MLC) NAND flash memory and Trinary Level Cell (TLC) NAND Flash memory, in which each memory cell of the SLC NAND flash memory can store 1 bit of data (ie, "1" and "0"), and each memory of the MLC NAND type flash memory The cell can store 2 bits of data and each memory cell of the TLC NAND type flash memory can store 3 bits of data.

In NAND-type flash memory, a physical stylized unit is composed of a plurality of memory cells arranged on the same word line. Since each memory cell of the SLC NAND type flash memory can store one bit of data, in the SLC NAND type flash memory, a plurality of memory cells arranged on the same word line correspond to one entity. Stylized unit.

Compared with the SLC NAND type flash memory, the floating gate storage layer of each memory cell of the MLC NAND type flash memory can store 2 bits of data, each of which is stored (ie, "11", "10", "01" and "00") include a Least Significant Bit (LSB) and a Most Significant Bit (MSB). For example, the value of the first bit from the left side in the storage state is the LSB, and the value of the second bit from the left side is the MSB. Therefore, a plurality of memory cells arranged on the same character line can form two physical stylized units, wherein the physical stylized units composed of the LSBs of the memory cells are referred to as lower physical stylized units, and thus The entity stylized unit composed of the MSB of the memory cell is called the upper entity stylized unit. In particular, the write speed of the lower stylized unit will be faster than the write speed of the upper stylized unit, and when the stylized upper stylized unit has an error, the data stored by the lower stylized unit may also Lost.

Similarly, in TLC NAND type flash memory, each memory cell can store 3 bits of data, each of which stores state (ie, "111", "110", "101", "100", "011", "010", "001" and "000") include the LSB of the first bit from the left and the intermediate significant bit of the second bit from the left (Center Significant Bit, CSB) ) and the MSB of the third bit from the left. Therefore, a plurality of memory cells arranged on the same character line can be composed into three physical stylized units, wherein the physical stylized unit composed of the LSBs of the memory cells is called a lower physical stylized unit, and thus the memory The entity stylized unit composed of the CSB of the cell is called the medium entity stylized unit, and the entity stylized unit composed of the MSBs of the memory cells is referred to as the upper entity stylized unit. Similarly, the lower entity stylized unit has higher stability than the middle entity stylized unit and the upper entity stylized unit, and the data is written to the lower physical stylized unit faster than the write data to the medium entity. The speed of the stylized unit and the upper stylized unit.

Each entity stylized unit typically includes a data bit area and a redundant bit area. The data bit area includes a plurality of physical access addresses for storing user data, and the redundant bit area is used to store system data (eg, control information and error correction codes). In this exemplary embodiment, each physical stylized unit has four physical access addresses in the data bit area, and one physical access address has a size of 512 bytes. However, in other exemplary embodiments, a greater or lesser number of physical access addresses may be included in the data bit area, and the present invention does not limit the size and number of physical access addresses. For example, in an exemplary embodiment, the physical erasing unit is The body block, and the entity stylized unit is a physical page or a physical sector, but the invention is not limited thereto.

In the exemplary embodiment, the rewritable non-volatile memory module 106 is a multi-level cell (MLC) inverse (NAND) type flash memory module. However, the present invention is not limited thereto, and the rewritable non-volatile memory module 106 may also be a single-level storage unit (SLC) NAND-type flash memory module, and a multi-level storage unit (Trinary Level Cell, TLC) NAND flash memory module, other flash memory modules or other memory modules with the same characteristics.

The control circuit 254 is configured to program data into or read data from the memory cell array 252 according to instructions from the memory controller 104.

The data input/output buffer 256 includes a first buffer 256a and a second buffer 256b. The first buffer 256a and the second buffer 256b are independent of each other and may have the same capacity, respectively. For example, the capacities of the first buffer 256a and the second buffer 256b are both the capacity of a physical stylized unit for temporarily storing data to be written to or read from the memory cell array 202. data.

The process of writing data in the rewritable non-volatile memory module 106 includes data transmission and data stylization. In the portion of the data transfer, the memory controller 104 (or the memory management circuit 202) transfers the page data to be written to the first buffer 256a, and thereafter, the page data to be written is moved to the second page. Buffer 256b. In the stylized portion of the data, the page data to be written is programmed from the second buffer 256b to the memory cell array 252. Especially when you want to write After the page data is moved from the first buffer 256a to the second buffer 256b, the memory controller 104 (or the memory management circuit 202) receives the completed write from the rewritable non-volatile memory module 106. The command confirmation message can be transmitted (or released) to the rewritable non-volatile memory module 106. Here, the first buffer 256a may also be referred to as a data cache area, and the second buffer 256b may also be referred to as a page buffer area, and is operated by the write operation of the second buffer 256b. It can be called a Cache Program operation.

It should be noted that, in an exemplary embodiment of the present invention, the memory controller 104 (or the memory management circuit 202) may also instruct the rewritable non-volatile memory module 106 to write without using the second buffer 256b. Enter the information. For example, in the example where the data input/output buffer 256 is not configured with the second buffer 256b or based on some factors without using the second buffer 256b, the rewritable non-volatile memory module 106 can also be based on the memory. The instructions of controller 104 (or memory management circuit 202) directly program the page data to be written from first buffer 256a into memory cell array 252. In this example, the memory management circuit 202 must wait until the rewritable non-volatile memory module 106 programs the page data from the first buffer 256a to the memory cell array 252 before receiving the write command. Confirmation message.

It must be understood that the present invention is not limited to the example of FIG. 6, and in another exemplary embodiment, the data input/output buffer 256 may also have only one buffer or more than two buffers.

FIG. 7 is a schematic diagram of a layout of an entity stylizing unit in a physical erasing unit according to an exemplary embodiment of the invention.

Referring to FIG. 7, the physical erasing unit of the MLC NAND flash memory is taken as an example for explanation and it is assumed that each physical erasing unit includes 256 physical stylizing units. The entity erasing unit 304(0) includes entity stylized units 701(0)-701(255). The entity stylization unit 701(0) is located on the same character line as the entity stylization unit 701(4), and the entity stylization unit 701(1) and the entity stylization unit 701(5) are on the same character line, and the entity program The unit 701(2) is located on the same character line as the entity stylization unit 701(8), and the entity stylization unit 701(3) is located on the same word line as the entity stylization unit 701(9), and the entity stylized unit 701 (6) is located on the same character line as the entity stylization unit 701 (12), and the entity stylization unit 701 (7) is located on the same word line as the entity stylization unit 701 (13), and the entity stylization unit 701 ( 10) On the same word line as the entity stylization unit 701 (16), the entity stylization unit 701 (11) is on the same word line as the entity stylization unit 701 (17), and so on. Here, the entity stylized units 701(0), 701(1), 701(2), 701(3), 701(6), 701(7), 710(10), 710(11), 701(14 ), 701 (15), ..., 701 (250) and 701 (251) belong to the lower entity program unit, and the entity stylized units 701 (4), 701 (5), 701 (8), 701 (9) 701 (12), 701 (13), 710 (16), 710 (17), ..., 701 (252), 701 (253), 701 (254), and 701 (255) belong to the upper physical program unit. It should be understood that the configuration shown in FIG. 7 is merely an example, and the present invention is not limited thereto.

FIG. 8 and FIG. 9 are schematic diagrams showing examples of managing a rewritable non-volatile memory module according to an exemplary embodiment.

It must be understood that the description of the rewritable non-volatile memory module is described herein. When the physical erase unit of 106 operates, it is a logical concept to operate the physical erase unit with words such as "extract", "swap", "group", and "rotation". That is to say, the actual position of the physical erasing unit of the rewritable non-volatile memory module is not changed, but the physical erasing unit of the rewritable non-volatile memory module is logically operated.

Referring to FIG. 8, the memory controller 104 (or the memory management circuit 202) logically groups the physical erasing units 304(0)-304(R) of the rewritable non-volatile memory module 106 into ( Or assigned to a data area 402, a spare area 404, a system area 406, and a replacement area 408.

The physical erasing unit logically belonging to the data area 402 and the spare area 404 is for storing data from the host system 1000. Specifically, the physical erasing unit (also referred to as a data entity erasing unit) of the data area 402 is a physical erasing unit that is regarded as stored data, and the physical erasing unit of the spare area 404 (also referred to as a standby entity) The erase unit is a physical erase unit for writing new data. For example, when receiving the write command and the data to be written from the host system 1000, the memory controller 104 (or the memory management circuit 202) extracts the physical erase unit from the spare area 404, and sorts out the write to be written. The data is written to the extracted physical erase unit.

The physical erasing unit logically belonging to the system area 406 is for recording system data, wherein the system data includes the manufacturer and model of the memory chip, the number of physical erasing units of the memory chip, and the physical erasing unit of each entity. Entity stylized Yuan, mapping table, etc. In particular, when the physical erasing unit is ready for writing system data, the memory controller 104 (or the memory management circuit 202) records a redundant bit area of the physical stylizing unit of the physical erasing unit. The system entity erases the unit tag to identify that the entity erase unit is a system entity erase unit that is used to store system data. It is worth mentioning that since the system data is quite important for the memory storage device 100, the rewritable non-volatile memory module 106 is an MLC NAND type flash memory module or TLC. In an exemplary embodiment of the NAND flash memory module, the memory controller 104 (or the memory management circuit 202) only uses the lower entity stylizing unit of the system entity erase unit to store system data to ensure data. Reliability.

The physical erase unit logically belonging to the replacement area 408 is an alternative physical erase unit. For example, the rewritable non-volatile memory module 106 will reserve 4% of the physical erasing unit for replacement when it leaves the factory. That is, when the physical erasing unit in the data area 402, the spare area 404, or the system area 406 is damaged, the physical erasing unit reserved in the replacement area 408 is used to replace the damaged physical erasing unit (ie, Bad entity bad block). Therefore, if the normal physical erasing unit still exists in the replacement area 408 and the physical erasing unit is damaged, the memory controller 104 (or the memory management circuit 202) extracts the normal physical erasing from the replacement area 408. Unit to replace the damaged physical erase unit. If there is no normal physical erasing unit in the replacement area 408 and the physical erasing unit is damaged, the memory controller 104 declares the entire memory storage device 100 as a write protect state, and cannot write again. Enter the information.

In particular, the number of physical erase units of data area 402, spare area 404, system area 406, and replacement area 408 may vary depending on different memory specifications. In addition, it must be understood that in the operation of the memory storage device 100, the grouping relationship associated with the physical erasing unit to the data area 402, the spare area 404, the system area 406, and the replacement area 408 may dynamically change. For example, when the physical erase unit in the spare area 404 is corrupted and replaced by the physical erase unit of the replacement area 408, the physical erase unit of the original replacement area 408 is associated with the spare area 404.

Referring to FIG. 9, as described above, the physical erasing unit of the data area 402 and the spare area 404 stores the data written by the host system 1000 in a rotating manner. In the present exemplary embodiment, the memory controller 104 (or the memory management circuit 202) configures the logical addresses LBA(0)~LBA(H) to the host system 1000 for accessing data. Each logical address is composed of several sectors. For example, in the present exemplary embodiment, each logical address is composed of 4 sectors. However, the present invention is not limited thereto. In another exemplary embodiment of the present invention, the logical address may also be composed of 8 sectors or 16 sectors. In the present exemplary embodiment, the size of one logical address is the same as the size of one physical stylized unit, and the number of physical stylized units of the physical erasing unit of the data area 402 and the spare area 404 is greater than the logical address. number.

For example, when the memory controller 104 (or the memory management circuit 202) starts to use the physical erasing unit 304(0) to store the data to be written by the host system 1000, regardless of the host system 1000 writing the logical address, The memory controller 104 (or the memory management circuit 202) writes the data to the physical process of the physical erasing unit 304(0). And when the memory controller 104 (or the memory management circuit 202) starts to use the physical erasing unit 304(1) to store the data to be written by the host system 1000, regardless of the host system 1000 writing the logic The address, memory controller 104 (or memory management circuit 202) will write the data to the entity stylizing unit of entity erase unit 304(1). That is, when writing the data to be written by the host system 1000, the memory controller 104 (or the memory management circuit 202) uses a physical stylizing unit in the physical erasing unit to write data, and when After the entity stylizing unit in the entity erasing unit is used, another physical erasing unit without storing data is selected, and the data is continuously written in the entity stylizing unit of the newly selected physical erasing unit.

In order to identify that each logical address is stored in that physical stylized unit, in the present exemplary embodiment, the memory controller 104 (or memory management circuit 202) records between the logical address and the physical stylized unit. Mapping relationship. Moreover, when the host system 1000 wants to access data in a sector, the memory controller 104 (or the memory management circuit 202) confirms the logical address to which the sector belongs, and the entity mapped in the logical address. Access the data in the stylized unit. For example, in the present exemplary embodiment, the memory controller 104 (or the memory management circuit 202) stores a logical address mapping table in the system area 406 of the rewritable non-volatile memory module 106 to record each The physical stylization unit to which the logical address is mapped, and when the data is to be accessed, the memory controller 104 (or the memory management circuit 202) loads the logical address mapping table into the buffer memory 208 for maintenance.

10 to 12 are written data according to an exemplary embodiment of the invention. An example of a physical stylized unit.

Referring to FIGS. 10-12, if a write command (hereinafter referred to as a first write command) and a data DATA1 to be written to the logical addresses LBA(0) to LBA(3) are received from the host system 1000, The memory controller 104 (or the memory management circuit 202) temporarily stores the data DATA1 to the buffer memory 208, and organizes the data DATA1 into the sub-data strings SDATA1, SDATA2, SDATA3, and SDATA4 according to the size of the physical stylized unit. Then, the memory controller 104 (or the error check and correction circuit 210) generates error check and correction codes ECC1, ECC2, ECC3, and ECC4 for SDATA1, SDATA2, SDATA3, and SDATA4, respectively. Thereafter, the memory controller 104 (or the memory management circuit 202) selects a physical erasing unit (eg, the entity stylizing unit 304(0)) and associates the substrings SDATA1, SDATA2, SDATA3, and SDATA4 with error checking. Correction codes ECC1, ECC2, ECC3, and ECC4 are respectively sequentially and sequentially programmed to the entity stylized units 701(0), 701(1), 701(2) and 701(3) of the entity stylized unit 304(0). . In particular, the memory controller 104 (or the parity information encoding and decoding circuit 212) generates the parity information P1 based on the sub-data strings SDATA1, SDATA2, SDATA3, and SDATA4. Then, the memory controller 104 (or the memory management circuit 202) temporarily stores the parity information P1 to the buffer memory 208 and deletes the sub-data strings SDATA1, SDATA2, SDATA3, and SDATA4 temporarily stored in the buffer memory 208. Specifically, since the entity stylized units 701(0), 701(1), 701(2), and 701(3) storing the sub-data strings SDATA1, SDATA2, SDATA3, and SDATA4 are all lower-organized units, and corresponding Lower physical stylized units 701(0), 701(1), 701(2) and 701(3) The entity stylization units 710(4), 710(5), 710(8), 710(9) have not yet been written to the material. Therefore, if the upper entity stylized units 710(4), 710(5), 710(8) corresponding to the lower entity stylized units 701(0), 701(1), 701(2) and 701(3) are subsequently followed. When 710(9) performs stylization and a stylization error occurs, the data stored in the lower entity stylized units 701(0), 701(1), 701(2), and 701(3) may be lost. Therefore, the parity information of the corresponding sub-data strings SDATA1, SDATA2, SDATA3 and SDATA4 is stored in the buffer memory 208 instead of the completed temporary data substrings SDATA1, SDATA2, SDATA3 and SDATA4, which can reduce the required buffer memory. Under the space of 208, the effect of protecting data is achieved.

13-15 are another example of writing data to a physical stylization unit according to an exemplary embodiment of the invention.

Please refer to FIG. 13~15, and continue to FIG. 10~12, if another write command (hereinafter referred to as a second write command) is received from the host system 1000 and is to be written to the logical address LBA(4)~LBA. When the data DATA2 of (11) is DATA2, the memory controller 104 (or the memory management circuit 202) temporarily stores the data to the buffer memory 208, and organizes the data DATA2 into the sub-data strings SDATA5 and SDATA6 according to the size of the physical stylized unit. , SDATA7, SDATA8, SDATA9, SDATA10, SDATA11 and SDATA12. Then, the memory controller 104 (or the error checking and correction circuit 210) generates error checking and correction codes ECC5, ECC6, ECC7 for the sub-data strings SDATA5, SDATA6, SDATA7, SDATA8, SDATA9, SDATA10, SDATA11 and SDATA12, respectively. ECC8, ECC9, ECC10, ECC11 and ECC12. After that, the memory controller 104 (or the memory management circuit 202) will substring the data. SDATA5, SDATA6, SDATA7, SDATA8, SDATA9, SDATA10, SDATA11 and SDATA12, and error checking and correction codes ECC5, ECC6, ECC7, ECC8, ECC9, ECC10, ECC11 and ECC12 are sequentially and sequentially programmed to the physical stylization unit 304 ( Entity stylized units 701 (4), 701 (5), 701 (6), 701 (7), 701 (8), 701 (9), 701 (10), and 701 (11). In particular, the memory controller 104 (or the parity information encoding and decoding circuit 212) generates the parity information P2 based on the sub-data strings SDATA7, SDATA8, SDATA11, and SDATA12. Then, the memory controller 104 (or the memory management circuit 202) temporarily stores the parity information P2 to the buffer memory 208 and deletes the sub-data strings SDATA5, SDATA6, SDATA7, SDATA8, SDATA9 temporarily stored in the buffer memory 208, SDATA10, SDATA11 and SDATA12. Specifically, since the entity stylized units 701 (6), 701 (7), 701 (10), and 701 (11) storing the sub-data strings SDATA7, SDATA8, SDATA11, and SDATA12 are all lower-organized units, and corresponding The upper entity stylized units 710(12), 710(13), 710(16), 710(17) of the lower entity stylized units 701(6), 701(7), 701(10) and 701(11) have not yet Was written to the data. Therefore, if the upper body stylized units 710 (12), 710 (13), 710 (16), 710 (17) are subsequently programmed and a stylized error occurs, the lower body stylized unit 701 (6) is stored. Information on 701(7), 701(10) and 701(11) may be lost. Therefore, the parity information of the corresponding sub-data strings SDATA7, SDATA8, SDATA11 and SDATA12 is stored in the buffer memory 208 instead of the completed temporary data substrings SDATA7, SDATA8, SDATA11 and SDATA12, which can reduce the required buffer memory. Under the space of 208, the effect of protecting data is achieved.

In another exemplary embodiment of the present invention, the memory controller 104 (or the memory management circuit 202) confirms whether the previously stored sub-data strings SDATA1, SDATA2, SDATA3, and SDATA4 are correct and are previously stored. When the data strings SDATA1, SDATA2, SDATA3, and SDATA4 are correct, the parity information P1 is deleted from the buffer memory 208. In addition, in another exemplary embodiment, the memory controller 104 (or the memory management circuit 202) may also delete the parity information P1 when the buffer memory 208 has insufficient space.

In the examples of FIGS. 13-15, the program occurs if the substring SDATA5, SDATA6, SDATA9 or SDATA10 is programmed into the stylized unit stylization unit 701(4), 701(5), 701(8) or 701(9). When the error occurs and the error data is caused by the substring SDATA1, SDATA2, SDATA3 or SDATA4, the memory controller 104 (or the memory management circuit 202) is stored in the entity stylizing unit 701(0) according to the parity information P1, The sub-data strings of 701(1), 701(2), and 701(3) are used to correct the error data (sub-string SDATA1, SDATA2, SDATA3, or SDATA4). As for the sub-data string SDATA5, SDATA6, SDATA9 or SDATA10 in which the stylization error has occurred, the buffer memory 208 still retains these sub-data strings without being lost.

It is worth mentioning that, in the present exemplary embodiment, the memory controller 104 (or the memory management circuit 202) recognizes which of the upper physical stylized units corresponding to the lower body stylization of the data has been written. It is programmed, and the memory controller 104 (or the co-located information encoding and decoding circuit 212) generates co-located information for the sub-data strings on the identified underlying stylized unit, but the invention is not limited thereto. E.g, In another exemplary embodiment of the present invention, the memory controller 104 (or the parity information encoding and decoding circuit 212) may also generate the parity information for all the sub-data strings to be written by the write command. For another example, in another exemplary embodiment of the present invention, the memory controller 104 (or the parity information encoding and decoding circuit 212) may also write the sub-data according to the previous time each time a sub-data is written to the physical stylizing unit. The previous parity information generated by the physical stylized unit and the currently written sub-data are used to generate new parity information.

FIG. 16 is a flow chart of data writing according to an exemplary embodiment.

Referring to FIG. 16, in step S1601, the memory controller 104 (or the memory management circuit 202) receives the write command and the corresponding data from the host system 1000.

In step S1603, the memory controller 104 (or the memory management circuit 202) temporarily stores the data to the buffer memory 208 and organizes the data into a plurality of sub-data strings.

In step S1605, the memory controller 104 (or the memory management circuit 202) selects at least one physical erasing unit (hereinafter referred to as a first physical erasing unit) and writes the sub-data string to the first entity erasing. The unit's entity is stylized in the unit. Specifically, the memory controller 104 (or the error checking and correction circuit 210) generates a corresponding error check and correction code for each sub-data string, and the memory controller 104 (or the memory management circuit 202) will The data string and the corresponding error check and correction code are written to the corresponding entity stylized unit.

In step S1607, the memory controller 104 (or the memory management circuit 202) determines the entity stylized list for writing the sub-data string to the first physical erasing unit. Whether a stylized error occurred during the meta process.

If no stylization error has occurred, in step S1609, the memory controller 104 (or the parity information encoding and decoding circuit 212) generates the parity information based on at least a portion of the sub-data strings of the sub-data strings. For example, as described above, the memory controller 104 (or the memory management circuit 202) identifies the corresponding upper stylized unit of the lower physical stylized unit storing the sub-data strings (hereinafter referred to as the first upper The entity stylized unit is a lower entity stylized unit (hereinafter referred to as a first lower entity stylized unit) that does not store data, and generates the parity information according to the sub-data string written to the first lower entity stylized unit.

In step S1611, the memory controller 104 (or the memory management circuit 202) stores the generated parity information in the buffer memory 208, and deletes the sub-data strings from the buffer memory 208. In particular, if the buffer memory 208 stores the parity information stored in the previous write command, the memory controller 104 (or the memory management circuit 202) shifts the old parity information in step S1611. except.

If a stylization error occurs, in step S1613, the memory controller 104 (or the parity information encoding and decoding circuit 212) decodes the sub-data string written by the previous write command according to the parity information in the buffer memory 208. At least some of them are used to correct the error data. Thereafter, the memory controller 104 (or the memory management circuit 202) can be reprogrammed.

In summary, the data writing method of the exemplary embodiment of the present invention uses the memory controller of the data writing method to effectively use the storage space of the buffer memory to execute the write command while avoiding data loss. Also, use this data to write The method memory storage device can smoothly execute a write command under a buffer memory configured with a small capacity while avoiding data loss.

S1601, S1603, S1605, S1607, S1609, S1611, S1613‧‧‧ steps of data writing method

Claims (24)

A data writing method for writing data to a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has at least one memory die, the at least one memory crystal The granule includes a plurality of physical erasing units, each of the physical erasing units includes a plurality of physical stylizing units, and the data writing method includes: receiving a first writing instruction and a corresponding writing instruction from a host system And a first data is temporarily stored in a buffer memory, wherein the first data includes a plurality of sub-data strings; and the sub-data strings are transmitted from the buffer memory to the rewritable non- The volatile memory module writes the sub-data strings to at least one of the first physical erasing units of the physical erasing units; and generates the same according to at least a part of the sub-data strings of the sub-data strings Bit information; and storing the parity information in the buffer memory and removing the first data from the buffer memory. The method for writing data according to claim 1, wherein the step of generating the information according to the at least a part of the sub-data strings of the sub-data strings comprises: according to all the sub-data strings Generate this information. The method for writing data according to claim 1, wherein each of the entity staging units of the physical erasing unit comprises a plurality of lower stylized units and a plurality of upper stylized units, and the data is written to The speed of the lower entity stylized unit The step of generating the information according to the at least a part of the sub-data strings among the sub-data strings is faster than writing the data to the upper physical stylization unit, and the step of generating the information according to the at least a part of the sub-data strings includes: The stylizing unit identifies at least one first sub-data string among the sub-data strings, wherein the at least one first sub-data string is stylized by at least one first lower entity stored in the lower physical stylized units And storing, by the unit, at least one of the first upper physical stylized units of the at least one first lower physical stylized unit; and generating the parity information according to the at least one first substring. The method for writing data according to claim 1, further comprising: receiving the same information in the buffer memory and removing the first data from the buffer memory, and receiving from the host system a second write command and a second data corresponding to the second write command. The data writing method of claim 4, further comprising: determining whether a stylized error occurs when the second data is written into the at least one first physical erasing unit from the buffer memory. And if the stylized error occurs when the second data is written into the at least one first physical erasing unit from the buffer memory, the isomorphic information stored in the buffer memory is decoded and stored in The at least one first sub-data string of the at least one first physical erasing unit corrects at least one erroneous sub-data string in the at least one partial sub-data string. For example, the method for writing data as described in item 5 of the patent application scope includes: And if the stylization error does not occur when the second data is written into the at least one first physical erasing unit from the buffer memory, the parity information is removed from the buffer memory. The method for writing data according to claim 4, further comprising: generating another parity information according to at least a portion of the second data; and storing the other parity information in the buffer memory and deleting The second information. The data writing method of claim 1, wherein the sub-data strings are transmitted from the buffer memory to the rewritable non-volatile memory module to write the sub-data strings to The step of the at least one first physical erasing unit among the physical erasing units includes: generating a plurality of error checking and correcting codes for the sub-data strings respectively; and separately separating the sub-data strings The error checking and correction codes corresponding to the sub-strings are transmitted to the rewritable non-volatile memory module to write the sub-strings and the error checking corresponding to the sub-strings respectively The correction code is in the physical stylized unit of the at least one first physical erasing unit. The method for writing data according to claim 1, wherein the step of generating the information according to the at least a part of the sub-data strings of the sub-data strings comprises: When one of the sub-data strings is written to the at least one first entity erasing unit, the co-located information is generated according to the one of the sub-data strings and a previous parity information. A memory controller for controlling a rewritable non-volatile memory module, the memory controller comprising: a host interface for coupling to a host system; a memory interface for coupling To the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has at least one memory die, the at least one memory die comprising a plurality of physical erase units, each The physical erasing unit includes a plurality of physical stylizing units; a buffer memory; a co-located information encoding and decoding circuit; and a memory management circuit coupled to the host interface, the memory interface, and the buffer memory And the parity information encoding and decoding circuit, wherein the memory management circuit is configured to receive a first write command and a first data corresponding to the write command from the host system and temporarily store the first data to a In the buffer memory, the first data includes a plurality of sub-data strings, wherein the memory management circuit is further configured to transfer the sub-data strings from the buffer memory to the rewritable non-swing The cryptographic memory module is configured to write the sub-data strings to at least one of the first physical erasing units, wherein the collocation information encoding and decoding circuit is configured to use the sub-data strings At least a portion of the sub-data strings are generated to generate a parity information, wherein the memory management circuit is further configured to store the parity information in the buffer memory and remove the first data from the buffer memory. The memory controller according to claim 10, wherein the root controller is The peer information encoding and decoding circuit generates the parity information according to all of the sub-data strings according to the at least a part of the sub-data strings in the sub-data strings to generate the information. The memory controller of claim 10, wherein the physical stylized unit of each of the physical erasing units comprises a plurality of lower physical stylized units and a plurality of upper physical stylized units, and the data is written to The lower physical stylizing units are faster than writing data to the upper physical stylizing units, wherein the memory is generated in the operation of generating the co-located information according to the at least a portion of the sub-strings among the sub-strings The body management circuit identifies at least one first sub-data string among the sub-data strings according to the entity stylizing unit storing the sub-data strings, and the information-based encoding and decoding circuit generates the first sub-data string according to the at least one first sub-data string The same information, wherein the at least one first substring is stored in at least one first lower entity stylizing unit among the lower entity stylizing units and corresponds to at least one of the first lower entity stylizing units An entity stylized unit does not store data. The memory controller of claim 10, wherein the memory management path is further configured to store the parity information in the buffer memory and remove the first data from the buffer memory. Receiving a second write command from the host system and a second data corresponding to the second write command. The memory controller of claim 13, wherein the memory management circuit generates another parity information according to the at least part of the second data and stores the other parity information in the buffer memory. And delete The second information. The memory controller of claim 10, wherein in the operation of generating the parity information according to the at least a part of the sub-data strings among the sub-data strings, each of the sub-data strings is When one of the sub-data strings is written to the at least one first entity erasing unit, the co-located information encoding and decoding circuit generates the co-located information according to the one of the sub-data strings and a previous parity information. A memory storage device includes: a connector for coupling to a host system; a rewritable non-volatile memory module having at least one memory die, the at least one memory die including Physical erasing units, each of the physical erasing units comprising a plurality of physical stylizing units; and a memory controller having a buffer memory coupled to the connector and the rewritable non-volatile memory a memory module, wherein the memory controller is configured to receive a write command and a first data corresponding to the write command from the host system and temporarily store the first data in a buffer memory, wherein the first module The data includes a plurality of sub-data strings, wherein the memory controller is further configured to transfer the sub-data strings from the buffer memory to the rewritable non-volatile memory module to write the sub-data strings And at least one first physical erasing unit of the plurality of physical erasing units, wherein the memory controller is configured to generate a parity information according to at least a part of the sub-data strings of the sub-data strings, wherein the The controller is further configured to, memory and parity information stored in the buffer memory The first data is removed from the buffer memory. The memory storage device of claim 16, wherein in the operation of generating the parity information according to the at least a portion of the sub-data strings among the sub-data strings, the memory controller is based on all of the The sub-data string is used to generate the co-located information. The memory storage device of claim 16, wherein the physical stylization unit of each of the physical erasing units comprises a plurality of lower physical stylized units and a plurality of upper physical stylized units, and the data is written to The lower physical stylizing units are faster than writing data to the upper physical stylizing units, wherein the memory is generated in the operation of generating the co-located information according to the at least a portion of the sub-strings among the sub-strings The body controller identifies at least one first sub-data string among the sub-data strings according to the entity stylizing unit storing the sub-data strings, and the memory controller generates the parity information according to the at least one first sub-data string The at least one first sub-data string is stored in at least one first lower physical stylized unit of the lower physical stylized units and corresponds to at least one first of the at least one first lower physical stylized unit The stylized unit does not store data. The memory storage device of claim 16, wherein the memory controller is further configured to store the parity information in the buffer memory and remove the first data from the buffer memory. Receiving a second write command from the host system and a second data corresponding to the second write command. The memory storage device of claim 19, wherein the memory controller is further configured to determine the second from the buffer memory Whether a stylized error occurs when the data is written into the at least one first physical erasing unit, wherein the second data is written into the at least one first physical erasing unit from the buffer memory In the stylized error, the memory controller uses the parity information stored in the buffer memory to decode the at least a portion of the sub-data strings stored in the at least one first physical erasing unit to correct the at least one sub-segment At least one error substring in the data string. The memory storage device of claim 20, wherein if the stylization error does not occur when the second data is written into the at least one first physical erasing unit from the buffer memory, The memory controller is further configured to remove the parity information from the buffer memory. The memory storage device of claim 19, wherein the memory controller generates another parity information according to the at least part of the second data and stores the other parity information in the buffer memory. And delete the second data. The memory storage device of claim 16, wherein the memory controller is further configured to generate a plurality of error checking and correction codes for the sub-data strings respectively, wherein the buffer memory is Transmitting the sub-data strings to the rewritable non-volatile memory module to write the sub-data strings into the operation of the at least one first physical erasing unit among the physical erasing units, The memory controller checks and corrects the sub-data strings and the corresponding errors corresponding to the sub-data strings respectively. Transmitting to the rewritable non-volatile memory module to write the sub-data strings and respectively corresponding to the error checking and correction codes of the sub-data strings to the at least one first physical erasing unit In the entity stylized unit. The memory storage device of claim 16, wherein in the operation of generating the parity information according to the at least a portion of the sub-data strings among the sub-data strings, each of the sub-data strings is When one of the sub-data strings is written to the at least one first physical erasing unit, the memory controller generates the co-located information according to the one of the sub-data strings and a previous parity information.