JP2012243332A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device able to improve the reliability of data at low cost.SOLUTION: For example, in a semiconductor device with a complementary memory, a parity bit is created with respect to positive polarity (Posi) data of (N+1) bits and a parity bit is created with respect to negative polarity (Nega) data of (N+1) bits during writing. During reading, parity check is carried out for the positive polarity side and the negative polarity side and also the positive polarity data and negative polarity data are compared for each bit number. Here, in the case where a bit number in which the positive polarity data and negative polarity data are the same is present, this bit number of the positive polarity data is specified as erroneous data if the positive polarity side parity check results to be abnormal, and this bit number of negative polarity data can be specified as erroneous data conversely when the negate polarity side parity check results to be abnormal.

Description

  The present invention relates to a semiconductor device including a memory unit, and more particularly to a technique effective when applied to a semiconductor device including a memory unit storing one bit with two storage elements.

  For example, Patent Document 1 discloses a technique in which verify read and normal read are performed using the same sense amplifier in a semiconductor nonvolatile memory in which complementary data is written in two memory cells. Patent Document 2 discloses a technique for detecting at high speed whether a plurality of twin cells are in a write state or a blank state in a semiconductor nonvolatile memory in which complementary data is written in two memory cells (twin cells).

JP 2009-252290 A JP 2009-272028 A

  For example, a microcomputer (so-called microcomputer) or the like may be equipped with a flash memory or the like instead of a conventional EEPROM (Electrically Erasable Programmable Read Only Memory) for data storage. In the flash memory, the threshold voltage (charge of the floating gate) serving as storage information of the memory cell gradually varies with time. A period during which the threshold voltage can be maintained in a normal range is called data retention. When the flash memory is used as a data storage area of a microcomputer or the like, many rewrite operations can occur, but data retention tends to deteriorate particularly when the number of rewrites increases. Therefore, in order to ensure data retention characteristics (data retention) even when the number of rewrites is large, it is beneficial to use a nonvolatile complementary memory as shown in Patent Document 1 or Patent Document 2. In the complementary memory, a 2-bit storage area is used to store 1-bit data, positive data is stored in one of the storage areas, and negative data is stored in the other. During the read operation, the data retention characteristic (data reliability) can be improved to some extent by using the difference between the positive electrode data and the negative electrode data.

  In recent years, microcomputers incorporating such a nonvolatile complementary memory are likely to be accessed (rewritten or read out) in units of small areas (for example, several bytes, several words, etc.) in accordance with various usage environments. It is becoming. For this reason, further improvement in the reliability of data is desired. In order to improve the reliability of data, it is conceivable to use techniques such as error detection and error correction, for example. As a representative of such a technique, it is known to add a Hamming code (ECC (Error Checking and Correction) code) to data. However, in this case, the area overhead associated with the addition of a Hamming code storage area and the addition of an arithmetic circuit for error detection / correction is large, and there is a possibility that the microcomputer and the like cannot be reduced in size and cost.

In particular, the problem of area overhead becomes more prominent as the access unit becomes smaller. The Hamming code has 2 ⁿ −1 bits, where n is the number of bits for inspection. That is, the number of original data bits is 2 ⁿ −1−n. For example, it is necessary to add a 7-bit Hamming code to data having an access unit of 8 bytes (64 bits), and it is necessary to secure 71/64 times (about 1.1 times) as a storage area. Become. In addition, it is necessary to add a 5-bit Hamming code to data having an access unit of 2 bytes (16 bits), and it is necessary to secure 21/16 times (about 1.3 times) as a storage area. Become.

  The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device (or a storage device) capable of improving data reliability at a low cost. . The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.

  The semiconductor device according to the present embodiment includes N (N ≧ 1) first storage nodes, N second storage nodes, a parity generation circuit, first and second parity storage nodes, and an error processing circuit. With. N-bit first data is written to the first storage node, and second data that is inverted data of the first data is written to the second storage node. The parity generation circuit generates first parity data for the data as the first data is written, and generates second parity data for the data as the second data is written. First and second parity data are written to the first and second parity storage nodes, respectively. The error processing circuit executes the first to fifth processes during the read operation. In the first process, a match / mismatch between the N-bit first read data from the first storage node and the N-bit second read data from the second storage node is determined for each bit number. In the second process, parity determination is performed using the first read data and the first parity data, and in the third process, parity determination is performed using the second read data and the second parity data. In the fourth process, if there is one matching bit number in the first process and the determination result of the second process / third process is abnormal / normal, the bit number in the first read data of N bits is incorrect. It is determined. In the fourth process, when there is one bit number that matches in the first process and the determination result of the third process / second process is abnormal / normal, the bit in the second read data of N bits The number is determined to be incorrect. In the fifth process, the bit determined to be an error in the fourth process is corrected.

  By using such a semiconductor device, the reliability of data can be improved, and the overhead of the circuit area associated with error correction can be reduced compared to the case where error correction is performed using, for example, a Hamming code. This can be suppressed and cost reduction can be achieved. More preferably, each of the first and second parity storage nodes may be constituted by a storage node of complementary bits (2 bits). As a result, the reliability of the data can be further improved. Further, it is desirable that the read operation from the first storage node and the read operation from the second storage node are performed in parallel using individual sense amplifier circuits or the like. As a result, the error processing operation (reading operation) can be speeded up.

  The effects obtained by typical embodiments of the invention disclosed in this application will be briefly described. In a semiconductor device (or a storage device) including a memory unit, data reliability is improved at low cost. It becomes possible.

1 is a schematic diagram illustrating a configuration example of a memory unit included in a semiconductor device (storage device) according to a first embodiment of the present invention. It is explanatory drawing which shows the operation example of the parity generation circuit in FIG. It is a flowchart which shows the operation example of the error processing circuit block in FIG. (A)-(e) is explanatory drawing which shows an example of a different specific process result at the time of using the operation example of FIG. 2 and FIG. (A)-(e) is explanatory drawing which shows the modification of FIG. 4 (a)-(e). In the semiconductor device by Embodiment 2 of this invention, it is a block diagram which shows an example of the whole structure. FIG. 7 is a circuit block diagram illustrating a schematic configuration example of a flash memory for storing data in the semiconductor device of FIG. 6. FIG. 8 shows details of each memory cell in FIG. 7, (a) is a circuit diagram showing a detailed configuration example of each memory cell, (b) is an explanatory diagram showing examples of various operating conditions in (a), (c) is explanatory drawing which shows an example of the threshold value state of each memory cell accompanying the operation | movement of (b). FIG. 8 is a schematic diagram illustrating a layout configuration example of a memory mat in the flash memory of FIG. 7. FIG. 10 is a circuit diagram illustrating a schematic configuration example around each sense amplifier circuit block in FIGS. 7 and 9. FIG. 11 is a circuit diagram illustrating a schematic configuration example around each sense amplifier circuit block obtained by modifying FIG. 10. (A) is a circuit diagram showing a detailed configuration example of the parity generation circuit in FIG. 7, (b) is a truth table showing an operation example of the addition circuit in (a). FIG. 8 is a truth table showing a detailed operation example of the error processing circuit block in FIG. 7. FIG. FIG. 8 is a circuit diagram illustrating a detailed configuration example of an error processing circuit block in FIG. 7. In the semiconductor device (memory | storage device) by Embodiment 3 of this invention, it is the schematic which shows the structural example of the memory unit contained in it. FIG. 16 is a flowchart showing a main operation example of the error processing circuit block in FIG. 15. In the semiconductor device (memory | storage device) by Embodiment 4 of this invention, it is the schematic which shows the structural example of the memory unit contained in it. FIG. 18 is a flowchart showing an operation example of the error processing circuit block in FIG. 17. (A)-(e) is explanatory drawing which shows an example of a different specific process result at the time of using the operation example of FIG.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). . In the embodiment, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (abbreviated as a MOS transistor) is used as an example of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), but a non-oxide film is not excluded as a gate insulating film. Absent.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
<< Schematic Configuration and Operation of Memory Unit [1] >>
FIG. 1 is a schematic diagram showing a configuration example of a memory unit included in a semiconductor device (storage device) according to Embodiment 1 of the present invention. The memory unit shown in FIG. 1 includes memory areas MEM1 and MEM2, parity generation circuits PRTYG1 and PRTYG2, parity storage nodes SN1p and SN2p, and an error processing circuit block ERCBK1. MEM1 includes (N + 1) -bit storage nodes SN1 [0] to SN1 [N], and MEM2 includes (N + 1) -bit storage nodes SN2 [0] to SN2 [N].

  Here, MEM1 and MEM2 are complementary memories having MEM1 as positive electrode (Posi) data and MEM2 as negative electrode (Nega) data. Here, SN1p is composed of complementary bits (2 bits) composed of storage nodes SN1pp and SN1pn, and SN2p is composed of complementary bits composed of storage nodes SN2pp and SN2pn. Each of SN1p and SN2p can be configured with 1 bit depending on circumstances, but in order to increase the reliability of the parity bit, it is configured with complementary bits (2 bits) from which a large read signal can be obtained by the difference. Is preferable.

  During the write operation, SN1 [0] to SN1 [N] of MEM1 are respectively connected to (N + 1) -bit data input signals DI [0] to DI [N] (DI [0: N] without distinction for convenience). May be written, and the same applies to other codes). Further, inverted data input signals (/ DI [0] to / DI [N]) of DI [0] to DI [N] are stored in SN2 [0] to SN2 [N] of MEM2, respectively. PRTYG1 calculates the value of the parity bit for DI [0] to DI [N] and writes the value to SN1p. PRTYG2 calculates the value of the parity bit for / DI [0] to / DI [N] and writes the value to SN2p.

  On the other hand, during the read operation, the stored data of SN1 [0] to SN1 [N] of MEM1 is read as pre-data signals PREDATp [0] to PREDATp [N], and SN2 [0] to SN2 [N] of MEM2 Stored data is read as pre-data signals PREDATn [0] to PREDATn [N]. ERCBK1 performs error detection and error correction using these pre-data signals and signals (parity bits) read from SN1p and SN2p, and (N + 1) -bit data output signal DO [0] after error correction. ~ DO [N] is output.

<< Error handling operation [1] >>
FIG. 2 is an explanatory diagram showing an operation example of the parity generation circuit in FIG. As shown in FIG. 2, the parity generation circuit PRTYG1 targets (N + 1) bits of positive polarity (Posi) data (DI [0] to DI [N]) in the (N + 1) bits and the parity bit (SN1p). The parity bit value is determined such that the total number of included “1” information is an odd number. That is, when the total number of “1” information included in the (N + 1) bits is an odd number, “0” information is written into SN1p, and the total number of “1” information included in the (N + 1) bits. If the number is even, "1" information is written into SN1p.

  Similarly, the parity generation circuit PRTYG2 includes (N + 1) bits of negative (Nega) data (/ DI [0] to / DI [N]) in the (N + 1) bits and the parity bit (SN2p). The parity bit value is determined such that the total number of “1” information is an odd number. In this way, in the example of FIG. 2, SN1p on the positive electrode side is set to “0”, and SN2p on the negative electrode side is set to “1”. Such a parity method is called odd parity. However, it goes without saying that not only odd parity but also even parity in which the total number of “1” information is even-numbered can be used.

  FIG. 3 is a flowchart showing an operation example of the error processing circuit block in FIG. As shown in FIG. 3, first, the error processing circuit block ERCBK1 includes a pre-data signal (PREDATp [0] to PREDATp [N] in FIG. 1) that is a single data string for positive polarity (Posi) and a parity for positive polarity. A bit (information of SN1p in FIG. 1) is read and a parity check is performed (S101). Here, the case where the parity check result (Parity Check P) is normal (that is, PREDATp [0: N], the number of “1” information in SN1p is an odd number) is expressed as “Parity Check P = 0”. A case where there is an abnormality (the number of “1” information is an even number) is expressed as “Parity Check P = 1”.

  Next, ERCBK1 reads a pre-data signal (PREDATn [0] to PREDATn [N] in FIG. 1) that is a single data string for the negative electrode (Nega), and a parity bit for the negative electrode (information of SN2p in FIG. 1). Parity check is performed (S102). Here, a case where the parity check result (Parity Check N) is normal (that is, PREDATn [0: N], the number of “1” information in SN2p is an odd number) is expressed as “Parity Check N = 0”. A case where there is an abnormality (the number of “1” information is an even number) is expressed as “Parity Check N = 1”. Note that S101 and S102 are characterized in that the positive data string and the negative data string are each independently read as a single data string. In other words, in a normal complementary memory, the positive data string and the negative data string are inseparably read as a differential pair, and only the positive data or only the negative data is read alone. Is not usually done.

  Subsequently, the ERCBK1 determines whether the positive pre-data signal (PREDATp [0] to PREDATp [N]) matches the negative pre-data signal (PREDATn [0] to PREDATn [N]) for each bit. Determine (S103). If all the bits do not match, it is determined that there is no error since complementary data is stored normally (S109). On the other hand, if there is a matching bit, ERCBK1 determines whether the parity check result (Parity Check P) in S101 is abnormal (“1”) or normal (“0”) (S104). If abnormal, ERCBK1 determines that the bit matched in S103 in the positive pre-data signal is erroneous data (S106), and corrects the bit (S110).

  In addition, when the parity check result (Parity Check P) in S104 is normal (“0”), ERCBK1 determines whether the parity check result (Parity Check N) in S102 is abnormal (“1”) or normal (“1”). 0 ") is determined (S105). If abnormal, ERCBK1 determines that the bit matched in S103 in the negative pre-data signal is erroneous data (S107), and corrects the bit (S110). On the other hand, if the result of S105 is normal, ERCBK1 determines that there is an error but correction is not possible (S108). In S106, S107, and S110, it is assumed that the bit matched in S103 is 1 bit. In the case of a plurality of bits, it is determined that correction is impossible although an error exists as in S108.

  FIGS. 4A to 4E are explanatory diagrams illustrating examples of specific processing results different from each other when the operation examples of FIGS. 2 and 3 are used. First, FIG. 4A shows an error-free state corresponding to S109 in FIG. Here, each bit in the positive data (PREDATp [0] to PREDATp [N]) and the negative data (PREDATn [0] to PREDATn [N]) is complementary data, and the parity check result for the positive data and the negative data Both are normal.

  FIG. 4B shows a state in which one bit in the positive polarity data has changed from “0” to “1”, corresponding to S106 in FIG. Here, the [0] bit in the positive and negative data is not complementary data, and the parity check result for the positive data is abnormal. Therefore, it can be determined that the [0] bit of the positive polarity data is erroneous data, and error correction can be realized by inverting the data. FIG. 4C shows a state in which one bit in the positive polarity data has changed from “1” to “0”, corresponding to S106 in FIG. Here, the [1] -th bit in the positive and negative data is not complementary data, and the parity check result for the positive data is abnormal. Therefore, it can be determined that the [1] -th bit of the positive electrode data is erroneous data, and error correction can be realized by inverting the data.

  FIG. 4D shows a state in which one bit in the negative electrode data has changed from “1” to “0”, corresponding to S107 in FIG. Here, the [0] -th bit in the positive and negative data is not complementary data, and the parity check result for the negative data is abnormal. Therefore, it can be determined that the [0] bit of the negative electrode data is erroneous data, and error correction can be realized by inverting the data. FIG. 4E shows a state in which one bit in the negative electrode data is changed from “0” to “1” corresponding to S107 in FIG. Here, the [1] -th bit in the positive data and the negative data is not complementary data, and the parity check result for the negative data is abnormal. Therefore, it can be determined that the [1] -th bit of the negative electrode data is erroneous data, and error correction can be realized by inverting the data.

  FIG. 5A to FIG. 5E are explanatory diagrams showing modifications of FIG. 4A to FIG. 5A to 5E, compared to FIGS. 4A to 4E, the value of the parity bit for the positive data and the value of the parity bit for the negative data are the same value. Is different. Except for this point, the processing results shown in FIGS. 5A to 5E are the same as those in FIGS. 4A to 4E.

  Here, in the operation example of FIG. 2 described above, when the number of data bits (N + 1) is an odd number, as shown in FIG. 2 and FIGS. As a result, different values are written on the positive electrode side and the negative electrode side. On the other hand, in the operation example of FIG. 2 described above, when the number of data bits (N + 1) is an even number, as shown in FIG. 5A to FIG. The same value is written on the negative electrode side. FIGS. 5A to 5E show an example of processing results on the assumption that the number of data bits (N + 1) is an even number in the operation example of FIG. In many cases, the number of data bits (the number of parallel bits) is an integer multiple of a byte (8 bits), and therefore, as shown in FIGS. 5A to 5E assuming an even number instead of an odd number. Processing results can occur more realistically.

<< Main effects of the first embodiment >>
As described above, the semiconductor device (storage device) according to the first embodiment identifies which one of the positive side and the negative side is abnormal from the parity check result for each of the positive bit string and the negative bit string. A function is provided that specifies one bit number from the comparison result for each bit and corrects 1-bit error at the specified location. This makes it possible to improve data reliability. At this time, since the parity bit is stored as a complementary bit, the reliability of the parity bit is improved, so that the reliability of the data can be further improved. Furthermore, it is possible to obtain such an effect of improving the reliability of data at a low cost. The cost reduction effect is more beneficial particularly when the number of parallel bits in the access unit is small.

  That is, when a Hamming code (ECC) method is used as a comparative example, for example, a 5-bit Hamming code (10 bits at complement) is added to parallel data of 2 bytes (16 bits) (32 bits at complement). , (32 + 10) / 32 times (about 1.3 times) storage area must be secured. On the other hand, when the system of the present embodiment is used, 1-bit parity bit for positive polarity (2 bits for complement) and 1-bit parity bit for negative polarity for 16-bit parallel data (32 bits when complementary) (2 bits at the time of complementation) may be added, and when the parity bit is complemented, a storage area of (32 + 4) / 32 times (about 1.1 times) may be secured. As described above, in the system according to the present embodiment, the area overhead associated with securing the storage area can be suppressed. Further, since the processing contents when generating parity bits, parity checking, and error correction are simple as compared with the case where the Hamming code (ECC) method is used as can be seen from FIGS. In addition, the area overhead associated with various processing circuits required for processing is sufficiently suppressed. As a result, the semiconductor device (memory device) can be reduced in size and cost.

(Embodiment 2)
In the second embodiment, a further specific example of a semiconductor device including the memory unit of the first embodiment will be described.

<< Overall configuration of semiconductor device >>
FIG. 6 is a block diagram showing an example of the overall configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 6 shows a microcomputer MCU formed as an example of a semiconductor device on one semiconductor chip such as single crystal silicon by a CMOS process or the like. The MCU is not particularly limited, but has a two-bus configuration of a high-speed bus HBS and a low-speed bus (peripheral bus) LBS. The HBS and the LBS are not particularly limited, but include a data bus, an address bus, and a control bus, respectively. By separating the bus into two bus configurations, the load on the bus is reduced as compared with the case where all the circuits are commonly connected to the common bus, and a high-speed access operation can be realized.

  A central processing unit CPU, a direct memory access controller DMAC, a bus interface circuit BSIF, a random access memory RAM, and a flash memory module FMDL as a nonvolatile memory module are connected to the high-speed bus HBS. The FMDL includes a flash memory FMD_D for storing data, a flash memory FMD_C for storing programs (codes), a high-speed access port HACSP, and a low-speed access port LACSP. FMDL is connected to the HBS via HACSP. The CPU executes predetermined arithmetic processing and the like while using the RAM as a work area. The DMAC controls data transfer between the RAM and FMDL based on a command from the CPU or the like. The BSIF controls the usage rights of the HBS and LBS, and controls the bus bridge between the HBS and the LBS.

  A flash memory module FMDL, a flash sequencer FSEQ, a timer TMR, external input / output ports PORT1 and PORT2, a bus interface circuit BSIF, and a clock generation circuit PLL are connected to the low-speed bus LBS. The FMDL is connected to the LBS via the low speed access port LACSP. FSEQ performs command access control for FMDL. The PLL generates various internal clock signals of the MCU. PORT1 and PORT2 control communication with the outside via external terminals Din / Dout of the MCU. The MCU further includes XTAL / EXTAL, STBY / RES, and Vcc / Vss as external terminals. For example, a crystal resonator is connected to XTAL / EXTAL or an external clock signal is supplied, and the PLL operates using the terminal. STBY is an external hardware standby terminal for instructing a standby state, RES is an external reset terminal for instructing a reset, Vcc is an external power supply voltage terminal, and Vss is an external ground power supply voltage terminal.

  Here, for example, a high-speed read access operation is possible between the CPU and the FMD_C or FMD_D in the FMDL via the HBS and the HACSP. For example, a write access operation via LBS, FSEQ, and LACSP is possible between the CPU and FMD_D in FMDL. As described above, the FMDL is a read / write access target of the CPU (or DMAC), and the CPU stores, for example, temporary data in the RAM and data used after the next power-on in the FMD_D while the FMD_C The code read from is appropriately executed. Since an actual flash memory requires several steps of processing along with the write operation, the FSEQ receives a write command from the CPU to the FMD_D, and the FSEQ requires various processes (FMD_D write operation) For example, the erase operation, the write operation, and the verify operation) are controlled in time series. The FSEQ is provided outside the FMDL here, but may be provided inside the FMDL. Although not particularly limited, FMD_C has a capacity value of several hundred kilobytes or more, and FMD_D has a capacity value of several tens of kilobytes or less.

  For example, in the microcomputer MCU as shown in FIG. 6, a large number of write accesses may occur from the CPU (or DMAC) or the like to the flash memory FMD_D for data storage in an access unit of a small area (for example, several bytes). is there. Along with this, there is a possibility that data retention may be deteriorated in FMD_D. Therefore, it is beneficial that FMD_D has a complementary memory and an error correction function. However, in this case, although there is a concern about an increase in area overhead, since FMD_D usually has a smaller capacity than FMD_C, it is acceptable to some extent. On the other hand, since FMD_C is used as a ROM (Read Only Memory) for storing codes in actual operation, data retention is less likely to occur compared to FMD_D, and because it has a larger capacity than FMD_D, the area is reduced. It may be a single memory with an emphasis on.

<Overall configuration of flash memory>
FIG. 7 is a circuit block diagram showing a schematic configuration example of a flash memory for storing data in the semiconductor device of FIG. FIG. 8 shows details of each memory cell in FIG. 7, FIG. 8 (a) is a circuit diagram showing a detailed configuration example of each memory cell, and FIG. 8 (b) shows various types in FIG. FIG. 8C is an explanatory diagram showing an example of operating conditions, and FIG. 8C is an explanatory diagram showing an example of the threshold state of each memory cell accompanying the operation of FIG. 8B. The flash memory FMD_D shown in FIG. 7 includes a memory mat MMAT, row decode circuits RDEC1 and RDEC2, a column decode circuit CDEC, a write data latch circuit WLT, a write column selection circuit WSEL, a verify circuit VRFY, an input / output buffer circuit IOBF, and an output buffer circuit. An OBF and an internal power supply generation circuit VG are provided.

  The MMAT includes two memory cells MC1 and MC2 that store 1-bit information in a complementary manner (positive and negative), and two memory cells MCp1 and MCp2 that store a parity bit for each positive-polarity memory cell in a complementary manner. , Two memory cells MCn1 and MCn2 for storing the parity bit for each memory cell for the negative electrode complementarily. Each memory cell (MC1, MC2, MCp1, MCp2, MCn1, MCn2) is, for example, a split gate type flash memory device illustrated in FIG. This memory element has a control gate CG and a memory gate MG disposed on a channel formation region between a source / drain region via a gate insulating film, and a silicon nitride is interposed between the memory gate and the gate insulating film. A charge trap region (SiN) such as a ride is arranged. The source or drain region on the CG side is connected to the bit line BL, and the source or drain region on the MG side is connected to the source line SL.

  As shown in FIG. 8B, when lowering the threshold voltage (Vth) of the memory cell, BL = 1.5V, CG = 0V, MG = −10V, SL = 6V, well region WELL = 0V It is said. As a result, electrons are extracted from the charge trap region (SiN) to WELL by a high electric field between WELL and MG. This processing unit is a plurality of memory cells sharing MG. When increasing the Vth of the memory cell, BL = 0V, CG = 1.5V, MG = 10V, SL = 6V, and WELL = 0V. As a result, a write current flows from SL to BL, whereby hot electrons generated at the boundary between CG and MG are injected into the charge trap region (SiN). Since the electron injection is determined by whether or not a current is supplied to BL, this process is controlled in units of bits. At the time of reading, BL = 1.5V, CG = 1.5V, MG = 0V, SL = 0V, and WELL = 0V. If Vth of the memory cell is low, the memory cell is turned on, and if it is high, it is turned off. Here, the operation of lowering the Vth of the memory cell is an erasing operation, and the operation of raising the Vth of the memory cell is a writing operation.

  The memory device is not limited to such a split gate flash memory device, and may be a widely known stacked gate flash memory device, for example. This memory element is configured by stacking a floating gate (FG) and a control gate (CG) on a channel formation region between a source / drain region via a gate insulating film. In such a memory element, for example, an operation for increasing the threshold voltage is performed by a hot carrier writing method, and an operation for decreasing the threshold voltage is performed by releasing electrons into the well region (WELL). In addition, for example, an operation of increasing the threshold voltage is performed by the FN tunnel writing method, and an operation of decreasing the threshold voltage is performed by releasing electrons to the bit line (BL).

  The memory cells MC1 and MC2 serving as complementary bits (twin cells) store information (data) of “0” or “1” in a state as shown in FIG. 8C, for example. That is, when writing data to MC1 and MC2, first, MC1 and MC2 are both brought into an initial state (a state in which Vth is low) by the erase operation described with reference to FIG. When writing "1" data from this state, the write operation described in FIG. 8B is performed on MC2 for negative electrode. As a result, MC1 is in an initial state, MC2 is in a write state (Vth is high), and this state corresponds to data ‘1’. On the other hand, when “0” data is written from the initial state of MC1 and MC2, the write operation described in FIG. As a result, MC2 is in an initial state and MC1 is in a write state, and this state corresponds to data “0”. Here, the state where Vth is low on the positive electrode side is data '1', and the state where Vth is high is data '0'. Of course, the correspondence relationship between data '0' and '1' can also be switched. It is.

  In the memory mat MMAT of FIG. 7, the memory gates MG of MC1, MC2, MCp1, MCp2, MCn1, and MCn2 are connected to a common memory gate selection line MGL, the control gate CG is connected to a common word line WL, and the source The nodes are connected to a common source line SL. Here, one twin cell (MC1, MC2) is typically shown as a memory cell for data, but in reality, a plurality of (for example, (N + 1) bits in FIG. 1) are provided in the same MGL, WL, SL. ) Twin cell is connected. In addition, although one MGL, WL, and SL are shown here, actually, a plurality of MGL, WL, and SL are sequentially arranged alongside the MGL, WL, and SL. A plurality of twin cells and memory cells for parity (MCp1, MCp2, MCn1, MCn2) are connected.

  MC1, MC2, MCp1, MCp2, MCn1, and MCn2 are connected to different sub-bit lines SBL, and are connected to different write-related main bit lines WMBL via the sub-bit line selection circuit BSEL. The sub-bit line SBL of MC1 is connected to one of the differential input terminals of the sense amplifier circuit SA1 via the read column selection circuit RSEL, and the SBL of MC2 is connected to the other of the differential input terminals of SA1 via the RSEL. The Although the details around SA1 will be described later, as described with reference to FIG. 3, the positive electrode side and the negative electrode side are devised so that each can be read as a single data string.

  The SBL of MCp1 is connected to one of the differential input terminals of the sense amplifier circuit SA2 via RSEL, and the SBL of MCp2 is connected to the other of the differential input terminals of SA2 via RSEL. The SBL of MCn1 is connected to one of the differential input terminals of the sense amplifier circuit SA3 via RSEL, and the SBL of MCn2 is connected to the other of the differential input terminals of SA3 via RSEL. Thus, by storing parity bits as complementary bits (twin cells) and reading them differentially using a sense amplifier circuit, the reliability of the parity bits can be improved. That is, by determining the information of the twin cell differentially, for example, the margin becomes larger than when determining the information of the single cell on the basis of the intermediate level, and the reliability of the parity bit (data retention characteristic) is correspondingly increased. improves. The parity bit is preferably composed of complementary bits (twin cells), but may be composed of single bits (single cells) in some cases. In this case, although the reliability is lowered, the area overhead can be suppressed.

  The word line WL is driven by the row decoding circuit RDEC1, and the selection signals of the memory gate selection line MGL, the source line SL, and the sub bit line selection circuit BSEL are driven by the row decoding circuit RDEC2. The selection operation in RDEC1 and RDEC2 follows the address information supplied to HACSP in FIG. 6 at the time of read access, and follows the address information supplied to LACSP in FIG. 6 in the data write operation and erase operation. Output signals of the sense amplifier circuits SA1 to SA3 are connected to different read-system main bit lines RMBL, respectively. In practice, SA1 and the corresponding RMBL are provided with the number of parallel bits (corresponding to (N + 1) bits in FIG. 1) as a data access unit.

  The output buffer circuit OBF includes an error processing circuit block ERCBK. The ERCBK receives the output signals from the SA1 to SA3 in the memory mat MMAT described above via the RMBL, and performs error detection and error correction by performing the processing described in FIG. That is, although details will be described later, ERCBK acquires a positive-side data string including MC1 and a negative-side data string including MC2 via SA1, and a parity bit value for the positive-side data string via SA2. And the parity bit value for the negative-side data string is obtained via SA3. The ERCBK corrects the error if there is a 1-bit error in the data string, and sends the corrected data output signals DO [0] to DO [N] via the high-speed access port HACSP in FIG. To the high-speed bus HBS.

  The write data latch circuit WLT includes latch circuits LT1, LT2, LTp1, and LTn1 respectively connected to the respective write main bit lines WMBL, and a write current is selectively applied to each WMBL based on the latch data of the latch circuit. Shed. In FIG. 7, the description of the latch circuit connected to the WMBL of MCp2 (referred to as LTp2) and the latch circuit connected to the WMBL of MCn2 (referred to as LTn2) are omitted. To do. The write column selection circuit WSEL selectively connects each latch circuit in the WLT to the input / output buffer circuit IOBF, and selectively connects the WMBL connected to each latch circuit to the verify circuit VRFY. The selection signal at this time is generated by the column decode circuit CDEC. The selection operation of CDEC follows the address information supplied to the low-speed access port LACSP in FIG.

  The verify circuit VRFY includes a verify sense amplifier circuit VSA connected to each WMBL, and the verify result of each VSA is output to the IOBF. The IOBF includes a parity generation circuit PRTYG, and data input signals DI [0] to DI [N] are input from the low-speed bus LBS of FIG. 6 through the low-speed access port LACSP, and data is transmitted to the LBS through LACSP. Output signals DO [0] to DO [N] are output. PRTYG receives DI [0] to DI [N] and generates parity bit values for positive and negative electrodes. The internal power supply generation circuit VG generates various operation power supplies necessary for the read operation, the write operation, and the erase operation.

<Overall operation of flash memory>
A write operation and a read operation for the flash memory FMD_D in FIG. 7 will be briefly described. First, when performing a write operation, the FMD_D performs an erase operation as shown in FIG. 8B in advance in accordance with the instruction of the flash sequencer FSEQ of FIG. 6, and the memory cells MC1, MC2, MCp1, MCp2, MCn1 , MCn2 is kept low as shown in FIG. 8C. Next, the input / output buffer circuit IOBF sets the value of each latch circuit in the write data latch circuit WLT based on the data input signals DI [0] to DI [N] in accordance with the FSEQ command. For example, assuming that the twin cells corresponding to DI [0] are MC1 and MC2, when DI [0] is “1”, “1” is set in the latch circuit LT1, and “0” is set in the latch circuit LT2. Is set. Conversely, when DI [0] is “0”, “0” is set to LT1, and “1” is set to LT2. Further, the parity bit values generated by the parity generation circuit PRTYG are set in the latch circuits LTp1 and LTn1, respectively, and a value obtained by inverting the parity bit value is set in the latch circuits LTp2 and LTn2 (not shown). .

  Here, the latch circuit set to “0” supplies the write current to the corresponding write system main bit line WMBL for a predetermined period, and the latch circuit set to “1” corresponds to the corresponding WMBL. The write current is not supplied. Therefore, for example, when DI [0] is “1”, LT2 supplies a write current to MC2 via WMBL and the sub bit line selection circuit BSEL, and as a result, the Vth of MC2 increases. Subsequently, a verify operation is performed in accordance with the FSEQ command. In the verify operation, the data stored in MC1, MC2, MCp1, MCp2, MCn1, and MCn2 are read out via BSEL and each WMBL. The data read to each WMBL is determined by the verify sense amplifier circuit VSA, and the Vth of the memory cell to which the write current is supplied (the memory cell in which “0” is set in the corresponding latch circuit) is set to a sufficient level. It is verified whether it has been reached. The verification result is notified to the FSEQ via the IOBF, and if the level has not reached a sufficient level, the write current is supplied again in response to the FSEQ command. As a result of such an operation, a write state as shown in FIG. 8C is realized.

  On the other hand, when performing a read operation, the storage data of MC1 and MC2 is input to the sense amplifier circuit SA1 via the read column selection circuit RSEL, and the storage data of MCp1 and MCp2 is input to the sense amplifier circuit SA2 via the RSEL. The data stored in MCn1 and MCn2 is input to the sense amplifier circuit SA3 via RSEL. SA1 to SA3 differentially amplify the input signal and output to the read main bit line RMBL. The error processing circuit block ERCBK in the output buffer circuit OBF performs error detection / error correction based on the information of the RMBL, and outputs data output signals DO [0] to DO [N] to the high-speed bus HBS.

<Flash memory memory mat configuration>
FIG. 9 is a schematic diagram showing a layout configuration example of a memory mat in the flash memory of FIG. As shown in FIG. 9, the memory mat MMAT includes a plurality of memory arrays MARYj [0,0] to MARYj [M, N + 2], MARYk [0,0] to MARYk [M, N + 2], and a plurality of sense amplifier circuit blocks. SABK [0, 0] to SABK [M, N + 2] are provided. SABK [0, 0] to SABK [M, N + 2] are “(M + 1) rows × (N + 3) columns” in the form of an array, with the word line array direction being the row and the bit line (sub-bit line) array direction being the column. It is arranged with. Similarly, MARYj [0,0] to MARYj [M, N + 2] are arranged in an array of “(M + 1) rows × (N + 3) columns”, and MARYk [0,0] to MARYk [M, N + 2] are It is arranged in an array of “(M + 1) rows × (N + 3) columns”. At this time, MARYj [0,0] and MARYk [0,0] are arranged so as to sandwich SABK [0,0] in the row direction, and MARYj [0,1] and MARYk [0,1] are SABK [0,1]. 0, 1] are arranged in the row direction, and MARYj [M, N + 2] and MARYk [M, N + 2] are similarly arranged in the form of sandwiching SABK [M, N + 2] in the row direction.

  Among these, MARYj [0, 0] to MARYj [M, N], MARYk [0, 0] to MARYk [M, N] and SABK [0] arranged in “(M + 1) rows × (N + 1) columns”, respectively. , 0] to SABK [M, N] are data areas. On the other hand, MARYj [0, N + 1] to MARYj [M, N + 2], MARYk [0, N + 1] to MARYk [M, N + 2] and SABK [0, N + 1] respectively arranged in “(M + 1) rows × 2 columns”. ~ SABK [M, N + 2] is a parity area. Of the parity regions for two columns, the region on the (N + 1) column side is for the positive electrode (Posi), and the region on the (N + 2) column side is for the negative electrode (Nega).

  In such a configuration, each memory array for data and parity has X (for example, 256) word lines WL and Y (for example, 32) subbits arranged so as to intersect the word lines. A line SBL and a memory cell arranged at the intersection of WL and SBL are provided. WL extends in the column direction so as to cross the memory arrays arranged in the same row. For example, when one WL arranged on MARYj [0,0] to MARYj [0, N + 2] on the same row is activated during a read operation, a plurality of memories connected to the WL are activated. A cell is selected. Also, one of the plurality of memory cells selected by WL is selected from each of MARYj [0,0] to MARYj [0, N] for data via the read column selection circuit RSEL of FIG. Twin cells (MC1, MC2) are selected. In addition to this, one twin cell (MCp1, MCp2) is selected from MARYj [0, N + 1] for parity (positive electrode) via RSEL, and MARYj [0, N + 2 for parity (negative electrode) is selected. ], One twin cell (MCn1, MCn2) is selected.

  Thus, the information of the twin cells output from each of the MARYj [0,0] to MARYj [0, N] for data is the sense amplifier circuit block SABK [0,0] to SABK arranged adjacent to the memory array. The signals are amplified by the sense amplifier circuit SA1 in [0, N] and output via the corresponding read system main bit lines RMBL [0] to RMBL [N]. With the signals RMBL [0] to RMBL [N], (N + 1) -bit parallel data (PREDATp [0: N], PREDATn [0: N]) in FIG. 1 is obtained. On the other hand, the information of the twin cell output from the parity (positive) MARYj [0, N + 1] is amplified by SA2 in the SABK [0, N + 1] adjacent to the memory array, and passes through RMBL [N + 1]. Is output. Similarly, the information of the twin cell output from the parity (negative electrode) MARYj [0, N + 2] is amplified by SA3 in the SABK [0, N + 2] adjacent to the memory array, and RMBL [N + 2] is obtained. Is output via. As a result, the value of the positive parity bit (SN1p) and the value of the negative parity bit (SN2p) in FIG. 1 are obtained.

  Each of RMBL [0] to RMBL [N + 2] extends in the row direction so as to cross the sense amplifier circuit blocks arranged in the same column. For example, RMBL [0] is arranged on SABK [0,0] to SABK [M, 0] in the same column, and similarly, SABK [0, N] to SABK [M, N] in the same column. RMBL [N] is arranged above. The output nodes of SA1 included in SABK [0,0] to SABK [M, 0] are connected in common to RMBL [0]. Similarly, RMBL [N] has SABK [0, N ] To SABK [M, N], SA1 output nodes respectively connected in common. For example, taking RMBL [0] as an example, any one output of SA1 in SABK [0,0] to SABK [M, 0] is output to RMBL [0] in response to activation of one WL during a read operation. 0] and the other outputs are controlled to a high impedance state. Each sense amplifier circuit block performs an amplification operation or the like on two memory arrays adjacently arranged in the row direction. For example, twin cell information from MARYj [0, 0] is amplified by SABK [0, 0], and twin cell information from MARYk [0, 0] is also amplified by SABK [0, 0].

<< Configuration around the sense amplifier circuit block [1] >>
FIG. 10 is a circuit diagram showing a schematic configuration example around each sense amplifier circuit block in FIG. 7 and FIG. As shown in FIG. 10, the sense amplifier circuit block SABKa (for example, SABK [0, 0] in FIG. 9) includes a plurality (here, 32) sub-bit lines SBLj0 <0> to SBLj0 <15> and SBLj1 <0> to SBLj1 <15> are connected. Further, the SABKa (for example, SABK [0,0]) includes a plurality (32 in this case) of sub-bit lines SBLk0 <0> from the other adjacent memory array (for example, MARYk [0,0] in FIG. 9). To SBLk0 <15> and SBLk1 <0> to SBLk1 <15> are connected.

  In this example, SBLj0 <0> to SBLj0 <7> and SBLj1 <0> to SBLj1 <7> corresponding to one of the memory arrays are connected to each positive-electrode memory cell in the memory array, and SBLj0 <8>. ~ SBLj0 <15>, SBLj1 <8> to SBLj1 <15> are connected to the negative-polarity memory cells in the memory array. Similarly, SBLk0 <0> to SBLk0 <7> and SBLk1 <0> to SBLk1 <7> corresponding to the other memory array are connected to the positive memory cells in the memory array, and SBLk0 <8> to SBLk0 <15>, SBLk1 <8> to SBLk1 <15> are connected to each negative-electrode memory cell in the memory array.

  SABKa (for example, SABK [0, 0]) includes a sense amplifier circuit SA, read column selection circuits RSELj, RSELk, and RSELjk, and eight common bit lines CBLj <0> to CBLj <3>, CBLk <0> to CBLk <3> and eight reference memory cells RMC are provided. RSELjk selects eight common bit lines as one or the other of the differential input terminals of SA in response to eight selection signals yrb <7: 0> generated from the column decoding circuit CDEC in FIG. Connecting. Here, one of the SA differential input terminals is selectively connected to one of CBLj <0>, CBLj <1> and CBLk <0>, CBLk <1>. One of CBLj <2>, CBLj <3> and CBLk <2>, CBLk <3> is selectively connected to the other terminal.

  Eight of the 16 sub-bit lines corresponding to the positive side of one memory array are connected to CBLj <0> via RSELj, and the remaining 8 of the 16 are connected to CBLj <1>. Are connected via RSELj. Eight of the 16 sub-bit lines corresponding to the negative side of one memory array are connected to CBLj <2> via RSELj, and the remaining 8 of the 16 are connected to CBLj <3>. Are connected via RSELj. Eight of the 16 sub-bit lines corresponding to the positive side of the other memory array are connected to CBLk <0> via RSELk, and the remaining 8 of 16 are connected to CBLk <1>. Are connected via RSELk. Eight of the 16 sub-bit lines corresponding to the negative side of the other memory array are connected to CBLk <2> via RSELk, and the remaining 8 of 16 are connected to CBLk <3>. Are connected via RSELk.

  RSELj is one of the eight sub-bit lines described above for each of CBLj <0> to CBLj <3> according to the eight selection signals yraj <7: 0> generated from the CDEC of FIG. Connect one. RSELk is one of the eight sub-bit lines described above for each of CBLk <0> to CBLk <3> in response to the eight selection signals yrak <7: 0> generated from the CDEC of FIG. Connect one. Eight reference memory cells RMC are connected to the eight common bit lines CBLj <0> to CBLj <3> and CBLk <0> to CBLk <3>, respectively. Each RMC includes a PMOS transistor PQr and an NMOS transistor NQr in which source / drain paths are connected in series between the corresponding common bit line and the ground power supply voltage GND. NQr functions as a current source when a fixed voltage Vref is applied to the gate, and PQr functions as a switch when a selection signal is applied to the gate. Here, the PQr in the four RMCs connected to CBLj <0> to CBLj <3> are commonly controlled by the selection signal refj, and the four RMCs connected to CBLk <0> to CBLk <3> Are controlled in common by a selection signal refk.

<< Operation around the sense amplifier circuit block [1] >>
When the configuration example as shown in FIG. 10 is used, one memory array (for example, MARYj [[e.g., MARYj [[ 0,0]) and complementary reading and single reading from the other memory array (for example, MARYk [0,0]). For example, when yraj <0>, yrak <0> and yrb <0>, yrb <2> are driven to the on level, one of the SA differential input terminals has a read path RT1 shown in FIG. In addition, one sub-bit line (SBLj0 <0>) on the positive electrode side in one memory array (for example, MARYj [0, 0]) is connected via CBLj <0>. At this time, one sub-bit line (SBLj0) on the negative side in one memory array (for example, MARYj [0, 0]) is connected to the other SA differential input terminal as shown in the read path RT2 of FIG. <8>) are connected via CBLj <2>. As a result, in SA, complementary reading is performed on the twin cell.

  Further, for example, when yraj <0>, yrak <0>, yrb <0>, yrb <6>, and refk are driven to the on level, one of the SA differential input terminals has a read path shown in FIG. As shown in RT1, one positive-side sub bit line (SBLj0 <0>) in one memory array (for example, MARYj [0, 0]) is connected via CBLj <0>. At this time, the reference memory cell RMC connected to CBLk <2> is connected to the other differential input terminal of SA as shown in the read path RT4 of FIG. For example, the RMC generates a current having an intermediate value between a current that flows when a normal memory cell is in a write state and a current that flows in an erase state (initial state). Thus, in SA, single reading is performed on the positive-side memory cell. At this time, in addition to RMC, one negative bit side sub-bit line (SBLk0 <8>) in the other memory array (for example, MARYk [0, 0]) is connected to CBLk <2>. The sub bit line is in a floating state because the word line is not selected, and functions as a capacitor.

  Also, for example, when yraj <0>, yrak <0>, yrb <2>, yrb <4>, and refk are driven to the on level, the other of the SA differential input terminals is connected to the read path of FIG. As shown at RT2, one sub-bit line (SBLj0 <8>) on the negative electrode side in one memory array (for example, MARYj [0, 0]) is connected via CBLj <2>. At this time, the reference memory cell RMC connected to CBLk <0> is connected to one of the differential input terminals of SA as shown in the read path RT3 of FIG. As a result, in SA, single reading is performed on the memory cell on the negative electrode side. At this time, in addition to RMC, one positive bit side sub-bit line (SBLk0 <0>) in the other memory array (for example, MARYk [0, 0]) is connected to CBLk <0>. The sub bit line is in a floating state because the word line is not selected, and functions as a capacitor.

  In this way, the positive-side data string and the negative-side data string are individually read out in the single mode, and in addition, the twin cell corresponding to the parity bit of the positive-side data string is read out in the complementary mode. By reading out the twin cell corresponding to the parity bit in the complementary mode, the above-described error detection / error correction processing of FIG. 3 can be realized. Here, in order to realize the reading in the single mode, it is only necessary to add the reference memory cell RMC to the normal complementary memory sense amplifier circuit, and the overhead of the circuit area can be suppressed. In addition, a flash memory that uses the sense amplifier circuit also at the time of verifying may already have an RMC, and in this case, the overhead of the circuit area can be further suppressed.

<< Configuration around the sense amplifier circuit block [2] >>
FIG. 11 is a circuit diagram showing a schematic configuration example around each sense amplifier circuit block obtained by modifying FIG. In FIG. 11, the sense amplifier circuit block SABKb (for example, SABK [0,0] in FIG. 9) has one adjacent memory array (for example, MARYj [0,0] in FIG. 9) as in FIG. A plurality (32 in this case) of sub-bit lines SBLj0 <0> to SBLj0 <15> and SBLj1 <0> to SBLj1 <15> are connected. Further, in the SABKb, similarly to the case of FIG. 10, a plurality of (here, 32) sub-bit lines SBLk0 <0> to the other adjacent memory array (for example, MARYk [0, 0] in FIG. 9). SBLk0 <15> and SBLk1 <0> to SBLk1 <15> are connected.

  SABKb (for example, SABK [0, 0]) includes read column selection circuits RSELj and RSELk similar to those in FIG. 10, eight common bit lines CBLj <0> to CBLj <3>, CBLk <0> to CBLk < 3> and 8 reference memory cells RMC. In addition to this, the SABKb mainly includes three sense amplifier circuits SAm, SAp, and SAn unlike the case of FIG. 10, and is accompanied by a read column selection circuit RSELjk2 that is different from the case of FIG. It has become a feature. RSELjk2 has eight common bit lines connected to three SAm, SAp, and SAn differential input terminals in response to four selection signals yrb <3: 0> generated from the column decoding circuit CDEC in FIG. Selectively connect to one or the other.

  Specifically, RSELjk2 connects CBLj <0> to one of the differential input terminals of SAm and CBLj <2> to the other when yrb <0> is driven to the on level, and differentials of SAp CBLj <0> is connected to one of the input terminals, CBLk <2> is connected to the other, CBLk <0> is connected to one of the differential input terminals of SAn, and CBLj <2> is connected to the other. In other words, the positive data (corresponding to CBLj <0>) and the negative data (CBLj <2>) of the twin cell are connected to the SAm for complementary reading. Twin-cell positive polarity data (corresponding to CBLj <0>) and a reference memory cell (corresponding to CBLk <2>) are connected to the SAp for single reading on the positive polarity side. Reference memory cells (corresponding to CBLk <0>) and twin-cell negative data (corresponding to CBLj <2>) are connected to SAn for single reading on the negative electrode side.

  RSELjk2 connects CBLj <1> to one of the SAm differential input terminals, and CBLj <3> to the other when yrb <1> is driven to the on level, and the SAp differential input terminal CBLj <1> is connected to one side, CBLk <3> is connected to the other, CBLk <1> is connected to one of the differential input terminals of SAn, and CBLj <3> is connected to the other. In other words, the positive data (corresponding to CBLj <1>) and the negative data (CBLj <3>) of the twin cell are connected to the SAm for complementary reading. Twin-cell positive polarity data (corresponding to CBLj <1>) and a reference memory cell (corresponding to CBLk <3>) are connected to the SAp for single reading on the positive polarity side. Reference memory cells (corresponding to CBLk <1>) and twin-cell negative data (corresponding to CBLj <3>) are connected to SAn for single reading on the negative electrode side.

  Further, RSELjk2 connects CBLk <0> to one of the SAm differential input terminals and CBLk <2> to the other when yrb <2> is driven to the on level, and the SAp differential input terminal CBLk <0> is connected to one side, CBLj <2> is connected to the other, CBLj <0> is connected to one of the differential input terminals of SAn, and CBLk <2> is connected to the other. That is, a process is performed in which “j” and “k” are interchanged when the above-described yrb <0> is driven to the on level. Similarly, RSELjk2 performs a process in which “j” and “k” are interchanged when yrb <1> is driven to the on level when yrb <3> is driven to the on level. Do.

<< Operation around the sense amplifier circuit block [2] >>
When the configuration example as shown in FIG. 11 is used, one memory array (for example, MARYj [[e.g., MARYj [[]]) is selected according to various selection signals yrb <3: 0>, yraj <7: 0>, yak <7: 0>, refj, 0,0]) complementary reading from the twin cell, single reading from the positive side cell, and single reading from the negative side cell can be performed in parallel. Similarly, complementary reading from the twin cell of the other memory array (for example, MARYk [0, 0]), single reading from the positive side cell, and single reading from the negative side cell can be performed in parallel. .

  For example, when yraj <0>, yrak <0>, yrb <0>, and refk are driven to the on level, one of the SAm differential input terminals has one side as shown in the read path RT1 in FIG. One sub-bit line (SBLj0 <0>) on the positive side in the memory array (for example, MARYj [0, 0]) is connected through CBLj <0>. At this time, one sub-bit line (SBLj0) on the negative side in one memory array (for example, MARYj [0, 0]) is connected to the other differential input terminal of SAm as shown in the read path RT2 of FIG. <8>) are connected via CBLj <2>. As a result, in SAm, complementary reading with respect to the twin cell is performed.

  In parallel with this, one of the differential input terminals of the SAp is connected to one positive side of one memory array (for example, MARYj [0, 0]) as shown in the read path RT1 of FIG. Sub-bit lines (SBLj0 <0>) are connected via CBLj <0>. At this time, the reference memory cell RMC connected to CBLk <2> is connected to the other differential input terminal of SAp as shown in the read path RT4 of FIG. For example, the RMC generates a current having an intermediate value between a current that flows when a normal memory cell is in a write state and a current that flows in an erase state (initial state). Thus, in SAp, single reading is performed on the positive-side memory cell. At this time, in addition to RMC, one negative bit side sub-bit line (SBLk0 <8>) in the other memory array (for example, MARYk [0, 0]) is connected to CBLk <2>. The sub bit line is in a floating state because the word line is not selected, and functions as a capacitor.

  Further, in parallel with these, one of the differential input terminals of SAn is connected to one negative electrode side of one memory array (for example, MARYj [0, 0]) as shown in the read path RT2 of FIG. Sub-bit lines (SBLj0 <8>) are connected via CBLj <2>. At this time, the reference memory cell RMC connected to CBLk <0> is connected to one of the differential input terminals of SAn as shown in the read path RT3 of FIG. Thereby, in SAn, single reading is performed on the memory cell on the negative electrode side. At this time, in addition to RMC, one positive bit side sub-bit line (SBLk0 <0>) in the other memory array (for example, MARYk [0, 0]) is connected to CBLk <0>. The sub bit line is in a floating state because the word line is not selected, and functions as a capacitor.

  In this way, the positive-side data string and the negative-side data string are individually read out in the single mode, and in addition, the twin cell corresponding to the parity bit of the positive-side data string is read out in the complementary mode. By reading out the twin cell corresponding to the parity bit in the complementary mode, the above-described error detection / error correction processing of FIG. 3 can be realized. Here, when the configuration example of FIG. 10 described above is used, it is necessary to perform single-mode readout on the positive electrode side and single-mode readout on the negative electrode side serially. However, in the configuration example of FIG. Therefore, the readout time can be shortened compared to the configuration example of FIG.

  When the processing of FIG. 3 is used, each sense amplifier circuit block included in the data area of FIG. 9 does not need to perform complementary reading, and therefore the SAm of FIG. 11 and the selection path on RSELjk2 associated therewith are omitted. It is also possible. However, for example, a function capable of enabling / disabling the error detection / correction function described above may be provided in the flash memory, and SAm may be used when this function is disabled. For example, when error detection is performed but error correction fails (for example, as in S108 of FIG. 3), the output from SAm can be used as a data output signal. It is also possible to check whether or not an error has been detected in the flow as shown in FIG. 3 when the power is turned on, and to validate the output data by complementary reading from SAm when other high-speed operation is required. Further, when the processing of FIG. 3 is used, each sense amplifier circuit block included in the parity area of FIG. 9 does not need to perform single reading in particular, so that SAp and SAn of FIG. 11 and the selection path on RSELjk2 associated therewith are It can be omitted.

<Configuration of parity generation circuit>
12A is a circuit diagram showing a detailed configuration example of the parity generation circuit in FIG. 7, and FIG. 12B is a truth table showing an operation example of the addition circuit in FIG. 12A. . The parity generation circuit PRTYG in FIG. 12A includes complementary data generation circuits CDS [0] to CDS [N], N addition circuits ADDp [1] to ADDp [N] for positive electrodes, and an inverter circuit IVp. N negative adder circuits ADDn [1] to ADDn [N] and an inverter circuit IVn are provided. CDS [0] to CDS [N] are data input signals DIp [0] to DIp [N] on the positive side from the data input signals DI [0] to DI [N] and data inputs on the negative side that are inverted data thereof. Signals DIn [0] to DIn [N] are generated.

  DIp [0] and DIp [1] are input to ADDp [1], and the addition result (EXOR (exclusive OR) operation result) and DIp [2] of ADDp [1] are input to ADDp [2]. Thereafter, similarly, the addition result of ADDp [N−1] and DIp [N] are input to ADDp [N]. IVp inverts the addition result of ADDp [N] to generate a parity bit PRTYBITp_W on the positive electrode side. As a result, an odd parity value is obtained as PRTYBITp_W. Similarly, DIn [0] and DIn [1] are input to ADDn [1], and the addition result (EXOR operation result) and DIn [2] of ADDn [1] are input to ADDn [2]. Similarly, the addition result of ADDn [N−1] and DIn [N] are input to ADDn [N]. IVn inverts the addition result of ADDn [N] to generate a negative parity bit PRTYBITn_W. As a result, an odd parity value is obtained as PRTYBITn_W. If even parity is used, IVp and IVn may be omitted, and each adder circuit can be replaced with an EXOR operation circuit.

<Details of error processing circuit block>
FIG. 13 is a truth table showing a detailed operation example of the error processing circuit block in FIG. FIG. 14 is a circuit diagram showing a detailed configuration example of the error processing circuit block in FIG. As shown in FIG. 14, the error processing circuit block ERCBK includes a parity check circuit PRTYCHKCTp for positive electrode, a parity check circuit PRTYCHKCTn for negative electrode, and (N + 1) error processing circuits ERC [0] to ERC [N]. I have. PRTYCHKCTp is an (N + 1) -bit data string (pre-data signals PREDATp [0] to PREDATp [N]) read in a single mode from the positive side via the circuit of FIG. 10 or FIG. Parity check is performed with bit PRTYBITp_R as an input. PRTYBITp_R is obtained by reading out PRTYBITp_W written in the memory cell (twin cell) after being generated by the circuit of FIG.

  PRTYCHKCTp includes N EXOR operation circuits EORp [1] to EORp [N] and one EXNOR (exclusive inversion OR) operation circuit ENRpp. EORp [1] to EORp [N] perform an EXOR operation on the (N + 1) inputs of PREDATp [0] to PREDATp [N]. In this example, EORp [1] calculates PREDATp [0] and PREDATp [1], EORp [2] calculates EORp [1] and PREDATp [2], and so on. EORp [N] performs an operation result of EORp [N-1] and PREDATp [N]. ENRpp performs an EXOR operation result (output of EORp [N]) of this PREDATp [0] to PREDATp [N] and an EXNOR operation of PRTYBITp_R, and outputs the result as a parity determination signal PRTYCHKp.

  Similarly, PRTYCHKCTn is an (N + 1) -bit data string (pre-data signals PREDATn [0] to PREDATn [N]) read in the single mode from the negative electrode side through the circuit of FIG. 10 or FIG. The parity check is performed with the parity bit PRTYBITn_R on the side as an input. PRTYBITn_R is obtained by reading PRTYBITn_W generated by the circuit of FIG. 12A and then written in the memory cell (twin cell). PRTYCHKCTn includes N EXOR operation circuits EORn [1] to EORn [N] and one EXNOR (exclusive inversion OR) operation circuit ENRnn. EORn [1] to EORn [N] generate the EXOR operation result of PREDATn [0] to PREDATn [N] as in the case of the positive electrode described above, and ENRnn generates the EXOR operation result of this EXOR operation and the EXNOR operation of PRTYBITn_R. And outputs the result as a parity determination signal PRTYCHKn.

  ERC [0] operates by inputting PREDATp [0] as positive data, PREDATn [0] as negative data, a parity determination signal PRTYCHKp from PRTYCHKCTp, and a parity determination signal PRTYCHKn from PRTYCHKCTn. ERC [0] includes one EXNOR operation circuit ENR1, three AND operation circuits AD1 to AD3, one OR operation circuit OR1, and three EXOR operation circuits EOR1 to EOR3. The input signal is subjected to a logical operation to generate five output signals. The five output signals are a positive-side data output signal DOp [0], a negative-side data output signal DOn [0], an error detection signal ERRPOT [0], an error correction failure signal ERRERR [0], and an error correction success signal, respectively. ERCSUC [0].

  ERC [N] inputs PREDATp [N] as positive data, PREDATn [N] as negative data, and parity determination signals PRTYCHKp and PRTYCHKCTn from PRTYCHKCTp as in ERC [0]. Works as. ERC [N] includes an internal circuit similar to ERC [0], and performs logical operation on the above-described input signal to generate five output signals. The five output signals are a positive-side data output signal DOp [N], a negative-side data output signal DOn [N], an error detection signal ERRPOT [N], an error correction failure signal ERERR [N], and an error correction success signal, respectively. ERCSUC [N]. Note that ERC [1] to ERC [N-1] are the same as ERC [N].

  Each internal circuit of ERC [0] to ERC [N] performs an operation based on the truth table of FIG. In FIG. 13, first, an EXNOR operation is performed on PREDATp serving as positive data and PREDATn serving as negative data to determine whether or not these are complementary data (corresponding to the signal CJ in FIGS. 13 and 14). . It is determined whether the error is on the positive side by performing an AND operation on CJ and PRTYCHKp (corresponding to the signal ERRp in FIGS. 13 and 14), and whether the error is on the negative side by performing an AND operation on CJ and PRTYCHKn. Is determined (corresponding to the signal ERRn in FIGS. 13 and 14). Therefore, the positive-side data output signal DOp after error correction can be generated by performing EXOR operation of ERRp and PREDATp, and the negative-side data output signal DOn after error correction can be generated by performing EXOR operation of ERRn and PREDATn. Can be generated.

  Further, an OR operation of PRTYCHKp, PRTYCHKn, and CJ is performed to generate an error detection signal ERRPOT that indicates the presence or absence of an error. Furthermore, an error correction success signal ERCSUC indicating whether or not the error correction is successful is generated by performing an AND operation on the EXOR operation result of PRTYCHPp and PRTYCHPn and CJ, and AND operation is performed on the inverted signal of ERRPOT and ERUCUC. Thus, an error correction failure signal ERRERR indicating whether or not the error correction has failed is generated. ERRPOT is “1” (error is present) when an abnormality is detected in the parity check result or the complementary data is not complementary, otherwise (the parity check result is normal and the complementary data is complementary). Is "0" (no error). ERCSUC is “1” (error correction success) when the complementary data of 筈 is not complementary and only one of the parity check results on the positive side and the negative side is abnormal. Therefore, DOp and DOn can be obtained correctly only when ERRPOT is “0” (no error) or ERCSUC is “1” (error correction is successful). In these cases, ERRERR is “0”, and in other cases, ERRERR is “1”. Therefore, the reliability of DOp and DOn can be identified by ERCERR.

  As can be seen from the description of FIGS. 13 and 14, the error processing circuit block ERCBK is a circuit for executing the processing contents of FIG. Further, as can be seen from the parity generation circuit PRTYG in FIG. 12 and the error processing circuit block ERCBK in FIG. 14, various arithmetic processes required for the error detection / error correction function of the present embodiment are general Hamming codes ( Compared with the case of using the ECC code), the circuit area overhead of the arithmetic circuit is sufficiently suppressed. As a result, the reliability of data can be improved at a low cost.

  As described above, by using the semiconductor device of the second embodiment, as in the case of the first embodiment, typically, the reliability of data can be improved and the effect can be obtained at low cost. Is possible. Furthermore, by applying the error detection / error correction function of the present embodiment to a data non-volatile memory block or the like built in a microcomputer or the like, the above-described effects can be obtained more remarkably. .

(Embodiment 3)
In the third embodiment, a semiconductor device (memory device) having only a part of the error detection / error correction functions described in the first embodiment will be described.

<< Schematic configuration and schematic operation of memory unit [2] >>
FIG. 15 is a schematic diagram showing a configuration example of a memory unit included in a semiconductor device (storage device) according to Embodiment 3 of the present invention. As in the configuration example of FIG. 1, the memory unit illustrated in FIG. 15 includes a memory area MEM1 having (N + 1) -bit storage nodes SN1 [0] to SN1 [N] and a (N + 1) -bit storage node SN2 [0. ] To SN2 [N], and an error processing circuit block ERCBK2 different from that shown in FIG. MEM1 and MEM2 form a complementary memory in which MEM1 is for the positive electrode (Posi) and MEM2 is for the negative electrode (Nega), as in the configuration example of FIG.

<< Error handling operation [2] >>
FIG. 16 is a flowchart showing a main operation example of the error processing circuit block in FIG. As shown in FIG. 16, the error processing circuit block ERCBK2 first reads a pre-data signal (PREDATp [0] to PREDATp [N] in FIG. 15) that is a single data string for the positive electrode (Posi) (S201). Similarly, pre-data signals (PREDATn [0] to PREDATn [N] in FIG. 15) that are single data strings for the negative electrode (Nega) are read (S202). Next, ERCBK2 determines whether or not the pre-data signal for the positive electrode (PREDATp [0] to PREDATp [N]) and the pre-data signal for the negative electrode (PREDATn [0] to PREDATn [N]) match each other for each bit. (S203). If all the bits do not match, it is determined that there is no error because complementary data is stored normally (S205). If there is a matching bit, it is determined that there is an error (S204).

  As described above, the semiconductor device (storage device) of the third embodiment is characterized in that the presence or absence of an error in each bit is determined using a complementary memory. In the example of FIG. 15, this error presence / absence determination is performed by the EXNOR operation circuit ENR10, and the ENR10 outputs the determination result as an (N + 1) -bit error detection signal ERRPOT [0: N]. Further, in the example of FIG. 15, each bit of the positive-side predata signal and the negative-side predata signal is amplified by the differential amplifier circuit DAMP, and the DAMP outputs the amplification result as the (N + 1) -bit data output signal DO [ 0: N]. For example, if “1” (with a coincidence bit) is output in any bit of ERRPOT [0: N] in a certain read cycle, the credibility of DO [0: N] in that cycle is suspicious. This can be communicated to the read request source or the like.

  As described above, when the semiconductor device (memory device) of the third embodiment is used, as can be seen from FIG. 15, an error can be detected by adding an EXNR arithmetic circuit or the like to the configuration of a normal complementary memory. Typically, the reliability of data can be improved, and the effect can be realized at low cost.

(Embodiment 4)
In the fourth embodiment, a configuration example obtained by modifying the configuration example of the first embodiment will be described.

<< Schematic Configuration and Operation of Memory Unit [3] >>
FIG. 17 is a schematic diagram showing a configuration example of a memory unit included in a semiconductor device (storage device) according to the fourth embodiment of the present invention. The memory unit shown in FIG. 17 includes memory areas MEM1 and MEM2, parity generation circuits PRTYG1 and PRTYG2, and parity storage nodes SN1p and SN2p, as well as the configuration example shown in FIG. A processing circuit block ERCBK3 is provided. The difference from FIG. 1 is the same as the (N + 1) -bit storage nodes SN1 [0] to SN1 [N] included in MEM1 and the (N + 1) -bit storage nodes SN2 [0] to SN2 [N] included in MEM2. The data is written (that is, the data is multiplexed), and the processing content of the ERCBK3 is slightly changed accordingly. Hereinafter, the description overlapping with the first embodiment will be omitted, and the description will be given focusing on the difference.

<< Error handling operation [3] >>
FIG. 18 is a flowchart showing an operation example of the error processing circuit block in FIG. As shown in FIG. 18, first, the error processing circuit block ERCBK3 first receives a data signal (DATA1 [0] to DATA1 [N] in FIG. 17) from MEM1 and a parity bit for MEM1 (FIG. 17). SN1p information) is read and parity check is performed (S301). Here, the case where the parity check result (Parity Check 1) is normal is expressed as “Parity Check 1 = 0”, and the case where it is abnormal is expressed as “Parity Check 1 = 1”.

  Next, ERCBK3 reads a data signal (DATA2 [0] to DATA2 [N] in FIG. 17) and a parity bit for MEM2 (information of SN2p in FIG. 17) from MEM2 and performs a parity check. This is performed (S302). Here, the case where the parity check result (Parity Check 2) is normal is expressed as “Parity Check 2 = 0”, and the case where it is abnormal is expressed as “Parity Check 2 = 1”. Subsequently, ERCBK3 determines the match / mismatch of DATA1 [0: N] and DATA2 [0: N] for each bit (S303). If all bits match, it is determined that there is no error because it is stored normally (S309). On the other hand, when there is a mismatch bit, the ERCBK 3 determines whether the parity check result (Parity Check 1) in S301 is abnormal (“1”) or normal (“0”) (S304). If it is abnormal, ERCBK3 determines that the mismatch bit in S303 is erroneous data in DATA1 [0: N] (S306), and corrects the bit (S310).

  In addition, when the parity check result (Parity Check 1) in S304 is normal (“0”), ERCBK3 determines whether the parity check result (Parity Check 2) in S302 is abnormal (“1”) or normal (“1”). 0 ") is determined (S305). If it is abnormal, ERCBK3 determines that the mismatch bit in S303 is erroneous data in DATA2 [0: N] (S307), and corrects the bit (S310). On the other hand, if the result of S305 is normal, ERCBK3 determines that there is an error but correction is not possible (S308). In S306, S307, and S310, it is assumed that the mismatch bit in S303 is 1 bit. In the case of a plurality of bits, it is determined that correction is impossible although an error exists as in S308.

  FIGS. 19A to 19E are explanatory diagrams illustrating examples of different specific processing results when the operation example of FIG. 18 is used. First, FIG. 19A shows an error-free state corresponding to S309 in FIG. Here, the bits in DATA1 [0: N] and DATA2 [0: N] are the same data, and the parity check result for DATA1 [0: N] and DATA2 [0: N] (in this example, odd parity) Both are normal.

  FIG. 19B shows a state in which one bit in DATA1 [0: N] is changed from “0” to “1” corresponding to S306 in FIG. Here, the [0] bit in DATA1 [0: N] and DATA2 [0: N] is not the same data, and the parity check result for DATA1 [0: N] is abnormal. Accordingly, it can be determined that the [0] bit of DATA1 [0: N] is erroneous data, and error correction can be realized by inverting the data. FIG. 19C shows a state in which one bit in DATA1 [0: N] is changed from “1” to “0”, corresponding to S306 in FIG. Here, the [1] bit in DATA1 [0: N] and DATA2 [0: N] is not the same data, and the parity check result for DATA1 [0: N] is abnormal. Therefore, it can be determined that the [1] -th bit of DATA1 [0: N] is erroneous data, and error correction can be realized by inverting the data.

  FIG. 19D shows a state in which one bit in DATA2 [0: N] is changed from “0” to “1” corresponding to S307 in FIG. Here, the [0] bit in DATA1 [0: N] and DATA2 [0: N] is not the same data, and the parity check result for DATA2 [0: N] is abnormal. Therefore, it can be determined that the [0] bit of DATA2 [0: N] is erroneous data, and error correction can be realized by inverting the data. FIG. 19 (e) shows a state in which one bit in DATA2 [0: N] has changed from “1” to “0”, corresponding to S307 in FIG. Here, the [1] bit in DATA1 [0: N] and DATA2 [0: N] is not the same data, and the parity check result for DATA2 [0: N] is abnormal. Therefore, it can be determined that the [1] bit of DATA2 [0: N] is erroneous data, and error correction can be realized by inverting the data.

  As described above, by using the semiconductor device (memory device) of the fourth embodiment, typically, as in the case of the first embodiment, data reliability can be improved and the effect can be reduced. It can be realized at a cost. For example, in a storage device such as a hard disk, data is sometimes duplicated and stored, as is known from RAID (Redundant Arrays of Inexpensive Disks) 1 and the like. In particular, in such a case, it is beneficial to apply the semiconductor device (memory device) of the fourth embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

  For example, an example of application to a flash memory is shown here as a specific example, but of course the invention is not limited to this and can be widely applied to various storage units in general. For example, a phase change memory that stores information according to its resistance value by changing the crystal state of the storage element, and a magnetoresistive memory (MRAM) that stores information according to its resistance value by changing the magnetization state of the storage element The present invention can be similarly applied to a semiconductor nonvolatile memory. Further, the present invention can be similarly applied to various semiconductor volatile memories represented by DRAM (Dynamic Random Access Memory) and the like, various external storage devices called so-called storages, and the like.

AD AND operation circuit ADD addition circuit BL bit line BSEL sub bit line selection circuit BSIF bus interface circuit CBL common bit line CDEC column decoding circuit CDS complementary data generation circuit CG control gate CJ, ERR signal CPU central processing unit DAMP differential amplification circuit DATA data Signal DI Data input signal DMAC Direct memory access controller DO Data output signal Din, Dout, XTAL, EXTAL, STBY, RES, Vcc, Vss External terminal ENR EXNOR arithmetic circuit EOR EXOR arithmetic circuit ERC error processing circuit ERCBK error processing circuit block ERCERR error Correction failure signal ERUCUC Error correction success signal ERRPOT Error detection signal FMD Flash memory F DL flash memory module FSEQ flash sequencer HACSP high-speed access port HBS high-speed bus IOBF I / O buffer circuit IV inverter circuit LACSP low-speed access port LBS low-speed bus LT latch circuit MARY memory array MC memory cell MCU microcomputer MEM memory area MG memory gate MGL memory gate Selection line MMAT Memory mat NQr NMOS transistor OBF Output buffer circuit OR OR operation circuit PLL Clock generation circuit PORT External input / output port PQr PMOS transistor PREDAT Pre-data signal PRTYBIT Parity bit PRTYCHK Parity check signal PRTYCHKCT Parity check circuit PRTYG Parity generation circuit R AM random access memory RDEC row decode circuit RMBL read system main bit line RMC reference memory cell RSEL read column selection circuit RT read path SA sense amplifier circuit SABK sense amplifier circuit block SBL sub bit line SL source line SN storage node TMR timer VG internal power generation Circuit VRFY verify circuit VSA verify sense amplifier circuit WELL well region WL word line WLT write data latch circuit WMBL write system main bit line WSEL write column selection circuit yrb, yraj, yrak, refj, refk selection signal

Claims (13)

N first storage nodes that store N (N is an integer greater than or equal to 1) bits, receive N-bit first write data at the time of writing, and output N-bit first read data at the time of reading;
N second storage nodes that store N-bit data, input N-bit second write data at the time of writing, and output N-bit second read data at the time of reading;
A parity generation circuit for generating first parity data for the first write data of N bits at the time of writing and generating second parity data for the second write data of N bits;
First and second parity storage nodes for storing the first and second parity data;
An error processing circuit,
The N-bit second write data is inverted data of the N-bit first write data,
The error processing circuit includes:
A first process of comparing the match / mismatch of the N-bit first read data and the N-bit second read data for each bit number;
A second process for performing parity determination using the first read data of N bits and the first parity data;
A third process for performing parity determination using the second read data of N bits and the second parity data;
When there is one matching bit number in the first process, the determination result of the second process is abnormal, and the determination result of the third process is normal, the N-bit first read data N bits when it is determined that the bit number is an error, there is one matching bit number in the first process, the determination result of the third process is abnormal, and the determination result of the second process is normal A fourth process for determining that the bit number in the second read data is an error;
And a fifth process for correcting a bit determined to be an error in the fourth process. The semiconductor device according to claim 1,
The first parity storage node is
A first positive parity storage node for storing the first parity data in a positive polarity;
A first negative parity storage node for storing the first parity data in a negative polarity;
The second parity storage node is
A second positive parity storage node for storing the second parity data in a positive polarity;
A second negative parity storage node for storing the second parity data in a negative polarity;
In the second processing of the error processing circuit, a differential amplification result of the output signal of the first positive parity storage node and the output signal of the first negative parity storage node is used as the first parity data,
In the third processing of the error processing circuit, a differential amplification result of the output signal of the second positive parity storage node and the output signal of the second negative parity storage node is used as the second parity data. Semiconductor device. The semiconductor device according to claim 1,
The error processing circuit further includes a first case where correction is performed in the fifth process, or there is no bit number matching in the first process, and the determination results of the second and third processes are The first signal of the first logic level is output in the second case where both are normal, and the first signal of the second logic level is output in cases other than the first and second cases. Semiconductor device. The semiconductor device according to claim 1,
Each of the N first storage nodes and the N second storage nodes is a flash memory cell. With a memory unit,
The memory unit is
A word line,
N (N is an integer of 1 or more) first bit lines, N second bit lines, third bit lines, and fourth bit lines that intersect the word lines;
N first memory cells respectively disposed at intersections of the word lines and the N first bit lines;
N second memory cells respectively disposed at intersections of the word line and the N second bit lines;
Third and fourth memory cells respectively disposed at intersections of the word line and the third and fourth bit lines;
A parity generation circuit that generates first parity write data for N-bit input data and generates second parity write data for N-bit inverted input data that is inverted data of the N-bit input data;
When the word line is activated in accordance with a write operation, the N-bit input data is written to the N first memory cells via the N first bit lines, and the N-bit inverted input Data is written to the N second memory cells via the N second bit lines, and the first and second parity write data are written to the third and fourth bit lines via the third and fourth bit lines. A first control circuit for writing to four memory cells;
When the word line is activated in accordance with a read operation, a signal read from the N first memory cells via the N first bit lines is amplified to thereby generate an N-bit first bit. Read data is output, and N bits of second read data are output by amplifying signals read from the N second memory cells via the N second bit lines, and the third And a second control circuit for outputting first and second parity read data by amplifying signals read from the fourth memory cell via the third and fourth bit lines, respectively.
An error processing circuit,
The error processing circuit includes:
A first process of comparing the match / mismatch of the N-bit first read data and the N-bit second read data for each bit number;
A second process for performing parity determination using the N-bit first read data and the first parity read data;
A third process for performing parity determination using the second read data of N bits and the second parity read data;
When there is one matching bit number in the first process, the determination result of the second process is abnormal, and the determination result of the third process is normal, the N-bit first read data N bits when it is determined that the bit number is an error, there is one matching bit number in the first process, the determination result of the third process is abnormal, and the determination result of the second process is normal A fourth process for determining that the bit number in the second read data is an error;
And a fifth process for correcting a bit determined to be an error in the fourth process. The semiconductor device according to claim 5.
The memory unit further includes:
Fifth and sixth bit lines intersecting the word line;
Fifth and sixth memory cells disposed at intersections of the word line and the fifth and sixth bit lines, respectively.
The first control circuit further writes the inverted data of the first parity write data to the fifth memory cell via the fifth bit line, and the inverted data of the second parity write data as the sixth bit line. To the sixth memory cell via
The second control circuit differentially amplifies a signal read from the third memory cell via the third bit line and a signal read from the fifth memory cell via the fifth bit line. As a result, the first parity read data is output, and the signal read from the fourth memory cell via the fourth bit line and the signal read from the sixth memory cell via the sixth bit line are read out. The semiconductor device is characterized in that the second parity read data is output by differentially amplifying the received signal. The semiconductor device according to claim 5.
The second control circuit includes:
N first sense amplifier circuits that amplify signals read from the N first memory cells through the N first bit lines using a predetermined first reference signal as a comparison target;
And N second sense amplifier circuits that amplify signals read from the N second memory cells via the N second bit lines using the first reference signal as a comparison target. A featured semiconductor device. The semiconductor device according to claim 7.
The second control circuit further includes:
A signal read from N first memory cells via N first bit lines is read from N second memory cells via N second bit lines. A semiconductor device comprising: N third sense amplifier circuits that amplify signals as comparison targets. The semiconductor device according to claim 5.
The error processing circuit further includes a first case where correction is performed in the fifth process, or there is no bit number matching in the first process, and the determination results of the second and third processes are The first signal of the first logic level is output in the second case where both are normal, and the first signal of the second logic level is output in cases other than the first and second cases. Semiconductor device. The semiconductor device according to claim 5.
Each of the N first memory cells, the N second memory cells, and the third and fourth memory cells is a flash memory cell. The semiconductor device according to claim 10.
The semiconductor device further includes:
A central processing unit for executing a predetermined program;
A bus connecting the central processing unit and the memory unit;
The semiconductor device according to claim 1, wherein the memory unit is a target of write and read access of the central processing unit. N first storage nodes that store N (N is an integer greater than or equal to 1) bits, receive N-bit first write data at the time of writing, and output N-bit first read data at the time of reading;
N second storage nodes that store N-bit data, input N-bit second write data at the time of writing, and output N-bit second read data at the time of reading;
An error processing circuit,
The second write data of N bits is the same data as the first write data of N bits or inverted data of the first write data of N bits,
The error processing circuit executes a first process for determining the presence or absence of an error by comparing the match / mismatch of the first read data of N bits and the second read data of N bits for each bit number. A featured semiconductor device. The semiconductor device according to claim 12, wherein
The semiconductor device further includes:
A parity generation circuit for generating first parity data for the first write data of N bits at the time of writing and generating second parity data for the second write data of N bits;
First and second parity storage nodes for storing the first and second parity data;
The error processing circuit further includes:
A second process for performing parity determination using the first read data of N bits and the first parity data;
A third process for performing parity determination using the second read data of N bits and the second parity data;
When there is one bit number determined to be an error in the first process, the determination result of the second process is abnormal, and the determination result of the third process is normal, the first read of N bits The bit number in the data is determined to be an error, there is one bit number determined to be an error in the first process, the determination result of the third process is abnormal, and the determination result of the second process is normal A fourth process for determining that the bit number in the second read data of N bits is an error,
And a fifth process for correcting a bit determined to be an error in the fourth process.

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