JPH08263391A - Information processor - Google Patents

Abstract

PURPOSE: To efficiently test a memory (RAM) where an error correction code is stored. CONSTITUTION: The information processor provided with a RAM 1, where the error correction code(ECC) which includes check bits generated by exclusive OR of even information bits and is capable of one-bit error correction and >=2-bit error detection is stored, is provided with an ALL 1 test mode flag 7 which goes to '0' for ALL0 of test data at the time of normal operation or RAM test and goes to '1' for ALL1 of test data at the time of RAM test, and is provided with the function, which adds the value of the ALL1 test mode flag to write data of the RAM 1 and generates all check bits by exclusive OR of odd information bits and writes only write data and generated check bits in the RAM 1, and the function which performs error correction and detection of read data of the RAM 1 based on ECC generated by adding the value of the ALL1 test mode flag 7 to a proper bit position of information bits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device of an information processing device, and more particularly to a memory test.

[0002]

2. Description of the Related Art In a conventional information processing apparatus, a random access memory (hereinafter, RA) for storing an error correction code is used.
As the test method of M), a method of generating an error correction code for an appropriate test pattern by using a normal memory access processing function, storing the error correction code in a RAM, and then reading the error correction code to detect an error of the error correction code. Is taken.

The error correction code includes 1-bit error correction and 2 bits.
A sub-bit error detection code (hereinafter referred to as ECC) is used.

Next, a conventional information processing apparatus will be described with reference to the drawings.

FIG. 4 shows an embodiment of this conventional information processing apparatus.

RA for storing ECC in the memory device 40
M1, ECC generation circuit 42, error correction / detection circuit 43
It is included.

The memory control device 50 controls the memory device 40. The signal line 201 is a signal line for sending the address of the RAM 1, and the signal line 202 is a write instruction (hereinafter referred to as WE) signal to the RAM 1.

In the memory device 40, the memory control device 50
RA received from the register 4 via the signal line 203 from
EC from the M1 write data in the ECC generation circuit 42
C is generated, and the signal line 202 is generated according to the WE of the signal line 201.
This ECC is set to the address indicated by.

Further, in the error correction / detection circuit 43, the syndrome is generated from the ECC of the address indicated by the signal line 202 of the RAM1. When the result of the error detected in the syndrome is a 1-bit error, the error-corrected data is set in the register 5 and the 1-bit error information is set in the error flag 6. Memory controller 5
At 0, the data of the register 5 and the information of the error flag 6 are received via the signal line 101 and the signal line 102, respectively. In the case of a 2-bit error, 2-bit error information is set in the error flag 6 and the content of the error flag 6 is reported to the memory controller 50 via the signal line 102.

When the RAM 1 test is processed in the memory device 40 according to the instruction of the signal line 204 of the memory control device 50, the test data is set in the register 4 from the memory control device 50 in the signal line 203, and the same process as described above is performed. Then, the ECC generated by the ECC generation circuit 42 is set in the RAM 1. When all writing to the RAM1 is completed, the memory control device 50 reads the RAM1. The ECC read at this time is subjected to error detection in the error correction / detection circuit 43 and is set in the error flag 6. The information of the error flag 6 is reported to the memory controller 50 via the signal line 102.

When the normal processing and the test processing are both used as in the apparatus shown in FIG. 4, considering the operating rate as an information processing apparatus, it is desired that the test time be shorter, which is one of the means for shortening the test time. One example is to reduce the test data pattern.

As test data, if all the bits of the RAM can be tested by writing "1" and reading correctly and by writing "0" and reading correctly, it can be said that the test is covered. You have to choose to meet.

In the ECC, depending on the data length, all data bit values are "1" (hereinafter referred to as ALL1. ALL.
0 is also the same), and at this time, RA is made with two data patterns of ALL1 and ALL0.
M tests can be covered.

FIG. 2 shows an example of ECC generation. E in FIG.
The CC is composed of 33 bits of information bits D1 to D33 and 7 bits of check bits C1 to C7. The check bits C1 to C7 are obtained by the exclusive OR of the bits corresponding to the bit positions where "1" is set in each of the first to seventh rows among the information bits D1 to D7. As can be seen from FIG. 2, the number of information bits for each check bit is an odd number. Therefore, the information bits D1 to D33
If all the values of 1 are 1, the values of the check bits C1 to C7 are also all 1. That is, the ECC shown in FIG. 2 is 40 bits A
It is an ECC that can take the value of LL1.

When the ALL1 coding of ECC is impossible, at least three data patterns are required, and the processing time becomes long.

In an information processing apparatus, a 32-bit (4 byte) length is common as a data processing unit, but 32
The ECC generated by adding 7 check bits to the information bits cannot be ALL1.

Therefore, the ECC check test of the RAM which processes 32-bit data cannot be covered unless the data pattern of at least 3 patterns is processed.

[0018]

In the memory test of the conventional information processing apparatus described above, at least three test data patterns are prepared when a check test is performed with an error correction code in which all bits cannot take the value 1. Therefore, there is a problem that the memory test time becomes long.

[0019]

An information processing apparatus according to the present invention generates an error correction code by adding an ALL1 test flag indicating that test data at the time of a memory test is ALL1 and an ALL1 test flag to the data. Means and
Means for performing error detection / correction by adding the ALL1 test flag to the error correction code read from the memory,
By the ALL1 test flag, the generation means, and the error detection / correction means, a test of a memory storing an error correction code that cannot take a value in which all bits are all 1 is performed, and virtually all bits have a value of 1. The feature is that the test is performed on the error correction code.

An information processing apparatus according to the present invention has a memory for storing an error correction code capable of detecting 1-bit error correction and 2 bits or less of an error, an error correction code generation circuit, and an error correction code syndrome generation circuit. An information processing device, all bits of which have a value of 1 in a test of the memory.
Is 1 when a test is performed on certain data, and a flag that indicates a value 0 when a test is performed on other data and other than the memory test process, and an even number of check bits generated by the error correction code generation circuit. In the case of the exclusive OR of the information bits of, the means for exchanging the exclusive OR of the check bit and the flag value and replacing the result with the check bit stored in the memory, and the syndrome generated in the syndrome generation circuit. Of the above, if the check bit that is the element for generating the syndrome is one that has been replaced by the above-mentioned means, means for making the syndrome an exclusive OR of flags for error correction and detection It is characterized by having and.

[0021]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the information processing apparatus of the present invention.

The present embodiment is an information processing apparatus having a memory device 10 and a memory control device 20, and also processes a memory test.

The memory device 10 includes a RAM1 and a RAM1.
Flag register 7 indicating the ALL1 test mode of
An error is detected from the register 4 that holds the write data of the AM1, the ECC generation circuit 2 that generates an ECC for the data of the register 4, and the ECC read from the RAM1.
It comprises an error correction / detection circuit 3 for correction, a register 5 for holding read data, and an error flag 6.

The memory controller 20 includes a RAM address signal line 201, a write instruction (WE) signal line 202, and RA.
M test mode signal line 204, ALL1 test signal line 2
The memory device 10 is controlled by 05, and RAM write data is sent to the memory device 10 via the signal line 203. Further, the read result of the RAM 1 is received via the signal line 101 and the signal line 102.

Next, details of this embodiment will be described with reference to FIG.

The information processing apparatus according to the present embodiment performs data processing units such as RAM reading and writing with 4 bytes (32 bits).

RAM1 has 32 information bits and 7
It is a memory that stores an error correction code (ECC) that can detect 1 bit error correction and 2 bits or less error consisting of check bits. The memory controller 20 sets the 32-bit data in the write data register 4 via the signal line 203. In the memory device 10, the ECC generation circuit 2 generates an ECC from the write data in the register 4,
RAM controlled by the signal line 202 and indicated by the signal line 201
This ECC is set to the address of 1.

In the memory device 10, error correction / correction
In the detection circuit 3, the syndrome is generated from the ECC indicated by the signal line 201. In the error correction / detection circuit 3,
When a 1-bit error is detected from the syndrome, ECC
Error is corrected, the corrected data is set in the register 5, and 1-bit error information is set in the error flag 6. Also, if a 2-bit error is detected, 2
Bit error information is set in the error flag 6. In the memory control device 20, the information of the read data register 5 and the error flag 6 is transferred to the signal line 101 and the signal line 102.
Receive each via.

In this way, the information processing apparatus of this embodiment realizes the memory write processing and memory read processing.

The information processing apparatus also processes the memory test by using the above-mentioned normal memory access means.

The memory controller 20 instructs the memory device 10 to test the RAM 1 via the signal line 204. The signal line 205 is a signal indicating the type of RAM test. When the signal line 205 sends "1", the RAM1 test should be performed with the write data ALL1 (hereinafter ALL1
It is called a test. The ALL0 test is also the same), and the flag register 7 is set to "1" at this time. ALL1
The signal line 205 sends "0" except during the test, and the flag 7
Holds '0'. In the ALL1 test mode, the flag 7 holds "1" until the writing process and error check process (write & read check) of the ALL1 test are completed.

The register 4 of the memory device 10 is connected to the signal line 2
04 indicates the RAM test mode, and the signal line 205 indicates "1".
Is indicated, the ALL1 data is set, and if the signal line 204 indicates the RAM test mode and the signal line 205 indicates '0', the ALL0 data is set.

The ECC generation circuit 2 generates an ECC for the data in the register 4.

In the ECC generation circuit 2, the value of the ALL1 test mode flag 7 is added to the 32-bit data input from the register 4 to form 33-bit virtual data. 33 bits of this virtual data are applied to the information bits D1 to D33 in FIG. The flag 7 added at this time is applied to the information bit D33, and the check bits C1 to C7 are obtained by exclusive OR according to the rule of FIG. 2 described in the prior art. In the ALL1 test of the RAM1, the value of the flag 7 is "1" and all the bits of the write data are "1". Therefore, all the information bits D1 to D33 contain "1" and all the check bits C1 to C7. Is generated at '1'. Flag 7 for ALL0 test
Is "0", the value "0" is added to the 32-bit ALL0 data to become 33-bit ALL0 data, and the check bits C1 to C7 generated from this are ALL0. Further, since the ALL1 test mode flag 7 indicates "0" even during the normal memory access processing, the information bit D33
Becomes "0", and the check bits C1 to C7 generated by the ECC generation circuit 2 at this time are the same as the check bits generated by using only 32 bits of the original data as information bits.

E generated by the ECC generation circuit 2 in this way
The 33rd information bit of CC is an information bit that is virtually embedded so that the data stored in RAM1 becomes ALL1 and is not stored in RAM1.

In FIG. 1, the control device 20 has a signal line 20.
When the RAM test processing is instructed in 3, the writing to the RAM 1 is instructed by the signal line 202. When the memory control device 20 finishes writing one test data pattern for all the addresses in the RAM 1, the memory control device 20
1 is read and the error check of RAM1 is performed. The error check is processed in the error correction / detection circuit 3.

When the ECC of the RAM 1 is read out, the error correction / detection circuit 3 adds the ALL1 test mode flag 7 to this ECC to form a 40-bit ECC and generate a syndrome. In the error correction / detection circuit 3,
The syndrome is generated according to the table shown in FIG. Referring to FIG. 3, bits E1 to E32 are bits D1 to D32 in FIG. 2 written and read in the RAM 1, and bits E34 to E40 are bits C1 in FIG.
What is read out by writing to C7 in RAM1 is stored, and the value of the ALL1 test flag is stored in bit E33. The generation of the syndrome can be obtained by the exclusive OR of the bits E0 to E40 corresponding to the bit positions where "1" is set in the first to seventh rows.
Here, since the bit E33 is the value of the ALL1 test mode flag, it is valid in the ALL1 test,
It has no meaning except during the ALL1 test. Therefore, 40-bit virtual ECC error detection is performed in the ALL1 test mode, and RA detection is performed except in the ALL1 test.
The 39-bit error detection as it is read from M1 is performed.

As described above, in this embodiment, the data in the RAM is stored in the virtual ECC of 40 bits during the ALL1 test.
By treating the RAM as an original 39-bit ECC except during the ALL1 test, the RAM storing the ECC in which the ALL1 pattern cannot be generated is subjected to two tests of ALL1 write & read check and ALL0 write & read check. It is designed to cover all RAM tests.

[0040]

As described above, the information processing apparatus of the present invention can perform normal memory access processing without investing hardware in testing a memory having an error correction code that cannot generate a pattern of all bit values 1. By making it possible to perform the test with the pattern data of all bit values 1 by using the means, it is possible to shorten the memory test time without impairing the completeness of the test and prevent the deterioration of the operating rate of the information processing device. The effect is that you can.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an information processing apparatus of the present invention.

FIG. 2 is a diagram for explaining generation of an error correction code.

FIG. 3 is a diagram for explaining the generation of a syndrome.

FIG. 4 is a block diagram of an embodiment of a conventional information processing device.

[Explanation of symbols]

 1 Random Access Memory (RAM) 2,42 Error Correction Code (ECC) Generation Circuit 3,43 Error Correction / Detection Circuit 4 Write Data Register 5 Read Data Register 6 Error Flag 7 ALL1 Test Mode Flag 10,40 Memory Device 20,50 Memory control device 101, 102 signal line 201-205 signal line

Claims (2)

[Claims] 1. The test data at memory test is ALL.
ALL1 test flag indicating 1 and the AL
The L1 test flag is added to the data to generate an error correction code, and the ALL1 test flag is added to the error correction code read from the memory to detect and correct the error. , A test of a memory that stores an error correction code that cannot take a value in which all bits are all 1 by the generation means and the error detection / correction means An information processing device characterized by performing a test of a correction code. 2. An information processing apparatus comprising: a memory for storing an error correction code capable of detecting an error of 1 bit and 2 bits or less; a generation circuit for the error correction code; and a syndrome generation circuit for the error correction code. In the memory test, when a test is performed with data in which all the bits have a value of 1, a flag indicating a value of 1 is used, and when a test is performed with other data, and a value other than the memory test process, a flag indicating a value of 0 is set. When the check bit generated by the error correction code generation circuit is formed of an exclusive OR of an even number of information bits, an exclusive OR of the check bit and the value of the flag is taken,
A means for replacing the result with a check bit stored in the memory; and a check bit, which is an element for generating the syndrome among the syndromes generated by the syndrome generation circuit, is replaced by the means. In this case, the information processing apparatus further comprises means for taking an exclusive OR of the flags for the syndrome to make a syndrome for error correction and detection.