JP2001167596A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid making algorithm complex in normal write-in operation and write-in operation before erasion. SOLUTION: This device is constituted so that a test bit is generated using a test bit generation matrix in which the number of elements of '1' of each row are the number of pieces required for generating a test bit and an odd number, in normal write-in operation and write-in operation before erasion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device used for an error correction circuit (hereinafter, referred to as an ECC circuit).

[0002]

2. Description of the Related Art In a nonvolatile memory such as a flash memory mounted on a highly reliable device, a defect rate (failure rate) has been a problem. Therefore, non-volatile memories for high reliability applications having an error correction function have been developed. An error correction method in this error correction function is, for example, as described in Japanese Patent Application No. 3-151809, by adding a plurality of redundant bits to information bits to be accessed to form a Hamming code. There is something to be done. If the information bits of the N bit performs error correction of 1 bit is required X-bit error correction code (check bit) of the test bit is determined by (N + X) + 1 ≦ 2 ^X. For example, when 1-bit error correction is performed on 32 information bits, a 6-bit error correction code (check bit) is required according to the above equation. The check bit generation matrix (A) for generating the check bits is represented by the following formula:
The check bits (P) are determined by a matrix of two columns, and the check bits (P) are combined with the check bit generation matrix (A) and the 32-bit information bits (D0 to D3).
It is obtained by the logical operation shown in Equation 2 of 1).

[0003]

(Equation 1)

(Equation 2) On the other hand, at the time of error detection, the matrix (B) of 6 rows × 38 columns shown in Equation 3 and the data including the 32-bit information bits (D0 to D31) including the 6 check bits (P0 to P5) are expressed in Equation 4. The position of the error bit can be specified by the logical operation shown.

[0004]

(Equation 3)

(Equation 4) A conventional ECC circuit having such a function includes a check bit generation circuit that generates a check bit for rewritten data at the time of writing, a syndrome calculation circuit that determines whether there is an error based on the information bit and the check bit at the time of reading, And a correction circuit for inverting and correcting the information bit when an error occurs.

Next, an access operation of a nonvolatile memory (FLASH EEPROM) having such an ECC circuit and performing erasing in a plurality of address units (blocks) will be described. First, in a read operation, a 32-bit information bit selected for an externally input address and a 6-bit check bit associated therewith are simultaneously accessed and read via a read circuit. The read result is input to the syndrome calculation circuit, and
Are performed, and it is checked whether or not the read information bit has an error. When an error is detected in the information bit in the syndrome calculation result, the information bit is corrected and output by the correction circuit based on the detection result. Next, in the write operation, 6-bit check bits are generated by the check bit generation circuit as shown in the above equation 2 for the 32-bit write data input from the outside. The write data is 38 bits for one address, and 32 information bits and 6 check bits are separately held.

In the erasing operation, the information bits and the check bits are simultaneously erased. Assuming that the value of each bit at the time of erasing is “1”, the values of all information bits and check bits become “1”. Naturally, each bit is read in this state, and if all the information bits become "1" and all the check bits become "1", all the bits read out to the outside become "1", which is a syndrome. This means that no error was detected in the calculation.

Originally, the matrix (B) shown in the above equation (3) at the time of syndrome calculation can be set arbitrarily, but inconsistencies may occur in the above-described erased state. In order to avoid these, if the data is internally inverted so that all the data in the erased state becomes “0”, the syndrome result becomes “0” no matter what matrix is set, and contradiction is avoided. be able to.

On the other hand, in a nonvolatile memory such as a flash EEPROM which performs intelligent control, writing is performed to all addresses before performing an erasing operation, and the threshold values of cells before erasing are made uniform. In some cases, an erase operation is performed thereafter to narrow the threshold distribution after erasure.

In such a method, in a write operation before erasure, all "1" information bits are all "1" check bits, or all "0" information bits are all "0". Check bits need to be written. Therefore, a check bit generation matrix that generates check bits of “1” for all information bits of “1” and check bits of “0” for all information bits of “0” is required. On the other hand, in a normal write operation, since the check bit generation matrix is set arbitrarily,
The check bits do not always become "1" for all "1" information bits. Therefore, the check bit generation matrix used for the normal write operation cannot be used for the write operation before erasure. For this reason, in the case where the above-mentioned method is adopted, it is necessary to change the algorithm of the erasing operation including the writing operation before erasing with respect to the one not adopting the method.

On the other hand, in the above-mentioned erasing operation, in a nonvolatile memory such as a flash EEPROM provided with an ECC circuit, information bits and check bits are simultaneously erased. For this reason, the current during the erasing operation has increased, and the current consumption has increased. Further, since the information bit and the inspection bit are read at the same time, the current at the time of reading increases, and the current consumption increases.

[0011]

As described above,
In a conventional nonvolatile memory having an ECC circuit, which adopts a method of adjusting a threshold distribution after erasing, a similar inspection bit generation matrix is used in a normal writing operation and a writing operation before erasing. Could not be used. For this reason, there has been a problem that the algorithm in the erasing operation is complicated. Also. Since the information bit and the inspection bit were simultaneously erased or read, a problem such as an increase in power consumption was caused.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object the complexity of an algorithm in a normal write operation and a write operation before erasure for adjusting the threshold value of a cell. Avoiding
An object of the present invention is to provide a nonvolatile semiconductor memory device that can achieve low power consumption.

[0013]

Means for Solving the Problems To achieve the above object, a first means for solving the problem is that an error necessary for performing error correction corresponding to each input information data is provided. A correction code (check bit) is generated based on a check bit generation matrix, and the check bit generation matrix is an odd number of “1” elements in each row that satisfies the minimum number required to generate a check bit. A check bit generation circuit comprising a matrix, a holding unit for writing the information data and the error correction code generated by the check bit generation circuit, and holding the written information data and the error correction code; and And a write circuit for writing the error correction code to the holding unit, and an erasing circuit for erasing the information data and the error correction code held in the holding unit A reading circuit for reading the information data and the error correction code held in the holding unit, and an error in the information data read by the reading circuit based on the error correction code read by the reading circuit. A checking circuit for checking whether or not there is an error, and a correcting circuit for correcting the erroneous information data when there is an error in the checking result of the checking circuit.

[0014] The second means is the first means,
The erasing circuit erases the information data and the error correction code held in the holding unit separately.

According to a third aspect of the present invention, in the first or the second aspect, the readout circuit reads the information data and the error correction code held in the holding section separately.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to one embodiment of the present invention. In FIG. 1, the nonvolatile semiconductor memory device according to this embodiment calculates an error correction code (check bit) required for performing error correction corresponding to each input information bit based on a check bit generation matrix. The check bit generation matrix 1 includes a check bit generation circuit 1 composed of a matrix in which the elements of "1" in each row are an odd number that satisfies the minimum number required to generate check bits, an information bit and a check bit. The check bit generated by the generation circuit 1 is written, and the information bit holding unit 2 holding the written information bit and the check bit holding unit 3 holding the check bit, and the information bits and the check bit holding units 2, 3 And an erasing circuit 5 capable of separately erasing the information bits and the check bits held in the holding units 2 and 3, respectively.
A decoder 6 for selecting the holding units 2 and 3 to be accessed in response to an address; a reading circuit 7 capable of separately reading the information bits and the check bits held in the holding units 2 and 3; And a syndrome calculation circuit serving as a check circuit for checking whether or not the information bits read from the information bit hold unit 2 by the read circuit 7 based on the check bits read from the check bit storage unit 3. 8 and a correction circuit 9 for correcting an erroneous information bit when an error is found in the check result of the syndrome calculation circuit 8. Hereinafter, as described above, 32
A case will be described in which 6-bit check bits are generated when 1-bit error correction is performed on 1-bit information bits.

The check bit generation circuit 1 calculates the above-mentioned equation (2) based on the check bit generation matrix (A) shown in the above equation (1).
, A 6-bit check bit (P) is generated.
As shown in Expression 2, each bit of the check bits P0 to P5
Is ｛a (0-5,0) × D0 + a (0-5,1) × D
.. + A (0-5, 31) × D31}. Here, + in the above expression indicates exclusive OR. Therefore, an exclusive OR (EX-OR) gate may be used to find the solution of the above logical operation. EX
In the case where the OR gate is used, in order to simplify the circuit and increase the operation speed, the number of “1” s of the elements a (0 to 5, 0 to 31) in each row of the check bit generation matrix (P) is It is necessary to reduce the input of the EX-OR gate as much as possible.
However, in order to generate 6 check bits when performing 1-bit error correction on 32 information bits, at least 14 "1" s are required in each row. Therefore, as in the conventional case, the number of “1” s in each row of the check bit generation matrix is set to 14 as shown in FIG.
Out of the check determinant shown in (1), the code for no error at the time of error check (NO1 in FIG. 2) and b (0 to 5, 32 to 3
An arbitrary matrix is selected so that the number of "1" s in each row is small and the number of "1s" in each row is the same except for the error checking code (NO2 to 7 in FIG. 2) of FIG. NO8-1
9, 23 to 42), for example, a check bit generation matrix shown in the following equation 5 is set, and an error check code (NO2 to 7 in FIG. 2) is added to the check bit generation matrix shown in the equation 5 above. The error detection matrix (B) in Expression 3 is set as shown in Expression 6, and error detection is performed.

[0019]

(Equation 5)

(Equation 6) Therefore, in such a case, the check bit generation circuit 1 is constituted by a 14-input EX-OR gate,
A bit check bit will be generated.

However, if all the inputs of the 14-input EX-OR gate constituting the check bit generation circuit 1 are "1", all the outputs are "0". Therefore, in the above-described writing before erasure, the check bit generation circuit 1 performs the above-described 1-bit operation on all the information bits of “1”.
When a 4-input EX-OR gate is used, all 6 check bits become "0". For this reason, when the check bit generation circuit 1 is configured by a 14-input EX-OR gate, it is not possible to generate all "1" check bits for all "1" information bits.
In the pre-erase write, it is impossible to write all the information bits of "1" and all the check bits of "1".

Therefore, in the check bit generation circuit 1 of this embodiment, the number of "1" s in each row of the check bit generation matrix (P) is used to perform one-bit error correction on the 32-bit information bits. Satisfies at least 14 required to generate 6 check bits, and all "1"
It is possible to generate an odd number of 15 (at least 15)
And an arbitrary matrix is selected from the parity check matrix shown in FIG. 2 in the same manner as described above (NO8 in FIG. 2).
To 19, 23 to 34, 41 to 48), for example, as shown in the following Expression 7.

[0022]

(Equation 7) Therefore, in the check bit generation matrix set as shown in Expression 7, the check bits (P0 to P5) are calculated by the logical operation shown in Expression 8 below. Further, codes for error checking (NO2 to NO7 in FIG. 2) are added to the check bit generation matrix shown in Equation 7, and the error detection matrix (B) in Equation 3 described above is set as shown in Equation 9 below. Detection is performed.

[0023]

(Equation 8)

(Equation 9) Here, + in the above expression indicates exclusive OR. Therefore,
The solution of the above logical operation can be obtained by a 15-input exclusive OR (EX-OR) gate which receives the 15 information bits shown in Expression 8 for each check bit. That is, the check bit generation circuit 1 is connected to the 15-input E
That is, it is only necessary to form an X-OR gate. When the check bit generation circuit 1 is composed of a 15-input EX-OR gate, if all the inputs of the EX-OR gate are "1", the output is "1", and if all the inputs are "0", The output is "0".

Therefore, when writing is performed before erasing the information bit holding unit 2 and the check bit holding unit 3 by the erasing circuit 5, all the information bits of "1" are used as the input data for writing. , The 15-input EX constituting the check bit generation circuit 1
-All six "1" check bits are generated by the OR gate, and all the generated "1" check bits are held together with the corresponding 32 "1" information bits via the write circuit 4 for the corresponding information bits. Part 2 is written to check bit holding part 3. Note that the same operation can be performed when “0” is written. This allows
The same check bit generation matrix can be used in the normal write operation and the write operation before erasure for adjusting the threshold value of the cell, and it is possible to avoid complication of the algorithm in the write operation. .

In addition, the incorporation of an ECC circuit eliminates the need for inverting information bits and changing the erasing algorithm, and the peripheral circuit can be configured with the same concept as when there is no conventional ECC circuit. Further, even before and after the ECC circuit is mounted, peripheral circuits such as a rewrite sequencer and a conversion circuit do not need to be changed, and write,
Circuits that affect characteristics, such as erase and read circuits, have the same number of stresses in the number of times of writing and the number of times of erasing for the memory cells for holding the information bits and the memory cells for holding the check bits. The data before mounting the ECC circuit can be used. On the other hand, in the write / erase test of the memory cell of the inspection bit holding unit, all bit write / erase does not require setting for the test.
It can be made the same as the normal operation. Further, the test vector before the mounting of the ECC circuit can be used as it is, and comparison with existing data can be easily performed in terms of characteristic evaluation.

Since the information bits held in the information bit holding unit 2 and the check bits held in the check bit holding unit 3 are separately erased by the erasing circuit 5, the operating current at the time of erasing is reduced. In addition, power consumption can be reduced. Further, since the information bits held in the information bit holding unit 2 and the check bits held in the check bit holding unit 3 are read separately by the read circuit 7, the operating current at the time of reading is reduced,
Low power consumption can be achieved.

[0027]

As described above, according to the present invention, the same check bit generation matrix can be used in a normal write operation and a write operation before erasure for adjusting the threshold value of a cell. It is possible to avoid complication of the algorithm in the writing operation. Thus, the control of the writing operation and the erasing operation can be controlled by the EC.
It becomes the same before and after the C circuit is mounted, and the one before the ECC circuit is mounted can be used. The circuit associated with the information bit and the inspection bit can be used in all of the write, erase, and read circuits, so that the characteristics can be made uniform and the design load can be reduced.

On the other hand, since the information bits and the inspection bits are separately erased or read,
Low power consumption can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a parity check matrix.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 check bit generation circuit 2 information bit holding unit 3 check bit holding unit 4 writing circuit 5 erasing circuit 6 decoder 7 reading circuit 8 syndrome calculation circuit 9 correction circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B025 AD00 AD08 AE06 5L106 AA10 BB01 BB12 GG05 GG07

Claims (3)

[Claims] 1. An error correction code necessary for performing error correction corresponding to each input information data is generated based on a check bit generation matrix, and the check bit generation matrix includes “1” of each row. A check bit generating circuit comprising an odd number of matrices in which the elements of "" satisfy the minimum number required to generate check bits, and the information data and the error correction code generated by the check bit generating circuit are written. A holding unit that holds the written information data and the error correction code, a writing circuit that writes the information data and the error correction code into the holding unit, and a writing circuit that holds the information data and the error held in the holding unit. An erasing circuit for erasing a correction code; a reading circuit for reading the information data and the error correction code held in the holding unit; An inspection circuit for inspecting the information data read by the read circuit for errors based on the error correction code read by the read / write circuit; and an error in the inspection result of the inspection circuit. in case of,
A non-volatile semiconductor storage device, comprising: a correction circuit for correcting information data having an error. 2. The non-volatile semiconductor memory device according to claim 1, wherein the erasing circuit erases the information data and the error correction code held in the holding unit separately. 3. The non-volatile semiconductor memory device according to claim 1, wherein the read circuit reads the information data and the error correction code held in the holding unit separately.