JP2000030500A - Nonvolatile semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device wherein an examination time can be reduced by interrupting the test at the time when any bits are not non-defective articles, and changing the procedure and judgment when there is a write/delete disabled bit. SOLUTION: It is judged from an output of an inverter 20 whether or not all the subject memory cells have resulted in a desired data, by setting VERIFY 1 to a level 'L', VERIFY 2 to a level 'H', charging a node 21 by transistors 19, 22, comparing a write data with a read data by an EXOR gates 11-14, and giving the comparison output to transistors 15-18. Next, a time required for write or erase fail is reduced by setting both of VERIFY 1, 2 to the level 'L', and judging whether or not all the memory cells except one memory cell have resulted in a desired data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to an electrically writable / erasable nonvolatile semiconductor memory device such as an EEPROM.

[0002]

2. Description of the Related Art In an electrically writable / erasable nonvolatile semiconductor memory device such as an EEPROM, a high electric field is generally applied to a floating gate insulated from its surroundings by an insulating film to inject or discharge charges. By doing so, data is stored by changing the threshold value of the memory cell. Since charge injection or release is performed through an extremely thin oxide film of about 10 nm, the probability of occurrence of a memory cell that does not operate properly increases as rewriting is repeated. Specific problems include that the threshold value does not change at all, and the time required to reach the desired threshold value becomes extremely slow. Therefore, in the EEPROM, the number of times of writing / erasing is generally limited to about 100 to 1,000,000 times.

Further, EEPROMs having an automatic writing / erasing function are generally used. This automatic writing function is based on the logic circuit inside the EEPROM.
An operation of applying a write pulse and an operation of determining whether or not desired data has been written to a target memory cell to be written (hereinafter, referred to as a VERIFY operation) are repeated so that all of the target memory cells have the desired data. At this point, the pulse application and the VERIFY operation are terminated, and a signal for notifying that the writing has been completed is output to the outside of the EEPROM.

Similarly, automatic erasing is performed by applying an erasing pulse,
When the RIFY operation is repeated and all the target memory cells are in the erased state, the pulse application and the VERIFY operation are terminated, and a signal is output to the outside of the EEPROM to inform that the erase has been completed.

FIG. 6 is a block diagram of a conventional EEPROM. In FIG. 6, the memory cell array 1 includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells connected to these bit lines and word lines, although not shown. The memory cell has a source electrode, a drain electrode, a floating gate electrode, and a control electrode. A corresponding word line is connected to the control gate electrode of each memory cell, and a corresponding bit line is connected to the drain electrode.

X decoder 2 receives an X address signal and selects one word line from a plurality of word lines of memory cell array 1. Y decoder / sense amplifier 3 receives a Y address signal, selects one bit line from a plurality of bit lines of memory cell array 1, amplifies data read to a corresponding bit line by a sense amplifier, and inputs / outputs the data. 5 or write the data input from the input / output buffer 5 to the specified memory cell.

The control circuit 4 performs various controls in the EEPROM. The status register 6 stores various statuses. The verify circuit 7 receives a signal from the control circuit 4, determines whether or not the data from the Y decoder / sense amplifier 3 is desired data, and provides the result to the control circuit 4.

FIG. 7 is a circuit diagram showing an example of the verify circuit shown in FIG. In FIG. 7, a verify circuit 7
Is to write 4-bit data at the same time, and EXOR
Gates 11 to 14 and n-channel MOS transistor 1
5 to 18, a p-channel MOS transistor 19 and an inverter 20.

To each of two inputs of each EXOR gate 11 to 14, read data 1 to 4 are inputted to one end, and write data 1 to 4 are inputted to the other end.
Outputs 1 to 14 are input to gates of n-channel MOS transistors 15 to 18, respectively. n-channel MO
The sources of S transistors 15 to 18 are grounded, and the drains are connected to node 21. A p-channel MOS transistor 19 is connected between the power supply and the node 21,
The VERIFY signal is input to the gate. The potential of the node 21 is inverted by the inverter 20, and RESULT
Is supplied to the control circuit 4.

FIG. 8 is a flow chart for explaining the operation of verify circuit 7 shown in FIG. I in FIG. 8 is the number of times the VERIFY operation is repeated, and in step (abbreviated as SP in the drawing) SP1, for example, I
= 15 times, and write data 1 is applied to one input terminal of EXOR gate 11 in step SP2, for example.
On the other hand, the read data 1 in the VERIFY operation is input to the input terminal, and the EXOR gate 11 compares the two. If they match, the transistor 15 turns on, and if they do not match, the transistor 15 turns off. The other transistors 16 to 18 perform the same operation according to the outputs of the EXOR gates 12 to 14. When all the transistors 15 to 18 are turned off, step S
In P3, the VERIFY signal causes the transistor 19
Is turned on, the node 21 is charged to the "H" level, and the "H" level is inverted by the inverter 20 and R
ESULT goes to "L" level.

When at least one of the transistors 15 to 18 is turned on, the level of the node 21 becomes a value determined by the resistance ratio between the transistor 19 and the transistors 15 to 18. By determining the transistor size such that the value is lower than the threshold value of the next-stage inverter 20, RE
SULT goes to "H" level.

In step SP4, when it is determined that RESULT has become "H" level,
At 5, it is determined whether or not I has become larger than the maximum value, as shown in FIG. 8.
Then, VERIFY is performed again to determine whether the write data matches the read data. If the write data 1-4 match the read data 1-4, RESUL
T = “L” level, it is determined that writing is normal, and the process ends. If any of the write data does not match the read data, and the VERIFY operation has been performed 15 times, the process ends as a write failure.

In the VERIFY operation, the judgment is made under a more severe condition than in the normal read operation in consideration of a voltage operation margin, a temperature operation margin, or a change with time of the threshold value of the memory cell 1.

[0014]

In the above-mentioned EEPROM, when a bit whose threshold value does not change at all is generated, if the writing / erasing using the automatic writing / erasing function is performed, the VERIFY operation is performed by the bit. Without passing
After performing a write / erase operation for a maximum time determined by a logic circuit inside the EEPROM, a write / erase operation is performed outside the EEPROM.
A signal notifying that erasing has been completed and a signal notifying that writing / erasing has failed are output. Also,
If a bit occurs that takes a very long time to reach the desired threshold value, the time to end the write / erase operation will be very long.

As described above, when the threshold value does not change or when a bit occurs that takes a very long time to reach the desired threshold value, a write pulse for writing the bit causes another bit to be applied. Could adversely affect the bits that should work correctly and cause other bits that would work correctly to malfunction.

Therefore, a main object of the present invention is to reduce the test time by suspending the test at the time when all the bits are not good when there are bits that cannot be written / erased, and changing the procedure and judgment. An object of the present invention is to provide a nonvolatile semiconductor memory device that can be used.

[0017]

The invention according to claim 1 is
An electrically writable / erasable non-volatile semiconductor memory device, comprising a plurality of memory cells each connected to a plurality of bit lines and a plurality of word lines, and a read circuit for reading data of the memory cells from the bit lines. Means, writing means for writing data to a memory cell, erasing means for erasing data in the memory cell, and all the target memory cells having desired data after writing by the writing means or erasing by the erasing means. And two types of determination means for determining whether or not all the memory cells except for one to several memory cells have become the desired data. .

[0018] The invention according to claim 2 includes changing means for changing a writing or erasing method based on two types of determination results by the determining means.

According to a third aspect of the present invention, there is provided a changing means for changing a judging method based on two kinds of judgment results by the judging means.

[0020]

FIG. 1 is a circuit diagram showing a verifying circuit according to an embodiment of the present invention. In the conventional verify circuit shown in FIG. 7, one VERIFY signal is supplied to the gate of the p-channel MOS transistor 19. However, in the embodiment of FIG. 1, a p-channel MOS transistor 22 is newly provided in parallel with the p-channel MOS transistor 19. And p-channel M
The VERIFY signal 1 is applied to the gate of the OS transistor 19.
And a VERIFY signal 2 is input to the gate of the p-channel MOS transistor 22. Other configurations are the same as those in FIG.

Next, writing by the verifying circuit shown in FIG. 1 will be described. The same applies to erasing. VERIFY signal 1 = "L", VERIFY signal 2
= “H” level, as in FIG.
Is "H" if all of the transistors 15 to 18 are off.
Level, and RESULT becomes the “L” level. However, when any one of the transistors 15 to 18 is turned on, RESULT goes to “H” level.

When the VERIFY signal 1 is at the "L" level and the VERIFY signal 2 is at the "L" level, when all of the transistors 15 to 18 are turned off or one of them is turned on, RESULT goes to the "L" level. When two or more transistors are turned on, the transistor size is determined so that RESULT attains an “H” level.

As described above, it is determined whether or not all the memory cells have become the desired data, and further, it is determined whether or not the desired data has been obtained except for one memory cell from all the memory cells.

FIG. 2 is a flowchart for explaining the operation of the embodiment of the present invention. Referring to FIGS. 1 and 2, a case where a defect occurs due to writing / erasing will be described.

In the embodiment shown in FIG. 2, it is determined whether or not all the target memory cells have become the desired data, and the desired data is obtained by removing one memory cell from all the memory cells. By determining whether or not the writing has failed, the time required for writing or erasing failure is reduced.

More specifically, I is VERIF
A counter for the number of Y times, which is incremented by one each time VERIFY is performed. If the writing does not end even when I reaches the maximum number of writings, the writing is completed by a write failure. J is the number of times that desired data has been obtained except for one of all memory cells. n is a coefficient for determining how many times writing is to be continued after desired data has been obtained except for one from all the memory cells, and the value is determined by reflecting variations in the characteristics of the memory cells.

Now, it is assumed that n = 1. Step SP11
, I = 1 and J = 1 are set and (I, J) =
In step SP12, a write pulse is applied to the EXOR gates 11 to 14 and compared with the read data, and the comparison output is output from the transistors 15 to
18 gates. On the other hand, at step SP13, VERIFY1 is set to "L" level,
FY2 is set to "H" level, transistor 19 is turned on, transistor 22 is turned off, and node 21 is charged to a predetermined potential.

When all of the transistors 15 to 18 are turned off in response to the comparison output of the EXOR gates 11 to 14, the node 21 goes high and RESULT goes low.
Level, and when one of the transistors is turned on, RESULT attains an "H" level.

In step SP14, RESULT is "H".
If it is determined that the level is the level, it is determined whether or not I is the maximum value in step SP15. If it is not the maximum value, I is incremented by one in step SP16 (I, J).
= (2, 1), and VERI is determined in step SP17.
By setting FY1 = “L” level and VERIFY2 = “L” level, it is determined whether desired data is obtained except for one memory cell from all memory cells.

Here, if at least two of the transistors 15 to 18 are turned on, the RES is set at step SP18.
It is determined that ULT is at the “H” level and that two or more memory cells have been completely written, and step SP1 is performed again.
Returning to 2, the second write pulse is applied. Then 2
If the state where writing has not been completed for more than one memory cell continues, the state of returning from step SP18 to step SP12 continues each time, so that I and J are (I, J) = (3, 1) → (4, 1).
→ (5,1) → (6,1) → Then, for example, for the first time, R
When ESULT goes to "H" level and RESULT goes to "L" level in step SP18, writing is completed except for one memory cell, and I and J become (I, J).
J) = (7,2).

Thereafter, assuming that the state of completion of writing except for one memory cell continues, the state of returning from step SP20 to SP12 continues, and I and J become (I, J) =
(8,3) → (9,4) → (10,5) → (11,6)
And change. Then, when (I, J) = (11, 6), the formula n × (I−J) <J in step SP20 is used.
Is 1 × (11−6) = 5 <6, the routine of the flowchart is performed, and the write failure is ended 2 to complete the writing.

Therefore, in this case, the fifth VERI
Up to FY, two or more memory cells have not been written yet, and the writing has been completed except for one memory cell in the sixth VERIFY, and the writing routine ends when the processing continues up to the tenth VERIFY. Will be.

Also, up to the fifth VERIFY, 2
VERI has not completed writing of more than one memory cell,
In the state where writing has been completed except one memory cell in FY,
If n = 2, the writing routine ends when the state of completion of writing except for one memory cell continues up to the fifteenth VERIFY. If n = 0.6, the eighth VER
Up to IFY.

FIG. 3 shows an example of variations in the write characteristics of the flash memory. Next, the coefficient n reflecting the variation in the characteristics of the memory cells will be described. In FIG. 3, the number of write pulses of the memory cell is distributed between 2 and 10.
That is, a memory cell which is written by 2 to 10 times of pulse application can be determined as a non-defective product. Therefore, FIG.
The memory cell indicated by is likely to be a memory cell that cannot be converted to desired data until the end when writing is performed, but is a non-defective memory cell within the range of variations in the characteristics of the memory cell. Therefore, it is necessary to apply several more write pulses until the desired data is obtained.

On the other hand, the memory cell shown in FIG. 3B is far from the variation in the write characteristics and can be determined as a defective memory cell. Such an intrinsic defective memory cell cannot provide desired data until the end.
When the number of memory cells becomes equal to one, it is necessary not to apply a write pulse more than necessary.

In one embodiment of the present invention, when desired data is obtained by removing one memory cell from all the memory cells, writing is completed in consideration of the influence on other memory cells. However, as described above, it is necessary to determine whether one memory cell that has not been written is within the range of the variation in the characteristics of the memory cell, or whether it is an intrinsic defect that largely deviates from the variation. .

N is a coefficient that is determined for each product by evaluating such variations in characteristics in product development. If the variation in the characteristics is small, n is set to a small value. In this case, the distribution in FIG. 3 becomes sharp, so that it is possible to determine (variation in characteristics) and (defective intrinsic) even if the number of times of writing is small. If the variation in the characteristics is large, the distribution width in FIG. 3 is widened, so that it is not possible to distinguish between (variation in the characteristics) and (defective intrinsic) unless n is set to a large value. As a result, the optimum number of write pulses can be determined for each product, and (variation in characteristics) and (intrinsic defect) can be determined.

It should be noted that n × (IJ) <J is merely an example, and conditions that are considered to be optimal may be set according to the memory cell characteristics and control method of each EEPROM.

When the system for controlling the EEPROM is a fault-tolerant system including an error correction circuit and the like, it is more acceptable to use the control method of this embodiment that allows a one-bit defect. It is considered that the reliability of the EEPROM and the system as a whole is improved rather than adversely affecting other memory cells. Also, the writing / erasing speed is improved.

FIG. 4 is a flowchart showing another embodiment of the present invention. In the above-described embodiment, if the one-bit defect continues, the write failure is ended at end 2; however, in this embodiment, the writing pulse application method is changed in step SP20, and the bit that is slow or cannot be written is changed. Is to be written. More specifically, the applied voltage at the time of writing is increased, or the physical mechanism of writing is changed (such as changing from FN tunneling injection to channel hot electron injection). In this case, the writing speed can be expected to be improved by using a writing method that is more efficient for bits that are writing slowly.

FIG. 5 is a flowchart showing still another embodiment of the present invention. In the embodiment shown in FIG.
If one bit failure continues, the process ends with write failure 2 and FIG.
In the embodiment shown in FIG. 5, the write pulse application method is changed, but in the embodiment shown in FIG.
Change the RIFY method. That is, step SP22
In, the write VERIFY voltage is changed. In this case as well, the operation margin at the time of subsequent reading of a bit that is slow in writing is reduced, but when used in a system such as a fault-tolerant system, it is considered that the reliability of the EEPROM as a whole is improved.

In the above description, the case of writing has been described, but the same judgment method and control method can be applied to erasing.

[0043]

As described above, according to the present invention, not only is it determined whether or not all the target memory cells have become the desired data after writing or erasing, but also one to several memory cells can be determined. By determining whether or not all the memory cells except the cell have the desired data, even if a bit occurs that takes a very long time to reach the desired threshold value, the The time required to complete the write / erase operation can be shortened. As a result, even if a bit occurs in which the threshold value does not change or the time required to reach the desired threshold value is extremely slow, another correct pulse can be applied by applying a write pulse for writing the bit. It is possible to reduce the risk of adversely affecting a bit that should operate or causing a malfunction of another bit that should operate correctly.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a verify circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the verify circuit according to one embodiment of the present invention;

FIG. 3 is a diagram showing reference values of variations in write characteristics of a flash memory.

FIG. 4 is a flowchart illustrating an operation of a verify circuit according to another embodiment of the present invention.

FIG. 5 is a flowchart showing an operation of a verify circuit according to still another embodiment of the present invention.

FIG. 6 is a block diagram showing the overall configuration of a conventional EEPROM.

7 is a specific circuit diagram of the verify circuit shown in FIG.

FIG. 8 is a flowchart for explaining a conventional VERIFY operation.

[Explanation of symbols]

1 memory cell, 2 X decoder, 3 Y decoder / sense amplifier, 4 control circuit, 5 input / output buffer, 7
Verify circuit, 11 to 14 EXOR gate, 15 to 15
18 n-channel MOS transistor, 19, 22 p
Channel MOS transistor, 20 inverter.

Continued on the front page (72) Inventor Megumi Maejima 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Inventor Nobuo Ando 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Co., Ltd. In-house F term (reference) 5B025 AA03 AD04 AD08 AD16 AE05 AE09 5L106 AA10 DD00 EE02 FF01

Claims (3)

[Claims] 1. An electrically writable / erasable nonvolatile semiconductor memory device, comprising: a plurality of memory cells each connected to a corresponding bit line and a word line; Reading means for reading the data, writing means for writing to the memory cell, erasing means for erasing the memory cell, and all the target memory cells after writing by the writing means or erasing by the erasing means. And a determination means for determining whether all the memory cells except one to several memory cells have the desired data, and determining whether the data has become the desired data. And a nonvolatile semiconductor memory device. And changing means for changing a writing or erasing condition by the writing means or the erasing means based on two kinds of judgment results by the judging means.
The nonvolatile semiconductor memory device according to claim 1. And changing means for changing a writing or erasing method by the writing means or the erasing means based on two kinds of determination results by the determining means.
The nonvolatile semiconductor memory device according to claim 1.