JP2004234739A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform control of erase, write and read by every memory transistor separately and independently. <P>SOLUTION: Every memory transistor 1 in a nonvolatile semiconductor memory is equipped with; a gate voltage selection circuit 2 which selects optionally any one of program voltage, program verify voltage, erase verify voltage or read voltage when a wordline is a signal level of one side, selects optionally any one of ground potential, the program voltage, the program verify voltage, or the erase verify voltage when the wordline is signal level of another side, and impresses it to a gate electrode; a drain voltage selection circuit 3 which selects optionally a case of impressing drain voltage to a drain electrode, a case of connecting a bit line to a drain electrode, or a case of neither impressing the drain voltage nor connecting the bit line to the drain electrode; and a source voltage selection circuit 4 which select optionally either the erase voltage or the ground potential and impresses it to a source electrode. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electrically writable and erasable nonvolatile semiconductor memory device.
[0002]
[Prior art]
As a nonvolatile semiconductor memory device, a flash memory is well known, and therefore, in this specification, a flash memory will be described as an example. In a flash memory, a memory cell is composed of one memory transistor having a floating gate. A row decoder (X decoder) for selecting a row line (word line) and a column decoder (Y decoder) for selecting a column line (bit line) are arranged in a cell array in which the memory transistors are arranged in a two-dimensional matrix, for example. Is done. A control gate, which is a so-called gate electrode of the memory transistor, is connected to a word line, and a drain electrode is connected to a bit line.
[0003]
In the above configuration, in the data write operation, a high voltage is applied to the control gates of all the memory transistors connected to the word line selected from the X decoder. Also, a high voltage is applied to the drain electrodes of all the memory transistors connected to the bit line selected from the Y decoder. At this time, the source electrode of the memory transistor is grounded. As a result, in all the memory transistors connected to the word line selected from the X decoder, electrons are injected into the floating gate, negatively charged, the threshold voltage as viewed from the control gate increases, and data is written. State.
[0004]
In the erase operation, a high voltage is applied to the source electrode and the control gate is grounded, or the control gate is grounded, for all the memory transistors constituting the cell array, or for all the memory transistors constituting the memory block having one or more word lines. Make it negative potential. As a result, the potential of the floating gate returns to neutral, the threshold voltage viewed from the control gate returns to the original state, and the data is erased.
[0005]
In a data read operation, a normal voltage is applied to the control gate of the memory transistor as a read voltage. Since the drain current does not flow in the memory transistor in the written state and the drain current flows in the erased memory transistor, the logic state “1” or “0” of the memory transistor can be distinguished.
[0006]
[Problems to be solved by the invention]
However, in the conventional flash memory, if one of the write operation, the erase operation, and the read operation is performed, the other operation cannot be performed until the operation is completed, so that the throughput cannot be improved. There is a problem.
[0007]
For example, during a write operation, a high voltage is applied to all word lines selected by the X decoder, and a high voltage is applied to all bit lines selected by the Y decoder. Therefore, when an access is performed to read a memory transistor other than a write target, a high voltage is applied from the word line selected by the X decoder and the bit line selected by the Y decoder, and erroneous writing occurs.
[0008]
In order to solve this problem, for example, Patent Document 1 discloses a nonvolatile semiconductor memory device in which two or more functions of erasing, writing, and reading can be performed simultaneously in separate memory blocks.
[0009]
However, in the technology described in Patent Document 1, although the range or content of the memory block is unknown, since the memory block is used as a unit, for example, when the SRAM is used like an SRAM, a change setting of several bits is required. Therefore, the entire memory block must be set again, which is inconvenient.
[0010]
Also, in a flash memory, the number of times of writing is limited because extra stress is applied to the memory transistor at the time of writing. Therefore, it is important to reduce the extra stress applied to the memory transistor and increase the number of times of writing. It is an issue. However, in the technology described in Patent Document 1, it is difficult to reduce the stress applied to the memory transistor because the memory block is used as a unit.
[0011]
[Patent Document 1]
JP-A-7-281952 (0024-0038, FIG. 1)
[0012]
The present invention has been made in view of the above, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of independently performing erasing, writing, and reading control for each memory transistor.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, in a nonvolatile semiconductor memory device according to the present invention, in a nonvolatile semiconductor memory device which is electrically writable and erasable, a nonvolatile transistor is applied to a gate electrode, a source electrode, and a drain electrode for each memory transistor. And a voltage selection circuit for selecting each voltage to be applied.
[0014]
According to the present invention, the control of erasing, writing, and reading can be executed independently for each memory transistor.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Preferred embodiments of a nonvolatile semiconductor memory device according to the present invention will be described in detail below with reference to the accompanying drawings.
[0016]
FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to one embodiment of the present invention. First, in order to facilitate understanding of the present invention, a general configuration and operation of a flash memory, which is a nonvolatile semiconductor memory device, will be described with reference to FIGS. FIG. 2 is a block diagram showing a general configuration example of a flash memory belonging to a nonvolatile semiconductor memory device to which the present invention is applied. FIG. 3 is a diagram illustrating the relationship between the threshold distribution of the memory transistor and the data determination threshold of the sense amplifier.
[0017]
In FIG. 2, the X decoder 51 controls n + 1 word lines WLx (WL0 to WLn). The Y decoder 52 controls m + 1 bit lines BLx (BL0 to BLm). In the illustrated example, the memory block 53 is configured using one word line WL as a unit. That is, the memory block 53 includes (m + 1) memory transistors 54 connected to one word line WL. Therefore, the cell array includes (m + 1) × (n + 1) memory transistors 54.
[0018]
The memory transistor 54 forming a memory cell includes a control gate CG and a floating gate FG, and the control gate CG is connected to a word line WLx (WL0 to WLn).
[0019]
The source electrodes S of all the memory transistors 54 constituting the memory block 53, that is, all the memory transistors 54 arranged in the column direction are connected to a source line SLx (SL0 to SLm) controlled by the erase voltage generating circuit 55 in common. I have. In each memory block 53, the drain electrodes D of all the memory transistors 54 arranged in the column direction are commonly connected to bit lines BLx (BL0 to BLm) controlled by the Y decoder 52.
[0020]
X decoder 51 includes a program voltage generating circuit 57 for generating a write (program) voltage, a program verify voltage generating circuit 58 for generating a program verify voltage for verifying write, and an erase for verifying erase. An erase verify voltage generating circuit 59 for generating a verify voltage and a read voltage generating circuit 60 for generating a read (read) voltage are connected.
[0021]
The Y decoder 52 is connected to a drain voltage generation circuit 56 that generates a drain voltage applied to the bit line BLx. The Y decoder 52 is connected to a sense amplifier 61 which amplifies and takes out a signal appearing on the bit line BLx.
[0022]
In the above configuration, in the data write operation, the high voltage generated by the program voltage generation circuit 57 is applied to the control gates CG of all the memory transistors 54 connected to the word line WLx selected from the X decoder 51. The high voltage generated by the drain voltage generation circuit 56 is applied to the drain electrodes D of all the memory transistors 54 connected to the bit line BLx selected from the Y decoder 52. At this time, the source electrode S of the memory transistor 54 is grounded. As a result, in the memory transistor 54 to be written, electrons are injected into the floating gate FG, the charge is negatively charged, the threshold voltage as seen from the control gate CG increases, and the data is written (see FIG. 3). .
[0023]
During this write operation, a high voltage is applied to all the word lines WLx selected by the X decoder 51, and a high voltage is applied to all the bit lines selected by the Y decoder. Therefore, when an access is made to read the memory transistor 54 other than the write target, a high voltage is applied from the word line WLx selected by the X decoder 51 and the bit line BLx selected by the Y decoder 52, so that an erroneous write is performed. Will happen.
[0024]
In order to execute program verification for confirming whether or not writing has been completed after writing, a program verification voltage generation circuit 58 applies a voltage to the control gate CG of the memory transistor 54 to which the high voltage generated by the program voltage generation circuit 57 is applied. The applied high voltage is applied, and the high voltage generated by the drain voltage generation circuit 56 is applied to the drain electrodes D of all the memory transistors 54 connected to the bit line BLx selected from the Y decoder 52 to perform writing. Data is sequentially extracted from the sense amplifier 61.
[0025]
Since the program verify voltage is higher than the read voltage, as shown in FIG. 3, the data judgment value (2) in the sense amplifier 61 at the time of program verification is larger than the data judgment value (1) of the sense amplifier 61 at the time of normal reading. Is also big. That is, the difference (margin) between the threshold voltage of the memory transistor 54 in the written state and the data determination value (2) in the sense amplifier 61 at the time of program verification is determined by the threshold voltage of the memory transistor 54 in the written state and the data determination value at the time of reading. It is smaller than the difference (margin) from (1). Therefore, at the time of program verification, data read from the memory transistor 54 that is not targeted for program verification lacks reliability.
[0026]
In the erasing operation, the erasing voltage generating circuit 55 connects the source line SLx to which all the memory transistors 54 constituting the cell array are connected or the source line SLx to which all the memory transistors 54 constituting the memory block 53 are connected. Apply the generated high voltage. At this time, the word line WLx to which the control gate CG of the memory transistor 54 is connected is grounded or a negative voltage is applied. As a result, the potential of the floating gate FG returns to neutral, the threshold voltage as viewed from the control gate CG returns, and the data is erased (see FIG. 3).
[0027]
If the range in which the erasing operation has been performed is called an erasing effective block, the memory transistor 54 in the erasing effective block has a leak during the erasing operation, so that the high voltage applied to the source electrode S causes the drain electrode to leak. D. The high voltage appearing at the drain electrode D of the memory transistor 54 in the effective erase block is applied to the drain electrode D of the memory transistor 54 outside the effective erase block that shares the bit line BL with the erase effective block.
[0028]
Therefore, if the memory transistor 54 outside such an effective erase block is accessed, erroneous writing may occur. If no access is made, erroneous erasure may occur due to the high voltage applied to the drain electrode D.
[0029]
In order to execute erase verify for confirming whether or not erasing has been performed after erasing, a high voltage generated by the erase verify voltage generating circuit 59 is applied to the control gate CG of the memory transistor 54 in the erase effective block, The data is sequentially read from the sense amplifier 61 to confirm that it is in a blank state.
[0030]
As shown in FIG. 3, the data judgment value (3) of the sense amplifier 61 at the time of this erase verify is smaller than the data judgment value (1) of the sense amplifier 61 at the time of reading. That is, the difference (margin) between the threshold voltage of the memory transistor 54 in the erased state and the data determination value (3) in the sense amplifier 61 at the time of erase verify is determined by the threshold voltage of the memory transistor 54 in the erased state and the data determination value at the time of reading. It is smaller than the difference (margin) from (1). Therefore, at the time of erase verify, data read from the memory transistor 54 outside the erase-effective block lacks reliability.
[0031]
As described above, in the current flash memory, data cannot be read during the data writing operation and the data erasing operation, so that there is a problem that the throughput cannot be improved.
[0032]
Therefore, in the present invention, the control of erasing, writing, and reading can be executed independently for each memory transistor 54. Hereinafter, a specific description will be given with reference to FIG. In FIG. 1, components that are the same as or equivalent to the configuration shown in FIG. 2 are denoted by the same reference numerals.
[0033]
In FIG. 1, one memory transistor 1 selected by the word line WL0 of the X decoder 51 and the bit line BL0 of the Y decoder 52 is representative of the (m + 1) × (n + 1) memory transistors shown in FIG. It is shown as an example. As shown in FIG. 1, a gate voltage selection circuit 2, a drain voltage selection circuit 3, and a source voltage selection circuit 4 are provided for each memory transistor 1.
[0034]
The gate voltage selection circuit 2 is provided between the control gate CG of the memory transistor 1 and the word line WL0. The program voltage generating circuit 57, the program verify voltage generating circuit 58, the erase verify voltage generating circuit 59, and the read voltage generating circuit 60 are connected to the gate voltage selecting circuit 2 instead of the X decoder 51.
[0035]
That is, in the gate voltage selection circuit 2, the word line WL0 is connected to one input terminal of the OR circuit. The output of the NAND circuit 27 is input to the other input terminal of the OR circuit 28. The output of the OR circuit 28 is connected to one input terminal of the NAND circuit 20. A control signal ECTL00 from a control circuit (not shown) is applied to the other input terminal of the NAND circuit 20, and an output terminal is commonly connected to the gate electrode of the NMOS transistor 21 and the gate electrode of the PMOS transistor 22.
[0036]
The source electrode of the NMOS transistor 21 is connected to the ground, and the drain electrode is connected to the drain electrode of the PMOS transistor 22. The drain electrode of the NMOS transistor 21 and the drain electrode of the PMOS transistor 22 are commonly connected to the control gate CG of the memory transistor 1. The drain electrodes of the PMOS transistors 23, 24, 25 and 26 are commonly connected to the source electrode of the PMOS transistor 22.
[0037]
The gate electrodes of the PMOS transistors 23, 24, 25 are connected to the input terminal of the NAND circuit 27, and the output terminal of the NAND circuit 27 is connected to the gate electrode of the PMOS transistor 26 and the other input terminal of the OR circuit 28. ing. The output terminal of the read voltage generation circuit 60 is connected to the source electrode of the PMOS transistor 26.
[0038]
A selection signal SEL00 is applied to the gate electrode of the PMOS transistor 23 from a control circuit (not shown). The output terminal of the program voltage generation circuit 57 is connected to the source electrode of the PMOS transistor 23.
[0039]
The selection signal SEL10 is applied to the gate electrode of the PMOS transistor 24 from a control circuit (not shown). The output terminal of the program verify voltage generation circuit 58 is connected to the source electrode of the PMOS transistor 24.
[0040]
A selection signal SEL20 is applied to the gate electrode of the PMOS transistor 25 from a control circuit (not shown). The output terminal of the erase verify voltage generation circuit 59 is connected to the source electrode of the PMOS transistor 25.
[0041]
Further, the drain voltage selection circuit 3 is provided between the drain electrode D of the memory transistor 1 and the output terminal of the bit line BL0 and the drain voltage generation circuit 56. That is, the drain voltage generation circuit 56 is connected not to the Y decoder 52 but to the drain voltage selection circuit 3.
[0042]
That is, in the drain voltage selection circuit 3, the source electrode of the PMOS transistor 31 is connected to the output terminal of the drain voltage generation circuit 56, and the drain electrode is connected to the source electrode of the PMOS transistor 32. To the gate electrode of the PMOS transistor 31, an inversion signal “bar of ECTL00” (hereinafter simply referred to as “inversion signal”) of the control signal ECTL00 is applied from a control circuit (not shown).
[0043]
The drain electrode of the PMOS transistor 32 is connected to the drain electrode D of the memory transistor 1 together with the drain electrode of the NMOS transistor 33, and the source electrode of the PMOS transistor 33 is connected to the bit line BL0. A control signal DCTL00 is commonly applied to the gate electrode of the PMOS transistor 32 and the gate electrode of the NMOS transistor 33 from a control circuit (not shown).
[0044]
Next, the source voltage selection circuit 4 is provided between the source electrode S of the memory transistor 1 and the output terminal of the erase voltage generation circuit 55. That is, in the source voltage selection circuit 4, the drain electrode of the NMOS transistor 41 and the drain electrode of the PMOS transistor 42 are commonly connected to the source electrode S of the memory transistor 1. The source electrode of the NMOS transistor 41 is connected to ground, and the source electrode of the NMOS transistor 42 is connected to the output terminal of the erase voltage generation circuit 55. A control signal ECTL00 is commonly applied to the gate electrode of the NMOS transistor 41 and the gate electrode of the PMOS transistor 42 from a control circuit (not shown).
[0045]
Hereinafter, the operation of the flash memory as the nonvolatile semiconductor device according to this embodiment will be described with reference to FIGS. In each gate voltage selection circuit 2 connected to the word line WL0, when the word line WL0 is at a low level, the control signal ECTL00 is at a high level, and one of the selection signals SEL00, SEL10, and SEL20 is at a low level, The output of the NAND circuit 27 goes high and the output of the OR circuit 28 goes high. As a result, the output of the NAND circuit 20 goes low, so that the NMOS transistor 21 performs an off operation, the PMOS transistor 22 performs an on operation, and the drain electrodes of the PMOS transistors 23, 24, 25, and 26 share a common memory transistor. 1 control gate CG. In this state, data write, program verify, and erase verify operations for the memory transistor 1 are performed.
[0046]
Further, in each gate voltage selection circuit 2 connected to the word line WL0, the output of the NAND circuit 20 becomes high when the control signal ECTL00 is low regardless of the level state of the word line WL0. The NMOS transistor 21 performs an on operation, the PMOS transistor 22 performs an off operation, and the control gate CG of the memory transistor 1 is connected to the ground. In this state, the erase operation is performed.
[0047]
In each gate voltage selection circuit 2 connected to the word line WL0, when the word line WL0 is at a high level and the control signal ECTL00 is at a high level, the output of the NAND circuit 20 is at a low level. The drain electrodes 23, 24, 25, and 26 are commonly connected to the control gate CG of the memory transistor 1. In this state, data write, program verify, erase verify, and read operations for the memory transistor 1 are performed.
[0048]
At the time of data writing, the word line WL0 for selecting the memory transistor 1 to be written is set to a high level, and the control signal ECTL00 applied to the gate voltage selection circuit 2 connected to the memory transistor 1 to be written is set to a high level. As a result, in the gate voltage selection circuit 2, the drain electrodes of the PMOS transistors 23, 24, 25, and 26 are commonly connected to the control gate CG of the memory transistor 1.
[0049]
In this state, the selection signal SEL00 given to the gate voltage selection circuit 2 connected to the memory transistor 1 to which data is to be written is set to low level, and the other selection signals SEL10 and SEL20 are set to high level. As a result, only the PMOS transistor 23 performs an ON operation, and the high voltage generated by the program voltage generation circuit 57 is applied to the control gate CG of the memory transistor 1 to which data is to be written.
[0050]
At the same time, the inversion signals of the control signals DCTL00 and ECTL00 given to the drain voltage selection circuit 3 connected to the memory transistor 1 to which data is to be written are both set to low level. Further, the control signal ECTL00 given to the source voltage selection circuit 4 connected to the memory transistor 1 to which data is to be written is set to a high level.
[0051]
As a result, in the drain voltage selection circuit 3 connected to the memory transistor 1 to which data is to be written, both the PMOS transistors 31 and 32 are turned on, and the high voltage generated by the drain voltage generation circuit 56 is applied to the memory to which data is to be written. The voltage is applied to the drain electrode D of the transistor 1. Since the NMOS transistor 33 performs an OFF operation, the memory transistor 1 to which the data is to be written is disconnected from the bit line BL0.
[0052]
In the source voltage selection circuit 4, the NMOS transistor 41 performs an ON operation, and the source electrode S of the memory transistor 1 to which data is to be written is grounded. Since the PMOS transistor 42 performs an off operation, the memory transistor 1 to which the data is to be written is disconnected from the erase voltage generation circuit 55.
[0053]
By these operations, the memory transistor 1 to which data is to be written is separated from the memory transistor 1 to which data is not to be written, and data is written independently.
[0054]
At the time of program verification, writing is performed as described above, the word line WL0 for selecting the memory transistor 1 to be subjected to program verification is set to a high level, and the gate voltage selection circuit connected to the memory transistor 1 to be program verified. 2 is set to a high level. As a result, in the gate voltage selection circuit 2, the drain electrodes of the PMOS transistors 23, 24, 25, and 26 are commonly connected to the control gate CG of the memory transistor 1.
[0055]
In this state, the selection signal SEL10 given to the gate voltage selection circuit 2 connected to the memory cell 1 to be program-verified is set to low level, and the other selection signals SEL00 and SEL20 are set to high level. As a result, only the PMOS transistor 24 turns on, and the high voltage generated by the program verify voltage generation circuit 58 is applied to the control gate CG of the memory transistor 1 to be program verified.
[0056]
At the same time, the control signal DCTL00 given to the drain voltage selection circuit 3 connected to the memory transistor 1 to be program-verified is set to a high level. Further, the control signal ECTL00 given to the source voltage selection circuit 4 connected to the memory transistor 1 to be program-verified is set to a high level.
[0057]
As a result, in the drain voltage selection circuit 3 connected to the memory transistor 1 to be program-verified, the PMOS transistor 32 performs an OFF operation, the NMOS transistor 33 performs an ON operation, and the drain electrode D of the memory transistor 1 to be program-verified. Are connected to bit line BL0. At this time, since the control signal ECTL00 is at a high level, the inverted signal of the control signal ECTL00 is at a low level, and the PMOS transistor 31 performs an on operation. However, the drain voltage generation circuit 56 performs Be separated.
[0058]
In the source voltage selection circuit 4, the NMOS transistor 41 is turned on, and the source electrode S of the memory transistor 1 to be program-verified is grounded. Since the PMOS transistor 42 performs an OFF operation, the memory transistor 1 to be subjected to the program verification is disconnected from the erase voltage generation circuit 55.
[0059]
By these operations, only the data judgment value of the sense amplifier 61 for the memory transistor 1 to be program-verified can be changed to the data judgment value (2) at the time of program verification shown in FIG.
[0060]
Next, at the time of data erasure, the control signal ECTL00 given to the gate voltage selection circuit 2 connected to the memory transistor 1 to be erased is set to a low level. The control signal ECTL00 given to the gate voltage selection circuit 2 connected to the memory transistor 1 not to be erased can be made high as described above.
[0061]
As a result, in the gate voltage selection circuit 2 connected to the memory transistor 1 to be erased, the output of the NAND circuit 20 goes high, so that the NMOS transistor 21 turns on and the PMOS transistor 22 turns off. The control gate CG of the memory transistor 1 is connected to the ground.
[0062]
In this state, the control signal ECTL00 given to the source voltage selection circuit 4 connected to the memory transistor 1 to be erased is set to a low level, and the high voltage generated by the erase voltage generation circuit 55 is changed to the source electrode S of the memory transistor 1 to be erased. Is applied.
[0063]
At the same time, the control signal DCTL00 applied to the drain voltage selection circuit 3 connected to the memory transistor 1 to be erased is set to low level to turn off the NMOS transistor 33, and the drain electrode D of the memory transistor 1 to be erased is changed from the bit line BL0 to the bit line BL0. Disconnect. At this time, the PMOS transistor 32 is turned on, but the inverted signal of the control signal ECTL00 given to the drain voltage selection circuit 3 is set to a high level to turn off the PMOS transistor 31. That is, the drain electrode D of the memory transistor 1 to be erased is not connected to the drain voltage generating circuit 56.
[0064]
With these operations, the memory transistor 1 to be erased is separated from the memory transistor 1 not to be erased, and performs its own erasing operation. Since the drain electrode D of the memory transistor 1 to be erased is separated from the bit line BL0, even if a high voltage due to leakage appears on the drain electrode D, it affects other memory transistors 1 sharing the bit line BL0. Never.
[0065]
Next, when performing the erase verify on the memory transistor 1 on which the erase operation has been performed as described above, the word line WL0 for selecting the memory transistor 1 to be erase-verified is set to a high level, and the memory transistor 1 to be erase-verified is set. Control signal ECTL00 applied to the gate voltage selection circuit 2 connected to the high level is set to a high level.
[0066]
As a result, in the gate voltage selection circuit 2 connected to the memory transistor 1 to be erase-verified, since the output of the NAND circuit 20 is low, the PMOS transistor 22 is turned on, and the PMOS transistors 23, 24, 25,. The state is such that the drain electrodes 26 are commonly connected to the control gate CG of the memory transistor 1.
[0067]
In this state, the selection signal SEL20 given to the gate voltage selection circuit 2 connected to the memory transistor 1 to be erase-verified is set to a low level, and the other selection signals SEL00 and SEL10 are set to a high level. As a result, only the PMOS transistor 25 turns on, and the voltage generated by the erase verify voltage generation circuit 59 is applied to the control gate CG of the memory transistor 1 to be erase verified.
[0068]
At the same time, the control signal DCTL00 applied to the drain voltage selection circuit 3 connected to the memory transistor 1 to be erase-verified is set to a high level. Further, the control signal ECTL00 applied to the source voltage selection circuit 4 connected to the memory transistor 1 to be erase-verified is set to a high level.
[0069]
As a result, in the drain voltage selection circuit 3 connected to the memory transistor 1 to be erase-verified, the PMOS transistor 32 performs an OFF operation, the NMOS transistor 33 performs an ON operation, and the drain electrode D of the memory transistor 1 to be erase-verified. Are connected to bit line BL0. At this time, since the control signal ECTL00 is at a high level, the inverted signal of the control signal ECTL00 is at a low level, and the PMOS transistor 31 performs an on operation. However, the drain voltage generation circuit 56 performs Be separated.
[0070]
In the source voltage selection circuit 4, the NMOS transistor 41 is turned on, and the source electrode S of the memory transistor 1 to be erase-verified is grounded. Since the PMOS transistor 42 performs an off operation, the memory transistor 1 to be erase-verified is disconnected from the erase voltage generation circuit 55.
[0071]
By these operations, only the data judgment value of the sense amplifier 61 for the memory transistor 1 to be erase-verified can be changed to the data judgment value (3) at the time of the erase verification shown in FIG.
[0072]
Next, a read operation will be described. When the selection signals SEL00, SEL10, and SEL20 applied to the gate voltage selection circuit 2 connected to the memory transistor 1 not to be written are all set to a high level during the write operation, the output of the NAND circuit 27 is changed. Since the level becomes low, only the PMOS transistor 26 performs an ON operation, and the voltage generated by the read voltage generation circuit 60 is applied to the control gate CG of the memory transistor 1.
[0073]
Similarly, when the selection signals SEL00, SEL10, and SEL20 applied to the gate voltage selection circuit 2 connected to the memory transistor 1 not subjected to the program verification during the program verification are all set to the high level, the output of the NAND circuit 27 is set to the low level. Therefore, only the PMOS transistor 26 performs the ON operation, and the voltage generated by the read voltage generation circuit 60 is applied to the control gate CG of the memory transistor 1.
[0074]
Similarly, when the selection signals SEL00, SEL10, and SEL20 given to the gate voltage selection circuit 2 connected to the memory transistor 1 not subjected to the erase verification during the erase verification are all set to the high level, the output of the NAND circuit 27 becomes the low level. Therefore, only the PMOS transistor 26 performs an ON operation, and the voltage generated by the read voltage generation circuit 60 is applied to the control gate CG of the memory transistor 1.
[0075]
Further, when the above-described erasing operation is being performed, the control signal ECTL00 given to the gate voltage selection circuit 2 connected to the memory transistor 1 not to be erased is set to a high level, and the output of the NAND circuit 20 is set to a low level. To do. At the same time, when the selection signals SEL00, SEL10, and SEL20 are all set to the high level, the output of the NAND circuit 27 is set to the low level. Therefore, only the PMOS transistor 26 is turned on, and the voltage generated by the read voltage generation circuit 60 is stored in the memory. The voltage is applied to the control gate CG of the transistor 1.
[0076]
As described above, in any of the write operation, the program verify operation, the erase operation operation, and the erase verify operation, the memory transistor 1 which is not the target is in a state where the read voltage is applied to the control gate CG independently. Can be produced.
[0077]
Then, in the drain voltage selection circuit 3 connected to the memory transistor 1 to be read, the control signals DCTL00 and ECTL00 are both set to high level, and the drain electrode D of the memory transistor 1 is connected to the bit line BL0. In the source voltage selection circuit 4 connected to the memory transistor 1 to be read, the control signal ECTL00 is set to a high level, and the source electrode S of the memory transistor 1 is connected to the ground.
[0078]
As a result, the data determination value at the time of reading by the sense amplifier 61 with respect to the memory transistor 1 to be read can always be (1) at which a sufficient margin shown in FIG. 3 can be obtained.
[0079]
Therefore, according to this embodiment, the following effects can be obtained. Since the write operation, the erase operation, and the read operation can proceed simultaneously for the entire memory, the throughput of the entire system can be improved.
[0080]
In addition, at the time of writing and at the time of erasing, each target memory transistor is cut off from other non-target memory transistors, so that a high voltage is not applied to other non-target memory transistors. That is, in the other non-target memory transistors, the application of extra stress can be reduced, and as a result, the number of write operations can be increased.
[0081]
Further, since the writing operation, the erasing operation, and the reading operation can be performed in bit units, the user can use the SRAM like an SRAM. In addition, since the nonvolatile SRAM is used, the number of components can be reduced.
[0082]
In this embodiment, an example in which a nonvolatile semiconductor memory device is applied to a flash memory in which a memory cell includes one memory transistor has been described. However, the present invention is not limited to this. In addition, the present invention can be similarly applied to, for example, an EEPROM in which a memory cell includes two elements.
[0083]
【The invention's effect】
As described above, according to the present invention, a voltage selection circuit for selecting a voltage to be applied to each of the gate electrode, the source electrode, and the drain electrode is provided for each memory transistor. And read control can be performed independently.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a general configuration example of a flash memory belonging to a nonvolatile semiconductor memory device to which the present invention is directed;
FIG. 3 is a diagram illustrating a relationship between a threshold distribution of a memory transistor and a data threshold of a sense amplifier.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 memory transistor, 2 gate voltage selection circuit, 3 drain voltage selection circuit, 4 source voltage selection circuit, 51 X decoder, 52 Y decoder, 55 erase voltage generation circuit, 56 drain voltage generation circuit, 57 program voltage generation circuit, 58 program Verify voltage generating circuit, 59 erase verify voltage generating circuit, 60 read voltage generating circuit, 61 sense amplifier.

Claims (2)

In a nonvolatile semiconductor memory device that can be electrically written and erased,
A voltage selection circuit for selecting a voltage to be applied to a gate electrode, a source electrode, and a drain electrode for each memory transistor,
A nonvolatile semiconductor memory device comprising: In an electrically writable and erasable nonvolatile semiconductor memory device, for each memory transistor,
When the word line is at one signal level, any one of the program voltage, the program verify voltage, and the erase verify voltage is arbitrarily selected, and when the word line is at the other signal level, the ground potential and the program voltage are selected. A gate voltage selection circuit for arbitrarily selecting any one of a voltage, a program verify voltage, and an erase verify voltage and applying the selected voltage to the gate electrode of the memory transistor;
A drain voltage selection circuit for arbitrarily selecting a case where a drain voltage is applied to a drain electrode of the memory transistor, a case where a bit line is connected, and a case where a drain voltage is not applied and a bit line is not connected;
A source voltage selection circuit for arbitrarily selecting any of an erase voltage and a ground potential and applying the selected voltage to a source electrode of the memory transistor;
A nonvolatile semiconductor memory device comprising:

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