JP4794231B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having a memory cell structure for storing data according to a threshold voltage level. More specifically, the present invention relates to a configuration for performing writing / erasing at high speed by adjusting a threshold voltage distribution with high accuracy in a nonvolatile semiconductor memory device.

  Nonvolatile semiconductor memory devices retain stored information even when power is shut off, and are used in a wide range of fields. A batch erase nonvolatile memory (referred to as a flash memory), which is one of nonvolatile semiconductor memory devices, has a memory cell formed of one transistor. Charges are stored in accordance with stored information in the floating gate of the memory cell transistor. The memory cell transistors have different threshold voltages depending on the amount of accumulated charges, and can store data of two or more values by associating the threshold voltages with stored data.

  In addition to the structure in which charges are stored in the floating gate of a stacked MOS transistor (insulated gate field effect transistor) such as a flash memory, the nitride film of an ONO film (oxide film-nitride film-oxide film) under the control gate is used. There is also a non-volatile memory having a memory cell structure for storing electrons and storing information. Also in this memory cell structure, information is stored by utilizing the fact that the threshold voltage varies depending on the amount of stored charge.

  In such a nonvolatile semiconductor memory device, when changing the threshold voltage of the memory cell transistor, charges (electrons) are moved through the insulating film. Therefore, the writing / erasing speed (charge moving speed) varies depending on the film quality of the insulating film of the memory cell transistor. Here, writing of data indicates an operation of injecting electrons so as to increase the threshold voltage of the memory cell, and erasing indicates an operation of extracting electrons from the charge storage layer so as to decrease the threshold voltage. It shall be shown.

  When such write / erase speeds are different, the threshold voltage change amount at the time of applying one write / erase pulse is different, and the variation of the threshold voltage becomes large.

  Patent Document 1 (Japanese Patent Laid-Open No. 2001-93291) is intended to prevent threshold voltage variation depending on the write / erase characteristics of the memory cell and narrow the threshold voltage distribution width. ).

  In the configuration disclosed in Patent Document 1, a latch circuit is provided corresponding to each bit line in a NAND flash memory. Write data is stored in this latch circuit. When writing data, after charging the bit line to the write inhibit voltage level, the latch circuit is connected to the bit line, and the bit line voltage is set to the write voltage level and write according to the data held in the latch circuit. Selectively set to forbidden voltage level. Thereafter, a write voltage is applied to the word line to write data. After writing is completed, a verify voltage is applied to the control gate (word line) of the memory cell transistor, and the bit line voltage is also charged to the verify voltage level. In this state, the bit line voltage is discharged through the memory cell. Thereafter, the latch data of the latch circuit is selectively inverted according to the voltage of the bit line according to the voltage of the bit line. That is, the latch data of the latch circuit corresponding to the memory cell for which writing has been completed is set to the writing completion state. The latch data of the latch circuit for the memory cell that has not been written is set to the write-permitted state.

In the next write cycle, after supplying the precharge voltage at the write inhibit voltage level to the bit line, the latch circuit and the bit line are connected, and the precharge voltage level of the bit line corresponds to the latch data of the latch circuit. Set to the state to be used. As a result, the bit line voltage is maintained at the write inhibit voltage level for the memory cells that have completed writing, and the bit line voltage is set to the write enable state level for memory cells that have not been written. Is set. In this state, writing to the memory cell is performed. For each write cycle (electron injection cycle), verify is performed to set the latch data of the latch circuit to the write enable / block voltage level. Even when the write characteristics of the memory cells are different, by stopping writing to the memory cells that have been written and executing writing only to the memory cells that are not yet written, "verify by bit" To reduce the variation in the threshold voltage of the memory cell.
Japanese Patent Laid-Open No. 2001-93291

  In recent nonvolatile semiconductor memory devices, multi-level chips (MLC: multi-level memory chips) that store three or more levels of data in 1-bit memory cells have become mainstream. When multi-value data such as quaternary data is stored, the number of threshold voltages taken by the memory cell increases accordingly. In order to store accurate data, it is required to reduce the threshold voltage distribution width so that the threshold voltage distributions do not overlap between data having different values. As shown in the above-mentioned Patent Document 1, for each write execution, by setting the latch data of the latch circuit in a state indicating the write completion / incomplete in the latch circuit, the verify operation for each bit is performed, The threshold voltage distribution width can be adjusted.

  However, when rewriting is performed on a memory cell whose threshold voltage is in the vicinity of the verify voltage level, the rewriting is performed by applying a write high voltage according to the write data latched by the latch circuit. Therefore, the threshold voltage changes greatly, and a state exceeding the upper limit value of the threshold voltage distribution range occurs. In this case, or a process for lowering the threshold voltage of the memory cell that exceeds the upper limit value is required, which causes a problem that the time required for writing becomes long.

  Further, once it is determined that the writing is completed, the rewriting of the memory cell is not executed thereafter. Therefore, when the bit line voltage changes due to the influence of noise or the like, it is determined that the memory cell in which writing has not been completed is in the writing completion state, and there is a possibility that there is a memory cell in which writing has failed. May not be able to be realized.

  In addition, a verify operation is performed in order to set latch data of the latch circuit for each write cycle, and the total time of the write cycle and the verify cycle becomes long, and high-speed writing can be realized. become unable.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a nonvolatile semiconductor memory device capable of writing with high accuracy and high speed.

A nonvolatile semiconductor memory device according to the present invention is arranged in a matrix, each of which is arranged corresponding to each row of memory cells, a plurality of nonvolatile memory cells each having a threshold voltage set in accordance with stored information, A plurality of word lines to which the memory cells in the corresponding row are connected and a first signal line to which the memory cells in the corresponding column are respectively connected and correspond to the memory cell columns, respectively. A plurality of second signal lines that are provided separately from the first signal line and each of which corresponds to a memory cell in a corresponding column, and the first and first signal lines in an operation mode in which the threshold voltage of the memory cell is changed. The first and second potentials are set to the two signal lines, respectively, the first signal line is set in a floating state, and a determination level voltage is supplied to the word line in the selected row, and then the first signal line is maintained in a floating state. In the state It comprises a voltage setting circuit for supplying a voltage of the threshold voltage changes in the word line and the second signal line 択行.
In the operation mode in which the threshold voltage is changed, the memory cell is connected between the corresponding first and second signal lines. The determination level is a voltage level for determining whether the selected memory cell satisfies the changed threshold voltage condition.

  After the threshold voltage changing operation, the first and second signal lines are set to the first and second voltage levels, and then the word line determination level voltage is applied. Therefore, in this state, the voltage of the first signal line is selectively changed according to the threshold voltage of the memory cell. Therefore, when a voltage for changing the threshold voltage is applied to the word line and the second signal line, the threshold voltage is selectively changed according to the voltage level of the first signal line. Therefore, even for the memory cell after the threshold voltage change, it is determined again whether the threshold voltage is at a predetermined value at the time of each threshold voltage change operation. Can be realized.

  In addition, since the first signal line is maintained in the floating state, the first signal line is maintained at a voltage level corresponding to the threshold voltage of the memory cell, and the threshold is determined according to the memory cell threshold voltage. A value voltage change amount is determined, an excessive threshold voltage change is prevented, and an accurate threshold voltage change can be realized.

  Further, it is not necessary to perform a verify operation for verifying the threshold voltage of the memory cell for each threshold voltage changing operation, and the time required for changing the threshold voltage of the memory cell can be shortened.

  In addition, when the threshold voltage change operation of the memory cell is performed, first, the threshold voltage change inhibition voltage of the memory cell is set to the potential level corresponding to the current flowing through the memory cell when the determination potential is supplied to the control electrode node of the memory cell The threshold voltage change inhibition voltage (write inhibition voltage) can be set to a voltage level corresponding to the threshold voltage state of the memory cell, and an accurate threshold adjustment operation can be performed. it can.

  In addition, it is not necessary to perform verification every threshold voltage changing operation, the threshold voltage changing processing time can be shortened, and the memory cell after changing the threshold voltage is also subjected to the determination potential again. Whether or not the threshold voltage can be changed can be determined, and an accurate threshold voltage changing process can be realized.

[Embodiment 1]
FIG. 1 schematically shows an overall configuration of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. In FIG. 1, a nonvolatile semiconductor memory device includes a memory cell array 1 in which nonvolatile memory cells are arranged in a matrix, an interface circuit 2 that takes in a control signal CTL and an address signal from the outside, and inputs and outputs data DQ; Data is exchanged with the data input / output circuit included in the interface circuit 2, the data register 3 that holds externally written data at the time of data writing, and the data writing at the time of data writing according to the data held in the data register 3 A sense latch circuit 4 that holds data and latches verification result data at the time of verify operation, and a word line corresponding to an addressed row of the memory cell array 1 according to an address signal supplied from an address buffer included in the interface circuit 2 X decoder 5 that drives to the selected state, An internal voltage generation circuit 6 for generating a voltage according to the operation mode, a write voltage supply circuit 7 for transmitting the write voltage VWD to the selected column in the write operation mode, and a control input buffer included in the interface circuit 2 The control circuit 8 sets the operation timing and operation sequence of the internal circuit in accordance with the command.

  Internal voltage generation circuit 6 generates word line voltage VWL transmitted to the word line corresponding to the selected row via X decoder 5 and write high voltage VWD supplied to the selected column at the time of writing. As shown. However, internal voltage generation circuit 6 sets the verify voltage, the negative voltage, the word line voltage during normal reading, and the control level of the transmission gate during internal high voltage transmission according to each operation mode. Generate voltage.

  The control circuit 8 is composed of, for example, a sequence controller. When a command for instructing an operation mode is given according to an external control signal CTL, an internal voltage generation sequence and an operation sequence and operation timing of each internal circuit are set according to the command To do.

  The address signal is supplied to the data terminal in parallel with the command when the command is applied, and is then supplied to the control circuit 8, where the start address of access (write or read) is set.

  FIG. 2 is a diagram showing an example of the configuration of the memory cell array 1 shown in FIG. FIG. 2 representatively shows memory cells MC0 to MC6 connected to word line WL. Each of memory cells MC0-MC6 is formed of a stacked gate type MOS transistor (insulated gate type field effect transistor) having a floating gate, and its threshold voltage is set according to the amount of electrons injected into the floating gate. Set and store data accordingly.

  In memory cell array 1, an assist gate is arranged in series with a memory cell for each memory cell. In FIG. 2, assist gate AT0 is arranged between memory cells MC0 and MC1, and assist gate AT1 is arranged between memory cells MC2 and MC3. Assist gate AT2 is arranged between memory cells MC4 and MC5, and assist gate AT3 is arranged between memory cell MC6 and memory cell MC7 (not shown).

  Assist gates AT0 to AT3 respectively include assist gate lines AGL0 to AGL3 continuously extending in the column direction and inversion layer regions IL0 to IL3 formed on the surface of the semiconductor substrate region below assist gate lines AGL0 to AGL3. Including. Assist gate lines AGL0, AGL2,... Commonly receive assist gate selection signal AG0, and assist gate lines AGL1, AGL3,. When the assist gate selection signals AG0 and AG1 are activated, inversion layers (channel regions) are formed in the inversion layer regions IL0 to IL3 below the assist gate lines AGL0 to AGL3, and a path through which charges continuously flow in the column direction is formed. Is done.

  Assist gates AT0 to AT3 are used to form a path through which current flows between adjacent memory cells in the row direction during data writing, and set the inversion layer region to a high resistance state. A high electric field is generated on the source side of the memory cell, and a channel hot current is generated and injected into the floating gate. This method of injecting electrons from the source side of the memory cell into the floating gate is usually called a source side injection method.

  These inversion layer regions are arranged in pairs, and the inversion layer regions forming a pair are connected in common. That is, inversion layer regions IL0 and IL1 are commonly coupled and selectively coupled to bit lines BL0 and BL1 via source selection gates SG0 and SG1. Similarly, inversion layer regions IL2 and IL3 are coupled in common and selectively coupled to bit lines BL2 and BL3 via source selection gates SG2 and SG3.

  Source selection signals STS0 are commonly supplied to the gates of source selection gates SG0 and SG2, and source selection gates SG1 and SG3 commonly receive source selection signal STS1. Source selection signals STS0 and STS1 are alternatively driven to a selected state. Thus, when the inversion layer is formed in the inversion layer region IL (IL0-IL3 is generically shown) below the assist gate AT (generically showing AT0-AT3), the inversion layer is coupled to the bit line. , Function as a source region for the selected memory cell.

  Diffusion wirings are continuously extended in the column direction at nodes on the opposite side of the assist gate of the memory cells MC (MC0 to MC6 are shown generically). This diffusion wiring is formed of a low-resistance impurity region. That is, diffusion line DL0 is connected to memory cell MC0, and the common connection node of memory cells MC1 and MC2 is coupled to diffusion line DL1. A common connection node of memory cells MC3 and MC4 is coupled to diffusion line DL2, and a common connection node of memory cells MC5 and MC6 is connected to diffusion line DL3. That is, diffusion lines DL0-DL3 act as source / drain impurity regions of memory cell transistors aligned in the column direction and are shared by adjacent memory cells in the row direction.

  Diffusion lines DL0 and DL2 are selectively coupled to bit lines BL0 and BL2 via drain selection gates SD0 and SD2. Diffusion lines DL1 and DL3 are coupled to bit lines BL1 and BL3 via drain select gates SD1 and SD3. The even-numbered drain selection gates SD0, SD2,... Commonly receive the drain selection signal STD0, and the odd-numbered drain selection gates SD1, SD3,.

  Bit lines BL0-BL3 are formed of metal wiring. In the memory cell array 1, a plurality of diffusion wirings and inversion layer regions shown in FIG. 2 are provided in the column direction for each block, and when the memory cell array 1 is composed of a plurality of memory cell blocks, Diffusion wiring and / or inversion layer region is selectively coupled to bit lines BL0-BL3, and data access (write, erase, read) is performed on the selected memory cell block. Therefore, when the memory cell array 1 has a block division structure in which the memory cell array 1 is divided into a plurality of blocks, the bit lines BL0 to BL3 continuously extend in the column direction in common to the plurality of memory cell blocks in the memory cell array 1. Diffusion lines DL0-DL3 are arranged extending in the column direction only in the memory cell block region in memory cell array 1.

  A memory having the array of memory cells shown in FIG. 2 is called an AG-AND flash memory (assist gate-AND flash memory). By selectively separating the memory cells with the assist gate AT, the area occupied by the memory cells can be reduced compared to a configuration in which a diffusion layer and a region for separating the diffusion layers are provided for each memory cell. The layout area of the memory cell array can be reduced.

  FIG. 3 shows connections and write currents at the time of data writing to the memory cells in the memory cell arrangement shown in FIG. In FIG. 3, memory cells MCa and MCb and an assist gate ATa therebetween are used. That is, in the configuration shown in FIG. 2, it is not possible to simultaneously write to memory cells MC0 to MC6. Data is simultaneously written into memory cell MC0 and memory cell MC4, and data is simultaneously written into memory cells MC1 and MC5. Data writing is simultaneously performed on memory cells MC2 and MC6. That is, data is simultaneously written into memory cell MCi and memory cell MC (i + 4).

  Memory cells MCa and MCb are memory cells connected in series via assist gates in memory cells MC0 to MC6 shown in FIG.

  The grouping of the memory cells in units of four memory cells is defined by the connection between the diffusion wiring and the bit line and the repeated arrangement in the row direction of the memory cells. Which of the four memory cells MCi (i = 0-4) is to be written is determined by the address signal. Depending on the position in the group of selected memory cells, it is determined whether a certain bit line is used as a source bit line or a drain bit line.

  In FIG. 3, when data is written to memory cell MCb, write high voltage VWD is applied to the drain node of memory cell MCb, and ground voltage VSS is supplied to the source node of memory cell MCa. . Word line write high voltage VPP is supplied to word line WL to which memory cells MCa and MCb are commonly connected. The assist gate selection signal AGa for the assist gate line of the assist gate ATa is set to 2.0 V, for example. Under this condition, although the inversion layer is formed in the assist gate ATa, the voltage level of the gate is low, the resistance value of the inversion layer is relatively high, and the source potential of the memory cell is at a relatively high voltage level. It becomes.

  In this case, as shown in FIG. 3, a current flows from the drain node of the memory cell MCb to the source node of the memory cell MCa. In the inversion layer of the assist gate ATa, its resistance is relatively high, a high electric field is generated, and channel hot electrons are generated by this source high electric field. The channel hot electrons are further drawn in the vertical direction by a high electric field in the vertical direction by the word line write high voltage VPP and injected into the floating gate FG (source side injection). A state where electrons are injected into the floating gate FG and the threshold voltage of the memory cell MCb is increased is referred to as a write state.

  On the other hand, when write inhibit voltage Vinh is applied to the source node of memory cell MCa, write inhibit voltage Vinh is approximately the same level as the voltage level of assist gate selection signal AGa. Therefore, assist gate ATa has the same gate and source potential, and is almost non-conductive. Therefore, in this case, no current flows through memory cell MCb, and writing to memory cell MCb is not performed.

  The write inhibition voltage Vinh does not have to be the same as the voltage level of the assist gate selection signal AGa. Any voltage level that can prevent generation of a high electric field enough to generate hot electrons in the horizontal direction (channel length direction) in the channel region of the memory cell MCb may be used.

  In the connection mode at the time of data writing shown in FIG. 3, in the adjacent memory cell (not shown) sharing the diffusion wiring, the corresponding assist gate is non-conductive (the assist gate selection signal is in the non-selected state). ) Since no channel inversion layer is formed in these assist gates, there is no path through which current flows, and the memory cell sharing the diffusion wiring with the memory cell MCb and the memory cell sharing the diffusion wiring with the memory cell MCa No write current flows, and data can be accurately written to memory cell MCb.

  FIG. 4 is a diagram showing an example of connection of memory cells at the time of data reading in the memory cell array shown in FIG. FIG. 4 also representatively shows memory cells MCa and MCb and assist gate ATa.

  At the time of data reading, the assist gate ATa is formed with an inversion layer in the inversion layer region ILa below the assist gate selection signal AGa, and the inversion layer region ILa is fixed to the ground voltage level. Therefore, the source node of memory cell MCb is maintained at the ground voltage level by the inversion layer of assist gate ATa. On the other hand, bit line read voltage Vbr is applied to the drain node of memory cell MCb. Word line read voltage Vrd is applied to word line WL. When the threshold voltage of memory cell MCb is higher than word line read voltage Vrd, no channel region is formed in memory cell MCb and no current flows. Therefore, the voltage Vbr at the drain node of the memory cell MCb hardly changes. On the other hand, when word line read voltage Vrd is higher than the threshold voltage of memory cell MCb, a channel region is formed in memory cell MCb, and the ground node is connected from memory cell MCb to the inversion layer of inversion layer region ILa. Current flows to the drain, and the voltage level of the drain read voltage Vbr decreases. The data stored in the memory cell MCb is detected by detecting the voltage at the drain node of the memory cell MCb, that is, the presence or absence of the drain current.

  At the time of reading, the drain node of memory cell MCa is in a floating state and does not affect the read current of memory cell MCb. Even during this reading, the adjacent assist gate (not shown) is in a non-conductive state (no inversion layer is formed).

  Connection of memory cells at the time of data writing and data reading shown in FIGS. 3 and 4 is made by selectively setting selection gates SG0-SG3 and SD0-SD3 shown in FIG. 2 to a conductive state (on state). Realized. Control of conduction / non-conduction of these selection gates SG0-SG3 and SD0-SD3 is determined according to the position of the selected memory cell, that is, the address signal and the operation mode of writing / reading data.

  FIG. 5 is a diagram showing an example of the threshold voltage distribution of the memory cells used in the first embodiment of the present invention when storing multi-value data. FIG. 5 shows an example of threshold voltage distribution when the memory cell stores four-value data “11”, “10”, “00”, “01”. In FIG. 5, the vertical axis indicates the threshold voltage Vth, and the horizontal axis indicates the number of memory cells (number of bits) including this threshold voltage distribution.

  The center threshold voltage of the threshold voltage distribution region I of data “11” is Vth0, and the center value of the threshold voltage distribution region II of data “10” is Vth1. The center value of threshold voltage distribution region III of data “00” is Vth2. The threshold voltage of the central value of the threshold voltage distribution region IV of data “01” is Vth3.

  When storing multi-value data, the width of each threshold voltage distribution region is made as narrow as possible and the interval between the threshold voltage distribution regions is widened, so that data can be read with high accuracy. . Therefore, at the time of writing, it is required to reduce the width of each threshold voltage distribution region as much as possible. For this reason, for example, the lower skirt voltage level of the threshold voltage distribution (voltage level slightly higher than the threshold voltage lower limit value) is set to the lower skirt determination voltage level (level LBL with respect to region III). The threshold voltage of the memory cell storing data “00” having a threshold voltage lower than the skirt determination level LBL is increased, and the threshold voltage distribution region III of the memory cell storing this data “00” is increased. Reduce the width. This operation is similarly performed for memory cells that store other data.

  When writing data to the memory cell, data is written using the connection configuration shown in FIG. 3, and the write data is read using the connection shown in FIG. Judgment was made.

  FIG. 6 is a diagram showing an example of the configuration of the data register 3 shown in FIG. In FIG. 6, the data register 3 includes a data holding unit 3a for storing data of the memory cell, and a transfer unit 3b for transferring the data stored in the data holding unit 3a to the sense latch circuit. Data holding unit 3a includes a data register circuit 10 provided for each row of memory cells. The data register circuit 10 includes a register circuit 10a for storing the lower bit LB and a register circuit 10b for storing the upper bit UB. These 2-bit LB and UB describe quaternary data.

  The data transfer unit 3b includes a selection gate 11a that selects the stored data LB and UB of the register circuits 10a and 10b according to the register selection signal Yi, and an EXNOR gate 11b that receives the lower bit LB from the selection gate 11a and the write expected value bit ED0. EXNOR gate 11c that receives upper bit UB and write expected value ED1 from select gate 11a, NAND gate 11d that receives the output signals of EXNOR gates 11b and 11c, and an inverter that receives the output signal of NAND gate 11d 11e is included.

  An output signal of NAND gate 11d is transmitted to a reference node IOR of a sense amplifier circuit portion of a sense latch circuit described later, and an output signal of inverter 11e is applied to sense node IOS of the sense amplifier circuit.

  As shown in FIG. 2, at the time of data writing, data is written in parallel by selecting one memory cell in each group of four memory cells. The selection gate 11a selects the data register circuit 10 (10a, 10b) corresponding to one memory cell in each group including four memory cells. Therefore, the selection gate 11a performs 4: 1 selection for selecting one memory cell from four memory cells, that is, one data register circuit from the corresponding four data register circuits.

  Expected value data bits ED0 and ED1 indicate a lower bit and an upper bit of the write data at the time of data writing, respectively. Since threshold voltage adjustment is performed for each write data, data indicating write prohibition / execution is transferred by NAND gate 11d and inverter 11e to the memory cell storing the data to be written. That is, when the stored data of register circuits 10a and 10b and write expected value bits ED0 and ED1 have the same logic level, the output signals of EXNOR gates 11b and 11c are at the H level ("1"), and the NAND gate accordingly The output signal of 11d becomes L level (“0”), and the output signal of the inverter 11e becomes H level. When data “0” (L level) is transferred to the reference node IOR of the sense amplifier circuit, data writing is permitted.

  On the other hand, when at least one of storage bits LB and UB of register circuits 10a and 10b and write expected value bits ED0 and ED1 does not match the logic level, at least one of the output signals of EXNOR gates 11b and 11c is at L level. Accordingly, the output signal of the NAND gate 11d becomes H level (“1”). In this case, “1” (H level) is transferred to the sense amplifier reference node IOR, and data writing is prohibited. Thereby, at the time of multi-value data writing, writing is executed to the memory cell storing the same value data, and data writing is prohibited to the memory cell writing another data value.

  That is, in the data write operation, from the threshold voltage distribution region I in the state of storing data “11” in the threshold voltage distribution shown in FIG. The threshold voltage is changed to II, and the threshold voltage is adjusted from region I to threshold voltage distribution region III storing data “00”. Similarly, data “01” is stored. Threshold voltage adjustment is performed from region I on threshold voltage distribution region IV corresponding to the state to be performed. The threshold voltage distribution region I is a state in which the memory cell is in the erased state and has the lowest threshold voltage. Starting from this state, the threshold voltage is individually transferred to regions II, III and IV. Adjustment is performed and data is written.

  FIG. 7 is a diagram showing an example of the configuration of one sense amplifier / latch circuit included in sense latch circuit 4 shown in FIG. This sense amplifier / latch circuit is provided corresponding to each selected memory cell, that is, arranged corresponding to each pair of bit lines.

  7, sense amplifier / latch circuit 4a latches data transferred from data register (3) shown in FIG. 6, and reference node IOR of sense latch 14 to node ND1 in accordance with transfer instruction signal TR. Transfer gate QT1 to be coupled is selectively turned on according to the signal potential on reference node IOR, and when turned on, transfer gate QT2 for transmitting precharge voltage FPC, and voltage applied from transfer gate QT2 according to precharge instruction signal PC A transfer gate QT3 for transmitting the signal ND1 to the node ND1, a transfer gate QT4 for connecting the node ND1 to the bit line BLa according to the bit line connection control signal STR0, and a transfer gate for connecting the node ND1 to the bit line BLb according to the bit line connection control signal STR1. T5, transfer gate QT6 for precharging bit line BLa to precharge voltage FRPC0 according to read bit line precharge instruction signal RPC0, and bit line BLb to precharge voltage FRPC1 according to read bit line precharge instruction signal RPC1. Transfer gate QT7 is included. Transfer gates QT1-QT7 are formed of N channel MOS transistors as an example.

  Precharge transfer gate QT3 precharges node ND1 by setting node ND1 to the precharge voltage FPC voltage level in accordance with precharge instruction signal PC when the voltage level of reference node IOR is at the H level. Transfer gate QT1 is used to separate sense latch signal SLR and the bit line during a write operation. When it is necessary to transfer the write inhibit voltage according to latch signal SLR of sense latch 14, transfer gate QT1 is rendered conductive according to transfer instruction signal TR, and bit line is driven by sense latch 14.

  When reference node IOR is at L level, even if precharge instruction signal PC is activated, transfer gate IOR is non-conductive, and the voltage level of node ND1 does not change. Therefore, the bit line voltage can be selectively set to the precharge voltage FPC level in accordance with the latch signal SLS of the sense latch 14, and the bit line can be set in a floating state to maintain the voltage level of the bit line.

  Transfer gates QT4 and QT5 couple node ND1 to one of bit lines BLa and BLb. Thus, by switching the connection path of the sense latch 14 according to the position of the selected memory cell, each bit line can be used as a drain bit line or a source bit line.

  Sense latch 14 includes a cross-coupled P-channel MOS transistor and a cross-coupled N-channel MOS transistor, a latch-type sense amplifier 14a having a CMOS inverter latch configuration, and a reference node IOR according to sense node precharge instruction signal RSAS Is precharged to precharge voltage FRSA, and precharge transistor 14r precharges sense node IOS to precharge voltage FRSA level in accordance with reference node precharge instruction signal RSAR.

  The precharging transistors 14s and 14r precharge the reference node IOR and the sense node IOS to the precharge voltage FRSA level when conducting. Thereby, sense node IOS and reference node IOR are precharged to sense amplifier low-side power supply voltage SLN (ground voltage level) when precharging transistors 14s and 14r are turned on, respectively.

  Sense amplifier / latch circuit 4a is further connected in series between sense node IOS and ground node and receives at its gate N-channel MOS transistors QT8 and QT9 receiving signal EC on node ND1 and verify activation signal SEN. N channel MOS transistor QT10 outputting signal ECR according to the signal potential of sense node IOS.

  The signal EC on the node ND1 and the signal ECR driven by the MOS transistor QT10 indicate whether the threshold voltage of the write target memory cell connected to the sense amplifier / latch circuit 4a has reached a predetermined value or higher during the verify operation. The output signal EC of a plurality of bit lines (sense amplifier / latch circuit) is wired-connected, and the signal ECR is also wired-connected, and all the bits to be written are predetermined based on the signals of the signal lines that are wired-connected. It is determined whether the above condition is satisfied or writing is completed.

  FIG. 8 is a flowchart showing a write operation sequence according to the first embodiment of the present invention. A data write operation of the memory cell according to the first embodiment of the present invention will be described below with reference to FIG.

  First, the connection to the selected memory cell is confirmed, and data indicating the prohibition / permission of data writing is transferred from the data register circuit 10 shown in FIG. 6 to the sense latch 14 (see FIG. 7). The signal SLS on the SLR and the sense node is established. Further, as a result of the determination of the connection path of the memory cell, a connection path to the memory cell MCb to be written is established as shown in FIG.

  That is, as shown in FIG. 9, the diffusion wiring DLa of the memory cell MCa is brought into a floating state. In assist gate ATa, inversion layer region ILa is coupled to bit line BLa via source selection gate SGa. In the inversion layer region ILa, an inversion layer is generated according to the assist gate selection signal AGa. In sense amplifier / latch circuit 4a, select gate QT4 shown in FIG. 7 is conductive and transfer gate QT5 is nonconductive, and sense latch 14 of sense amplifier / latch circuit 4a is coupled to bit line BLa. Source selection gate SGa is one of selection gates SG0 and SG1 or one of selection gates SG2 and SG3 shown in FIG.

  On the other hand, diffusion line DLb shown in FIG. 9 is coupled to bit line BLb through drain select gate SDb. Bit line BLb is coupled to the ground node by a drain ground transistor (not shown). This drain select gate SDb is the other of the drain select gates SD0 and SD1 or the other of SD2 and SD3 shown in FIG. Drain selection signals SDa and SDb correspond to selection signals STD0 and STD1.

  The inversion layer of the inversion layer region ILa of the assist gate ATa is used, and this inversion layer region ILa is used as the source region of the memory cell MCb.

  Next, as shown in FIG. 10, all the source bit lines BLa are precharged with 1.2 V, and the drain bit line BLb is set to the ground voltage GND level. That is, precharge transfer gate QT6 shown in FIG. 7 is rendered conductive in accordance with precharge instruction signal RPC0, and precharge voltage FRPC0 of 1.2 V is transmitted to bit line BLa. At this time, transfer gate QT1 is non-conductive. Therefore, a voltage of 1.2 V is transmitted to the source bit line BLa regardless of the latch data of the sense latch 14. In this state, word line WL is in a non-selected state, and memory cells MCa and MCb are in a non-conductive state. On the other hand, assist gate selection signal AGa is at a voltage level higher than the precharge voltage, an inversion layer is reliably formed in assist gate ATa, and a precharge voltage of 1.2 V is transferred. Thereby, the process of step SP1 shown in FIG. 8 is completed.

  Next, the word line verify voltage is transmitted to the word line WL (step SP2 in FIG. 8). For example, in the threshold voltage distribution shown in FIG. 5 described above, this word line verify voltage is the voltage level of the lower skirt determination level LBL when data of region III is written (for example, 3.0 V). ). Source bit line BLa is maintained in a floating state at a precharge voltage level.

  Here, as an example of the data writing sequence, data writing is sequentially performed from region I to region II, region III, and region IV shown in FIG. The verify operation is executed after writing for each area. When data of the same value is written to memory cells MCa and MCb, if memory cell MCa has previously been written with data, the threshold voltage of memory cell MCa is set to the value of memory cell MCb. It is a state higher than the threshold voltage. Even in this case, by using the inversion layer of the assist gate ATa, when the word line verify voltage is applied, even if the memory cell MCa is in a non-conductive state, the precharge voltage is surely applied to the source of the memory cell MCb. Can communicate.

  In this state, as shown in FIG. 11, when the threshold voltage Vth of the memory cell MCb is higher than the lower skirt side determination level voltage Vlbl (for example, 3.0 V), no current flows in the memory cell MCb. The voltage level of the bit line BLa and the inversion layer formation region ILa does not change, and the precharge voltage of 1.2 V is maintained.

  On the other hand, when the threshold voltage of memory cell MCb is equal to or lower than determination level voltage Vlbl, current flows from inversion layer region ILa to diffusion wiring DLb via memory cell MCb according to the threshold voltage level. Flows. As a result, the bit line BLa has already completed the precharge operation and is in a floating state, and its precharge voltage level is lowered. The amount of decrease in the precharge voltage of the bit line BLa differs according to the threshold voltage level of the memory cell MCb, and the magnitude of the current I that flows is smaller as the threshold voltage is closer to the lower skirt determination level voltage Vlbl.

  Therefore, as shown in FIG. 12, in the inversion layer region ILa, that is, the precharge voltage 1.2V of the source bit line BLa, the threshold voltage Vth of the memory cell MCb is higher than its lower skirt determination level voltage Vlbl. However, the voltage level of the source bit line BLa is maintained at the precharge voltage level (1.2 V) without being discharged. On the other hand, when the threshold voltage Vth is equal to or lower than the lower skirt determination level voltage Vlbl and the difference is small, a slight current flows and discharge is performed slowly. (Within the period during which the lower skirt determination level voltage Vlbl is applied to the word line WL). On the other hand, when the threshold voltage Vth of the memory cell MCb is much smaller than the lower skirt determination level voltage Vlbl, a relatively large current flows through the memory cell MCb, and its inversion layer region ILa, ie, bit The voltage level of line BLa is reduced to the level of ground voltage GND.

  Therefore, when the voltage level of source bit line BLa is 0.6 V or lower, the threshold voltage of memory cell MCb is determined to be a threshold voltage lower than lower skirt determination level LBL (Vlbl). .

  In this case, as shown in FIG. 5, when the threshold voltage distribution range is narrowed in the region III, the region II and the region I having a threshold voltage lower than the lower skirt determination level LBL (Vlbl) exist. In these cases, however, the source bit line potential is lowered. Therefore, it is necessary to prohibit rewriting to the memory cells in these regions II and I.

  Therefore, as shown in FIG. 8, after the word line WL is driven to a non-selected state in step SP3, a write inhibition voltage is generated based on the latch data of the sense latch 14 shown in FIG. That is, in the sense latch 14 shown in FIG. 7, “0” is latched for the write target memory cell in the reference node IOR of the sense latch 14, while the write non-target memory cell On the other hand, data “1” is held. Therefore, the reference node IOR is “1”, that is, the H level for the memory cell not to be written, and the transfer gate QT2 is in the conductive state. Therefore, the precharge voltage 1.2V is transmitted to the node ND1 by the precharge voltage FPC using the transfer gate QT3. At this time, transfer gate QT1 is non-conductive. Thereby, the precharge voltage can be transferred to the source bit line of the write asymmetric memory cell without affecting the latch data of the sense latch 14. In the memory cell to be written, the sense latch signal SLS is at L level, the transfer gate QT2 is non-conductive, the precharge voltage FPC is not transmitted, and the source bit by applying the word line verify voltage in the previous step SP2 Maintained at line voltage level.

  In this state, as shown in FIG. 13, the precharge voltage is 1.2V for the bit line BLa of the memory cells in the threshold voltage distribution regions I and II. In region III, the voltage level of bit line BLa for the memory cell whose threshold voltage is higher than lower determination voltage Vlbl is 1.2 V. On the other hand, from lower determination level LBL (determination voltage Vlbl) in region III In the memory cell having a lower threshold voltage, the voltage level of the corresponding bit line BLa is 0.6V or less.

  In the case of the memory cell having the threshold voltage of region IV, since writing has not yet been performed, the threshold voltage is lower than the lower skirt determination level. 7 is a non-target memory cell, and the voltage level of the reference node IOR of the sense amplifier / latch circuit 4a is H level. Similarly, the transfer gate QT2 in FIG. 7 is in a conductive state, and the corresponding source bit line is set by the precharge voltage FPC. The voltage level of BLa is recharged to the precharge voltage (1.2V).

  Therefore, in the threshold voltage distribution region III to be written, the voltage level of the source bit line BLa is 0.6 V only for the memory cells lower than the lower skirt determination level LBL (lower determination voltage level Vlbl). In the following, the source bit line voltages of the remaining memory cells are at the precharge voltage (1.2 V) level.

  Next, in step SP4 in the flowchart shown in FIG. 8, it is determined whether all the voltage levels of the source bit lines BLa are 0.6V or more. If all the voltages of the source bit lines are 0.6 V or higher, the threshold voltage of the memory cell to be written is equal to or higher than the lower skirt determination level LBL (voltage Vlbl), and the lower region LR of region III The threshold voltage of the memory cell has moved to the upper region UR. Therefore, the threshold voltage distribution width in region III is small, and it is not necessary to perform further writing to the memory cells in region III, and the next verify operation is executed (step SP6 in FIG. 8). During the verify operation, it is determined whether the threshold voltage distribution of the memory cell is within the range of the upper limit value and the lower limit value in region III.

  The determination of the voltage levels of all the source bit lines in step SP4 shown in FIG. 8 is executed using the configuration shown in FIG. In FIG. 14, all source bit line potential determination units are connected in parallel between determination power supply node V and output node ND2, and each gate is connected to signal EC0- from node ND1 of corresponding sense amplifier / latch circuit 4a. P channel MOS transistors PQ1-PQm receiving ECm, and an N channel MOS transistor NQ connected between the output node and the ground node and receiving reset signal RST at its gate are included.

  MOS transistors PQ1-PQm have their thresholds such that the sum of the absolute value Vthp of the threshold voltages and the source bit line determination voltage level (0.6V), that is, Vthp + 0.6 is equal to the voltage of power supply node V. The value voltage and the voltage of the determination power supply node V are set.

  For example, it is assumed that the voltage level of determination power supply node V is 1.2V, and the absolute value Vthp of the threshold voltages of MOS transistors PQ1-PQm is 0.6V. Prior to the determination operation, node ND2 is set to the ground voltage level in accordance with tension setting signal RST. In this state, after the node ND2 is brought into a floating state, the signals EC0 to ECm are made valid in the determination unit. When any of the source bit line voltage determination signals EC0 to ECm from the node ND1 of the sense amplifier / latch circuit 4a is 0.6 V or less, any of the MOS transistors PQ1 to PQm is turned on, and the voltage of the node ND2 Level increases. On the other hand, if all of these signals EC0-ECm are 0.6V or higher, MOS transistors PQ1-PQm are all non-conductive, and node ND2 is at the L level reset by resetting transistor NQ. According to the voltage level of determination signal ALL from node ND2, it can be determined whether the voltage levels of all the bit lines are 0.6V or higher.

  As the configuration of the voltage level determination unit for all the source bit lines, a configuration is used in which all the signals EC0 to ECm are wired-connected and the voltage levels of the signal lines that are wired-connected are compared with the voltage level of the reference value. May be. At the time of this wired connection, when the source bit line potential is 0.6 V or less, the voltage level of the wired connection signal line is also 0.6 V or less and 0.6 V is used as the reference voltage due to the so-called wired AND configuration. Thus, the voltage levels of all source bit lines can be determined.

  Returning to FIG. 8, in step SP4, when at least one source bit line voltage is equal to or lower than the determination level of 0.6 V, writing is executed while maintaining the source bit line voltage (step SP5). That is, the word line is driven again to the selected state, the selected word line is set to the write high voltage VPP level, and the write high voltage VWD is transmitted to the drain bit line.

  FIG. 15 is a diagram showing a memory cell connection state and an applied voltage at the time of writing in step SP5 shown in FIG. In FIG. 15, the diffusion line DLa of the memory cell MCa is connected to the bit line BLa via the drain selection gate STDa. As shown in FIG. 7, bit line BLa has its internal node ND1 coupled to bit line BLa by transfer gate QT4 (selection signal STR0 is in an active state (on state)).

  On the other hand, the inversion layer region ILa of the assist gate ATa is set in a floating state. Assist gate line AGLa is set to a voltage level of 1.2 V, for example.

  Diffusion line DLb of memory cell MCb is coupled to bit line BLb via drain select gate SDb. The drain selection gate SDb has a drain selection signal STDb at a high voltage level of, for example, 8V, and a write high voltage VWD (about 4.5V) supplied from the VBL supply circuit 20 to the bit line BLb is diffused. Transmit to DLb.

  Word line write high voltage VPP is supplied to word line WL. This high voltage VPP is, for example, 12V. Therefore, the memory cell MCa is set to a conductive state regardless of the threshold voltage.

  In the diffusion line DLa, the voltage level of the source bit line BLa with respect to the memory cell to be written is 0.6 V or less by the above-described source bit line potential setting process. It is about 1.2V. Therefore, since assist gate line AGLa is about 1 or 2 V, in inversion layer region ILa of assist gate ALa, the voltage level of diffusion line DLa and the voltage level of assist gate line AGLa are substantially the same. In the gate ATa, no inversion layer is formed, and no write current flows.

  On the other hand, when the voltage applied from source bit line BLa to diffusion line DLa is 0.6 V or less, an inversion layer is formed in inversion layer region ILa according to the voltage level of assist gate line AGLa, and the source node of memory cell MCb Is supplied with a voltage level of 0.6V or less.

  In the write execution step SP5, the write high voltage VWD is supplied to the diffusion line DLb, a current flows through the memory cell MCb, hot electrons are generated by the high electric field in the inversion layer region ILa, and the memory cell MCb Electrons are injected into the floating gate. In this case, when the voltage level of diffusion line DLa is about 0.6 V, a write current flows in accordance with write high voltage VWD, and electrons are slightly injected into memory cell MCb. However, when the threshold voltage of memory cell MCb increases in accordance with this electron injection, equivalently, the source potential of memory cell MCb increases, and the source voltage increases due to the inflow of the write current. The channel hot electrons are not formed by the horizontal electric field in the channel region in FIG.

  In a memory cell in which the voltage level of source bit line BLa is 0V, the drain-source voltage is large, many channel hot electrons are generated, electrons are injected into the floating gate, and the threshold voltage rises. To do. Thereby, the threshold voltage of the memory cell in region LR lower than the lower skirt determination level of region III shown in FIG. 13 is increased according to the difference between this lower skirt determination level LBL and the threshold voltage. Can do.

  Note that, when the connection between the inversion layer region ILa and the diffusion wiring DLa is switched, the inversion layer region ILa is brought into a floating state, and the diffusion wiring DLa is connected to the bit line BLa. Therefore, in the inversion layer region ILa, the charge charged upon completion of step SP3 shown in FIG. 8 is held. Therefore, even if the charge amount is reduced in the diffusion line DLa by switching the connection path, the diffusion line and the inversion layer region ILa are electrically connected when the memory cell MCa is selected (when a high voltage is applied), and the source of the memory cell MCb The potential returns almost to the voltage level at the completion of step SP3.

  Further, even when the voltage level of the diffusion line DLa is lower than the voltage level at the completion of step SP3 due to the parasitic capacitance of the diffusion line DLa, the assist gate ATa has a corresponding charge in the inversion layer region ILa. The resistance value of the inversion layer is increased, and the source voltage for the memory cell MCb can be set substantially in accordance with the voltage level at the completion of step SP3. Therefore, it is possible to reliably execute writing to a memory cell in which writing is defective. Further, even if the source voltage drops from the precharge voltage level of 1.2 V to about 1.0 V, for example, writing can be reliably prevented (the drain-source electric field is so high that channel hot electrons are generated). Absent).

  When this writing is completed, the operation from step SP1 shown in FIG. 8 is repeated.

  When the verify operation is completed in step SP6 shown in FIG. 8 and there is a memory cell with a verify failure, the process returns to step SP1 and the rewrite operation is executed (step SP7).

  If it is determined in step SP7 that the threshold voltages of all bits are normal, it is determined whether there is data to be written next (step SP8). If there is next write data, the next data is transferred to the sense latch (step SP9). Data transfer to the sense latch is data indicating execution / blocking of writing.

Next, the operation from step SP1 is repeated, and the next data is written.
On the other hand, when it is determined in step SP8 that writing of all data has been completed, the writing operation ends (step SP10).

  FIG. 16 is a diagram illustrating an example of the applied voltage of each unit during data writing. FIG. 16 shows a state in which write inhibition voltage VSTL2 is set to 1.2V. The memory cell to be written is the memory cell MCb, and electrons are injected according to the source side injection method. High side power supply voltage SLP of sense latch 14 is 2.0V, and low side power supply node SLN is at a voltage level of 0V. The precharge voltage FPC transmitted by the transfer gate QT2 is 1.2V, and the transfer gate QT2 can transmit the voltage FPC at the 1.2V level as a write inhibition voltage with a margin.

  Transfer instruction signal TR to transfer gate QT1 is 0 V during writing, and transfer gate QT1 is non-conductive during writing. This transfer signal TR is set to 3.5 V when it is necessary to transmit the latch signal at the H level (1.2 V) of the sense latch 14 as a write inhibition voltage. Precharge instruction signal PC applied to transfer gate QT3 is 0V, and transfer gate QT3 is in a non-conductive state during a write operation. Bit line selection instruction signal STR0 applied to transfer gate QT4 is 3.5V, and a voltage of 1.2V can be transmitted with a margin.

  The selection signal STDa applied to the drain selection gate SDa connecting the bit line BLa and the diffusion line DLa is 8V, and the selection signal STDb applied to the drain selection gate SDb is also 8V. This is because writing high voltage VWD is 4.5V, and writing high voltage VWD may be supplied to both bit lines BLa and BLb so that these drain selection signals STDa and STDb are written. The voltage level at that time is set to 8V.

  Even if the write inhibition voltage VSTL2 applied to the diffusion line DLa is 1.2V and the write high voltage VWD is 4.5V, the gate voltage of the assist gate ATa is about 1.2V. Even if ATa is in a conductive state, the drain-source voltage of the channel region of the memory cell MCb is lower than the voltage level for generating channel hot electrons, so that channel hot electrons are not generated and writing is blocked. .

  When writing is performed on memory cell MCb, the voltage level of diffusion line DLa is 0.6 V or less as described above.

  FIG. 17 is a diagram showing the relationship between the voltage level of the source bit line and writing at the time of writing. In FIG. 17, the vertical axis represents the source bit line voltage, and the horizontal axis represents the word line verify voltage application time in step SP2 shown in FIG. After the source bit line is set to 1.2 V, the word line is set to the voltage level Vlbl of the lower skirt determination level, and the source bit line is discharged through the memory cell for a time tDIS. When the threshold voltage is lower than the determination voltage Vlbl, the voltage level decreases with time. Finally, when the voltage of the source bit line has reached 1 V, writing can be prevented during writing (channel hot electrons cannot be generated).

  On the other hand, when the source bit line drops to 0.6V, channel hot electrons are generated and can be written a little, and electrons can be injected into the floating gate of the memory cell below this voltage level. . However, in the memory cell in which the voltage level of the source bit line is around 0.6 V, the writing is stopped as the threshold voltage increases due to the injection of electrons into the floating gate and the writing current flows. . Therefore, when writing to a memory cell whose source bit line voltage level is 0.6 V, the threshold voltage rise is small, and the threshold voltage of the memory cell in the vicinity of determination level LBL in region LR shown in FIG. Only rises a little. A memory cell having a threshold voltage near the lower limit of region III has a threshold voltage level that rises significantly and has a threshold voltage level higher than the determination level LBL, thereby reducing the threshold voltage distribution width. can do.

  FIG. 18 is a flowchart showing the detailed operation of verify step SP6 shown in FIG. 8, and FIG. 19 is a diagram schematically showing the connection path between the memory cell and the sense amplifier / latch circuit 4a during the verify operation. FIG. 20 is a signal waveform diagram showing an operation during verification. Hereinafter, the verify operation of step SP6 shown in FIG. 8 will be described with reference to FIGS.

  First, the source / drain connection to the memory cell to be written is established, and the source and drain voltages are set (step SPP1).

  When the memory cell connection is completed, as shown in FIG. 19, inversion layer region ILa of assist gate ATa is coupled to the ground node via source selection gate SGa. In accordance with the assist gate selection signal AGa, an inversion layer is formed in the inversion layer region ILa, and the source of the memory cell MCb is grounded.

  On the other hand, in sense amplifier / latch circuit 4a, transfer gate QT5 shown in FIG. 7 is rendered conductive (ON state) in accordance with connection control signal STR1, and internal node ND1 is connected to bit line BLb. The bit line BLb is connected to the diffusion line DLb via the drain selection gate SDb. Diffusion wiring DLa of memory cell MCa is in a floating state. In this state, as shown in the operation waveform of FIG. 20, the bit line BLb is applied to the precharge voltage FRPC1 of 2.0V (or 1.2V), for example, in accordance with the one-shot read precharge instruction signal RPC1 shown in FIG. Charge to level. Drain selection signal STDb is at a level of voltage (for example, 3.5V) higher than read precharge voltage 2.0V, and voltage level of 2.0V (or 1.2V) is applied to diffusion line DLb. It is supplied as the drain voltage of the cell MCb.

  After completion of the precharge of the drain node, verify voltage Vlbl is transmitted to the word line as shown in FIG. 20 (step SPP2 in FIG. 18). When the threshold voltage of memory cell MCb shown in FIG. 19 is higher than verify voltage Vlbl on word line WL, memory cell MCb becomes conductive and the precharge voltage of the drain node (diffusion wiring DLb) becomes the assist gate. The voltage is discharged to the ground node via ATa, and the voltage level is lowered (see the broken line waveform at node ND1 in FIG. 20).

  FIG. 20 shows a state where sense latch signal SLS of sense node IOS is set to “1” to indicate that data writing is to be performed. By this discharge operation, in the sense amplifier / latch circuit 4a shown in FIG. 7, the voltage level of the node ND1 becomes the precharge voltage level or the ground voltage level according to the voltage level of the drain bit line BLb.

  Next, in step SPP3, the precharge signal PC is set at the H level and the transfer instruction signal TR is maintained at the L level, and the voltage level of the drain bit line, that is, the node ND1, is selectively changed according to the sense latch signal SLR. In this state, for the memory cell not to be written, sense latch signal SLR is at H level, transfer gate QT2 is in a conductive state, node ND1 is at H level, and in the memory cell to be written, The transfer gate QT2 is non-conductive, and the voltage level of the drain bit line is maintained. Therefore, the voltage level of the drain bit line not to be written is set to the H level, and the voltage of the drain bit line of the memory cell in which writing is completed among the memory cells to be written is at the H level. The drain bit line of the memory cell having the threshold voltage lower than the lower skirt determination voltage becomes L level.

  Next, EXNOR between the signal (voltage) of the drain bit line BLb and the sense latch signal SLS is taken, and the latch signal SLS of the sense latch 14 is selectively corrected according to the calculation result. That is, verify activation signal SEN is set to H level, and MOS transistor QT8 shown in FIG. 7 is turned on. If the voltage level of node ND1 is high, latch signal SLS of sense node IOS is driven to L level, and accordingly, writing of the target memory cell is completed (the voltage level of bit line is 2.). In the case of 0V high level, the threshold voltage of the corresponding memory cell is higher than the reference voltage Vlbl).

  On the other hand, when the voltage level of drain bit line BLb, that is, the voltage level of node ND1, is low, MOS transistor QT8 in FIG. 7 is non-conductive, and as shown by the broken line in FIG. 20, sense latch signal SLS The state does not change and maintains the H level. When the sense latch signal SLS is at H level, the MOS transistor QT10 is turned on, and the determination result signal ECR is maintained at L level. On the other hand, when the sense latch signal SLS is at L level, the MOS transistor QT10 is turned off. Determination result signal ECR becomes H level by a pull-up element (not shown), for example. By wire-connecting this determination result signal ECR for all sense amplifiers, it is possible to determine whether writing has been completed for all memory cells.

  That is, for the memory cells not to be written, even when the sense latch signal SLS is at L level and the threshold voltage of the corresponding memory cell is lower than the verify voltage Vlbl, the sense latch signal SLS is It is at L level and does not affect the logic level of the determination result signal ECR. Therefore, if all the sense latch signals SLS are at the L level and the determination result signal ECR is at the H level, the threshold voltages of the memory cells to be written are all higher than the verify voltage level Vlbl. As shown, writing is complete. Therefore, writing is repeatedly executed until all the sense latch signals SLS become L level. In this case, the sense latch signal SLS is at the H level only for the memory cell in which writing is defective, and writing is executed only for the memory cell in which writing is defective.

  If it is necessary to confirm that the threshold voltage of the memory cell to be written is lower than the upper limit value of the corresponding threshold distribution region, for example, the following method is executed. An upper limit verify voltage is applied to the word line to detect whether the voltage level of the node ND1 is all L level. For example, the sense latch signal SLS is set to H level, and the sense latch signal SLS is selectively discharged by the transistor QT8. If all sense latch signals SLS are discharged to L level, the determination or cache signal is all set to H level (by the pull-up element), and it is identified that the threshold voltage of the memory cell is lower than the upper limit value. . When there is a memory cell whose threshold voltage is equal to or higher than the upper limit value, the sense latch signal SLS is maintained at the initial H level, the corresponding determination result signal ECR becomes L level, and the threshold voltage exceeding the upper limit value is set. It is identified that there is a memory cell having.

  However, in this determination of the upper limit value, the memory cell exceeding the lower threshold voltage is not written, so that the threshold voltage distribution of the memory cell is within the upper limit value range in the erased state. If it is guaranteed that it exists, there is no need to do this.

  In a normal conventional verify operation, thereafter, the voltage level of node ND1 is set to a high level or a low level according to sense latch signal SLS in accordance with precharge signal PC and transfer signal TR. By connecting node ND1 to the source bit line (see FIG. 15), rewriting can be performed on a memory cell whose threshold voltage is lower than the lower skirt determination level (Vlbl). For a memory cell higher than the level, a write inhibition voltage is transmitted and writing is inhibited.

  However, in the first embodiment, after this verify operation is completed, the node ND1 is connected to the source bit line (BLa), and then all the source bit lines are precharged to 1.2V. Therefore, in the signal waveform diagram shown in FIG. 20, it is not necessary to set the voltage level of node ND1 by precharge instruction signal PC and transfer instruction signal TR in the present embodiment. It is only necessary to perform steps up to which the sense latch signal SLS is set according to the EXOR operation result during the verify operation (step SPP4 in FIG. 18 is not particularly required).

  Next, step SP7 shown in FIG. 8 is executed, a verify determination operation is performed, all the memory cells to be written are written, and the threshold voltage is equal to or higher than the lower skirt determination level. If it is determined that it is within the range, the process proceeds to step SP8 (see FIG. 8). If there is a memory cell with write failure, the process proceeds to step SP1 in FIG. 8 and the write operation is executed again.

  Therefore, in the first embodiment, the operation of precharging the source bit line, selectively discharging through the memory cell, and selectively precharging the source bit line with respect to the memory cell in which writing is defective, and applying the write pulse Compared with the process of performing the verify operation by applying the write pulse after selectively precharging the source bit line (supplying the write inhibition voltage) in accordance with the sense latch signals SLR and SLS. The following advantages can be obtained. That is, during selective source line precharging, the normality / defectiveness of the threshold voltage is again determined for all bits, and writing is executed based on the determination result. Therefore, it is possible to detect a defective memory cell with high accuracy, perform rewriting, adjust the threshold voltage, and realize high accuracy writing. In the first embodiment, the write inhibit voltage is not set according to the latch data of the sense latch, that is, the source bit line is not driven by the sense latch. After the selective source line precharge, the voltage of the source bit line of the memory cell to be written is maintained and used as a write inhibition voltage. Therefore, the source line voltage of the memory cell near the lower threshold judgment level of the threshold voltage is relatively high, writing to this memory cell can be suppressed, and the threshold voltage change amount can be reduced. It is possible to suppress the threshold voltage from changing beyond the distribution, and to realize writing with higher accuracy.

  The verify operation is executed after determining that the threshold voltage of the memory cell is normal for all the bits written by each selective precharge. Therefore, it is not necessary to repeatedly execute the write pulse application and verify, and the bit line precharge time and the number of times of writing at the time of verify can be shortened. During the verify operation, when the bit line voltage is set according to the latch data of the sense latch and the write inhibition voltage is set based on the bit line voltage, the source voltage of the memory cell at the time of writing is 0 V and the write voltage is fully applied Since the threshold voltage change becomes large, it is necessary to execute verification after each writing.

  In the above description, the configuration of the AG-AND type flash memory is described. However, as a nonvolatile memory, an insulating film charge trapping nonvolatile memory that adjusts a threshold voltage by trapping charges in the insulating film, a normal one-transistor flash memory, a NOR flash memory, and a memory cell The first embodiment can also be applied to a NAND flash memory in which are connected in series.

  Further, in the connection control of the memory cell and the sense latch circuit according to the first embodiment of the present invention, the control circuit 8 shown in FIG. 1 is composed of a sequence controller, and the sequence controller receives a command given from the outside. (Control signal CTL) is decoded, and the generation of the internal voltage and the activation / inactivation of the control signal are controlled according to the decoding result and the address signal.

[Embodiment 2]
FIG. 21 is a flowchart showing a data write sequence of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. A data write sequence according to the second embodiment of the present invention will be described below with reference to FIG. The circuit configuration used is the same as the circuit configuration used in the first embodiment.

  First, it is determined whether an external command (control signal CTL in FIG. 1) designates a specific test mode (step SP20). When a specific test mode is designated, a mode for writing the same value data to the selected memory cell is designated. When this specific test mode is designated, the data write sequence according to the second embodiment of the present invention is activated. That is, in sense amplifier / latch circuit 4a shown in FIG. 7, sense latch signals SLS and SLR are set to a write instruction state of “1” and “0”, respectively (step SP21). That is, the precharge transistor 14r shown in FIG. 7 is turned on (by the control signal RSAR), the sense latch signal SLS is set to “1”, and the sense latch signal SLR is set to “0” by the latch type sense amplifier 14a. Set.

  Next, the connection of the memory cells is established and the precharge of all the source bit lines to the write inhibit voltage (1.2 V) level is performed (step SP22). In step SP22, the connection arrangement shown in FIG. 9 is formed as in the first embodiment, and sense amplifier / latch circuit 4a is coupled to the source node of the selected memory cell via an assist gate. Then, the transfer gate QT6 or QT7 of the sense amplifier / latch circuit 4a shown in FIG. 7 is turned on for a predetermined period to precharge the write inhibition voltage to all the source bit lines.

  Next, the selected word line is set to the verify voltage level (voltage Vlbl in the first embodiment) (step SP23). This state is the same as the voltage application state shown in FIG. 11 in the first embodiment. In this state, if the threshold voltage of the memory cell to be written is equal to or higher than this level determination voltage Vlbl, the source bit line voltage does not decrease and the precharge voltage level (write inhibition voltage level) is reached. To maintain. On the other hand, when the threshold voltage of the memory cell to be written is lower than the determination voltage Vlbl, the write inhibition voltage is discharged through this memory cell, and the voltage level of the source bit line is lowered.

  Next, it is determined whether or not the voltages of all the source bit lines are equal to or higher than a predetermined value (0.6 V) (step SP24). This determination operation is also the same as that shown in the first embodiment, and the determination unit shown in FIG. 14 is used to determine the voltage levels of all the source bit lines.

  Next, when at least one source bit line of 0.6 V or less exists among all the source bit lines, all the memory cells are memory cells to be written, and the source potential of the memory cells is maintained. Then, the write high voltage is supplied to the word line, and the drain write high voltage is supplied to the drain of the memory cell (step SP25). The connection state at this time is the same as the connection configuration shown in FIG. 15 in the first embodiment, and the applied voltage is also the same as the voltage shown in FIG. After the completion of the write operation step SP25, the process returns to step SP22 again, and the precharge operation for all the source bit lines is executed. In this case, the states of sense latch signals SLS and SLR do not change.

  On the other hand, if it is determined in step SP24 that the voltages of all the source bit lines are 0.6 V or higher, verify read is performed (step SP26). In the verify read step SP26, the same operation as that shown in step SP6 shown in the first embodiment and steps SPP1 to SPP4 shown in FIG. 18 is executed. That is, at the time of this verify read, the latch signals SLS and SLR of the sense amplifier are set according to the drain voltage change due to the word line verify voltage.

  After the verify read, when at least one of the drain voltages of the memory cell is discharged and the voltage level is lowered to a predetermined value or less, there is a memory cell with a write failure, and the operation from step SP22 is performed again. Is executed.

  On the other hand, if it is determined in step SP27 that the drain voltage of all the memory cells is maintained by the verify operation and the threshold voltage of the memory cell is equal to or higher than the word line verify voltage level, then all the memories It is determined whether or not data writing for the cell is completed (step SP28). If there is still a memory cell to be written at the time of the test, the address of the next memory cell is designated, the memory cell is selected, and its connection path is set (step SP29).

  Thereafter, the operation from step SP21 is performed again for the next memory cell, the latch signals SLS and SLR of the sense latch are set to the initial write instruction state, and the subsequent operation from step SP22 is repeated. Executed.

  On the other hand, if it is determined in step SP28 that writing has been completed for all memory cells, it is then determined whether writing of all data has been completed (step SP30). That is, when storing a plurality of types of data in the memory cell, if it is determined in step SP28 that data of the same value has been written, it is next determined whether or not data of a different value is written. It is. If there is a memory cell to which another value is written during the test, the verify voltage (word line verify voltage (lower determination level)) for the next data is reset (step SP31).

  Thereafter, the processing from step SP21 is again executed, and writing of each data is executed. If it is determined in step SP30 that writing of all data has been completed, writing of this test data is completed.

  Therefore, in the operation sequence shown in FIG. 21, when the same data is written to the memory cell, it is unnecessary to write the same value of data to the data register circuit from the outside and then transfer the data to the sense latch. . Therefore, in addition to the effects in the first embodiment, the time for loading test data can be shortened, and the effect that the test time can be shortened can be obtained.

  In addition, a process for changing the logical value of data can be performed for each memory cell row, and in the case of a source side injection type memory cell, writing to each type of memory cell of four types of memory cells is performed. Therefore, when different data is written as test data in these four types of memory cells, it is not necessary to load data, and the load time of test data can be further shortened. In addition, various patterns of data can be written in the memory cells and the test can be executed, and tests such as inter-memory cell interference can be executed in a short time.

  In the configuration of the nonvolatile semiconductor memory device according to the second embodiment, the test sequence is executed under the control of the sequence controller in the control circuit 8 shown in FIG. 1, and a particularly complicated circuit configuration is not required.

[Embodiment 3]
FIG. 22 shows a data write sequence of the semiconductor memory device according to the third embodiment of the present invention. FIG. 22 shows an operation of writing data (“11”) corresponding to a state in which the threshold voltage is the lowest, that is, an erase operation sequence. A data write (erase) sequence according to the third embodiment of the present invention will be described below with reference to FIG.

  First, it is determined whether an erase mode has been designated (step SP40). This erase mode is executed for all non-target memory cells when multi-valued data is written because data erase is performed for all memory cells when data is written. Is done. Alternatively, an erase command may be simply given from the outside.

  If it is determined that the erase mode is designated, the erase operation according to the third embodiment of the present invention is activated.

  Next, a memory cell is selected in accordance with an address signal applied to this erase mode (data write mode), and connection to the memory cell is set (step SP41).

  In this erase mode, as shown in FIG. 23, diffusion line DLb of memory cell MCb to be erased is coupled to bit line BLb via drain select gate SDb. On the other hand, in the assist gate ATa, the inversion layer region ILa is connected to the bit line BLa via the source selection gate SGa. The conduction of these selection gates SGa and SGb is controlled by selection signals STSa and STDb. A VBL supply circuit 20 is coupled to the bit line BLb, and the positive drain erase voltage VDE is supplied to the bit line BLb by the VBL supply circuit 20. Bit line BLa is coupled to the ground node.

  Adjacent memory cell MCa has its diffusion line DLa in a floating state. Thus, after the connection path to the memory cell is set, the source voltage and the drain voltage are set (step SP42).

  Next, in this state, the word line erase verify voltage VEV is applied to the word line WL for a predetermined period (step SP43). This word line erase verify voltage VEV is at a voltage level close to the upper limit value of the threshold voltage distribution of the erased memory cell. Therefore, as shown in FIG. 24, the drain node is selectively discharged in accordance with the threshold voltage of memory cell MCb to be erased, and the voltage level of the drain node selectively changes from voltage VDE.

  That is, as shown in FIG. 25, after the voltage level of the drain node (diffusion wiring) DLb is precharged to the write high voltage VDE level, the word line WL rises to the verify voltage VEV level. When the threshold voltage Vth of the memory cell MCb is higher than the upper erase verify voltage (voltage level close to the upper limit of the threshold voltage distribution region in the erased state and slightly lower than that) VEB, the memory cell MCb has no current. Does not flow, and the drain node voltage VDE is maintained. On the other hand, when the threshold voltage of memory cell MCb is lower than upper erase verify voltage VEB, a current flows through memory cell MCb, and the voltage level of drain diffusion line DLb becomes equal to the threshold value of memory cell MCb. Decreases with voltage. In FIG. 25, a state in which the threshold voltage Vth of the memory cell MCb is close to the upper erase verify voltage VEB is indicated by a broken line waveform, and the threshold voltage Vth is larger than the upper erase verify voltage VEB and smaller. Indicates a signal waveform thereof by a one-dot chain line.

  It is determined whether all the drain node voltages are equal to or lower than a predetermined voltage level (step SP44). When at least one drain voltage is equal to or higher than a predetermined voltage level, as shown in step SP45 of FIG. 22, an erase high voltage is applied to the word line while maintaining this drain voltage. In this case, as shown in FIG. 26, in selected memory cell MCb, inversion layer region ILa to which the source node is connected is in an open state. The drain voltage Vd of the drain diffusion wiring DLb is the voltage level of the drain diffusion wiring DLb shown in FIG. A negative erase voltage VNN is applied to the control gate, that is, the word line. Therefore, when the drain node voltage Vd is at the positive high voltage VDE level, the voltage difference between the word line erase voltage VNN and the drain erase voltage VDE is large, and accordingly, the voltage Vfg of the floating gate FG of the memory cell MCb and the drain node Is large, and electrons (−e) flow out from the floating gate FG to the drain node (FN tunneling current flows from the drain node to the floating gate FG). Thereby, the threshold voltage of memory cell MCb is lowered. On the other hand, when the threshold voltage of memory cell MCb is slightly lower than upper erase verify voltage VEV, an FN tunneling current flows according to the difference between drain voltage Vd and floating gate voltage Vfg. However, as electrons are injected into the floating gate FG, the potential of the floating gate FG increases and the voltage at the drain node decreases, the voltage difference between the floating gate voltage Vfg and the drain voltage Vd decreases, and the tunneling current stops. . Therefore, when the threshold voltage of memory cell MCb is close to upper erase verify voltage VEB, electrons are extracted by the inflow of a small amount of tunneling current, and the threshold voltage is only slightly decreased.

  On the other hand, when the drain voltage Vd is at or near the ground voltage level, the voltage difference between the negative word line erase voltage VNN and the drain voltage Vd is small, the FN tunneling current does not flow, and the threshold voltage is It does not change.

  Therefore, as shown in FIG. 27, in the threshold voltage distribution having threshold voltage Vth0 as the central threshold voltage, the threshold value close to the lower limit value of lower region LL in region I corresponding to the erased state. The threshold voltage of the voltage memory cell does not change, and the threshold voltage of the memory cell of the threshold voltage near the verify voltage VEV level in the lower region LL slightly decreases. On the other hand, the threshold voltage of the memory cell in the upper region UU is greatly reduced. In FIG. 27, the vertical axis represents the threshold voltage Vth, and the horizontal axis represents the number of bits, that is, the number of memory cells.

  Thereby, the threshold voltage of the memory cell in the upper region in the threshold voltage distribution region I can be shifted to the lower region LL, and the width of the threshold voltage distribution can be reduced. Further, since the memory cell whose threshold voltage has already sufficiently decreased is not erased, an over-erased state in which the threshold voltage becomes a negative voltage level can be prevented. Precision erasure can be realized.

  Further, during this erase operation, the drain node is in a floating state, an FN tunneling current due to the drain voltage Vd flows, the drain voltage Vd charged and held in the wiring capacitance is also lowered, and this FN tunneling is automatically performed. The current stops as the drain voltage Vd decreases. Therefore, the upper limit of the inflow FN current amount during the erase operation is defined by the charge amount of the drain voltage Vd, and it is possible to prevent the erase current from flowing excessively, thereby preventing the memory cell from being overerased.

  In the erase operation, selective erase can be realized by using a configuration in which the erase latch voltage (ground voltage) is applied to the memory cell to be erased using the sense latch signal of the sense amplifier / latch circuit. can do. That is, in the sense amplifier / latch circuit, the sense latch signal SLR of the reference node shown in FIG. 7 is set to the H level for the memory cell not to be erased, and the node ND1 is transferred from the transfer gate QT3 according to the precharge instruction signal PC. Via the corresponding drain bit line, signal FPC at the ground voltage level is transmitted. Without changing the drain voltage of the memory cell to be erased, the drain voltage can be set to the ground voltage level for the memory cell not to be erased. The memory cell to be erased is maintained at the voltage level after the verify voltage is applied to the word line.

  After this word line erase voltage is applied and selective erase is performed, the process returns to step SP42 again to reset the drain voltage.

  On the other hand, if it is determined in step SP44 that the drain node voltages are all equal to or lower than the predetermined value, it is determined that the memory cell to be erased is in the erased state, and the process proceeds to step 46 to execute the erase verify operation. To do. In erase verify step SP46, the source node of the memory cell is again held at the ground voltage level, and a read current is applied to the drain of the memory cell (for example, using a sense amplifier / latch circuit). Next, after setting the word line to a predetermined voltage level (upper erase verify voltage level), the level of the drain voltage is determined for all bits (step SP47). If it is determined in the verify determination operation of step SP47 that the threshold voltages of all the memory cells are not set to a predetermined value or less and there is an insufficiently erased memory cell, the processing from step SP42 is repeated again. .

  On the other hand, if it is determined in step SP47 that the threshold voltages of all the memory cells are equal to or lower than the upper threshold voltage level, it is then determined whether all the memory cells to be erased have been erased. (Step SP48). If the memory cell to be erased still remains, the next address is set (step SP49), and the processing from step SP41 is performed again according to the set address.

  On the other hand, when it is determined in step SP48 that the erasure of all the memory cells to be erased is completed, the erasure (data “11” writing) operation is terminated.

  For example, the configuration shown in FIG. 28 can be used as a configuration for determining whether or not the drain voltages are all lower than a predetermined value during the verify operation in step SP45.

  In FIG. 28, the erase determination unit is connected between N-channel MOS transistors NQ10-NQ1m connected in parallel between output node ND10 and ground node, and between node ND10 and voltage node Vc and has a reset signal at its gate. P channel MOS transistor PQ10 receiving ZRST is included. Signals EC0 to ECm are signals from node ND1 of sense amplifier / latch circuit 4a shown in FIG.

  The threshold voltage of MOS transistors NQ10-NQ1m is set to 0.6V, for example. If the voltage of at least one drain bit line is higher than 0.6V, one of the signals EC0-ECm is 0.6V or higher and one of the N-channel MOS transistors NQ10-NQ1m is on. Thus, the signal ECE from the node ND10 becomes L level. On the other hand, when the drain node voltages are all 0.6V or less, the signals EC0 to ECm are all 0.6V or less, the MOS transistors NQ10 to NQ1m are all non-conductive, and the signal ECE from the node ND10 is the MOS transistor. The voltage Vc is precharged by PQ10. As a result, it is possible to determine whether or not the voltage levels of the drain bit lines have all dropped below a predetermined value, and the threshold of all memory cells to be erased (memory cells erased in one erase cycle). It can be determined whether the value voltages are all lower than the upper threshold voltage determination level (VEV).

  In this erase operation sequence, connection control and voltage application of each memory cell are executed under the control of the control circuit 8 shown in FIG.

  FIG. 29 schematically shows a structure of a portion related to writing / erasing of control circuit 8. In FIG. Referring to FIG. 29, control circuit 8 generates an operation node instruction signal and an address signal according to the command and address signal, and controls each operation timing, and the control of main control circuit 40. An AG decoder 42 that operates downward and generates assist gate selection signals AG0 and AG1 according to an address signal and an operation node instruction signal; and STD decoder 44 that generates drain selection signals STD0 and STD1 according to an address signal and an operation node instruction signal; STS decoder 46 for generating source selection signals STS0 and STS1 according to the address signal and operation node instruction signal, and transfer instruction signal TR and bit line connection control signal to the sense amplifier / latch circuit according to the operation mode instruction signal and address signal. And a sense latch control circuit 48 for generating various control signals, such as STR.

  The main control circuit 40 is composed of, for example, a sequence controller, and sets operation contents and sequences to be executed according to commands, and sets a generation voltage level at each operation.

  AG decoder 42 sets one of assist gate lines AG0 and AG1 to a selected state in accordance with the position of the selected memory cell during write and erase operations and read. The voltage levels of assist gate line selection signals AG0 and AG1 are selected by main control circuit 40 based on the internal voltage from the internal voltage generation circuit shown in FIG. In 42, the internal voltage from the internal voltage generation circuit is selected and set as the operation power supply voltage in accordance with the operation mode instruction signal from the main control circuit 40.

  The STD decoder 44 selectively sets the drain selection signals STD0 and STD1 to the selected state so as to select the diffusion wiring corresponding to the drain bit line at the time of erasing and reading (including verification). In the write state, drain selection signals STD0 and STD1 are both set to the selected state. The voltage levels of the drain selection signals STD0 and STD1 are set under the control of the main control circuit 40.

  The STS decoder 46 connects the inversion layer region of the assist gate to the bit line during the operation using the inversion layer of the assist gate as the source region, that is, during the source line precharge operation at the time of writing and the verify operation based on the drain voltage. As described above, the source selection signals STS0 and STS1 are generated according to the selected memory cell position (according to the address signal). The voltage levels of the source line selection signals STS0 and STS1 are also set according to each operation mode under the control of the main control circuit 40.

  The sense latch control circuit 48 generates a signal STR0 / 1 (STR0 and STR1) for controlling connection between the sense amplifier / latch circuit and the bit line according to the operation mode and the position of the selected memory cell. The sense amplifier / latch circuit is selectively coupled to the source bit line and the drain bit line in accordance with STR0 and STR1 based on this signal. Transfer instruction signal TR is activated in an operation that requires transmission of the source write inhibition voltage in accordance with the latch signal of the sense latch. The sense latch control circuit also generates a signal for setting the memory cell source voltage (signal PC, voltage FPC, etc. in FIG. 7) in accordance with the latch signal of the sense latch and activates at the time of verifying the precharge voltage A signal (SEN) is generated. In the sense latch control circuit 48, the voltage level of the generation signal and the generation sequence of the control signal are set under the control of the main control circuit 40.

  The configuration of the control circuit 8 shown in FIG. 29 can be commonly applied to the first to third embodiments.

  As described above, according to the third embodiment of the present invention, in the erase operation mode in which the threshold voltage is lowered, the drain voltage of the memory cell to be erased is precharged to a predetermined voltage level, and the word line voltage is A predetermined threshold judgment level is set, and in this state, the drain node voltage is set to a voltage level corresponding to the threshold voltage of the memory cell, and then an erase voltage is applied to the word line. As a result, it is not necessary to perform a verify operation every time an erase pulse is applied to the memory cell, and the time required for erasing can be shortened.

  In addition, the erase operation is performed with the drain node in a floating state, and the erase operation is performed with the drain node voltage maintained at a voltage level corresponding to the threshold voltage. A threshold voltage change amount corresponding to the threshold voltage is realized, over-erasure can be prevented, and highly accurate erasure can be realized.

  INDUSTRIAL APPLICABILITY The present invention can be applied to a nonvolatile memory that stores data in accordance with the amount of charge stored in a floating gate, and an insulating film trap type nonvolatile memory cell that stores information by trapping charges in the insulating film It can also be applied to.

  In addition, the configuration of the nonvolatile memory cell is not limited to the above AG-AND type flash, but can also be applied to a normal flash memory including a one-transistor memory cell. The present invention can also be applied to a NOR flash memory and a NAND flash memory.

  Further, the data writing is not limited to the AG-AND flash memory cell structure in which the data writing is performed according to the source side injection method, and the writing is executed by using a high drain electric field using the inversion layer of the assist gate as the source / drain region. It may be a memory cell structure.

  Further, the present invention can be applied even to a nonvolatile memory in which the erased state corresponds to the state where the threshold voltage is the highest.

  Also, the data to be stored is not limited to four-value data, and may be binary data or multi-value data such as eight values.

1 schematically shows an entire configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. FIG. 2 is a diagram illustrating an example of a configuration of a memory cell array illustrated in FIG. 1. FIG. 3 is a diagram schematically showing a memory cell connection configuration and a path through which a write current flows during data writing in the memory cell array structure shown in FIG. 2; FIG. 3 is a diagram showing a connection path of memory cells at the time of data reading in the memory cell array structure shown in FIG. 2. It is a figure which shows the response | compatibility of the memory | storage information and threshold voltage distribution of the non-volatile memory used by this invention. FIG. 2 is a diagram schematically showing an example of a configuration of a data register shown in FIG. 1. FIG. 2 is a diagram showing an example of a configuration of a sense amplifier / latch circuit included in the sense latch circuit shown in FIG. 1. It is a flowchart which shows the data writing sequence in Embodiment 1 of this invention. FIG. 9 schematically shows a connection path of memory cells in the write sequence shown in FIG. 8. It is a figure which shows the applied voltage in the memory cell connection path | route in Embodiment 1 of this invention. It is a figure which shows roughly the applied voltage and electric current path | route in the write-in sequence in Embodiment 1 of this invention. It is a figure which shows typically the change of the source voltage of the memory cell in the voltage application state shown in FIG. FIG. 9 is a diagram showing a correspondence between a threshold voltage of a memory cell and a voltage of a source bit line in step SP4 of the write sequence shown in FIG. It is a figure which shows an example of a structure of the write verify determination part in Embodiment 1 of this invention. It is a figure which shows roughly the connection form and applied voltage of the memory cell at the time of the data writing in Embodiment 1 of this invention. FIG. 16 is a diagram schematically showing an applied voltage of each gate and a connection path between a memory cell and a sense amplifier in the write state shown in FIG. 15; It is a figure which shows a response | compatibility with the source bit line voltage and upper threshold voltage determination level in Embodiment 1 of this invention. FIG. 9 is a flowchart showing a detailed operation of verify step SP6 shown in FIG. FIG. 19 schematically shows a connection path between a memory cell and a sense latch circuit during the verify operation shown in FIG. 18; It is a signal waveform diagram which shows the operation | movement in the flowchart shown in FIG. It is a flowchart which shows the write sequence according to Embodiment 2 of this invention. It is a flowchart which shows the write sequence according to Embodiment 3 of this invention. FIG. 23 is a diagram schematically showing a memory cell connection path in step SP41 shown in FIG. 22; It is a figure which shows the connection of a memory cell at the time of step SP43 application shown in FIG. 22, and an applied voltage. FIG. 25 is a diagram showing a change in voltage of a memory cell drain node and a change in word line when the voltage shown in FIG. 24 is applied. FIG. 22 is a diagram schematically showing paths of an applied voltage and an erase current of a memory cell in step SP25 shown in FIG. 21. FIG. 27 is a diagram schematically showing the correspondence between the threshold voltage distribution of the memory cell and the upper determination level during the erase operation in FIG. 26. It is a figure which shows an example of a structure of the drain bit line voltage determination part in Embodiment 3 of this invention. FIG. 2 schematically shows a configuration of a portion related to write and erase operations of the control circuit shown in FIG. 1.

Explanation of symbols

  1 memory cell array, 2 interface circuit, 3 data register, 4 sense latch circuit, 4a sense amplifier / latch circuit, 7 write voltage supply circuit, 6 internal voltage generation circuit, 8 control circuit, MC0-MC6, MCa, MCb memory cell , AT0-AT3, ATa, ATb Assist gate, 14 sense latch, 14a latch type sense amplifier, QT1-QT10 transfer gate, PQ1-PQm P channel MOS transistor, 20 VBL supply circuit, 40 main control circuit, 42 AG decoder, 44 STD decoder, 46 STS decoder, 48 sense latch control circuit.

Claims (8)

A plurality of nonvolatile memory cells arranged in a matrix, each having a threshold voltage set according to stored information;
A plurality of word lines arranged corresponding to each memory cell row and connected to the memory cells in the corresponding row,
Are arranged corresponding to respective memory cell columns, a plurality of first signal lines to which the memory cell of a corresponding column in each of which is coupled, and are arranged corresponding to each of said memory cell columns Rutotomoni said first signal A plurality of second signal lines, which are provided separately from the lines and to which the memory cells in the corresponding column are coupled, and in the operation mode in which the threshold voltage of the memory cell is changed, the selected memory cell corresponds to the first And electrically connected between the second signal line,
In the operation mode in which the threshold voltage of the memory cell is changed, the first signal line and the second signal line are set to the first and second potentials, respectively, and a determination level voltage is applied to the word line of the selected row. A voltage setting circuit for supplying a voltage for changing a threshold voltage to the word line of the selected row and the second signal line in a state where the first signal line is maintained in a floating state after being supplied; wherein the determination level Ru voltage level der determines the selected memory cell meets the condition of the threshold voltage after the change, the non-volatile semiconductor memory device. Each of the memory cell columns further includes a corresponding sense latch circuit that latches write data, and the threshold voltage changing operation mode is an operation mode for increasing the threshold voltage. ,
The nonvolatile semiconductor memory device according to claim 1, wherein latch data of the sense latch circuit is maintained separately from the first and second signal lines in the threshold voltage changing operation mode.   A sense control circuit that selectively supplies a threshold voltage change prevention voltage to the first signal line in accordance with data held in the sense latch circuit before application of a voltage for changing the threshold voltage; The nonvolatile semiconductor memory device according to claim 2.   In the threshold voltage changing operation mode, the voltage setting circuit is configured to fix the first signal line and the second signal line, respectively, regardless of the latch data of the corresponding sense latch circuit. The nonvolatile semiconductor memory device according to claim 2, wherein the nonvolatile semiconductor memory device is set to a voltage level of 2. A determination means for determining whether a voltage level of the plurality of first signal lines satisfies a threshold voltage change condition before applying the threshold voltage change voltage;
2. The voltage setting circuit according to claim 1, wherein the voltage setting circuit applies the threshold voltage change voltage when the determination means indicates that there is a first signal line that satisfies the threshold voltage change condition. Nonvolatile semiconductor memory device. A determination means for determining whether a voltage level of the plurality of first signal lines satisfies a threshold voltage change condition before applying the threshold voltage change voltage;
2. The voltage setting circuit according to claim 1, wherein the voltage setting circuit stops applying the threshold voltage changing voltage when the determination means indicates that there is no first signal line that satisfies the condition for changing the threshold voltage. Nonvolatile semiconductor memory device.   When the threshold voltage change voltage application of the voltage setting circuit is stopped, the threshold voltage of the memory cell connected to the word line of the selected row satisfies the condition determined by the threshold voltage change voltage application. The nonvolatile semiconductor memory device according to claim 6, further comprising a circuit that determines whether or not.   The nonvolatile semiconductor memory device according to claim 1, wherein the operation mode for changing the threshold voltage is an operation mode for reducing a threshold voltage of the nonvolatile memory cell.

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