JP2009301691A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce variation of threshold voltage of a memory cell after write-in/erasure by suppressing influence due to variation of initial threshold voltage of an insulation film electric charges accumulating type memory cell, and to reduce variation of an electric property of a memory cell. <P>SOLUTION: In a write-in operation mode or an easing operation mode, in accordance with an address of a memory cell, a level of voltage required for erasing operation, voltage required for write-in operation, or voltage required for verify is adjusted. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and in particular, a write / read margin of a nonvolatile semiconductor memory device having a split gate type or dual gate type cell structure in which a memory cell is composed of a serial body of a memory transistor and a select transistor. It is related with the structure for improving. More specifically, the present invention relates to a configuration for reducing variation in electrical characteristics of memory cells of a nonvolatile semiconductor memory device having an insulating film charge storage type memory cell that stores charges in an insulating film.

  As a nonvolatile semiconductor memory device that can be electrically written / erased, for example, a flash memory using a floating gate type memory cell is widely known. In the case of this flash memory, the memory cell is composed of one transistor, and this memory cell transistor has a stacked gate structure of a floating gate and a control gate. In the case of this stacked gate type memory cell, when it is formed on the same semiconductor chip as other circuits such as a processor, a step of forming a floating gate is required in addition to a CMOS process for forming a logic transistor such as a processor. In addition, the height of the memory cell is different from that of a component transistor such as another processor.

  For this reason, an insulating film charge storage type memory cell in which an insulating film is stacked and charges are accumulated at the interface or a trap in the insulating film is known as a memory cell having good compatibility with a logic manufacturing process such as a processor. Yes. The configuration of such an insulating film charge storage type memory cell is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-319065 and Japanese Patent Application Laid-Open No. 2006-135341.

  When this insulating film charge storage type memory cell structure is used, it is possible to form a memory with good consistency with a manufacturing process of a CMOS transistor (complementary insulated gate field effect transistor) such as a floating gate. It is described in.

  In this insulating film charge storage type memory cell, a memory transistor for storing information and a selection transistor for selecting a memory cell are arranged in series. The gate insulating film of the memory transistor is formed of a bottom oxide film, a nitride film, and an ONO film of a top oxide film, and the memory transistor has a so-called MONOS (metal-oxide-nitride-oxide-silicon) structure. The gate insulating film of the selection transistor is usually formed of an oxide film. The gate (memory gate) of this memory transistor is formed by the same process as the side wall insulating film formation of the gate (selection gate) of the selection transistor. This memory cell is a dual gate type memory cell (insulating film charge storage type memory cell) having a selection gate, a memory gate and two gates, and writing, erasing, holding and reading are performed as follows. .

  At the time of writing, a positive potential is applied to the memory transistor side impurity layer (source line), and a memory gate write voltage higher than that of the source line is applied to the gate (memory gate) of the memory transistor. For example, a bit line write voltage at the same ground potential level as that of the semiconductor substrate region is applied to the impurity layer (bit line) of the gate (select gate) of the select transistor. A voltage slightly higher than the threshold voltage of the selection transistor is applied to the gate (selection gate) of the selection transistor.

  In this state, a channel is formed in the memory transistor, and a current flows from the source line toward the bit line. The selection transistor is set to a voltage level whose selection gate voltage is slightly higher than the threshold voltage, is in a weak ON state, and even when a channel is formed, its channel resistance is relatively high. For this reason, a strong electric field is generated near the boundary between the memory transistor and the selection transistor, a lot of hot electrons are generated in the channel current of the memory transistor, and hot electrons are injected and trapped in the insulating film (nitride film) below the memory gate. The This write state is a state in which the threshold voltage of the memory transistor is high, and is associated with a state in which data “0” is stored.

  At the time of erasing, a negative potential is applied to the memory gate and a positive potential is applied to the memory gate side impurity layer (source line). The selection transistor is in an off state. In this state, strong inversion occurs in a region where the end portion of the impurity layer connected to the source line of the memory gate overlaps with the memory gate, causing a band-to-band tunneling phenomenon to generate a hole. The generated holes are drawn by the negative bias of the memory gate and injected into the insulating film (nitride film) below the memory gate. First, electrons and holes injected at the time of writing are neutralized to lower the threshold voltage of the memory gate. This erase state is a state in which the threshold voltage of the memory transistor is low, and is associated with a state in which data “1” is stored.

  In the holding state (standby state), charges are held as charges (electrons or holes) injected into the insulating film below the memory gate. This charge transfer in the insulating film is small and slow. As a result, charges are held in the insulating film in a state where no voltage is applied to the memory gate.

At the time of reading, a positive read potential is applied to the impurity layer (bit line) of the selection transistor, a positive potential is applied to the selection gate, and the selection transistor is set in a conductive state. A potential intermediate between the threshold voltages in the write and erase states is applied to the memory gate. In this state, the memory transistor is turned on or off according to the stored information. Information stored in the memory cell is read by detecting the current flowing through the bit line.
JP 2004-319065 A JP 2006-135341 A

  When the transistor is manufactured, if the impurity concentration or shape is different, the characteristics of the transistor vary. In particular, as the transistor becomes finer, the influence of the manufacturing parameters and the mask misalignment increases. In the nonvolatile semiconductor memory device, information is stored by the threshold voltage of the memory transistor. Therefore, when the threshold voltage of the memory transistor varies, accurate information cannot be stored, read and written.

  In the case where charges are accumulated in the insulating film, the movement speed of the charges is small and the charges are held in the local region. However, the charge in the insulating film is not completely trapped in the trap, but there is a charge that moves probabilistically away from this trap due to thermal fluctuations, etc., and the amount of trap charge in the insulating film There is a certain time dependency.

  In particular, when the memory cell is maintained in the holding state, in the memory transistor in the writing state, accumulated electrons gradually escape, and the initial threshold value is increased from a high threshold voltage (writing threshold voltage). The threshold voltage changes in the voltage direction. On the contrary, the memory cell in the erased state similarly changes from the low threshold voltage toward the initial threshold voltage. The write / erase operation changes the threshold voltage from the initial threshold voltage of the memory transistor. Therefore, a memory cell having a high initial threshold voltage has a higher write margin because its threshold voltage is increased by writing. Conversely, a memory cell having a low initial threshold voltage can set its threshold voltage to a lower voltage level and has a large margin for erasure.

  That is, a memory cell having a high initial threshold voltage has a high writing speed, and a memory cell having a low initial threshold voltage has a high erasing speed.

  As shown in Patent Documents 1 and 2, in the insulating film charge storage type memory cell structure, a memory gate is formed on the side wall of the selection gate, and the memory cell has an asymmetric shape. The memory cells are arranged in mirror symmetry so that the bit line contact is shared by the two memory cells. Therefore, the layout of the memory cells has a mirror symmetrical shape at the even and odd address positions of the control gate / memory gate. For this reason, there arises a problem that a difference occurs in ion implantation (impurity concentration) and effective gate size in the manufacturing process, and the initial threshold voltage fluctuates.

  In the above-mentioned Patent Document 1, in order to reduce the variation in the threshold voltage fluctuation amount of the memory transistor at the time of writing to the memory cell, a constant current circuit generates a constant current as a write current. Show. By generating this constant current write current, the dependency of the write current on the threshold voltage of the selection transistor is reduced, and accordingly, the amount of change in the threshold voltage of the memory transistor during writing is kept constant. To do.

  In Patent Document 2, in the insulating film charge storage type memory cell structure, electrons are injected into the insulating film by source side injection (SSI), and holes are injected by the band-to-band tunneling phenomenon at the time of erasing. In this case, the electron and hole injection regions are different, the amount of change in the threshold voltage of the memory transistor is small, and the problem that the write / erase efficiency is lowered is solved. For this reason, in Patent Document 2, an erase pulse is applied to the memory transistor a plurality of times during erasure, and the applied voltage level is increased. In addition, by applying a high voltage to the memory gate, the horizontal electric field is increased, and by increasing the horizontal electric field at the impurity stage (source line) connection portion, the generated holes are accelerated in the channel direction and insulated. It is intended to reduce the position dependency of the hole density in the film and improve the erase efficiency.

  However, in Patent Documents 1 and 2, the same correction (correction) is performed on all the memory cells to reduce variations in writing or erasing the threshold voltage.

  As described above, in the insulating film charge storage type memory cell, a mirror-symmetric layout is used as the memory cell layout so as to share the bit line contact. In this case, when a mask misalignment occurs in a direction orthogonal to the bit line, the change direction of the channel length of the selection transistor and the memory transistor is reversed in the two memory cells sharing the bit line contact (the selection transistor is in the bit direction). The transistor characteristics change in the opposite direction because they are arranged close to each other with respect to the line contact. Therefore, there arises a problem that transistor characteristics such as the initial threshold voltage change depending on the position where the memory cell does not exist.

  In the configuration disclosed in Patent Document 1, a write current having a constant magnitude is supplied during writing to narrow the threshold voltage distribution width after writing. However, this Patent Document 1 does not perform any writing in consideration of variations in characteristics depending on the position in the array such as the initial threshold voltage of the memory transistor.

  In Patent Document 2, holes are efficiently injected into the insulating film at the time of erasing, but variations in injection efficiency due to changes in memory transistor characteristics are not taken into consideration. Further, Patent Document 2 does not consider any configuration for compensating the write / erase characteristics depending on the position in the array of memory cells.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a non-volatile semiconductor memory device capable of reducing variations in electrical characteristics of memory cells after writing / erasing regardless of the value of the initial threshold voltage. is there.

  In summary, the nonvolatile semiconductor memory device according to the present invention adjusts the voltage level of the internal voltage applied to the selected memory cell in accordance with the address signal of the selected memory cell.

  In one embodiment, a nonvolatile semiconductor memory device according to the present invention includes a plurality of memory cells each storing information in a nonvolatile manner, an internal voltage generating circuit that generates an internal voltage according to an operation mode, and an address signal. An internal voltage adjustment circuit that adjusts the voltage level of the internal voltage and applies it to the selected memory cell is provided. Each memory cell includes a memory transistor that stores information according to the amount of charge accumulated in the insulating film, and a selection transistor for selecting a memory cell connected in series with the memory transistor.

  The internal voltage level applied to the selected memory cell is adjusted according to the address information of the selected memory cell. Therefore, even when the layout of the memory cell differs according to the position in the memory cell array, the difference in the electrical characteristics of the memory cell according to the position in the array can be reduced, and the variation in the initial threshold voltage is suppressed. Thus, a nonvolatile semiconductor memory device that operates stably can be realized.

[Embodiment 1]
FIG. 1 schematically shows a cross-sectional structure of a memory cell used in a nonvolatile semiconductor memory device according to the present invention. In FIG. 1, the memory cell includes a gate insulating film 4 on the surface of the semiconductor substrate region 1 so as to overlap with impurity regions 2 and 3 formed on the semiconductor substrate region 1 and a part of the impurity region 2. A select gate 5 formed therebetween, an insulating film 7 formed on the side wall of the select gate 5 and the surface of the semiconductor substrate region 1, and a memory gate 6 formed on the insulating film 7.

  Impurity regions 2 and 3 are coupled to bit line BL and source line SL, respectively, and select gate 5 and memory gate 6 are coupled to select gate line CG and memory gate line MG, respectively. The memory gate 6 is formed using the same method as the sidewall spacer of the selection gate 5. In this case, for example, a polysilicon film is deposited on the selection gate 5, and this polysilicon film is patterned by etching. Therefore, the length of the memory gate can be adjusted by the thickness of the polysilicon film, and the memory gate 6 is compared with the selection gate 5 even in the configuration in which two gates of the selection gate 5 and the memory gate 6 are provided. It can be made sufficiently short and the memory cell size can be reduced.

  The insulating film 7 has a laminated structure of a bottom oxide film 7a, a nitride film 7b, and a top oxide film 7c. Electric charges are accumulated in the nitride film 7b, and data (information) is stored according to the accumulated electric charge amount.

  In the memory cell shown in FIG. 1, a selection transistor is formed by selection gate 5, impurity region 2 and semiconductor substrate region 1, and a memory transistor is formed by memory gate 6, impurity region 3 and semiconductor substrate region 1. As shown in FIG. 1, the memory gate 6 is disposed only on one side of the selection gate 5. Therefore, in the cross-sectional structure shown in FIG. 1, the structure of the memory cell is an asymmetric structure.

  In the configuration of the memory cell shown in FIG. 1, as shown in FIG. 2, a select transistor ST and a memory transistor MT are connected in series between a bit line BL and a source line SL. At the time of data reading, a positive voltage is applied to selection gate 5 to form a channel on semiconductor substrate region surface 1 immediately below selection gate 5. On the other hand, when a positive voltage between the threshold voltages of the erased state and the written state is applied to the memory gate 6, the surface of the semiconductor substrate below the memory gate 6 depends on the amount of charge accumulated in the insulating film 7. A channel is selectively formed.

  FIG. 3 schematically shows a planar layout of the memory cell shown in FIG. In FIG. 3, a set of a select gate line CG and a memory gate line MG is arranged with a gap therebetween. In FIG. 3, select gate lines CG0-CG4 and memory gate lines MG0-MG4 are representatively shown. These selection gate line CG and memory gate line MG continuously extend in the X direction, and constitute selection gate 5 and memory gate 6 (see FIG. 1), respectively.

  Source lines SL1 and SL2 formed of impurity regions are arranged between adjacent memory gate lines MG0 and MG1 and between memory gate lines MG2 and MG3. In FIG. 3, source lines SL0 and SL3 are further shown to show the regularity of the layout.

  Bit line contact BCT is arranged for impurity region 4 shown in FIG. This bit line contact BCT is shared by memory cells adjacent in the Y direction.

  An insulating film 10 for element isolation is provided between memory cells adjacent in the X direction. Thereby, the selection transistor and the memory transistor of the memory cell adjacent in the X direction are separated from each other.

  As shown in FIG. 3, in the planar layout, adjacent select gate lines CG (CG1, CG2) are arranged so as to sandwich the bit line contact BCT, and the source line SL (SL1 or SL2) is sandwiched therebetween. Thus, memory gate lines MG (MG0, MG1 or MG2, MG3) are arranged. Therefore, in the planar layout of the memory cell MC, the memory cells are arranged in mirror symmetry with respect to the bit line contacts, and the memory cells are repeatedly arranged in the Y direction in a mirror symmetrical layout with respect to the source lines.

  For example, when a mask misalignment occurs in the direction in which the width of the selection gate line CG0 becomes wider (when a mask displacement occurs in the −Y direction), the widths of the selection gate lines CG0, CG2, and CG4 become wider. The select gate lines CG1 and CG3 are conversely narrowed. In this case, the impurity regions 2 and 3 shown in FIG. 1 are formed in a self-aligned manner with respect to the selection gate line CG and the memory gate line MG, and impurity implantation into the channel formation region on the surface of the semiconductor substrate region 1 is also performed in these regions. The selection gate 5 and the memory gate 6 are executed in a self-aligned manner. Therefore, when the widths of the select gate lines CG0 and CG1 are different, the widths of the impurity regions 2 and 3 are different, and accordingly, the channel lengths of the memory transistor and the select transistor are different, the impurity concentrations are also different, and the electrical characteristics are different. A state arises.

  In this case, even-numbered select gate lines CG0, CG2, CG4, even-numbered memory gate lines MG0, MG2, and MG4, odd-numbered selected gate lines CG1, CG3, and odd-numbered memory gate lines MG1 and MG3 have opposite electrical characteristics. Direction. Therefore, the threshold voltages of the transistors in the odd-numbered and even-numbered memory cells are different, and the erase / write characteristics are different. Here, the memory cell row is defined as the X direction in which the selection gate line CG and the memory gate line MG extend.

  4 schematically shows a cross-sectional structure taken along line L4-L4 shown in FIG. In FIG. 4, impurity region 3 constituting source line SL is arranged between impurity regions 4. Impurity region 2 is electrically connected to bit line BL extending continuously in the Y direction via bit line contact BCT.

  As shown in FIG. 4, the select gate line CG is arranged so as to sandwich the bit line contact BCT, and the memory gate lines MG0, MG0, MG0, MG are opposed to the impurity regions 3 constituting the source lines SL (SL1-SL3). MG1 and MG2 and MG3 are arranged. Therefore, as described above, when mask misalignment occurs, the impurity concentration under the memory gate line MG or the channel length of the memory transistor having this memory gate is different, and the electrical characteristics are different. In FIG. 4, with respect to the Y direction, the layout of the memory cells is sequentially arranged in mirror symmetry. Therefore, it is considered that the electrical characteristics of the memory cell due to the difference in the layout are different from each other in the position in the Y direction, that is, every memory cell row. In the present invention, the change in the electrical characteristics depending on the position in the array of memory cells is compensated at the time of writing / erasing / verifying.

  FIG. 5 schematically shows an entire configuration of the nonvolatile semiconductor memory device according to the first embodiment of the invention. 5, the nonvolatile semiconductor memory device selects a memory cell array 20 in which memory cells are arranged in a matrix, a row selection drive circuit 22 that drives a row of the memory cell array 20 to a selected state, and a column of the memory cell array 20. And a column selection drive circuit 24 to be operated.

  In the memory cell array 20, the memory cells shown in FIG. 1 are arranged in a matrix, and a selection gate line (CG) and a memory gate line (MG) are provided corresponding to each memory cell row. A line (SL) is provided. Bit lines (BL) are arranged corresponding to the memory cell columns.

  Row selection drive circuit 22 drives a specified row of memory cell array 20 to a selected state in accordance with an internal address signal applied from address input circuit 30. The row selection drive circuit 22 controls the potentials of the selection gate line CG and the source line SL. The column selection drive circuit 24 also selects the addressed column of the memory cell array 20 according to the internal column address signal from the address input circuit 30, precharges the selected column to a predetermined voltage level, and selects the necessary voltage to the selected column. To communicate.

  In this nonvolatile semiconductor memory device, sense amplifier circuit 26 for reading data, data latch circuit 28 for latching write data for data writing, and external input / output of data An input / output circuit 32 is provided. In the sense amplifier circuit 26, a verify sense amplifier circuit and a read sense amplifier for reading data to the outside may be provided separately, and these verify sense amplifier and read sense amplifier are shared. May be. Data latch circuit 28 latches externally applied write data at the time of data writing, and the corresponding memory cell is set to an erase state or a write state (program state) in accordance with the latched write data.

  The internal operation of the nonvolatile semiconductor memory device is controlled by a control circuit 34 that receives an external command CMD.

  The internal voltage from the internal voltage generation circuit 40 is applied to the row selection drive circuit 22 and the column selection drive circuit 24. In FIG. 5, internal voltage generation circuit 40 includes selection gate voltage Vcg, memory gate voltage Vmg and source line voltage Vsl applied to row selection drive circuit 22, and bit line voltage Vbl applied to column selection drive circuit 24. Is representatively shown. The internal voltage generation circuit 40 adjusts the voltage level of the internal voltage generated in each operation mode according to a predetermined address bit (Add) of the row address ADX supplied from the address input circuit 30.

  FIG. 6 schematically shows an example of the configuration of memory cell array 20 and row selection drive circuit 22 shown in FIG. In FIG. 6, in the memory cell array 20, the memory cells MC are arranged in a matrix. Memory cell MC includes a serial body of select transistor ST and memory transistor MT, and FIG. 6 representatively shows memory cells MC arranged in 2 rows and 4 columns.

  A set of selection gate line CG and memory gate line MG is arranged corresponding to each row of memory cells MC. In FIG. 6, select gate lines CGa and CGb arranged corresponding to the row of select transistor ST of memory cell MC, and memory gate lines MGa and MGb arranged corresponding to the row of memory transistor MT of the memory cell. Is representatively shown. A source line SLa is provided in common for the memory cells in the row, and is connected in common to the memory transistors MT of the memory cells in the corresponding row.

  A sub bit line SBL (SBLa-SBLd) is provided corresponding to each column of memory cells MC. Bit line contacts BCT for these sub-bit lines SBLa to SBLd are shared by two memory cells adjacent in the column direction (sub-bit line extending direction), and each select transistor ST is electrically connected to the corresponding sub-bit line. .

  In row selection drive circuit 22 shown in FIG. 5, selection gate drive circuits 50a and 50b are provided corresponding to selection gate lines CGa and CGb, and memory gate drive circuit 52a is provided corresponding to memory gate lines MGa and MGb. And 52b are provided. A source line drive circuit 54a is provided corresponding to source line SLa.

  Select gate drive circuits 50a and 50b are supplied with select gate voltage Vcg, and memory gate drive circuit 52a is supplied with memory gate voltage Vmg. Source line voltage Vsl is applied to source line drive circuit 54a. The voltage levels of these voltages Vcg, Vmg, and Vsl are set according to the operation mode (erase mode, write mode, and read mode (including verify)), respectively. The setting of the voltage level is executed in the internal voltage generation circuit 40 shown in FIG.

  A bit line peripheral circuit 60 is provided for sub bit lines SBLa-SBLd. Bit line peripheral circuit 60 includes a column selection drive circuit 24, a sense amplifier circuit 26 and a data latch circuit 28 shown in FIG. By this bit line peripheral circuit 60, a voltage necessary for a write / read (including verify) operation is applied to the bit line in accordance with each operation mode, and write and erase verify are executed. .

  As shown in FIG. 6, the memory cells MC are arranged mirror-symmetrically with respect to the source line SLa. Therefore, in order to suppress the influence of the variation in the electrical characteristics of the memory cell transistors (ST, MT) due to the influence of the mirror-symmetric layout, the voltages Vcg, Vsl and Vmg are selected according to the selected position of the memory cell. Adjusting at least one of the voltage levels.

  FIG. 7 schematically shows configurations of bit line peripheral circuit 60 and memory cell array 20 shown in FIG. FIG. 7 also shows a configuration of a portion related to writing / erasing of control circuit 34 shown in FIG.

  In FIG. 7, the memory cell array 20 is divided into a plurality of memory blocks BK0 to BKn. Memory block BK0 includes block selection circuit BSK0 and subarray SAY0, and memory block BKn includes block selection circuit BSKn and subarray SAYn. A memory block BKi (not shown) is also provided with a block selection circuit BSKi and a subarray SAYi.

  In each of these sub-arrays SAY0-SAYn, sub-bit lines SBL0-SBLm are arranged corresponding to the memory cell columns. In each of block selection circuits BSK0-BSKn, Y-select gates corresponding to each of sub-bit lines SBL-SBLm. YG0-YGm are provided.

  Main bit lines MBL0 to MBLm are provided in common to sub bit lines SBL0 to SBLm of these memory blocks BK0 to BKn. Block selection circuits BSK0 to BSKn couple corresponding sub bit lines SBL0 to SBLm to main bit lines MBL0 to MBLm in accordance with block selection signals Z0 to Zn, respectively.

  Therefore, sub bit lines SBL0-SBLm are coupled to corresponding main bit lines MBL0-MBLm in the memory block designated by block selection signals Z0-Zn, and data is written / read.

  One main bit line MBL is arranged for two sub bit lines SBL, and one of the two sub bit lines is further selected according to block selection signal Z0-Zn. A configuration connecting to a corresponding main bit line may be used. In this case, each of the block selection signals Z0-Zn includes a block signal for selecting an odd subbit line and a block selection signal for selecting an even subbit line. In the block selection circuit BSK, a block selection signal for selecting an odd subbit line and a block selection signal for selecting an even subbit line are applied to the Y selection gate of the odd subbit line and the Y selection gate of the even subbit line, respectively.

  In bit line peripheral circuit 60, a bit-by-bit verify circuit 62 is provided in sense amplifier circuit 26, and this bit-by-bit verify circuit 62 is coupled to data latch circuit 28. The bit-by-bit verify circuit 62, which will be described later, detects whether the corresponding memory cell is in the erase state or the write state in the erase mode and the write mode, and outputs a signal indicating the detection result. Generate.

  Data latch circuit 28 includes a data latch provided corresponding to main bit lines MBL0-MBLm, and latches applied write data when data is written.

  In the control circuit 34, a verify determination circuit 70 for determining whether all memory cells are set to an erased state or a state corresponding to write data in accordance with a verify result instruction signal from the bit-by-bit verify circuit 62, and a verify determination circuit A write / erase control unit 72 that further performs writing or erasing according to the determination result of 70 is included.

  The control circuit 34 is constituted by, for example, a sequence controller, and generates an internal voltage and an internal control signal in a predetermined sequence in accordance with an operation mode specified by an external command CMD.

  FIG. 8 is a flowchart showing an operation in the data write mode of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. Hereinafter, the operation in the data write mode of the nonvolatile semiconductor memory device shown in FIGS. 5 to 7 will be described with reference to FIG.

  First, the control circuit 30 shown in FIG. 5 waits for an external command CMD to be set to a state instructing data writing (step S1). In the following description, when a write instruction is given and data “1” or “0” is written, a mode in which erasing to lower the threshold voltage is referred to as an erasing operation mode. The operation mode in which the value voltage is increased is referred to as a write operation mode. When the area to be written is in the erased state, data is written to the target area. When the area to be written is already in the data writing state, the erase operation mode and the write operation mode are executed in the write mode.

  When this command CMD is a write command for instructing data writing, control circuit 34 first supplies write data supplied via input / output circuit 32, for example, a page buffer (not shown) or a data latch circuit shown in FIG. 28 is latched (step S2).

  In the following description, writing data “0” to a non-volatile memory cell corresponds to setting the memory cell to a write state, and writing data “1” erases the memory cell. Corresponds to setting the state. Therefore, since it is not identified which of the write data “0” or “1” is given as the write data, it is necessary to first set the memory cell group including the memory cell to be written to the erased state. is there. Therefore, when a write instruction is given, it is first determined whether the area to be written is in an erased state (step S3).

  When the area to be written is in the write state, the erase operation is set up (step S4). At the time of setup of this erase operation, memory gate voltage Vmg is set to a negative erase high voltage of, for example, −6V, and source line voltage Vsl is set to a positive erase high voltage of, for example, 6.5V.

  Next, an erase operation is performed on the memory cell to be written in accordance with the address signal (AD) (step S5). In this case, for example, in FIG. 6, when writing is performed on memory cell MC connected to selection gate line CGa and memory gate line MGa, first, source line SLa is set to the erase high voltage (6.5 V), The memory gate line MGa is set to a negative erase high voltage (−6V). Select gate lines CGa and CGb are maintained at the ground voltage level, and memory gate line MGb is maintained at the ground voltage level. Thereby, holes are injected from the source line SLa to the insulating film (7) in the memory transistor MT coupled to the memory gate line MGa by a high voltage between the memory gate line MGa and the source line SLa, and the memory transistor MT Is set to the erased state. This erased state is a state in which the threshold voltage is low, and corresponds to a state in which data “1” is written as described above.

  After the erase operation is completed, first, the memory gate voltage Vmg and the source line voltage Vsl are reset, and the memory gate drive circuit 52a and the source line drive circuit 54a are in a state where the memory gate line MGa and the source line SLa are not selected. Is set to the initial state (step S6).

  Next, after this erase operation, erase verify is executed (step S7). At the time of erase verify, a verify voltage is generated for determining whether or not a memory cell in a write target area is in an erased state. A verify voltage Vers having a voltage level slightly higher than the threshold voltage in the erased state is applied to the memory gate line MGa as the memory gate voltage Vmg, and is supplied to the select gate line CGa via the select gate drive circuit 50a, for example. A voltage of 1.5V is applied. In this state, data reading is executed. When memory cell MC is not in the erased state and its threshold voltage is higher than erase verify voltage Vers, no current flows through main bit line MBL and sub-bit line SBL. On the other hand, when memory cell MC is in the erased state and its threshold voltage is lower than erase verify voltage Vers, a current flows through main bit line MBL and sub bit line SBL.

  The voltage level of each main bit line is held by the bit-by-bit verify circuit 62 included in the bit line peripheral circuit 60 shown in FIG. In accordance with the verify result held in the bit-by-bit verify circuit 62, a verify determination circuit 70 (see FIG. 7) included in the control circuit 34 determines whether all memory cells to be written are in an erased state (step). S8). If all the memory cells to be written are not in the erased state, the process returns to step S4 again, and the erase operation and erase verify are executed.

  When the memory cell in the area to be written is set to the erased state, data is written into the area symmetrical to writing. That is, it is determined in step S3 that the memory cells in the area to be written are in an erased state (for example, referring to the erase flag), or all memory cells to be written in step S8. Is determined to be in the erased state, data “0” is then written. At the time of writing, the memory gate voltage Vmg is set to a positive writing high voltage level of 11.5 V, for example, and the source line voltage Vsl is set to 5.5 V, for example, for the memory cell to which data “0” is written. Positive write high voltage level. Select gate voltage Vcg is 1.5V, and bit line (sub bit line) voltage Vbl is set to 0.8V, for example. In this case, for the memory cell to which data “1” is written, the voltage of the bit line (main bit line and sub bit line) is approximately the same as the selection gate voltage Vcg (1.2 to 1.5 V). ) And the selection transistor is maintained in a non-conductive state (step S8).

  Next, data “0” is written according to the generated internal voltages Vmg and Vsl (step S10). That is, for the memory cell to which data “0” is written, the memory gate voltage Vmg is set to 11.5 V by the corresponding memory gate drive circuit (52a), while the source line SLa is the source line drive circuit. The positive write high voltage (5.5V) is set by 54a. The selection gate line CGa is set to 1.5V. In sub-bit lines SBLa-SBLb, the write data is set to the corresponding write voltage level according to “0” and “1”, respectively. When the bit line voltage (sub-bit line and main bit line) is set to a voltage level lower than the selection gate voltage Vcg by a threshold voltage of the selection transistor ST or more and the selection transistor is set to a weak ON state, the memory transistor MT Both the select transistors ST are turned on, hot electrons from the channel current are injected into the insulating film of the memory transistor MT, and the threshold voltage rises.

  On the other hand, for the memory cell to which data “1” is written, the voltage of the bit line (sub-bit line and main bit line) is the same level as the selection gate voltage Vcg, and the selection transistor ST is not turned on. In the conductive state, no channel current flows in this memory cell MC, and hot electrons are not generated. Therefore, the threshold voltage maintains the threshold voltage in the erased state, and the memory cell is maintained in a state of holding data “1”.

  After the write operation is completed, the write operation is reset (step S11). At the time of resetting the write operation, the voltage levels of the voltages Vcg, Vmg and Vsl are set to initial values (for example, internal power supply voltage level), and a memory gate arranged corresponding to the selected row The line MGa, the selection gate line CGa, and the source line SLa are driven to the non-selected state.

  At the time of writing, even if source line SLa is set to the write high voltage level, memory gate line MGb in the adjacent row is in a non-selected state (ground voltage level), and memory transistor MT is in a non-conductive state. And channel hot electrons are not generated.

  Next, in order to verify whether or not the threshold voltage of the memory cell has risen to a predetermined value or higher by this writing, first, a setup of write verification is performed (step S12). In the write verify setup, a write verify voltage Vprg lower than the threshold voltage of the memory cell in the written state is generated as the memory gate voltage Vmg. Select gate voltage Vcg is set at an internal power supply voltage level (1.5 V), for example, and bit lines (sub-bit line and main bit line) are set at a read voltage level. Source line SLa is maintained at the ground voltage level.

  When the memory cell is in the write state, the threshold voltage of the memory transistor is higher than the write verify voltage Vprg, no current flows through the memory cell, and the bit line (main bit line and sub bit) Line) is substantially maintained at the read voltage level in the precharged state. On the other hand, when the threshold voltage of the corresponding memory transistor is lower than the write verify voltage Vprg, a current flows through the memory cell (because the memory transistor MT becomes conductive). As a result, the voltage of the main bit line becomes a voltage level lower than the read voltage in the precharged state.

  The voltage of the bit line (main bit line) is detected by a verifying sense amplifier included in the sense amplifier circuit 26 (see FIG. 5) and latched to execute verification (step S12). The verify sense amplifier may be a sense amplifier used when data is read out to the outside.

  After completion of the write verify operation, each verify voltage reset is executed (step S14). It is determined whether or not the memory cell to which data “0” is written is in a write state (a state in which the threshold voltage is high) according to the output signal of each verify sense amplifier (step S14). When this data “0” is all in the write state (PASS state), the write is completed.

  On the other hand, if the threshold voltage of the memory cell to which data “0” is written is 1 bit or lower than the write verify voltage Vprg (in the case of FAIL), the process returns to step S9 again to write the memory cell to be written In response to this, the writing operation is executed again.

  In the present invention, at least one of the voltages generated during the erase operation, the write operation, and the verify operation in the write mode is adjusted according to the value of the address (row) of the memory cell.

  FIG. 9 schematically shows an example of the configuration of the 1-bit verify circuit of bit-by-bit verify circuit 62 shown in FIG. FIG. 9 also shows a 1-bit configuration of data latch circuit 28 shown in FIG.

  In FIG. 9, the 1-bit verify circuit of the bit-by-bit verify circuit 62 includes a P-channel MOS transistor 80 for supplying a read current to the main bit line MBL and a bit in the memory cell MC via the main bit line MBL during a write operation. P channel MOS transistor 82 and N channel MOS transistor 84 that supply line write voltage, verify sense amplifier 88 that compares the potential on main bit line MBL with reference voltage Vref during a verify operation, and an output signal of sense amplifier 88 Latch 90 for latching. In FIG. 9, a configuration in which a sense amplifier is provided for verification is shown as an example. This verify sense amplifier 88 may be used for reading data to the outside.

  P channel MOS transistor 80 supplies current from the power supply node to memory cell MC via main bit line MBL and sub bit line SBL in accordance with activation (L level) of read operation activation signal ZREN. Read operation activation signal ZREN is activated in the data read mode and verify read mode. The power supply voltage Vdd is, for example, a voltage level of 1.5V.

  P channel MOS transistor 82 supplies current from the power supply node to main bit line MBL in accordance with activation of write (programming) operation activation signal ZPRG. MOS transistor 84 is selectively turned on according to the output signal of NOR gate 86 receiving latch data of 1-bit data latch 95 and write operation activation signal ZPRG.

  When MOS transistors 82 and 84 are both turned on, the voltage level of main bit line MBL is set to the voltage level determined by the on-resistance of MOS transistors 82 and 84, and the sub bit connected to memory cell MC accordingly. The potential of the line is set, and the bit line write voltage is supplied to the selected memory cell. Write operation activation signal ZPRG is activated when the memory cell is set in the write state, that is, in the write operation mode.

  Verify sense amplifier 88 is activated in accordance with activation of verify sense activation signal VSEN, and compares the potential on main bit line MBL with reference voltage Vref. The latch 90 latches the output signal of the verify sense amplifier 88. The output signal of latch 90 is applied to verify determination circuit 70 shown in FIG. When all the latch data of the latch 90 is set to the state indicating the erase state, the verify determination circuit 70 determines that all the memory cells are set to the erase state during the erase operation. On the other hand, in the write operation, verify determination circuit 70 determines whether or not the write data from 1-bit latch 95 and the latch data from latch 90 match, and the memory cell to be written according to the determination result. Is completely written.

  1-bit data latch 95 included in data latch circuit 28 includes inverters 96 and 98 and transfer gate 100 for transferring write data D to internal node 99 in accordance with activation of latch instruction signal LAT. Inverter 96 inverts and transfers the signal from transfer gate 94 to internal node 99, and inverter 98 inverts the signal at internal node 99 and transfers it to transfer gate 94. The 1-bit data latch 95 may be provided separately from the data latch circuit 28 without being included in the data latch circuit 28 shown in FIG. The inverted data of the latch data of the 1-bit data latch 95 is applied to the verify determination circuit 70, and the match / mismatch of the read data and the inverted data is determined at the time of write verify.

  The latch instruction signal LAT is activated when an external command instructs writing, and the transferred write data is latched in the 1-bit data latch 95. It is assumed that the data writing unit is one row of memory cells, similarly to the erasing unit. However, after the memory cells in one row are erased, for example, data writing may be performed in units of bytes. When writing in byte units, the main bit line is further selected and coupled to the data latch circuit. In this case, a 1-byte data latch is arranged in the data latch circuit 28. The 1-bit data latch of the 1-byte data latch corresponds to the 1-bit data latch 95 shown in FIG.

  In the following description, the write data D is set to the H level when the logical value is “1” corresponding to the erased state, and is set to the L level when the logical value is “0” corresponding to the written state. Let's say.

  In the erase operation, memory gate voltage Vmg is set to a negative erase high voltage (for example, −6 V), and source line SL is set to a positive erase high voltage (for example, 6.5 V). Select gate voltage Vcg is at the ground voltage level, and sub-bit line (SBL) is set in a floating state. As a result, holes are injected into the insulating film of the memory cell MC, and the threshold voltage is lowered.

  In the erase verify mode, memory gate voltage Vmg is set to the erase verify voltage (Vers) level, and select gate voltage Vcg is set to the voltage level of internal power supply voltage Vdd (for example, 1.5 V). In accordance with read operation activation signal ZREN, MOS transistor 80 is rendered conductive, and current is supplied from the power supply node to memory cell MC via main bit line MBL. When the threshold voltage Vthm of the memory cell MC is higher than the erase verify voltage Vers, the memory transistor cannot discharge the current supplied from the MOS transistor 80, and the voltage level of the main bit line MBL is The voltage level is higher than the reference voltage Vref. Therefore, when verify sense amplifier 88 performs a sensing operation in accordance with activation of verify sense activation signal VESN, the output signal of verify sense amplifier 88 becomes H level, and an H level signal is latched in latch 90, causing an erase failure. Is shown.

  On the other hand, when the threshold voltage Vthm of the memory cell MC is lower than the erase verify voltage Vers, the memory transistor of the memory cell MC becomes conductive, the current supplied from the MOS transistor 80 is discharged, and the main bit line MBL The voltage becomes lower than the reference voltage Vref. In this case, when verify sense amplifier 88 is activated in accordance with activation of verify sense activation signal VSEN, its output signal becomes L level, and accordingly, an L level signal is latched in latch 90, indicating normal erasure. It is.

  The latch signal of latch 90 is applied to verify determination circuit 70 shown in FIG. In verify determination circuit 70, an erase instruction signal is applied to write / erase control unit 72 (see FIG. 7) until all latch signals of latch 90 become L level. The write / erase control unit 72 applies a voltage necessary for erasure to the selection gate line, the memory gate line, and the source line in accordance with the erasure instruction from the verify determination circuit.

  When all the latch data of the latch 90 is set to the L level indicating the erased state, the threshold voltage of, for example, one row of memory cells in the erase unit is lower than the erase verify voltage Vers, and all the memory cells are erased. The verify determination circuit 70 provides the write / control unit 72 with a signal indicating that the erase operation has been completed. The write / erase control unit 72 completes the erase operation according to the output signal of the verify determination circuit 70. When a write command is applied, the write / erase control unit 72 shifts to a write operation.

  In the write operation mode, write operation activation signal ZPRG is activated (set to L level). In 1-bit data latch 95, internal node 99 holds a voltage level corresponding to write data D. Therefore, when write data D is at logical value “1” and at H level, the output signal of NOR gate 86 is maintained at L level regardless of activation of write operation activation signal ZPRG, and MOS transistor 84 Maintains a non-conductive state. In this state, during the write operation, MOS transistor 82 is rendered conductive in accordance with activation of write operation activation signal ZPRG, and main bit line MBL and sub bit line SBL are precharged to power supply voltage Vdd level. Therefore, even if the selection gate voltage Vcg in the memory cell MC is, for example, the power supply voltage level of 1.5 V, the selection transistor is in the off state because the gate-source voltage of the selection transistor is lower than the threshold voltage. Writing data to the memory cell MC is prohibited. That is, the memory cell MC is maintained in the erased state and maintains the data “1”.

  On the other hand, when the write data D has the logical value “0” and is at the L level, the output signal of the NOR gate 86 becomes the H level in accordance with the activation of the write operation activation signal ZPRG, and the MOS transistor 84 becomes conductive. In this case, the voltage levels of main bit line MBL and sub-bit line SBL are set according to the on-resistance ratio of MOS transistors 82 and 84. Therefore, in memory cell MC, the voltage difference between select gate voltage Vcg and sub-bit line (SBL) is slightly higher than the threshold voltage of this select transistor. Source line SL is set to the write high voltage, and memory gate voltage Vmg is also set to the write high voltage level. In this state, a channel current flows through the memory cell MC, hot electrons are generated and injected into the insulating film of the memory transistor, and the threshold voltage shifts in a higher direction.

  In the verify operation, read operation activation signal ZREN is activated. Memory gate voltage Vmg is set to write verify voltage Vprg level, and select gate voltage Vcg is set to internal power supply voltage Vdd level. When the threshold voltage Vthm of the memory cell MC is lower than the write verify voltage Vprg, the memory transistor is turned on, a current flows through the main bit line MBL, and the voltage level of the main bit line MBL is equal to the reference voltage Vref. Lower than. In this case, the output signal of the verify sense amplifier 88 becomes L level in accordance with the activation of the verify sense activation signal VSEN, and the L level signal is latched in the latch 90.

  On the other hand, when the threshold voltage Vthm of the memory cell MC is higher than the write verify voltage Vprg, the memory transistor is turned off, no current flows through the main bit line MBL, and the voltage of the main bit line MBL The level becomes higher than the reference voltage Vref. When verify sense amplifier 88 performs a sensing operation according to activation of verify sense activation signal VSEN, its output signal becomes H level, and an H level signal is latched in latch 90.

  When the threshold voltage Vthm of the memory cell is higher than the write verify voltage Vprg and the latch data of the latch 90 is at the H level, if the write data D is a logical value “0”, the write data and the memory cell The stored data has the same logical value. On the other hand, if the threshold voltage Vthm of the memory cell is lower than the write verify voltage Vprg, the latch data of the latch 90 is L level, and the logical value of the write data D is “0”, the write data And the logical value of the data stored in the memory cell do not match.

  When the write data is “1”, the memory cell is in the erased state, writing to the corresponding memory cell is not performed and the erased state is maintained, and the threshold voltage Vthm is higher than the write verify voltage Vprg. At a low voltage level, the latch 90 holds L level data. At this time, the write data has a logical value of “1”.

  Therefore, if the logical value of the inverted write data from inverter 98 and the logical value of latch 90 match, the stored data in the corresponding memory cell matches the write data, and it can be determined that the writing has been performed normally. .

  Writing is repeatedly executed until the pattern of data stored in the latch 90 provided corresponding to the write data matches the input data pattern.

  The control signals ZREN, ZRPG, VSEN, and LAT shown in FIG. 9 are generated from the write / erase control unit 72 shown in FIG.

  FIG. 10 is a diagram schematically showing a change with time of the threshold voltage of the nonvolatile memory cell. In FIG. 10, the vertical axis indicates the threshold voltage Vth of the memory cell in the unit V (volt), and the horizontal axis indicates time. In FIG. 10, a broken line indicates a change over time in a threshold voltage of a memory cell having a high initial threshold voltage Vthi, and a solid line indicates a threshold of a memory cell having a low initial threshold voltage (low Vthi cell). The change with time of the value voltage is shown.

  In FIG. 10, at time t0, immediately after the completion of the write / erase operation, the memory cell holding data “0” has the threshold voltage Vth at the threshold voltage PV level in the written state. The threshold voltage Vth of the memory cell holding “1” is the voltage level of the threshold voltage EV in the erased state. Here, in FIG. 10, the change with time of the threshold voltage of one memory cell is considered.

  In memory cell MC, carriers (electrons or holes) accumulated in the insulating film are gradually released as time passes, and the threshold voltage Vth changes. In the case of a memory cell that retains data “0”, the retained electrons are released with the passage of time, and the threshold voltage thereof decreases. In this case, the threshold voltage of the memory transistor changes in the direction of shifting to the stable initial threshold voltage. Therefore, the threshold voltage Vth changes in a state where the threshold voltage Vth of the high Vthi cell having a high initial threshold voltage Vthi is higher than that of the low Vthi cell having a low initial threshold voltage Vthi. That is, a memory transistor having a low initial threshold voltage Vthi tends to reduce electrons relatively quickly. As for the write characteristics, the memory cell having a low initial threshold voltage tends to be slower in writing.

  On the other hand, in the memory cell holding data “1”, the threshold voltage changes toward the initial threshold voltage in the stable state with time. That is, the accumulated holes in the insulating film are released, and the threshold voltage Vth increases. In this case, the threshold voltage of the high Vthi cell having a high initial threshold voltage Vthi is higher than that of the low Vthi cell having a low initial threshold voltage Vthi.

  The dependency of the threshold voltage Vth over time on the initial threshold voltage can also be considered as follows. That is, it is assumed that the electrical characteristics of the insulating film are the same in the high Vthi cell and the low Vthi cell. A high Vthi cell is equivalent to a state where there are more electrons in the insulating film than a low Vthi cell, and a low Vthi cell is equivalent to a state where the hole concentration in the insulating film is equivalently higher than that of a high Vthi cell. Corresponding to Therefore, when electrons and holes are released from the insulating film over time, the high Vthi cell is equivalently slower than the low Vthi cell, whereas the low Vthi cell is equivalently slower. Is equivalently slower than the high Vthi cell.

  At the time of data reading including verification, read voltage Vread is applied as memory gate voltage Vmg. Therefore, in the high Vthi cell and the low Vthi cell, the margin for the memory gate read voltage Vread decreases with time. In this case, in order to read data “0” and “1” correctly, “0” read lower limit value for reading this data “0” and “1” read lower limit value for reading data “1” correctly. Exists. Therefore, memory cells having different initial threshold voltages Vthi have smaller margins for the “0” read lower limit value and the “1” read lower limit value, respectively. Therefore, when the threshold voltage of the memory transistor after writing / erasing is set to the same voltage level, the “0” read margin is reduced for a low Vthi cell having a low initial threshold voltage Vthi. For a high Vthi cell having a high threshold voltage Vthi, the “1” read margin is reduced. Therefore, when the initial threshold voltage Vthi of each memory cell varies, the margin for the read voltage Vread varies, the electric characteristics of the memory cell vary, and the reading speed varies, so that stable reading can be ensured. There is a possibility of disappearing.

  FIG. 11 schematically shows a change with time of the threshold voltage of the memory transistor of the memory cell according to the present invention. In FIG. 11, the vertical axis represents the threshold voltage Vth of the memory cell, and the horizontal axis represents time. The solid line shows the change over time in the threshold voltage of the low Vthi cell, and the broken line shows the change over time in the threshold voltage Vth of the high Vthi cell.

  In the present invention, the threshold voltage after writing is set to voltage PV1 for a high Vthi cell having a high initial threshold voltage Vthi, and the threshold value after writing is applied to a low Vthi cell. The voltage is set to a voltage PV2 higher than the voltage PV1. On the other hand, the threshold voltage after erasure is set to the voltage EV2 for the low Vthi cell for the memory cell holding the erased data “1”, and for the high Vthi cell, The voltage EV1 is set lower than that of the low Vthi cell.

  When the memory cell holds data “0”, the change with time of the threshold voltage Vth of the high Vthi cell is faster than that of the low Vthi cell. . As for the memory cell that holds data “1”, the high Vthi cell has a lower threshold voltage change rate (rising rate) than the low Vthi cell. The time-varying characteristics of the Vthi cell are almost the same.

  Therefore, after a certain time has elapsed after writing / erasing, in the memory cell, the high Vthi cell and the low Vthi cell have the same margin with respect to the “0” read limit value and the “1” read upper limit value, respectively. Therefore, the electrical characteristics can be the same, and stable data reading can be performed.

  The existence of the high Vthi cell and the low Vthi cell is considered to be caused by the change of the layout pattern as described above. Therefore, it is possible to identify whether the memory cell is a high Vthi cell or a low Vthi cell in advance according to the memory cell position based on the difference in the layout pattern, and according to the address position of the memory cell. The starting threshold voltage at time t0 after the erasing or writing is set. The distribution of the initial threshold voltage of the memory cell can be identified by measuring the threshold voltage distribution of the memory cell (memory transistor) during a test after the manufacturing process.

  FIG. 12 schematically shows an example of a configuration of internal voltage generation circuit 40 according to the first embodiment of the present invention. FIG. 12 shows an example of the configuration of the part that generates the memory gate voltage Vmg.

  12, an internal voltage generation circuit 40 includes an oscillator 102 that generates a buffered clock signal CLK, a charge pump 104 that generates a boosted voltage Vpp by performing a charge pump operation according to the clock signal CLK during operation, and this booster. Voltage divider 106 that divides voltage Vpp, comparator 108 that controls the operation of charge pump 109 according to the voltage level of divided voltage Vpp 2 generated by voltage divider 106, and the operations of oscillator 102 and voltage divider 106 are controlled. A voltage control circuit 110 is included.

  The voltage control circuit 110 receives the operation mode instruction signal OPMOD and the address signal ADX from the control circuit 34 shown in FIG. 1, and when the operation mode instruction signal OPMOD indicates an operation mode that requires a boost operation, that is, erase, write When the read and read (including verify) operations are indicated, the clock enable signal CKEM for the oscillator 102 is activated, and the level selection signal LVL <n: 1> for designating the voltage level according to the operation mode instruction signal OPMOD. Is supplied to the voltage divider 106. The voltage control circuit 110 also extracts a predetermined address bit Add from the row address signal ADX from the address input circuit and supplies it to the voltage divider 106.

  The oscillator 102 is formed of, for example, a ring oscillator, and performs an oscillation operation when the clock enable signal CKEN is activated to generate a clock signal CLK having a certain period. Comparator 108 compares divided voltage (step-down voltage) Vpp2 generated by voltage divider 106 with reference voltage VREF, generates pump enable signal PUEN according to the comparison result, and is supplied to charge pump 104. When pump enable signal PUEN is activated, charge pump 104 performs a charge pump operation with a capacitor according to clock signal CLK to generate boosted voltage Vpp.

  Voltage divider 106 changes the voltage dividing ratio of boosted voltage Vpp according to level selection signal LVL <n: 1> from voltage control circuit 110 and address bit Add, and generates divided voltage (step-down voltage) Vpp2. In the voltage divider 106, the voltage dividing ratio is adjusted by a specific address bit Add to adjust the voltage level of the boosted voltage Vpp according to the address of each memory cell.

  The boosted voltage Vpp is applied to the memory gate line (MG) as the memory gate voltage Vmg. When operation mode instruction signal OPMOD indicates the write verify mode, the threshold voltage of the memory cell (memory transistor) storing data “1” is adjusted by adjusting the voltage level of memory gate voltage Vmg. Can be adjusted. Even when the operation mode instruction signal OPMOD indicates the erase verify mode, the erase verify voltage level applied to the memory gate line is similarly adjusted in accordance with the specific address bit Add to thereby erase the memory cell. The threshold voltage can be adjusted.

  FIG. 13 is a diagram schematically showing an example of the configuration of the voltage divider 106 shown in FIG. In FIG. 13, the thicker 106 includes a voltage level adjusting circuit 120 that generates a voltage level switching signal SW <n: 1> that specifies a voltage level in accordance with the level selection signal LVL <n: 1> and the address bit Add, and a booster. Resistor voltage dividing circuit 122 for resistance-dividing voltage Vpp, and step-down voltage (divided voltage) Vpp2 according to the divided voltage of resistance voltage dividing circuit 122 and voltage level switching signal SW <n: 1> from voltage level adjusting circuit 120 Is included.

  Resistance voltage dividing circuit 122 includes resistance elements R1-R (n + 1) connected in series between a boosting node (output node of charge pump 104) for supplying boosted voltage Vpp and a ground node. Here, FIG. 13 shows, as an example, a configuration in which the voltage level is switched to five levels. Therefore, the level selection signal LVL <n: 1> is a 5-bit level selection signal LVL <5: 1>. In addition, the voltage dividing resistance voltage dividing circuit 122 includes resistance elements R1 to R6.

  A divided voltage V1-V5 is generated from a connection node of the resistance elements R1-R6. Corresponding to these divided voltages V1-V5, switch gates SX1-SX5 are provided in selection circuit 125. These switch gates SX1-SX5 select the corresponding divided voltage in accordance with voltage level switching signals SW <1> -SW <5> from voltage level adjustment circuit 120 to generate step-down voltage Vpp2.

  Voltage level adjustment circuit 120 includes an inverter IV0 for inverting address bit Add and a gate circuit group provided corresponding to each of voltage level switching signals SW <1> -SW <5>. A gate circuit G1 is provided for voltage level switching signal SW <1>. Gate circuit G1 sets voltage level switching signal SW <1> to an active state of an H level when voltage level selection signal LVL <1> and complementary address bit / Add are both at an H level.

  For voltage level switching signal SW <2>, there are provided gate circuits G2 and G3 and a gate circuit GT1 for receiving the output signals of these gate circuits G2 and G3. Gate circuit G2 receives voltage level selection signal LVL <1> and address bit Add, and outputs an H level signal when both are at H level. Gate circuit G3 receives voltage level selection signal LVL <2> and complementary address bit / Add, and outputs an H level signal when both are at H level. Gate circuit GT1 sets voltage level switching signal SW <2> to an active H level when one output signal of gate circuits G2 and G3 is at an H level.

  Gate circuits G4, G5 and GT2 are provided for voltage level switching signal SW <3>. Gate circuit G4 receives voltage level selection signal LVL <2> and address bit Add, and outputs an H level signal when both are at H level. Gate circuit G5 receives voltage level selection signal LVL <3> and complementary address bit / Add, and outputs an H level signal when both are at H level. Gate circuit GT2 sets voltage level switching signal SW <3> to the active state at the H level when one of the output signals of gate circuits G4 and G5 is at the H level.

  Gate circuits G6, G7 and GT3 are provided for voltage level switching signal SW <4>. Gate circuit G6 receives voltage level selection signal LVL <3> and address bit Add, and outputs an H level signal when both are at H level. Gate circuit G7 receives voltage level selection signal LVL <4> and complementary address bit / Add, and outputs an H level signal when both are at H level. Gate circuit GT3 sets voltage level switching signal SW <4> to an active state at an H level when one output signal of gate circuits G6 and G7 is at an H level.

  Gate circuits G8, G9 and GT4 are provided for voltage level switching signal SW <5>. Gate circuit G8 receives voltage level selection signal LVL <4> and address bit Add, and outputs an H level signal when both are at H level. Gate circuit G9 receives voltage level selection signal LVL <5> and complementary address bit / Add, and outputs an H level signal when both are at H level. Gate circuit GT4 sets voltage level switching signal SW <5> to the active state at the H level when one of the output signals of gate circuits G8 and G9 is at the H level.

  Switch gates SX1-SX5 select the corresponding divided voltage V1-V5 when the applied voltage level switching signals SW <1> -SW <5> are in the active state (H level), respectively, and step down. A voltage Vpp2 is generated.

  One of voltage level selection signals LVL <1> -LVL <5> is set to an active state of H level according to the operation mode. The internal voltage generation circuit may be provided according to each operation mode, that is, corresponding to each of the write operation mode, the erase operation mode, the write verify mode, the erase verify mode, and the read mode, A voltage other than the negative erase high voltage may be generated by the internal voltage generation circuit shown in FIG.

  The address bit Add is, for example, the least significant address bit. In the first embodiment, the bit value is set according to whether the selected memory cell is in an even row or an odd row.

  As an example of the initial threshold voltage distribution of the memory cells, it is assumed that the initial threshold voltage Vthi of the even-numbered memory cells is low and the threshold voltage Vthi of the odd-numbered memory cells is high. The distribution of the initial threshold voltage Vthi is detected by the distribution of the initial threshold voltage distribution in the test mode (detected by the operation margin test).

  In the voltage divider 106 shown in FIG. 13, when the address bit Add is “0” (L level) and an even cell (an even row of memory cells) is designated, the gate circuits G1, G3, G5, G7 and G9 are Enabled, gate circuits G2, G4, G6, and G8 are maintained in a disabled state. Accordingly, in this case, voltage level switching signals SW <1> -SW <5> are generated in accordance with voltage level selection signals LVL <1> -LVL <5>.

  On the other hand, when the address bit Add is “1” (H level) and an odd cell (an odd row memory cell) is designated, the gate circuits G2, G4, G6 and G8 are enabled, and the gate circuits G1, G3 , G5, G7, and G9 are disabled. In this case, voltage level switching signals SW <2> -SW <5> are activated according to voltage level selection signals LVL <1> -LVL <4>.

  For example, when voltage level selection signal LVL <2> is active and address bit Add is at H level, voltage level switching signal SW <3> is activated and switch gate SX3 selects divided voltage V3. . On the other hand, in this case, when address bit Add is “0”, voltage level switching signal SW <2> is activated, and voltage V2 is selected as step-down voltage Vpp2 by switch gate SX2.

As shown in FIG. 12, the voltage level of boosted voltage Vpp is adjusted according to the output signal of comparator 108 so that the voltage levels of step-down voltage Vpp2 and reference voltage VREF are equal. In this case, boosted voltage Vpp is expressed by the following equation:
Vpp = VREF · Z / r
Here, Z is a combined resistance value of the resistance elements R1-R6, and r indicates a voltage dividing ratio.

  Therefore, the voltage level of boosted voltage Vpp is higher when voltage V3 is selected than when voltage V2 is selected (because r becomes smaller). That is, address bit Add is “0”, and the voltage level of boosted voltage Vpp is increased when an even cell is selected. Here, as described above, it is assumed that the even cells are low Vthi cells and the odd cells are high Vthi cells. When the addresses of the low Vthi cell and the high Vthi cell are reversed, the address bit application mode shown in FIG. 13 is reversed.

  When the low Vthi cell is selected, the voltage level of the memory gate voltage Vmg is higher than when the high Vthi cell is selected. As described below, in the first embodiment, this voltage Vmg is a write or erase verify voltage, and the lower limit value of the threshold voltage of the low Vthi cell after writing is set to the high Vthi cell. The erasure upper limit threshold voltage of the memory transistor of the high Vth cell after erasure is made lower than that of the low Vthi cell. As a result, the read margin at the time of data access is ensured to the same extent for the high Vthi cell and the low Vthi cell, and variation in electrical characteristics at the time of reading the memory cell is reduced.

  FIG. 14 shows an example of an application mode of boosted voltage Vpp according to the first embodiment of the present invention. In FIG. 14, boosted voltage Vpp is applied to memory gate drive circuits 52e and 52o as memory gate voltage Vmg. These memory gate drive circuits 52e and 52o are provided with decode circuits 130e and 130o, respectively. These decode circuits 130o and 130e decode address signal ADX, respectively, and corresponding memory gate drive circuits 52e and 52o. A selection signal is supplied to. This address signal ADX includes the specific address bit Add shown in FIG. 13 as the least significant bit, for example, so that the selected memory cell is an even cell in an even row or an odd row. Whether the cell is an odd cell is identified.

  Memory gate lines MGe and MGo are provided corresponding to memory gate drive circuits 52e and 52o, respectively. These memory gate lines MGe and MGo are coupled to the memory gates of even cell MCe and odd cell MCo, respectively. As an example, the even cell MCe is a low Vthi cell, and the odd cell MCo is a high Vthi cell.

  Select gate lines CGe and CGo are provided in parallel with memory gate lines MGe and MGo, and impurity regions (conducting nodes) of select transistors of these memory cells MCe and MCo are commonly coupled to bit line BL. Impurity regions (conducting nodes) of the memory transistors of memory cells MCe and MCo are coupled to source line SL.

  At the time of write verify, write verify voltage Vprg is applied to memory gate line MGe or MGo. As described above, the write verify voltage Vprg, that is, the boosted voltage Vpp level is set to a high voltage level for the even-numbered memory cells MCe, while the memory gate drive circuit is set for the odd-numbered memory cells MCo. From 52o, boosted voltage Vpp set at this low voltage level is applied as write verify voltage Vprg. According to the write verify voltage Vprg, whether or not the memory cell MCe or MCo is in the write state is identified.

  FIG. 15 schematically shows threshold voltage distribution of the memory cell of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. The threshold voltage distribution of the memory cell differs depending on the writing state storing data “0” and the erasing state storing data “1”.

  At the time of write verify, write verify voltage Vprg that defines the lower limit of the threshold voltage of the write state is applied. For odd cells, an odd write verify voltage Vprgo corresponding to the lower limit value of the threshold voltage distribution is applied. On the other hand, even-numbered program verify voltage Vprge higher than odd-numbered program verify voltage Vprgo is applied to even-numbered cells. At the time of write verify, if the threshold voltage of the memory transistor is set to a value higher than the lower limit write verify voltages Vprgo and Vprge, it is determined that the write state has been reached. Therefore, the threshold voltage of the even-numbered cell, that is, the low Vthi cell is set higher than the threshold voltage after the writing of the high-Vthi cell (odd number cell) is completed.

  On the other hand, at the time of erase verify in the erase operation mode in which the memory cell is set to the erase state, the erase verify voltage Vers is set to a voltage level corresponding to the upper limit value of the threshold voltage distribution in the erase state. In this case, one of the voltage level selection signals LVL <5: 1> is selected (activated). Even in this case, the upper-limit erase verify voltage Verse is higher than the upper-limit erase verify voltage Verso of the odd-numbered cells for even-numbered cells. Therefore, the threshold voltage distribution of the even-numbered cell, that is, the low Vthi cell is higher than the threshold voltage distribution of the high-Vthi cell (odd number cell).

  Thus, after completion of erasure, as shown in FIG. 11, the starting threshold voltage after completion of writing / erasing is set such that the threshold voltage of the low Vthi cell is higher than the threshold voltage of the high Vthi cell. be able to. As a result, the threshold voltage of the memory cell can be set to substantially the same voltage level for the high Vthi cell and the low VThi cell even after the erasure / write completion time has elapsed, and the electrical characteristics of the memory cell Difference can be reduced, and the data retention characteristics can be set substantially the same.

  Further, in the threshold voltage distribution shown in FIG. 19, even when an erase lower limit verify operation is performed in which the lower limit of the threshold voltage distribution in the erased state is set to a predetermined value or higher, the high Vthi cell is similarly operated. The erase lower limit value is set higher than the erase state lower limit verify voltage of the threshold voltage of the low Vthi cell. The determination as to whether the threshold voltage of the memory cell in the erased state is increased or decreased is made to prevent the memory transistor from being overerased and operating in the depletion mode. When there is no problem even if the selection transistor is provided and the memory transistor is in an overerased state, the lower limit value of the threshold voltage of the memory cell in the erased state may not be adjusted.

  As described above, according to the first embodiment of the present invention, when the electrical characteristics differ according to the address position due to the layout of the memory cell, the verify voltage is changed according to the address position. In addition, variations in the electrical characteristics of the memory cell due to the layout can be reduced, and the memory cell can be set to a state having substantially the same electrical characteristics after erasing / writing. Thus, it is possible to realize a nonvolatile semiconductor memory device in which data retention characteristics (read margin) are small and data can be read stably.

[Embodiment 2]
FIG. 16 schematically shows a structure of internal voltage generation circuit 40 according to the second embodiment of the present invention. FIG. 16 shows a configuration of a portion for generating memory gate voltage Vmg included in internal voltage generation circuit 40. The memory gate voltage generation unit includes a memory gate write verify voltage generation circuit 135, a memory gate write voltage generation circuit 137, and a memory gate read voltage generation circuit 139 to generate a voltage related to writing. Outputs of these voltage generation circuits 135, 137 and 139 are coupled in common to generate a memory gate voltage Vmg. A specific address bit Add is applied to memory gate write verify voltage generation circuit 135.

  Memory gate write verify voltage generation circuit 135 generates a voltage applied to the memory gate at the time of write verification. Memory gate write voltage generation circuit 137 generates a memory gate voltage applied to the selected gate line in the write operation mode. Memory gate read voltage generation circuit 139 generates a voltage applied to the memory gate in the read mode, that is, in the mode of reading data to the outside.

  The internal voltage generation circuit further includes a memory gate erase voltage generation circuit 140 and a memory gate erase verify voltage generation circuit 142 in order to generate a voltage related to the erase operation. The outputs of these voltage generation circuits 140 and 142 are also coupled to a common output with voltage generation circuits 135, 137 and 139.

  Memory gate erase voltage generation circuit 140 generates an erase voltage (negative erase high voltage) applied to the memory gate in the erase operation mode. Memory gate erase verify voltage generation circuit 142 generates an erase verify voltage applied to the memory gate line in the erase verify mode.

  The voltage levels generated by these voltage generation circuits 135, 137, 139, 140 and 142 are adjusted (trimmed) in the test mode and the like, respectively. In the final step of the manufacturing process, the write / erase / read characteristics of the memory are tested for each chip, and the output voltage level of each voltage generating circuit is set to an optimum voltage level according to these characteristics. In the second embodiment of the present invention, a specific access bit Add is applied to memory gate write verify voltage generation circuit 135. A voltage level selection signal programmed in advance is selected by the address bits Add “0” and “1”, and the voltage dividing ratio of the voltage divider is adjusted.

  FIG. 17 schematically shows an example of a configuration of memory gate voltage verify voltage generating circuit 135 shown in FIG. The configuration of memory gate write verify voltage generation circuit 135 shown in FIG. 17 is different from the configuration of internal voltage generation circuit shown in FIG. 12 in the following points. That is, the voltage control circuit 110 provides the clock enable signal CKEN to the oscillator 102 in accordance with the operation mode instruction signal OPMOD, extracts a specific address bit Add from the address signal ADX, and supplies it to the voltage divider 150. Voltage divider 150 steps down boosted voltage Vpp at a pre-programmed voltage dividing ratio according to this specific address bit Add to generate stepped down voltage Vpp2.

  The other configuration of the memory gate write verify voltage generating circuit 135 shown in FIG. 17 is substantially the same as the configuration of the internal voltage generating circuit shown in FIG. 12, and corresponding portions are denoted by the same reference numerals, Detailed description thereof is omitted.

  FIG. 18 schematically shows an example of the configuration of voltage divider 150 shown in FIG. In FIG. 18, a voltage divider 150 includes a voltage level adjustment circuit 155 that generates voltage level selection signals LVL <1> -LVL <5>, a resistance voltage dividing circuit 122 that steps down the boosted voltage Vpp, and the voltage level adjustment circuit. 155 includes a selection circuit 125 that selects a divided voltage of resistance voltage dividing circuit 122 in accordance with voltage level selection signal LVL <1> -LVL <5> from 155. Configurations of resistance voltage dividing circuit 122 and selection circuit 125 are substantially the same as those of the resistance voltage dividing circuit and selection circuit according to the first embodiment shown in FIG.

  The voltage level adjustment circuit 155 includes selectors 162a- provided corresponding to sets of two level setting circuits, that is, level setting circuits 160a-160j whose holding data is fixedly set in advance and level setting circuits 160a-160j. 162e.

  Level setting circuits 160a to 160j are configured by an electrically programmable circuit such as a flash memory or a laser fusing program circuit or an antifuse, for example, and the initial threshold voltage Vthi of the memory cell is distributed during a test. The stored data of the level setting circuits 160a-160j is programmed according to other distributions. Therefore, in level setting circuits 160a-160j, active level data is held in one level setting circuit corresponding to the even value (“0”) and odd value (“1”) of address bit Add. .

  Selector 162a selects one stored data of level setting circuits 160a and 160b according to the bit value of address bit Add, and generates voltage level selection signal LVL <1>. Selector 162b selects one of the data stored in level setting circuits 160c and 160d in accordance with address bit Add to generate voltage level selection signal LVL <2>. Selector 162c selects one stored data of level setting circuits 160e and 160f according to the bit value of address bit Add, and generates voltage level selection signal LVL <3>. Selector 162d selects one of the stored data of level setting circuits 160g and 160h according to the bit value of address bit Add to generate voltage level selection signal LVL <4>. Selector 162e selects one stored data of level setting circuits 160i and 160j according to the bit value of address bit Add, and generates voltage level selection signal LVL <5>.

  One of the voltage level selection signals LVL <1> -LVL <5> generated by the selectors 162a-162e is in an active state, and the switch gates SX1-SX5 have these voltage level selection signals LVL <1>- One of divided voltages V1-V5 is selected according to LVL <5> to generate step-down voltage Vpp2.

  As in the first embodiment, the high Vthi cell is an odd cell and the low Vthi cell is an even cell. In this case, when the address bit Add is “0” (L level), the selectors 162 a-162 e select a voltage level selection signal for designating a high voltage level in the corresponding level setting circuit, and the address bit Add is “ When it is 1 ″ (H level), stored data specifying a low voltage level in the corresponding level setting circuit is selected. Thus, as in the first embodiment, the voltage level of the memory gate write verify voltage Vprg is adjusted, the starting threshold voltage after writing of the high Vthi cell is set to a low state, and the write of the low Vthi cell is set. It is possible to set the starting threshold voltage after insertion to a high threshold voltage level.

  In the case of the configuration according to the second embodiment, the level of the verify voltage generated at the time of write verify can be set in advance by the program circuit (level setting circuits 160a to 160j). Thus, in the voltage control circuit, it is not necessary to use logic gates (gate circuits G1-G9 and GT1-GT4 (see FIG. 13)) in order to generate the level selection signal, and current consumption is reduced. In addition, by programming the data stored in level setting circuits 160a-160j in accordance with the measurement result at the time of the test, the voltage level of the write verify voltage can be accurately set by address bit Add.

  In the configuration of the second embodiment, the configuration shown in FIG. 18 can also be applied to a circuit that generates an erase verify voltage. In this case, the configuration shown in FIG. 18 may be used for generating the write verify voltage and the erase verify voltage, respectively. Further, the voltage divider shown in FIG. 18 may be used to generate both the erase verify voltage and the write verify voltage.

[Embodiment 3]
FIG. 19 schematically shows a configuration of voltage control circuit 110 of the internal voltage generation circuit according to the third embodiment of the present invention. In the configuration shown in FIG. 19, an address scramble circuit 170 is provided which scrambles the address signal ADX, generates a predetermined bit Add, and applies the bit Add to the voltage divider 106 or 150. The address scramble circuit 170 replaces a bit at a specific bit position of the address signal ADX with the least significant bit to generate an address bit Add. When the address signal ADX indicates the address ADX_a, ADX_b,..., ADX_n, the address bit Add is set to a predetermined logic level.

  20A and 20B are diagrams showing an example of the scramble operation of the address scramble circuit 170 shown in FIG. In FIG. 20A, the row address signal ADX has (k + 1) -bit address bits Ak-A0. Address bit Ak is the most significant bit MSB, and address bit A0 is the least significant bit. In this case, the address scramble circuit 170 exchanges the address bit Aj at the specific bit position with the least significant address bit A0. Here, j is any one of 1 to k. After this replacement, as shown in FIG. 20B, the address bit Aj is generated as a specific address bit Add.

  FIG. 21 is a diagram showing an example of address bit allocation to the memory cell array 20. In FIG. 21, in the memory cell array 20, even-numbered subarray blocks SMABe and odd-numbered subarray blocks SMABo defined by even (“0”) and odd (“1”) address bits Aj are alternately arranged. Address signals ADX_a,..., ADX_n shown in FIG. 19 are included in one subarray block. That is, in this case, the address signals ADX_a, ADX_b... ADX_n are addresses that specify memory cell rows in one subarray block.

  Therefore, by using address bit Aj for threshold voltage adjustment, the threshold voltage of memory cells can be adjusted in units of subarray blocks. When the address bit Aj is the most significant bit MSB, the threshold voltage can be adjusted in the upper half region and the lower half region of the memory cell array 20. When memory block address bits designating memory blocks BK0 to BKn are used as address bits Aj, the threshold voltage level can be changed for odd memory blocks and even memory blocks.

[Example of change]
FIG. 22 schematically shows a structure of a modification of address scramble circuit 170 according to the third embodiment of the present invention. In FIG. 22, an address scramble circuit 170 includes an address bit extractor 172 that extracts an address bit at a specific bit position of an address signal ADX, and a decode circuit 174 that decodes an address bit extracted by the address bit extractor 172. including.

  The address bit extractor 172 is composed of, for example, wiring, and extracts one or more specific address bits from the address signal ADX. The decode circuit 174 decodes the address bits supplied from the address bit extractor 172, generates a specific address bit Add according to the decoding result, and supplies it to the voltage divider 106 or 150.

  FIG. 23 schematically shows an operation of address scramble circuit 170 shown in FIG. Address signal ADX has address bits Ak-A0, where address bit Ak is the most significant bit MSB and address bit A0 is the least significant bit LSB. In this case, the address bit extractor 172 extracts address bits Ai-Aj at a specific position by signal wiring indicated by broken lines. The decode circuit 174 sets the address bit Add to “1” when these extracted address bits Ai-Aj have a specific pattern, and sets the specific address bit Add to “0” otherwise. To do. Address bit Add from decode circuit 174 is applied to the voltage divider shown in the first or second embodiment.

  FIG. 24 schematically shows address assignment in the memory cell array according to the modification of the third embodiment of the present invention. In FIG. 24, memory cell array 20 includes subarray block SSAY1 in which address bits Ai-Aj have a specific pattern, and subarray blocks SSAY0 and SSAY2 in which address bits Ai-Aj have a pattern other than the specific pattern. For the sub-array block SSAY1, the specific address bit Add is “1”, and for the remaining sub-array blocks SSAY0 and SSAY2, the address bit Add is “0”. Therefore, in this decoding mode, boosted voltage (verify voltage) Vpp for subarray block SSAY1 is increased, and boosted voltage (verify voltage) Vpp is decreased for remaining subarray blocks SSAY0 and SSAY2.

  Note that the bit value of the specific address bit Add shown in FIG. 24 may be set so that “0” and “1” are reversed.

Further, the address bits supplied to the decode circuit 174 may not be intermediate address bits, but may be address bits at positions consecutive from the most significant bit Ak. Further, the address bits may be arranged discontinuously and discretely. Where i and j satisfy the following equation:
k ≧ i ≧ j ≧ 0.
When all the address bits Ak-A0 are decoded, the threshold voltage for the memory cells in one row can be set higher or lower than the memory cells in the other rows.

  Note that the extracted address bits supplied to the decoding circuit 174 may include a block address specifying the memory blocks BK0 to BKm shown in FIG. In this case, the threshold voltage of the memory cell (memory transistor) is set higher or lower than in the other memory blocks only in a specific area of the specific memory block. The threshold voltage is adjusted in the same manner as in the first or second embodiment.

  As described above, according to the third embodiment of the present invention, the threshold voltage is adjusted with respect to the memory cell row arranged in a specific region instead of the even row / odd row by address scrambling. Therefore, locality exists in the distribution of the high Vthi cell and the low Vthi cell. For example, when the high vthi cell is locally distributed in a specific region, the threshold after the completion of programming / erasing is accurately determined. The value voltage can be adjusted according to the memory cell characteristics. The effects of the first and second embodiments can also be obtained.

[Embodiment 4]
FIG. 25 schematically shows a structure of an internal voltage generating circuit according to the fourth embodiment of the invention. The internal voltage generation circuit shown in FIG. 25 also shows the configuration of the portion that generates memory gate voltage Vmg. The internal voltage generation circuit 40 shown in FIG. 25 differs from the internal voltage generation circuit shown in FIG. 16 in the following points. That is, the voltage level of the verify voltage generated from memory gate write verify voltage generation circuit 180 is constant regardless of the address position of the memory cell. On the other hand, a specific address bit Add is applied to memory gate write voltage generation circuit 182, and the voltage level of the memory gate write voltage generated in the data write operation mode is adjusted according to the address position of the memory cell. The The other configuration of the internal voltage generating circuit shown in FIG. 25 is the same as the configuration of internal voltage generating circuit 40 shown in FIG. 16, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  As the configuration of memory gate write voltage generation circuit 182, any of the configurations of the previous first to third embodiments may be used. According to a specific address bit Add, the voltage level of the generated memory gate write voltage is adjusted according to the address position of the memory cell, as in any of the first to third embodiments.

  FIG. 26 schematically shows a level of the generated voltage in the write operation mode of internal voltage generating circuit 40 according to the fourth embodiment of the present invention. In FIG. 26, a write target memory cell is supplied with a select gate voltage Vcg (for example, 1.5 V) to select gate line CG at the time of writing, and bit line BL is connected to impurity region 2 via bit line BL. Write voltage Vd (for example, 0.8 V) is applied. Source line write voltage Vsl (for example, 5.5 V) is applied to impurity region 3 through source line SL.

  At the time of writing, as described above, a channel is formed below the selection gate line CG (selection gate 5) on the surface of the semiconductor substrate. In the channel current flowing under the memory gate 6, hot electrons are generated by a high electric field at the boundary between the selection gate 5 and the memory gate 6. According to the memory gate write voltage Vmg applied to the memory gate 6 through the memory gate line MG, the generated electrons are injected into the insulating film 7 and held. Therefore, the amount of electrons held in insulating film 7 varies depending on the voltage level of memory gate write voltage Vmg. For high Vthi cells, the memory gate write voltage Vmg is lowered to reduce the amount of injected electrons, while for low Vthi cells, the memory gate write voltage Vmg is increased to increase the amount of injected electrons. The amount of injected electrons is increased. Thereby, the starting threshold voltage of the memory transistor after writing can be set to a low state for the high Vthi cell and to a high state for the low Vthi cell (see FIG. 15). The voltage level is adjusted by adjusting the difference between the boosted voltage Vpp and the step-down voltage Vpp2 as in the first to third embodiments. That is, when voltage difference Vpp-Vpp2 is small, memory gate write voltage Vmg is lowered, and when voltage difference Vpp-Vpp2 is large, memory gate write voltage Vmg is raised. As the internal configuration of memory gate write voltage generation circuit 182, any configuration of the voltage generation circuits shown in the first to third embodiments may be used.

[Example of change]
FIG. 27 schematically shows a structure of a modification of the internal voltage generation circuit according to the fourth embodiment of the present invention. The internal voltage generation circuit 40 shown in FIG. 27 generates a memory gate voltage Vmg, and differs in configuration from the internal voltage generation circuit shown in FIG. 25 in the following points. That is, a specific address bit Add is applied to the memory gate erase voltage generation circuit 184. The specific address bit Add is not applied to the memory gate write verify voltage generation circuit 180 and the memory gate write voltage generation circuit 137. Other configurations of the internal voltage generating circuit shown in FIG. 27 are the same as those of the internal voltage generating circuit shown in FIG. Accordingly, the corresponding voltage generation circuits of the internal voltage generation circuit 40 shown in FIG. 25 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the configuration of the internal voltage generation circuit shown in FIG. 27, in the erase operation mode, the voltage level of the memory gate erase voltage applied to the memory gate line is adjusted according to the position in the array of memory cells.

  FIG. 28 schematically shows a voltage applied to the selected memory cell in the erase operation mode. In the erasing operation mode, the impurity region 2 is set to an open state (open) via the bit line BL, and is set to a floating state. For example, selection gate voltage Vcg of 0 V is applied to selection gate 5 via selection gate line CG. Impurity region 3 is supplied with positive erase source line voltage Vsl of 6.5 V, for example, via source line SL. An erase memory gate voltage Vmg is applied to memory gate 6 through memory gate line MG. During this erasing operation, holes are injected into the insulating film 7 due to the band-to-band tunneling phenomenon due to a high electric field in the vicinity of the impurity region 3, and the threshold voltage is lowered. The larger the amount of holes injected in the insulating film 7, the lower the threshold voltage of the memory cell. Therefore, for high Vthi cells, the memory gate voltage Vmg is lowered to a deeper negative voltage level, and the starting threshold voltage Vth after erasure is lowered. For the low Vthi cell, the memory gate erase voltage Vmg is set to a high voltage (shallow negative voltage level), and the starting threshold voltage Vth after the erase is set high.

  As a result, the threshold voltage of the memory cell in the erased state can be set according to the initial threshold voltage Vthi of the memory cell in accordance with the position of the memory cell during the erase operation, and variations in electrical characteristics can be achieved. Can be reduced.

  Note that the voltage of the memory gate generated during the erase operation is a negative voltage. Therefore, unlike the other voltage generation circuits, this memory gate erase voltage generation circuit 184 is required to generate a negative voltage. In this case, for example, in the voltage divider shown in FIG. 13, a resistance voltage dividing circuit is connected between the boosted voltage supply node and the power supply node. 12 compares positive reference voltage Vref and positive step-down voltage Vpp2, and controls the operation of charge pump 104 according to the comparison result. In this case, charge pump 104 generates a negative voltage as boosted voltage Vpp. As a charge pump that generates a negative voltage, a circuit that uses the charge pump operation of a capacitor can be used as well as a charge pump that generates a positive high voltage. Therefore, as an internal configuration of a memory gate erase voltage generating circuit, The configurations shown in Embodiments 1 to 3 can be used.

  As shown by a broken line in FIG. 27, if a specific address bit Add is given to the memory gate erase verify voltage generation circuit 142, the erase verify voltage level can be adjusted as in the first embodiment. Similarly, the threshold voltage of an erased memory cell can be adjusted. Further, the configurations shown in FIGS. 25 and 27 may be used in combination. That is, both the write voltage and the erase voltage for the memory gate may be adjusted according to the address position of the memory cell.

  As described above, according to the fourth embodiment of the present invention, the voltage level applied to the memory gate at the time of writing or erasing is adjusted according to the initial threshold voltage level (memory cell position) of the memory cell. As in the first to third embodiments, variations in the electrical characteristics of the memory cells can be reduced.

  As the method for adjusting the threshold voltage, any of the configurations of the first to third embodiments may be used.

[Embodiment 5]
FIG. 29 schematically shows a structure of an internal voltage generating circuit according to the fifth embodiment of the present invention. FIG. 29 shows a configuration of a portion for generating the source line voltage Vsl of the internal voltage generation circuit 40. In FIG. 29, the source line voltage generation unit includes a write source line voltage generation circuit 190 and an erase source line voltage generation circuit 192. Output nodes of these voltage generation circuits 190 and 192 are interconnected, and a source line voltage Vsl is generated from the common output node.

  A specific address bit Add is applied to write source line voltage generation circuit 190. Write source line voltage generation circuit 190 includes any of the configurations of internal voltage generation circuits of the first to third embodiments, and the generation mode of this specific address bit Add is set according to the embodiment to be used. Is done. Note that a specific address bit Add is not applied to the erase source line voltage generation circuit 192, and an erase source line high voltage of a predetermined level is generated regardless of the memory cell position.

  FIG. 30 schematically shows a voltage application mode of a selected memory cell in the write operation mode of the nonvolatile semiconductor memory device according to the fifth embodiment of the present invention. In FIG. 30, a write bit line voltage (Vd, for example, 0.8V) is applied to impurity region 2 through bit line BL, and selection gate 5 has a selection of, for example, 1.5V through selection gate line CG. A gate voltage Vcg is applied. Memory gate write high voltage Vmg of 11.5 V, for example, is applied to memory gate 6 via memory gate line MG. Impurity region 3 is supplied with source line voltage Vsl through source line SL.

  In this write operation mode, a channel is formed on the surface of semiconductor substrate region 1. In this case, the resistance value of the channel formed immediately below the selection gate 5 is high, and a high electric field is generated near the boundary between the control gate 6 and the memory gate 6. The amount of hot electrons generated increases as the high electric field generated in this boundary region increases. The voltage applied to the source line SL is almost applied to the boundary region between the selection gate 5 and the memory gate 6. Therefore, the higher the source line voltage Vsl, the higher the electric field in this boundary region.

  The higher the amount of electrons injected into the insulating film 7, the higher the threshold voltage of the memory transistor. Therefore, a low voltage is applied as the write source line voltage Vsl to the high Vthi cell, and the starting threshold voltage Vth after the completion of writing is set to a low voltage level. On the other hand, for the low Vthi cell, write source line voltage Vsl is set to a high voltage level, and starting threshold voltage Vth after completion of writing is set to a high voltage level.

  By adjusting source line voltage Vsl according to the memory cell position according to address bit Add, threshold voltage (starting threshold voltage) Vth after completion of writing according to initial threshold voltage Vthi of the memory cell The voltage level of the memory cell can be adjusted, and the difference in the electrical characteristics of the memory cell can be reduced accordingly.

  Adjustment of the voltage level of the portion that generates the write high voltage in write source line voltage generation circuit 190 is performed according to the same configuration as that of any one of the first to third embodiments (the step-down voltage of the voltage divider is reduced). Adjust the voltage level according to the address bits).

[Example of change]
FIG. 31 schematically shows a structure of a modification of the internal voltage generating circuit according to the fifth embodiment of the present invention. FIG. 31 shows a configuration of a portion that generates source line voltage Vsl, similarly to the configuration shown in FIG. In the source line voltage generating portion shown in FIG. 31, a specific address bit Add is applied to erase source line voltage generating circuit 195. No specific address bit Add is applied to write source line voltage generation circuit 194. Accordingly, in the erase operation mode, the source line voltage is adjusted according to the selected memory cell position, while in the write operation mode, the source line voltage is not adjusted according to the selected memory cell position.

  FIG. 32 schematically shows a manner of voltage application to the selected memory cell in the erase operation mode in the modification of the fifth embodiment of the present invention. As shown in FIG. 32, in the erase operation mode, the impurity region 2 is set to an open (open) floating state via the bit line BL. For example, selection gate voltage Vcg and memory gate voltage Vmg, which are voltage levels of 0 V and −6 V, are applied to selection gate 5 and memory gate 6 via selection gate line CG and memory gate line MG, respectively.

  Impurity region 3 is supplied with source line erase high voltage Vsl through source line SL. In this erase operation mode, holes are injected into the insulating film 7 by the band-to-band tunneling phenomenon due to the high electric field in the vicinity of the impurity region 3. In this case, if the voltage level of the source line SL is high, many holes are generated, and many holes are injected into the insulating film 7 due to the band-to-band tunneling phenomenon, so that the threshold voltage of the memory transistor is lowered. Therefore, for the high Vthi cell, the source line voltage Vsl is set to a high voltage level, more holes are injected, and the starting threshold voltage Vth after the erase operation is set to a low voltage level. On the other hand, for the low VThi cell, the source line voltage Vsl during the erase operation is set to a low voltage level to reduce the hole injection amount, and the starting threshold voltage Vth after the erase is set to a high voltage level. . Thereby, variations in the electrical characteristics of the memory cell after erasure can be reduced in accordance with the characteristics of the initial threshold voltage Vthi of the memory cell.

[Modification 2]
FIG. 33 schematically shows a structure of an internal voltage generation circuit according to a second modification of the fifth embodiment of the present invention. In the configuration shown in FIG. 33, specific address bit Add is applied to write source line voltage generation circuit 190 and erase source line voltage generation circuit 195. Therefore, according to the configuration of the source line voltage generating portion shown in FIG. 33, the threshold voltage Vth is set in accordance with the level of initial threshold voltage Vthi of the memory cell during the write operation and the erase operation. Adjusted. Therefore, regardless of the erased state and the written state of the memory cell, variations in its electrical characteristics can be reduced, and the operation margin can be further improved.

[Modification 3]
FIG. 34 is a flowchart showing an operation sequence of the third modification of the fifth embodiment of the present invention. In FIG. 34, an erase command is applied, and an area designated by the erase command is erased. In FIG. 34, in step S20, an erase command is applied and an erase operation is executed. The operations from step S21 to step S25 after application of the erase command are the same as the erase setup, execution, reset, verify, and verify determination processing from step S4 to step S shown in FIG. Detailed description is omitted.

  Even when erasing is simply performed, the voltage applied to the memory cell is adjusted according to the initial threshold voltage level such as the position of the memory cell to compensate for variations in the electrical characteristics of the memory cell. The voltage level is adjusted according to any one of the aspects described in the first to fifth embodiments.

[Modification 4]
FIG. 35 shows an operation sequence of the fourth modification of the fifth embodiment of the present invention. In FIG. 35, the erase operation is not executed when the write command is applied. Only writing is performed. Therefore, an erase command is applied in order to put an area to be written into an erased state before the write command is applied. In FIG. 35, an erase command is first applied before writing (step S30). When an erase command is applied and an erase operation is designated, erase is executed (step S31). In the erase operation executed in step S31, the setup, execution, reset, verify, and verify determination of the erase operation from step S4 to step S shown in FIG. 8 are performed. Therefore, detailed description thereof is omitted here.

  When it is determined that all the memory cells are in the erased state, the erase is completed (step S32). After this erasure is completed, a write command is applied and data writing is designated (step S33).

  The area to be written is already in the erased state, and writing is executed according to the write data. The processing steps performed after the application of the write command are the same as the flow of the write operation sequence shown in FIG. 8, and the same reference numerals are assigned to the same processing steps (steps S9 to S15). Detailed description is omitted.

  When the erase command and the write command are applied, the voltage level applied to the memory cell is adjusted according to the position of the memory cell as described in the above embodiments. As a result, variations in the electrical characteristics of the memory cell due to variations in the initial threshold voltage of the memory cell can be reduced.

  As described above, according to the fifth embodiment of the present invention, the voltage level applied to the source line during the write and / or erase operation is adjusted according to the position of the memory cell, that is, the initial threshold voltage level. ing. Therefore, even when variations in the initial threshold voltage of the memory cell occur, the variation can be compensated, the electrical characteristics can be set uniformly, and stable data reading can be performed.

  The above-described first to fifth embodiments may be used in appropriate combination.

  In general, the present invention can be applied to a nonvolatile semiconductor memory device in which a memory cell is formed of a serial body of a memory transistor and a selection transistor. The configuration of the memory cell is not limited to a configuration in which electric charges are accumulated in the insulating film, and the present invention can be applied to any memory device in which the memory cell layout is repeatedly arranged in a mirror-symmetric manner in the memory cell array. is there. The nonvolatile semiconductor memory device may be a single chip nonvolatile semiconductor memory device, or a device used for a system LSI integrated on the same semiconductor substrate as other devices such as a processor. May be.

  In the above description, the source line is arranged in parallel with the memory gate line and the control gate line, and erasing / writing is performed in units of memory cells in one row. However, when the source line SL is arranged in a direction orthogonal to the control gate line and the memory gate line, that is, in a direction parallel to the bit line BL, write / erase is performed in units of 1-bit memory cells. can do. In this case, if the memory block can correspond to each IO terminal, writing / erasing in byte units can be realized. In this case as well, the specific address bit Add can be obtained by adjusting the internal voltage level formed when the position of the memory cell, that is, the combination of the specific bit of the row address and the column address satisfies a predetermined condition. An effect can be obtained.

It is a figure which shows roughly the cross-section of the memory cell used in this invention. FIG. 2 is a diagram showing an electrical equivalent circuit of the memory cell shown in FIG. 1. FIG. 2 is a diagram schematically showing a planar layout when the memory cells shown in FIG. 1 are arranged in two rows. FIG. 4 is a diagram schematically showing a cross-sectional structure taken along line L4-L4 shown in FIG. 3. 1 schematically shows an entire configuration of a nonvolatile semiconductor memory device according to the present invention. FIG. FIG. 6 schematically shows a configuration of the memory cell array shown in FIG. 5 and a configuration of its peripheral circuits. FIG. 7 is a diagram schematically showing an overall configuration of a memory cell array and a configuration of a bit line peripheral circuit shown in FIG. 6. FIG. 7 is a flowchart showing a data write operation when a write command is applied in the nonvolatile semiconductor memory device according to the first embodiment of the present invention. FIG. 8 is a diagram illustrating an example of a configuration of a bit-by-bit verify circuit and a data latch circuit illustrated in FIG. 7. It is a figure which shows roughly the time-dependent change of the threshold voltage of the memory cell after the conventional writing / erasing (after data writing). FIG. 7 is a diagram showing a change with time of a threshold voltage of a memory cell after completion of writing / erasing (after data writing) of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. It is a figure which shows roughly the individuality of the internal voltage generation circuit according to Embodiment 1 of this invention. It is a figure which shows schematically the structure of the voltage divider shown in FIG. It is a figure which shows an example of a response | compatibility with the high VThi cell and low Vthi cell and address bit according to Embodiment 1 of this invention. FIG. 7 schematically shows a threshold voltage distribution of a memory cell after write and erase operations of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. It is a figure which shows schematically the structure of the internal voltage generation circuit according to Embodiment 2 of this invention. FIG. 17 schematically shows a configuration of a memory gate write verify voltage generating circuit shown in FIG. 16. FIG. 18 schematically shows a configuration of a voltage divider shown in FIG. 17. It is a figure which shows roughly the structure of the specific address generation part of the voltage control circuit according to Embodiment 3 of this invention. (A) and (B) are diagrams schematically showing a scramble operation of the address scramble circuit shown in FIG. It is a figure which shows roughly a response | compatibility with the area | region of the memory cell array according to Embodiment 3 of this invention, and a specific address (scrambled address bit). It is a figure which shows roughly the structure of the voltage control circuit of the example of a change of Embodiment 3 of this invention. FIG. 23 schematically shows an operation of the voltage control circuit shown in FIG. 22. It is a figure which shows roughly a response | compatibility with the specific address bit and the designation | designated area | region of a memory cell array in the modification of Embodiment 3 of this invention. It is a figure which shows schematically the structure of the internal voltage generation circuit according to Embodiment 4 of this invention. It is a figure which shows roughly the voltage application mode at the time of the write-operation mode of the memory cell according to Embodiment 4 of this invention. It is a figure which shows schematically the structure of the example of a change of the internal voltage generation circuit of Embodiment 4 of this invention. It is a figure which shows roughly the voltage application aspect at the time of the erase operation mode of the memory cell in the modification of Embodiment 4 of this invention. It is a figure which shows schematically the structure of the internal voltage generation circuit according to Embodiment 5 of this invention. It is a figure which shows roughly the voltage application aspect at the time of the write-in operation mode of the memory cell of the non-volatile semiconductor memory device according to Embodiment 5 of this invention. It is a figure which shows schematically the structure of the internal voltage generation circuit of the modification of Embodiment 5 of this invention. It is a figure which shows roughly the voltage application aspect with respect to the memory cell of the example of a change of Embodiment 5 of this invention. It is a figure which shows schematically the structure of the other modification of the internal voltage generation circuit according to Embodiment 5 of this invention. It is a flowchart which shows the operation | movement sequence of the example of a change according to Embodiment 5 of this invention. It is a figure which shows the operation | movement sequence of the further another modification according to Embodiment 5 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate area | region, 2, 3 impurity area | region, 5 selection gate, 6 memory gate, 7 insulating film, MG memory gate line, CG selection gate line, SL source line, BL bit line, 20 memory cell array, 22 row selection drive circuit , 24 column selection drive circuit, 26 sense amplifier circuit, 28 data latch circuit, 30 address input circuit, 34 control circuit, 40 internal voltage generation circuit, 60 bit line peripheral circuit, 62 bit verify circuit, 70 verify determination circuit, 72 Write / erase control unit, 102 oscillator, 104 charge pump, 106 voltage divider, 108 comparator, 110 voltage control circuit, 120 voltage level adjustment circuit, 122 resistance voltage divider circuit, 125 selection circuit, 52, 52e, 52o memory gate Drive circuit, 135 memory gate write verify Voltage generation circuit, 137 memory gate write voltage generation circuit, 139 memory gate read voltage generation circuit, 140 memory gate erase voltage generation circuit, 142 memory gate erase verify voltage generation circuit, 150 voltage divider, 155 voltage level adjustment circuit, 160a-160j level setting circuit, 162a-162e selector, 170 address scramble circuit, 172 address bit extractor, 174 decode circuit, 180 memory gate write verify voltage generation circuit, 182 memory gate write voltage generation circuit, 190, 194 Source line voltage generation circuit, 192, 195 Erase source line voltage generation circuit.

Claims (10)

Each of the memory cells includes a plurality of memory cells that store information in a nonvolatile manner, and each of the memory cells is connected in series with a memory transistor that stores information according to a charge amount accumulated in an insulating film, A selection transistor that forms a path through which a current flows when at least writing / reading storage information of the memory transistor;
An internal voltage generating circuit for generating an internal voltage applied to the selected memory cell according to an operation mode, wherein the internal voltage generating circuit adjusts a voltage level of the internal voltage according to an address signal designating the selected memory cell; A nonvolatile semiconductor memory device including a voltage adjustment circuit.   2. The nonvolatile memory according to claim 1, wherein the internal voltage is a voltage applied to a gate of a memory transistor of the selected memory cell in a write verify mode for verifying whether the selected memory cell is normally written. Semiconductor memory device.   2. The nonvolatile semiconductor device according to claim 1, wherein the internal voltage is a voltage applied to a gate of a memory transistor of the selected memory cell in an erase verify mode for verifying whether or not the selected memory cell has been normally erased. Storage device.   The nonvolatile semiconductor memory device according to claim 1, wherein the internal voltage is a voltage applied to a gate of a memory transistor of the selected memory cell in a write operation mode for setting the selected memory cell to a write state.   The nonvolatile semiconductor memory device according to claim 1, wherein the internal voltage is a voltage applied to a gate of a memory transistor of the selected memory cell in an erase operation mode for setting the selected memory cell to an erased state. The memory transistor of each memory cell has an impurity region connected to the source line,
The internal voltage is a voltage applied via the source line to an impurity region of a memory transistor of the selected memory cell in a write operation mode in which the selected memory cell is set in a write state. Nonvolatile semiconductor memory device. The memory transistor of each memory cell has an impurity region connected to the source line,
2. The nonvolatile memory according to claim 1, wherein the internal voltage is a voltage applied via the source line to an impurity region of a memory transistor of the selected memory cell in an erase operation mode for setting the selected memory cell to an erased state. Semiconductor memory device. The internal voltage adjustment circuit includes:
A data storage circuit for storing data specifying the amount of change in voltage level is provided, the specified data is programmable, and further, the stored data of the data storage circuit is selected according to the address signal and the level of the internal voltage is specified. The nonvolatile semiconductor memory device according to claim 1, further comprising a circuit that generates a level selection signal to be generated. The address signal is a multi-bit address signal having a plurality of bits;
The internal voltage adjustment circuit includes:
A scramble circuit that scrambles the multi-bit address signal to generate an address bit at a predetermined bit position;
The nonvolatile semiconductor memory device according to claim 1, further comprising a circuit that adjusts a level of the internal voltage in accordance with a scramble result of the scramble circuit. The address signal is a multi-bit address signal having a plurality of bits;
The internal voltage generation circuit includes:
A voltage control circuit that generates a level selection signal that specifies a level of the internal voltage according to an operation mode and extracts an address bit at a specific position of the multi-bit address signal;
The nonvolatile semiconductor memory device according to claim 1, wherein the internal voltage adjustment circuit generates a voltage level switching signal that specifies a level of the internal voltage in accordance with the level selection signal and the extracted address bits.

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