JPH11273387A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent malfunction of a non-volatile semiconductor memory device, and to improve its yield. SOLUTION: When data are written to the memory cell of odd columns by an even/odd data signal O/E being supplied to a selector 1, a first constant- voltage diode 2 and a first cell transistor 3 for correction in the same structure as even columns are selected. On the other hand, when data are written to even columns, a second constant-voltage diode 4 and a second cell transistor 5 for correction in the same structure as the odd columns are selected. According to the difference between the threshold voltages of the first and second transistors 3 and 5 for correction, a writing voltage being supplied to a writing control circuit 31 from a booster circuit 32 is adjusted, the amount of charge being injected to a floating gate is controlled, and the fluctuation of the characteristics of a memory cell transistor is adsorbed for deleting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device in which a memory cell having a floating gate can be electrically rewritten.

[0002]

2. Description of the Related Art Electrically rewritable EEPROM
(Electrically Erasable Programmable Read Only Mem
ory) includes what is called a flash memory. A flash memory stores information by controlling a state in which charge is injected into a floating gate and an erased state for each memory cell.

FIG. 2 shows a unit cell structure of a flash memory. (11) is a P-type semiconductor substrate, for example, (1)
2) and (13) are a drain region and a source region made of an N-type diffusion layer, (14) is an oxide film, (15) is a floating gate made of polycide, (16) is an oxide film, and (17) is a polycide. (18) is an interlayer insulating film, and (19) is a bit line. The bit line (19) is connected to the drain region (12). In the structure described here, a part of the control gate (17) extends above the floating gate (15), and the remaining part is a split gate type in which the channel is directly controlled on the oxide film (14). I have. In particular, a protrusion is provided at an end of the floating gate (15), and electrons are extracted from the floating gate (15) to the control gate (17) at the time of erasing. In addition, the drain region (1
2) and the source region (13) are formed by ion implantation and thermal diffusion using the floating gate (15) and the control gate (17) as masks. In particular, the source region (13) has a large implantation amount. Therefore, the thermal diffusion region extends below the floating gate (15), and a capacitive coupling is formed between the floating gate and the floating gate (15).

FIG. 3 shows a cell array of a flash memory. In the center of the figure, a word line (21) and a source line (23) run in parallel, and a bit line (22) runs crossing it. At the intersection of the word line (21) and the source line (23) with the bit line (22), one memory cell transistor (20) shown in FIG.
Are formed. The word line (21) is connected to all control gates (17) in the same row. The bit line (22) is connected to all drain regions (12) in the same column, and the source line (23) is connected to all source regions (13) in the same row. The source line (23) is further connected to a power supply line (26). The source line (23) is obtained by extending the source region (13) shown in FIG. 2 in the direction perpendicular to the plane of the drawing. On the left side of the figure, a row decoder (2
7) are connected to each word line (21). In the upper part of the figure, a column decoder (28) for selecting a column position
And controls on / off of a column selection transistor (24) connected to the data line (25) and each bit line (22). The power supply line (26) is connected to the first write control circuit (3
The first write control circuit (31) is supplied with the voltage of the booster circuit (32). The data line (25) is controlled by a second write control circuit (33).

When writing with this configuration, first,
The high voltage generated in the booster circuit (32) is applied to the power supply line (26) from the first write control circuit (31), and 15 V is applied to the source region (13) via the source line (23). I do. At the same time, the data line (25) is grounded by the second write control circuit (33). In this state, for example,
When writing to the memory cell (20) at the upper left position (1, 1), the first word line (2
1) is selected, a 2V voltage is applied to the control gate (17), and the first column selection transistor (24) is turned on by the column decoder (28), and the drain region (12) is grounded. Then, a high voltage is applied to the floating gate (15) for capacitive coupling with the source region (13), and as a result, the memory cell transistor (20) is turned on. As a result, the electrons supplied to the drain region (12) are accelerated and injected as hot electrons through the oxide film (14) into the floating gate (15). As described above, the threshold value of the memory cell transistor (20) in which electrons are injected into the floating gate (15) is high.

When reading the written cell,
First, the power supply line (2) is supplied by the first write control circuit (31).
6) is grounded, and the source region (13) is grounded via the source line (23). At the same time, a low voltage is applied to the data line (25) by the second write control circuit (33). In this state, the memory cell (2) at the position (1, 1)
To read 0), the first word line (21) is selected from the row decoder (27), 2 V is applied to the control gate (17), and the first column is selected by the column decoder (28). The transistor (24) is turned on, and the drain region (1) is connected via the data line (25).
3) 1V is applied. In the memory cell transistor (20), since electrons are injected into the floating gate (15) and the threshold is raised, the memory cell transistor (20) does not turn on yet and no current flows. As a result, the voltage of the bit line (22) does not fluctuate, and the bit line (2) is
0) The voltage is compared with the reference voltage, and “1” is read.

On the other hand, if no data is written to the memory cell transistor (20) at the position (1, 1),
The memory cell transistor (20) is turned on by the voltage applied to the control gate (17), and a current flows between the source and the drain. As a result, the voltage of 1 V applied to the bit line (22) changes, so that the sense circuit compares the changed bit line (22) voltage with the reference voltage and reads "0".

When erasing, the first write control circuit (3
1) and the second write control circuit (33), the power supply line (2
6) and the data line (25) are grounded, and all the column selection transistors (24) are turned on by the column decoder (28), so that the drain region (12)
And the source region (13) is grounded. In this state, all the rows are further selected by the row decoder (27),
A high voltage of 14 V is applied to the control gate (17). Then, an electric field concentrates on the protrusion formed on the floating gate (15), and electrons are extracted to the control gate (17) by a tunnel effect.

[0009]

The split gate type flash memory shown in FIG. 2 has a problem that the occupied area of the memory cell is larger than that of a stack gate type in which a control gate and a floating gate are vertically stacked. . For this reason, as shown in FIG. 2, a structure is adopted in which the occupied area is made as small as possible by forming a cell array in which the positions of the drain (12) and the source region (13) are reversed in the row direction between adjacent rows. Have been. However, such a cell array causes a new problem as described below.

If there is a mask shift during the manufacturing process, the planar positional relationship between the drain region (12) and the source region (13), the floating gate (15), and the control gate (17) may be shifted. Therefore, the on-current value may fluctuate due to a change in the channel length or a change in the amount of electrons injected into the floating gate (15). As a result,
In the written cell, "1" should be read because no ON current flows, but the ON current value becomes large and "0" is read.

[0011] Such a problem is caused by mask displacement.
Although it is possible to solve the problem by a method such as finely adjusting the reference voltage at the time of writing, in the cell array structure of FIG. 3, it is necessary to increase or decrease the reference voltage in the odd rows and the even rows. Is different. Therefore, in order to solve the problem of the mask shift by adjusting the reference voltage, the circuit configuration becomes too complicated.

[0012]

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and a plurality of memory cell transistors for storing write information by injecting electric charge into an electrically insulated floating gate are arranged in a matrix. Wherein the memory cell transistors are arranged so that the positional relationship between the source and the drain thereof is reversed between odd-numbered rows and even-numbered rows. A first correction cell transistor having the same source-drain positional relationship as the transistor and a first limiter circuit including a constant voltage diode; and a second limiter circuit having the same source-drain positional relationship as the odd-numbered memory cell transistors. And a second limiter circuit comprising a compensating cell transistor and a constant voltage diode. Select the first or second limiter circuit by the row position information of the memory cell transistor selected in order to inject charge into computing gate,
The configuration includes a control circuit that controls a write voltage according to the selected limiter circuit.

Accordingly, the write voltage is adjusted under the influence of the characteristic variation of the first or second correction cell transistor in accordance with the writing to the even-numbered row or the writing to the odd-numbered row. The amount of charge injected into the floating gate is controlled, and fluctuations in the characteristics of the memory cell transistor are absorbed and erased.

[0014]

FIG. 1 is an equivalent circuit diagram of a correction circuit according to an embodiment of the present invention. A selector (1), a first constant voltage diode (2), a first correction cell transistor (3), a second constant voltage diode (4), and a second
(5). The high voltage VH from the booster circuit (32) is supplied to the first write control circuit (3
1) and supplied to the input terminal of the selector (1). The selector (1) is a row decoder (27)
The same row position data as above, in particular, the data of the least significant bit that determines whether the row is an odd row or an even row is received as an even / odd data signal O / E, and selection switching of two output terminals is controlled. One of the two output terminals of the selector (1) has the same source / drain direction as the odd-numbered row of the memory cell transistor (20) shown in FIG. 2 through the first constant voltage diode (2). The selection gate (17) of the first correction cell transistor (3) is connected to the source region (13), and the other output terminal is connected to the same as the even-numbered row via the second constant voltage diode (4). The selection gate (17) of the second correction cell transistor (5) having a source / drain direction is connected to the source region (13).
These first and second correction cell transistors (3)
The drain region (12) of (5) is connected to the ground power supply VSS. The first and second correction cell transistors (3) and (5) are memory cell transistors (20).
At the same time, they are manufactured on the same substrate. In addition, the first and second
Constant voltage diodes (2) and (4) have the same characteristics.

For example, the floating gate 15 and the select gate 1
The planar positional relationship of 7) may be shifted. In FIG. 2, the floating gate (15) and the selection gate (1
7) is shifted to the left and right, and the even rows are changed in a direction away from each other, and the odd rows are changed in a direction approaching each other. Drain region (12) and source region (13)
Are the floating gate (15) and the selection gate (1
7) is formed using the mask as a mask, so that the channel length becomes longer for even rows and the channel length becomes shorter for odd rows. As a result, the on-resistance increases and the threshold voltage increases for even rows, and the on-resistance decreases and threshold voltage decreases for odd rows.

In the present invention, the selector (1) is controlled by the even / odd data signal O / E when writing, and the first constant voltage diode (2) and the first
When selecting the first limiter including the correction cell transistor (3) and writing the data in an odd-numbered row, the second limiter including the second constant voltage diode (4) and the second correction cell transistor (5) Select As a result, the high voltage VH generated by the booster circuit (32) is controlled to adjust the write voltage.

The booster circuit (32) is a circuit for increasing the voltage without any limitation and obtaining a high voltage VH. In addition, limiters (2,
3) (4, 5) is a ground power supply when a voltage exceeding the sum Va, Vb of the threshold voltage of the correction transistors (2) (4) and the breakdown voltage of the constant voltage diodes (3, 5) is applied. By applying a current to VSS, a constant voltage is output regardless of the current value. That is, the high voltage VH output from the booster circuit (32) is controlled and stabilized by the voltages Va and Vb connected via the selector (1). Further, since the first correction transistor (3) of the present invention has the same structure as the memory cell transistors (20) in the odd-numbered rows, the threshold value is relatively small, and the voltage Va is relatively low. Further, since the second correction transistor (5) has the same structure as the memory cell transistors (20) in the even rows, the threshold value is relatively large and the voltage Vb is relatively high.

In this configuration, when writing data to an even-numbered row, the first limiter (2, 3) is selected, and the high voltage VH is controlled to be lower by the voltage Va. ), The write voltage applied to the power supply line (26) is made lower. As a result, the voltage applied to the source region (13) of the memory cell transistor (20) decreases, the amount of electrons injected into the floating gate (15) decreases, and the written memory cell transistor (20) Rise of the threshold value is suppressed to a small value. As a result, the on-resistance decreases, and the increase in the on-resistance due to the mask shift is offset. Also, when writing to an odd-numbered row, the second limiter (4, 5) is selected, and conversely, the high voltage VH applied from the booster circuit (32) to the first write control circuit (31) is applied. , The voltage Vb is controlled to be higher, and the write voltage is made higher. Therefore, the voltage applied to the source region (13) becomes relatively high, and the amount of electrons injected into the floating gate (15) increases. As a result,
The on-resistance of the written memory cell transistor (20) increases, and the decrease in on-resistance due to mask shift is offset.

Further, in the present invention, as shown in FIG. 1, the first and second correction transistors (3) and (5) are formed by connecting several tens of transistors (3) and (5) in parallel. ing. Therefore, the current between the source and the drain of each of the first and second correction transistors (3) and (5) becomes substantially zero, and the total current flowing through each of the limiters (2, 3) (4, 5) becomes Regardless, the voltages Va and Vb are stabilized.

As described above, according to the present invention, whether the writing is performed in the even-numbered row or the odd-numbered row, the first and second correction cell transistors (3) (3) ( In this configuration, the write voltage is controlled by utilizing the characteristic change of 5). Therefore, even if the characteristics of each memory cell transistor (20) fluctuate due to a mask shift during the manufacturing process, the amount of charge injected into the floating gate (15) is controlled in a direction to absorb the fluctuation in the characteristics. Therefore, malfunction can be prevented.

[0021]

As described above, according to the present invention,
Since it is possible to automatically absorb and erase fluctuations in characteristics occurring during the manufacturing process of the nonvolatile semiconductor memory,
Malfunction is prevented, and the yield is improved.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a correction circuit of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a cell structure of a nonvolatile semiconductor memory device.

FIG. 3 is an equivalent circuit diagram showing a cell array of the nonvolatile semiconductor memory device.

[Explanation of symbols]

 Reference Signs List 1 selector 2, 4 constant voltage diode 3, 5 correction cell transistor 12 drain region 13 source region 15 floating gate 17 selection gate 21 word line 19, 22 bit line 23 source line 24 column selection transistor 25 data line 26 power supply line 27 low Decoder 28 Column decoder 31, 33 Write control circuit

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (3)

[Claims] 1. A plurality of memory cell transistors for storing write information by injecting electric charge into an electrically insulated floating gate are arranged in a matrix.
In the non-volatile semiconductor memory device, the memory cell transistors are arranged in such a manner that the positional relationship between the source and the drain thereof is reversed between odd-numbered rows and even-numbered rows. A first limiter circuit comprising a first correction cell transistor and a constant voltage diode having the following positional relationship, and a second correction cell transistor having the same source / drain positional relationship as the memory cell transistors in the odd rows. A second limiter circuit including a constant voltage diode, wherein the first or second limiter circuit is selected and selected based on row position information of the memory cell transistor selected to inject electric charge into the floating gate; Having a control circuit for controlling a write voltage in accordance with the limiter circuit A nonvolatile semiconductor memory device characterized by the above-mentioned. 2. The non-volatile memory according to claim 1, wherein each of the first correction cell transistor and the second correction cell transistor has a plurality of correction cell transistors connected in parallel. Semiconductor memory device. 3. The control circuit selects the first limiter circuit when the row position information indicates an even-numbered row, and selects the second limiter circuit when the row-position information indicates an odd-numbered row. The nonvolatile semiconductor memory device according to claim 1.