JPH11297086A - Nonvolatile semiconductor memory, integrated circuit including the same and method of adjusting write time of memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory and integrated circuit contg. the same such as microcomputers wherein the write time can be adjust able as desired in a process after the chip manufacturing. SOLUTION: The nonvolatile semiconductor memory or integrated circuit contg. the same having a power source circuit 25 having a reference voltage generator circuit 50, first booster circuits 90, 70 for generating writing high voltages and second booster circuits 90, 80 for generating erasing high voltages, power source switching circuit comprises a first trimming circuit 53 for adjusting the reference voltage generated by the reference voltage generator circuit 50, and second trimming circuits 72, 92 for adjusting the writing high voltage generated by the first booster circuit so as to change the voltage generated by the first booster circuit according to the counted no. of applying times of the writing voltage to the memory element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique which is effective when applied to fine adjustment of a writing time in an electrically erasable nonvolatile semiconductor memory. For example, data can be erased collectively in block units. The present invention relates to a technology that is effective when used in a microcomputer having a built-in flash memory chip.

[0002]

2. Description of the Related Art A flash memory uses a nonvolatile memory element having a control gate and a floating gate as a memory cell, and the memory cell can be constituted by one transistor. In such a flash memory, in the write operation, as shown in FIG. 14B, the voltage of the drain region D of the nonvolatile memory element is set to, for example, 6.7 V (volt), and the control gate C is turned on.
-GATE is connected to a word line, for example, -10.0V
The floating gate F-GATE
, The charge is drawn out to the drain region D to lower the threshold voltage (logic "0"). In the erase operation, as shown in FIG. 14C, the source region S and the base P-SUB are set to, for example, -10.0 V, the control gate C-GATE is set to a high voltage such as 10.5 V, and the floating gate is set. A negative charge is injected into F-GATE to bring the threshold value to a high state (logic "1"). This gives 1
One bit of data is stored in one storage element.

In a flash memory, writing is generally performed simultaneously, for example, on a sector basis, that is, for one row of memory cells having a common word line, and erasing is performed on a block basis, that is, a plurality of sectors having a common well region. And at the same time, unless otherwise specified in the embodiments of the present invention.

[0004]

In a flash memory, different voltages are applied to storage elements in a write operation, an erase operation, a read operation, and the like. Such various voltages are generated in the power supply circuit inside the memory, but the characteristics of the elements constituting the power supply circuit vary due to process variations, and the voltages generated thereby also vary. as a result,
Correct operation of the memory is no longer guaranteed. Therefore, in order to be able to finely adjust the generated voltage at a stage after the chip is manufactured, it has been studied to provide a voltage trimming circuit.

However, even if the reference voltage generated by the power supply circuit in the memory is adjusted to a desired value by the trimming circuit, there is a problem that the writing time greatly varies and the yield decreases. Was. That is, in the MOSFET constituting the storage element of the flash memory, parameters such as the size of each part of the element such as the thickness of the gate oxide film and the impurity concentration of the drain region vary depending on the process. As a result, when a screening test based on the writing time is performed on the flash memory that has only been subjected to the voltage adjustment, it becomes clear that a chip that becomes a non-defective product is determined as a defective product if the writing voltage is slightly increased, and the non-defective product ratio is reduced. Was. Also, if there is a product in the assembly line of the user system where the writing time does not fall within the specified time, data writing to the flash memory will not be completed within the time set in the assembly line,
There is a possibility that a trouble that the line stops will occur.

The write time can be shortened by increasing the write voltage. However, if the write time is too short, the threshold voltage of, for example, 0.5 to 1.0 V should be stored in a normal storage element. Another problem occurs in that a storage element in a so-called depleted state in which the threshold value of the element becomes 0 V or less occurs. Therefore, the write voltage cannot be extremely increased, and a reselection test based on the write time cannot be omitted for a memory adjusted to increase the write voltage.

An object of the present invention is to provide a nonvolatile semiconductor memory capable of arbitrarily adjusting a writing time in a process after manufacturing a chip, and a semiconductor integrated circuit such as a microcomputer incorporating the same.

Another object of the present invention is to adjust the non-defective rate of a non-volatile semiconductor memory in which the writing time varies due to process variations or a semiconductor integrated circuit such as a microcomputer incorporating the same, and to adjust the writing time in a process after chip manufacture. The purpose is to be able to improve by doing.

Still another object of the present invention is to provide a technique of adjusting a write voltage capable of efficiently executing a selection test based on a write time of a nonvolatile semiconductor memory or a semiconductor integrated circuit such as a microcomputer incorporating the same. .

Still another object of the present invention is to provide a system for assembling a system using a nonvolatile semiconductor memory or a semiconductor integrated circuit such as a microcomputer incorporating the same in which the writing time to the nonvolatile memory is longer than the line transfer interval. It is an object of the present invention to prevent the occurrence of troubles such as a long line stop.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

The following is a brief description of an outline of typical inventions disclosed in the present application.

That is, a reference voltage generating circuit, a first boosting circuit for generating a high voltage for writing (negative voltage or positive voltage), and a second boosting circuit for generating a high voltage for erasing (positive voltage or negative voltage) A power supply circuit having a circuit and a power supply switching circuit, wherein data is stored by changing a threshold value of a storage element having a gate, a source, and a drain by controlling a voltage applied to the gate, the source, and the drain. A trimming circuit that adjusts a reference voltage generated by the reference voltage generation circuit, and a writing circuit that is generated by the first booster circuit. A second trimming circuit for adjusting the high voltage is provided, and a means for counting the required writing time is provided. Also it is obtained so as to vary the generated voltage of the second trimming circuit.

According to the above-described means, the reference voltage generated by the reference voltage generation circuit can be adjusted by the first trimming circuit so that the reference voltage is the same even if it varies between chips. Even if the characteristics vary between chips, the writing time can be corrected to be substantially constant between chips by adjusting the high voltage for writing generated in the first boosting circuit by the second trimming circuit. .

As means for counting the required writing time, there are, for example, a counter for counting the number of application of the writing voltage to the word line connected to the gate of the storage element and a timer for directly determining the writing time. Further, this counter is preferably a soft counter or a soft timer updated by a program for performing write control, but may be a counter circuit or a timer circuit operated by a signal. However, the configuration using software has the advantage that the amount of hardware can be reduced and the chip size can be reduced.

Further, the number of times of application of the write pulse to the word line at the time of the write operation is counted by a test for checking the function of the decoder by sequentially selecting all the word lines and the data lines in the memory. The voltage of the second trimming circuit is adjusted based on the numerical value. As a result, even if the write characteristics of the storage element vary between chips, the write time can be corrected so that the write time becomes substantially constant between the chips, and a write test is performed after trimming to make sure that the write time is within the allowable range. By sorting, only the chip having really a problem with the writing time can be regarded as defective, and the yield rate can be improved.Also, even if a chip with a slow writing comes out, the writing time can be adjusted by adjusting the writing time. Can be shortened.

Although not described in the present embodiment, a third trimming circuit is added to a second booster circuit for generating a high voltage for erasing, and the number of times of application of the erasing voltage is increased in the same manner as in writing. After counting, the erasing voltage is adjusted by the third trimming circuit based on the counted value, so that even if the erasing time varies between chips, it can be corrected so as to be substantially constant between chips.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a microcomputer having a built-in flash memory (hereinafter referred to as a flash microcomputer) will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a flash microcomputer to which the present invention is applied. Although not particularly limited, each circuit block shown in FIG. 1 is formed on one semiconductor chip such as single crystal silicon.

In FIG. 1, FLASH is a MOSF having a floating gate as shown in FIG.
A memory array in which memory cells as nonvolatile storage elements made of ET are arranged in a matrix, an address decoder for selecting memory cells, an address and data latch circuit, a sense amplifier for amplifying data, writing, erasing, and reading of data FLC is a flash controller that performs writing, erasing and trimming on the flash memory circuit, CPU is a central processing unit that controls the entire chip, and RAM is Random access memory for temporarily storing data and providing a work area for the central processing unit CPU; BUS is the central processing unit CPU, flash memory circuit FLASH, flash controller F
A bus that connects between the LC and the high-speed memory RAM, and a BSC is a bus controller that controls the occupancy of the bus.

Although not shown in FIG. 1, in the case of a microcomputer such as a single-chip microcomputer, in addition to the above-mentioned circuit blocks, a DMA (direct memory) between an internal memory and an external memory is used. Memory access)
DMA transfer control circuit for controlling transfer, interrupt control circuit for determining the occurrence and priority of an interrupt request to the CPU and issuing an interrupt, serial communication interface circuit for performing serial communication with an external device, various timer circuits, analog An A / D converter for converting signals and digital signals, a watchdog timer for system monitoring, an oscillator for generating a clock signal required for system operation, and the like are provided as necessary.

FIG. 2 shows the flash memory circuit FL
The schematic configuration of the ASH is shown. In FIG. 2, 11
Is a memory array in which memory cells are arranged in a matrix as nonvolatile memory elements formed of MOSFETs having floating gates as shown in FIG. 14, 12 is a data register for holding externally input write data, Reference numeral 13 denotes a write circuit for writing data to the memory array 11 based on the data held in the data register 12.

An address register 14 holds an address signal, and an X decoder 15 selects one word line corresponding to the X address taken into the address register 14 from the word lines in the memory array 11. ,
Reference numeral 16 denotes a Y decoder for decoding the Y address taken into the address register 14 and selecting one byte (or one word) of data in one sector, and 17 an erasure for selecting a block (mat) at the time of erasure. Control circuit, 1
Reference numeral 8 denotes a sense amplifier that amplifies and outputs data read from the memory cell array 11.

Further, in the flash memory circuit of this embodiment, in addition to the above-described circuit blocks, a control circuit 27 for converting an external control signal into a control signal for each circuit of the flash memory, and an input of an address signal and a data signal. An I / O buffer circuit 23 for performing output, a power supply circuit 25 for generating a voltage required inside the chip such as a write voltage, an erase voltage, a read voltage, a verify voltage based on a power supply voltage Vcc supplied from the outside, and a memory A power supply switching circuit 26 for selecting a desired voltage from these voltages according to the operation state and supplying the selected voltage to the memory array 11 is provided.

Although a detailed configuration of the flash controller FLC is omitted, the flash controller FLC of this embodiment has a control register, and the CPU has a RAM.
When the control register is written in accordance with the program stored in the flash controller F,
The LC forms a control signal for the flash memory circuit FLASH in accordance with the bit state of the control register, and performs operations such as writing, erasing, reading, and verifying.

FIG. 3 shows a control register CNTR for controlling writing and erasing of the control registers.
Is shown. The register of this embodiment includes a bit FWE for protecting the data from being carelessly written and erased, a bit SWE for instructing power supply to the power supply circuit 25, a polarity of output of the decoder, power supply switching, and the like. Write setup bit PS for making memory array and its peripheral circuits ready for writing
V, a bit P for giving a write pulse, an erase setup bit ESV for putting the memory array and its peripheral circuits into an erase preparation state, a bit E for giving an erase pulse, and a bit for giving an erase verify It comprises an EV, a bit PV for instructing to perform write verification, and the like.

The flash controller FLC has, in addition to the control register CNTR for the write / erase control, an erase select register for selecting an erase block from a plurality of blocks in the memory array at the time of erasing, and a voltage trimming described later. Registers TRMR1 for setting values
TRMR2 (see FIG. 4) is provided with a register for holding rescue information for replacing a memory column including a defective bit in the memory array with a spare memory column.

Although not particularly limited, in this embodiment, the values of the trimming registers TRMR1 and TRMR2 are stored in a predetermined area in the memory array of the flash memory circuit FLASH, and are read from the flash memory circuit at reset. Trimming register TR
MR1 and TRMR2 are set. The control register CNTR for the write / erase control includes:
Not only in the test and trimming value determination described below,
It is also used during normal writing and erasing operations.

In a conventional flash memory, a control signal for each circuit in the memory is sequentially transmitted in order to decode a command given from an external CPU or the like and execute a process corresponding to the command based on the decoded result. It has a control circuit (sequencer) for forming and outputting, and the control circuit stores a series of microinstructions necessary for executing a command (instruction), for example, like a control section of a microprogram type CPU. In this embodiment, the flash controller FLC includes the above-described control register CNTR, and the CPU includes a RAM (Read Only Memory).
When the control register is written in accordance with the program stored in the flash controller F,
Since the LC is configured to form a control signal for the flash memory circuit FLASH in accordance with the bit state of the control register CNTR and perform operations such as writing, erasing, reading, and verifying, the controller of the conventional command method is used. There is an advantage that the scale of hardware can be reduced as compared with the above.

FIG. 4 shows a specific example of the power supply circuit 25. The power supply circuit of this embodiment includes a reference voltage generation circuit 5
Based on 0 and a reference voltage Vrefa such as 2.5 V generated by the reference voltage generating circuit 50, a voltage Vr such as 4.25 V applied to a control gate of a memory cell via a word line at the time of reading. Or a voltage V such as 2.5 V applied to the control gate during write verification.
a voltage generating circuit 60 for generating pv, and a voltage for generating a voltage Vpd such as 6.7 V applied to the drain of the memory cell during writing and a voltage Vev such as 6.7 V applied to the control gate during erase verify Generator 7
0, applied to control gate during erase
A voltage generation circuit 80 that generates a voltage Ve such as 5 V;
A voltage generating circuit 90 for generating voltages Vp and Ves such as -10.0 V applied to a control gate during writing and a source (and well) during erasing, respectively;
It comprises a ring oscillator 100 for generating a clock φc for driving a charge pump, a voltage generating circuit 70 to 90 and a clamp power supply circuit 110 for generating a power supply voltage for the ring oscillator 100.

The voltage generating circuits 70 to 90 are configured so that 70 and 80 generate a positive boosted voltage, and 90 is configured to generate a negative boosted voltage. Although not particularly limited, in this embodiment, the reference voltage generating circuit 50 is used.
And voltage generating circuits 70, 90, respectively, are provided with voltage trimming circuits 53, 72, 92, respectively. Of these, the trimming circuit 53 includes a flash controller FL.
The value set in the trimming register TRMR1 in C is supplied, and the values set in the trimming register TRMR2 are supplied to the trimming circuits 72 and 92.

The reference voltage generation circuit 50 includes a reference voltage circuit 51 and a reference voltage V generated by the reference voltage circuit 51.
It comprises an operational amplifier 52 that receives ref at its non-inverting input terminal and functions like a voltage follower, and a trimming circuit 53 that adjusts the output voltage of the operational amplifier 52. As will be described later, the trimming circuit 53 includes a resistor ladder RRD for dividing the output voltage of the operational amplifier by resistance, and a value set in the trimming register TRMR1 in the flash controller FLC among outputs of the taps of the resistor ladder circuit. And a switch circuit SWC that feeds back one voltage corresponding to the above to the inverting input terminal of the operational amplifier 52 (see FIG. 5). The operation is performed so as to match the reference voltage Vref from 51.

In this embodiment, the resistance ladder R is set so that the output voltage Vrefa of the operational amplifier 52 becomes 2.5 V.
The resistance ratio of RD is set. The output voltage Vrefa of the operational amplifier 52 is applied to the voltage generation circuits 60 and 7.
0, 80 as the reference voltage,
To 90 and a clamp power supply 110 for generating a power supply voltage for the ring oscillator 100.
Is supplied as a reference voltage of the operational amplifier 111. Thereby, the voltage generation circuits 70 to 90
Even if the power supply voltage Vcc (5V ± 0.5V) varies, it is possible to generate a boosted voltage independent of the power supply.

The voltage generating circuit 60 receives the reference voltage Vrefa generated by the reference voltage generating circuit 50 at a non-inverting input terminal, and has an operational amplifier 61 functioning as a voltage follower, and an output of the operational amplifier 61. And a selection switch SW1 and a switch SW2 connected between the resistance voltage dividing circuit 62 and an inverting input terminal of the operational amplifier 61.
1 and SW2 are read / write verify control signals R / P
V is selectively turned on and off by V. A write verify voltage Vpv such as 2.5 V is output when SW1 is on, and a read voltage Vr such as 4.25 V is output when SW2 is on. The resistance ratio of the resistors R1 and R2 constituting the resistor voltage dividing circuit 62 is set.

The voltage generating circuit 70 comprises a charge pump circuit 71 for performing a charging operation by a clock φc formed by the ring oscillator 100, a resistance ladder RRD and a switch circuit SWC, and outputs the output voltage of the charge pump circuit 71. Adjusting trimming circuit 72
And the reference voltage Vrefa is compared with a voltage obtained by dividing the output voltage of the charge pump circuit 71 by a resistance ladder in the trimming circuit 72. When the reference voltage Vrefa is higher, a high level is output and the reference voltage Vrefa is output. Is lower, the comparator 73 outputs a low level, and a clock control gate circuit 74 that supplies or cuts off the clock φc generated by the ring oscillator 100 to the charge pump circuit 71 based on the output of the comparator 73. It is configured.

Thus, the voltage generation circuit 70
While the output voltage of the charge pump circuit 71 is lower than, for example, 6.7 V, the charging operation is performed by the clock φc generated by the ring oscillator 100. When the output voltage of the charge pump circuit 71 exceeds 6.7 V, the ring oscillator 100 Is stopped and the charging operation is stopped, so that the voltage Vpd such as 6.7 V applied to the drain of the memory cell at the time of writing and the control voltage 6.7 applied to the control gate at the time of erase verify.
A voltage Vev such as V is generated. In addition, the voltage generating circuit 70 includes a trimming circuit 72 including a resistance ladder RRD and a switch circuit SWC (see FIG. 5), which will be described later.
, The generated voltage can be adjusted. Further, the write drain voltage Vpd and the erase verify voltage Vev
Are designed at the same level and are generated by the same voltage generating circuit 70, so that the power supply circuit 25 can be simplified.

Since the voltage generation circuit 70 generates the write drain voltage Vpd and the erase verify voltage Vev, if the write drain voltage Vpd is changed, the erase verify voltage Vev will change. Since there is no erasure, the erasure level is set higher.
Even if the drain voltage Vpd at the time of programming is changed, there is no problem in the erase level within the range of change. Even if the erase verify voltage Vev is slightly deviated from the design value by adjusting the program drain voltage Vpd, the operation of the circuit will not be affected. No problem. Therefore, in this embodiment, the power supply circuit 25 is simplified by generating the write drain voltage Vpd and the erase verify voltage Vev by the same voltage generation circuit 70 as described above.

On the other hand, the voltage generating circuit 80 includes a charge pump circuit 81 which performs a charging operation by a clock φc formed by the ring oscillator 100, a resistance voltage dividing circuit 82, and a resistance ratio of the resistance voltage dividing circuit 82. The comparator 83 compares the voltage obtained by dividing the output voltage of the charge pump circuit 81 by resistance with the reference voltage Vrefa, and outputs a high level while the reference voltage Vrefa is higher, and outputs a low level when the reference voltage Vrefa is lower. And the clock φc generated by the ring oscillator 100 based on the output of the comparator 83 and the charge pump circuit 81
Clock control gate circuit 8 for supplying to or shutting off the clock
4.

As a result, the voltage generation circuit 80
The output voltage of the charge pump circuit 81 is, for example, 10.5 V
If the output voltage of the charge pump circuit 81 exceeds 10.5 V, the clock φc from the ring oscillator 100 is cut off to stop the charging operation when the output voltage exceeds 10.5 V. Thus, a voltage Ve such as 10.5 V applied to the control gate at the time of erasing is generated. This voltage generating circuit 80 is not provided with a trimming circuit 82. Erasing is performed in units of blocks that share a larger well area than in units of writing sectors, so the erasing time is shorter than the writing time, and the specification (requirement from the user) requires higher accuracy than the writing time. It is because it is not. If the erasing time becomes a problem, a trimming circuit may be added to the voltage generating circuit 80 to adjust the voltage Ve based on the erasing time.

Although the voltage generating circuit 90 is a negative booster circuit, it has a configuration similar to that of the voltage generating circuit 70.
That is, the output of the charge pump circuit 91 includes a charge pump circuit 91 for performing a negative charge operation by the clock φc formed by the ring oscillator 100, and a resistor ladder RRD and a switch circuit SWC (see FIG. 5) described later. Trimming circuit 92 for adjusting voltage
And the resistance ladder in the trimming circuit 92 compares the voltage obtained by dividing the output voltage of the charge pump circuit 71 with the ground potential. When the ground potential is higher, a high level is output and the ground potential is higher. A comparator 93 that outputs a low level when the signal becomes low, and a clock φc generated by the ring oscillator 100 based on the output of the comparator 93.
And a clock control gate circuit 94 for supplying and shutting off to the charge pump circuit 91.

As a result, the voltage generation circuit 90
When the output voltage of the charge pump circuit 91 is, for example, -10.5
While the voltage is higher than V, the charging operation is performed by the clock φc formed by the ring oscillator 100. When the output voltage of the charge pump circuit 91 exceeds (falls) -10.5V, the clock φ from the ring oscillator 100 is output.
When the charge operation is stopped by cutting off c, voltages Vp and Ves such as -10.5 V applied to the control gate of the memory cell at the time of writing and the source and the base of the memory cell at the time of erasing are generated.

Further, since the voltage generating circuit 90 includes the trimming circuit 92 including a resistance ladder and a switch circuit, the generated voltage can be adjusted. Also,
Since the voltage generation circuit 90 also uses the write voltage Vp and the source voltage Ves at the time of erasure in common, the power supply circuit 25 can be simplified. The reason why the write voltage Vp and the source voltage Ves at the time of erasing can be generated by the same voltage generation circuit is the same as that described for the voltage generation circuits 70 and 80.

As described above, in this embodiment, the reference voltage Vref generated by the reference voltage generation circuit 50 can be adjusted by the trimming circuit 53 so that the reference voltage Vref becomes the same even if it varies between chips. Even if the write characteristics of the storage element vary between chips, the trimming circuits 72 and 92 adjust the write high voltages Vpd and Vp generated by the voltage generating circuits 70 and 90 as boosting circuits, so that the write time varies between chips. The correction can be made to be substantially constant.

Note that a trimming circuit 92 is provided in the voltage generating circuit 90 as the second boosting circuit, and the trimming circuit 72 is not provided in the voltage generating circuit 70 as the third boosting circuit. May be adjusted.

FIG. 5 shows a specific circuit configuration example of the trimming circuit. A resistor ladder RRD connected between an output terminal of each of the voltage generating circuits 50, 70, and 90 and a reference potential point (GND or Vrefa);
1, a switch circuit SWC comprising a MOSFET provided in a pyramid shape between N2 ‥‥ Nn and an output terminal OUT.
By controlling the on / off state of each MOSFET with the bit signals B1, B2 # of the trimming register TRMR1 or TRMR2, any one of the nodes N1, N2 ‥‥ Nn is controlled. The voltage is supplied to the output terminal OUT. FIG. 5 shows a trimming circuit configured to output any one of 16 levels of voltages. However, the number of adjustable voltage levels is not limited to this, and the trimming registers TRMR1 and TRMR2 have It is also possible to configure so that the adjustment can be performed in more stages in relation to the number of bits.

Next, the operation procedure of the flash controller at the time of trimming the writing time will be described with reference to FIGS.

In order to trim the writing time, it is necessary to know the characteristics of the flash memory circuit of the target chip. The flash microcomputer of this embodiment is configured to know the characteristics of the flash memory circuit during a test process after chip manufacture and perform trimming using the result. FIG. 6 is a flowchart showing a test operation procedure of the flash memory circuit portion. In this test, first, a chip leak test is performed by measuring the current of the chip in the standby state (step S1). If a current equal to or more than a predetermined value flows in the leak test, it can be estimated that a leak current is flowing, and thus it is determined to be defective.

Next, for example, by applying a test probe to a test pad, the voltages (reference voltage Vref and write voltages Vp, Vpd) output from the power supply circuit 25 in the flash memory circuit FLASH are as designed. (Step S2). If there is a deviation from the design value, a trimming value is determined in accordance with the deviation amount (step S3). The trimming value is stored in a predetermined area in the flash memory circuit. If writing is not completed even after a predetermined time has elapsed, it is determined that the product is defective (step S4).

Then, the trimming value is stored in the trimming register TRMR in the flash controller.
1, TRMR2, and the trimming value is supplied to the trimming circuits 53, 72, and 92 to adjust the generated voltage. Then, it is determined again whether the voltage output from the power supply circuit 26 is as designed (step S5).

Subsequently, an initial erase test for putting all memory cells of the flash memory circuit into an erased state (for example, a state having a high threshold) is performed. Is determined (step S6).

Next, as shown in FIG. 9, a signal decoder test for efficiently testing the decoder by sequentially selecting all the word lines and all the data lines one by one (step S7). . At this time, if there is a defective decoder, it is determined to be defective. Moreover, in this embodiment, the write time of each chip can be measured by this diagnostic test. Therefore, the trimming value of the voltage generating circuit composed of the booster circuit is determined based on the write time, and the trimming of the write time is also adjusted using the trimming value. To do it. A specific procedure for trimming the writing time will be described later in detail.

Thereafter, various characteristics tests (steps S8 to S12) of the flash memory circuit are performed to select good products and defective products. As a characteristic test of the flash memory circuit, a checker writing test (step S8) is performed in which each memory cell in the memory array is written in a checker pattern as shown in FIG. 10 to check whether the writing can be normally performed. Data "0" for the memory cell
(Zero threshold state) All-zero write test to check whether normal writing can be performed by writing (step S9)
And whether the threshold value of a non-selected memory cell sharing a data line and a word line when writing data "0" does not change, and whether the threshold value does not change while reading the memory. For example, a disturb test (step S10) of "0" side data for examining data, etc., and erasure for setting data of all memory cells to "1" (high threshold state) to check whether normal erasure can be performed. Test (Step S
11), when writing data "0", the threshold value of a non-selected memory cell sharing a data line and a word line does not change, or the threshold value changes while reading the memory. There is a disturb test (step S12) of "1" side data for checking whether or not there is any data.

Next, the specific procedure of the write time trimming performed in step S7 will be described with reference to the flowcharts of FIGS. When performing the write time trimming, first, processing for determining a trimming value is performed. In this embodiment, the trimming value of the writing time is determined by using the signal writing test. The diagnostic write test is performed according to the procedure shown in FIG. That is, first, a counter Twdn for counting the number of write pulse application times of the memory array is initialized (reset) (step S21). Next, the power supply circuit 25 in the flash memory circuit is activated (Step S22). The activation of the power supply circuit 25 can be performed by the CPU setting the SWE bit of the control register in the flash controller FLC to "1".

Then, the CPU generates the data (one-bit data of which one bit is set to "0") and the X and Y addresses by the CPU for writing the signal, and also generates one sector (one word with a common word). The counter N for counting the number of write pulses per memory cell group (for example, a memory cell group of 32 bytes) to be written is set to "0".
(Step S23). Then, the generated write data is transferred to the working memory RAM (step S2).
4). Subsequently, the write data in the RAM is transferred to the data register 12 in the flash memory circuit FLASH (step S25). Also, the X and Y addresses are transferred from the CPU to the flash memory circuit.

Next, the transferred X in the memory array 11 is
A write pulse is applied to one word line corresponding to the address (step S26). The application of the write pulse can be performed by the CPU setting "1" to the P bit of the control register in the flash controller FLC. Subsequently, the values of counters Twdn and N for counting the number of application of the write pulse are respectively incremented (+1) (step S27). Thereafter, reading for verification is performed while keeping the X and Y addresses as they are (step S28). Then, the read data and the write data are compared to determine whether the writing has been completed (step S29).

Here, if the writing has not been completed, it is determined whether the value of the counter N is, for example, 400 or more (step S30). If it is less than 400, rewrite data is generated (step S31), and the process proceeds to step S24 to repeat the above operation. As a result, data writing to one sector is performed up to 400 times.
Then, when the 400th time is reached, the operation of the power supply circuit 25 in the flash memory circuit is stopped (step S3).
2) The process ends as a write failure. The power supply circuit 25 can be stopped by the CPU writing “0” to the SWE bit of the control register in the flash controller FLC.

On the other hand, if it is determined in step S29 that the write operation is completed while the above-described write operation is repeated, it is determined whether the write operation has reached the final address (step S33). If it is not the final address, the process returns to step S3 to generate the next write data and the X and Y addresses, and repeats the above operation. Here, the next write data is data obtained by shifting the position of “0” of the previous write data by one bit, and the X and Y addresses are values obtained by incrementing (or decrementing) the previous address value. If it is determined in step S33 that the address is the last address, the operation of the power supply circuit 25 in the flash memory circuit is stopped (step S34), and the write operation ends. When the writing of the signal is completed in this way, the counter T
wdn holds the number of times a write pulse has been applied to the memory array.

In the write trimming, as shown in FIG. 8, the counter Tdwn is first set after the completion of the digital write.
And the initial setting value of the trimming register TRMR2 are read into the CPU (step S41). The initial setting value of the trimming register TRMR2 is selected so that the generated voltage is exactly at the center of the voltage range that can be adjusted by the trimming circuit. Next, the range of the value of the counter Tdwn read in step S41 is determined (steps S42 to S49). Then, the reference tap of the trimming table is changed according to the range in which the value of the counter Tdwn is included (step S52).
To S59), the trimming value to be set in the trimming register TRMR2 is read out, written into the trimming information area in the memory array of the flash memory circuit FLASH, and the process ends (step S60). The trimming table is stored in the working memory RAM together with the program before the start of the test.

The trimming value stored in the trimming information area is read from the flash memory circuit and set in the trimming register TRMR2 in the flash controller FLC at the time of the write test in step S8 in the flow of FIG. Is done. As a result, the voltages generated from the voltage generation circuits 52 and 54 for generating the write voltage in the power supply circuit 25 of the flash memory circuit are adjusted to the optimum voltages according to the characteristics of the memory. Also,
Also in the normal operation, for example, when a reset is entered, the bus controller BSC automatically reads the data from the flash memory and sets the trimming register TRMR2.

Further, a program for determining the trimming value is also stored in a predetermined area of the flash memory, and is automatically read from the flash memory by the bus controller BSC in which a predetermined mode (for example, a test mode) is designated. Then, the program may be transferred to the work memory RAM and executed by the CPU.

As described above, according to the present embodiment, it is possible to adjust the reference voltage generated by the reference voltage generation circuit 50 of the flash memory circuit by the trimming circuit 53 so that the reference voltage is the same even if it varies between chips. The trimming circuits 72 and 92 enable the voltage generation circuits 70 and 90 even if the write characteristics of the storage elements vary between chips.
By adjusting the writing high voltages Vpd and Vp generated in the above, the writing time can be corrected so as to be substantially constant between chips.

In the embodiment, the number of times of application of a write pulse at the time of a write operation is counted in a signal test in which all word lines and data lines in the memory are sequentially selected to check the function of the decoder. The voltage of the trimming circuit (72, 92) is adjusted based on the count value. Strictly speaking, the writing voltage is not adjusted based on the detected required writing time. However, since the number of application of the write pulse is substantially proportional to the write time, even if the write voltage is adjusted by the number of application of the write pulse as described above, almost accurate adjustment is possible.

FIG. 11A shows the relationship between the number of application of the write pulse and the write time in the diagnostic test performed by the inventor when developing the flash microcomputer. As can be seen from the figure, although the number of application of the write pulse in the diagnostic test varies greatly depending on the sample,
All the samples are distributed substantially on a straight line, which indicates that the number of application of the write pulse and the write time in the digital test are almost in a proportional relationship. Also,
FIG. 11B shows the relationship between the number of application of the write pulse and the write time in the diagnostic test performed by changing the write voltage. In the drawing, those having the same symbols are set at the same write voltage, and it can be seen that they are distributed on a straight line. It is apparent from this that even if the write voltage is changed, the number of application of the write pulse is proportional to the write time.

FIG. 12 shows the relationship between the number of application of the write pulse and the write time in the all "0" write test performed by the inventor when developing the flash microcomputer. As can be seen from the figure, the number of times of application of the write pulse in the all "0" write test varies greatly depending on the sample, but all the samples are completely distributed on a straight line. It can be seen that the number of times and the writing time are completely proportional to each other. Therefore, when it is desired to perform voltage adjustment with higher accuracy, voltage trimming may be performed using the number of write pulse application times obtained by performing a write test of all “0” or a checker pattern write test. .

However, by using the result of the diagnostic write test as in the embodiment, there is an advantage that an optimum trimming value can be obtained with some accuracy and in a short time. In addition, the use of a soft counter to estimate the write time eliminates the need for a device that measures time outside the chip. It will be easier.

FIG. 13 shows all “0” s in the flash memory that has been subjected to voltage trimming by applying this embodiment.
Shows the required writing time as determined by a writing test. In the same figure, the bars in white frame are the measurement results of the sample in which only the reference voltage was trimmed by the trimming circuit 60 in FIG. 2, and the hatched bars indicate the trimming circuit in FIG. 2 in addition to the trimming of the reference voltage. 62,
Reference numeral 64 shows the measurement results of the samples on which the write voltage was trimmed. In the drawing, A is the allowable range of the writing time. As can be seen from the figure, only the trimming of the reference voltage was still insufficient.
It can be seen that the non-defective product rate is greatly improved by applying this embodiment.

The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the above embodiment, the flash memory of the type in which the threshold value of the storage element is raised by the erasing operation and the threshold value of the storage element is lowered by the writing has been described, but the present invention is not limited to this. The present invention can be similarly applied to a flash memory in which the threshold value is lowered and the threshold value of the storage element is raised by writing, and a semiconductor integrated circuit incorporating the same.

In this embodiment, the number of application of the write pulse is counted to determine the trimming value of the write voltage. However, a timer built in the chip is used or a soft timer is configured on the RAM by a program. Then, the write time may be measured, and the trimming value of the write voltage may be determined using the write time. further,
In the embodiment, the range of the number of application of the write pulse is determined and the table is referred to determine the trimming value of the write voltage. However, an appropriate operation formula is given to calculate the number of application of the write pulse. The trimming value of the write voltage may be determined by calculation by substituting into the equation.

Further, in the above embodiment, the write voltage is adjusted by counting the number of times of application of the write pulse.
Also, a trimming circuit may be provided to adjust the erase voltage by counting the number of erase pulse applications. The trimming circuit 92 is provided only in the voltage generating circuit 90 as the second booster circuit, and the trimming circuit 72 is not provided in the voltage generating circuit 70 as the third booster circuit, and the write time is adjusted only by the write voltage Vp. May be performed.

In the above description, the case where the invention made by the present inventor is mainly applied to a microcomputer having a built-in flash memory, which is the field of application, has been described. However, the present invention is not limited to this. Instead, the present invention can be widely used for a nonvolatile memory having the same configuration as the flash memory circuit FLASH and the flash controller FLC shown in FIG. 1 and a semiconductor integrated circuit incorporating the same.

[0070]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, it is possible to obtain a nonvolatile semiconductor memory capable of arbitrarily adjusting a writing time in a process after chip manufacture and a semiconductor integrated circuit such as a microcomputer incorporating the same. In addition, the non-defective semiconductor memory in which the writing time varies due to the process variation or the non-defective product rate of a semiconductor integrated circuit such as a microcomputer incorporating the same can be improved by adjusting the writing time in a process after manufacturing the chip.

Further, a sorting test based on the write time of a nonvolatile semiconductor memory or a semiconductor integrated circuit such as a microcomputer including the same can be efficiently executed, and the nonvolatile semiconductor memory or a semiconductor integrated circuit such as a microcomputer including the same can be efficiently performed. In the assembly line of the system using the system, it is possible to prevent the occurrence of troubles such as the stoppage of the line due to the writing time to the non-volatile memory being longer than the line transfer interval.

[Brief description of the drawings]

FIG. 1 is an overall block diagram schematically showing an embodiment of a microcomputer incorporating a flash memory to which the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration example of a flash memory circuit unit to which the present invention is applied.

FIG. 3 is an explanatory diagram showing a configuration example of a control register in a flash controller.

FIG. 4 is a block diagram illustrating a configuration example of a power supply circuit of the flash memory circuit.

FIG. 5 is a circuit diagram illustrating a configuration example of a trimming circuit of the flash memory circuit;

FIG. 6 is a flowchart illustrating an example of a test procedure in a flash memory.

FIG. 7 is a flowchart illustrating an example of a procedure of a diagnostic test as one of the tests in the flash memory.

FIG. 8 is a flowchart showing an example of a trimming procedure in a flash memory to which the present invention is applied.

FIG. 9 is an explanatory diagram showing a write pattern in a diagnostic test of a flash memory.

FIG. 10 is an explanatory diagram showing a write pattern in a checker pattern test of a flash memory.

FIG. 11 is an explanatory diagram showing the relationship between the number of pulse applications and the all-zero write time in the diagnostic write test of the flash memory.

FIG. 12 is an explanatory diagram showing the relationship between the number of times of application of a write pulse and the all-zero write time in the all-zero write of the flash memory.

FIG. 13 is a graph showing a change in write time before and after write voltage trimming in a flash memory to which the present invention is applied.

FIG. 14 is a sectional explanatory view showing a typical structure of a storage element of a flash memory and an example of an applied voltage in each operation mode.

[Explanation of symbols]

 Reference Signs List 11 memory array 12 data register 13 writing circuit 14 address register 15 X decoder 17 Y decoder 25 power supply circuit 26 power supply switching circuit FLC flash controller CNTR control register TRMR1, TRMR2 trimming register

Claims (4)

[Claims] A power supply circuit having a reference voltage generation circuit and a booster circuit for generating a high voltage for writing and erasing; and a power supply switching circuit, wherein a threshold value of a storage element having a gate, a source, a well, and a drain is set. A nonvolatile semiconductor memory configured to control and change a voltage applied to the gate, the source, the well, and the drain to store data, wherein a first voltage adjusted by the reference voltage generating circuit is adjusted; A trimming circuit and a second trimming circuit for adjusting a high voltage for writing and erasing generated by the boosting circuit are provided, and a means for counting a required time for writing and erasing is provided. Setting the trimming value of the second trimming circuit to change the voltage generated by the boosting circuit for writing and erasing; Non-volatile semiconductor memory which is characterized. 2. The means for counting the required writing time comprises:
2. The nonvolatile semiconductor memory according to claim 1, wherein the nonvolatile semiconductor memory is a soft counter for counting the number of times of application of a write pulse to a storage element. 3. A semiconductor integrated circuit comprising the nonvolatile semiconductor memory according to claim 1 or 2. 4. A decoder for a nonvolatile semiconductor memory according to claim 1 or 2, wherein all word lines and data lines in the memory are sequentially selected. The number of times of application of a write pulse at the time of a write operation is counted by a test for inspecting the function, and the trimming value of the second trimming circuit is determined based on the counted value to adjust the voltage generated by the booster circuit. Characteristic memory write time adjustment method.