JP2009301681A - Nonvolatile semiconductor memory device and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device and its control method by which erroneous read-out due to a source line noise is prevented. <P>SOLUTION: In the nonvolatile semiconductor memory device provided with a nonvolatile memory cell array recording a multi-value by setting a plurality of different threshold values to each memory cell, and a control circuit controlling so that data are read out from each memory cell using read-out voltage R1, read-out voltage R2, and read-out voltage R3 (R1<R2<R3) while controlling writing to the memory cell array, during read-out using read-out voltage R1, the control circuit does not perform pre-charge of a bit line for reading out during read-out using read-out voltage R3 for a memory cell determined as data of an erasing state, while the control circuit performs pre-charge of a bit line for reading out during read-out using read-out voltage R3 for a memory cell determined as data other than data of the erasing state. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM) such as a flash memory and a control method thereof.

  2. Description of the Related Art A NAND-type nonvolatile semiconductor memory device is known in which a NAND string is formed by connecting a plurality of memory cell transistors (hereinafter referred to as memory cells) in series between a bit line and a source line to realize high integration. (For example, refer nonpatent literature 1-4.).

  In a general NAND type nonvolatile semiconductor memory device, erasing is performed by applying a high voltage of, for example, 20V to the semiconductor substrate and applying 0V to the word line. As a result, electrons are extracted from the floating gate, which is a charge storage layer made of, for example, polysilicon, and the threshold value is made lower than the erase threshold value (for example, −3 V). On the other hand, in writing (programming), 0 V is applied to the semiconductor substrate, and a high voltage of, for example, 20 V is applied to the control gate. As a result, by injecting electrons from the semiconductor substrate into the floating gate, the threshold value is made higher than the write threshold value (for example, 1 V). A memory cell having these threshold values depends on whether a current flows through the memory cell by applying a read voltage (for example, 0 V) between the write threshold value and the read threshold value to the control gate. The state can be determined.

  In the nonvolatile semiconductor memory device configured as described above, when a write operation is performed on a memory cell to be written by a program operation, charges are injected into the floating gate of the memory cell transistor and the threshold voltage rises. As a result, even when a voltage equal to or lower than the threshold is applied to the gate, no current flows, and a state in which data “0” is written is achieved. In general, the threshold voltage of an erased memory cell varies. Therefore, when a program operation is executed by applying a predetermined write voltage and the threshold voltage is verified to be equal to or higher than the verify level, the threshold voltage of the memory cell after writing has a certain distribution above the verify level. It will be a thing. Here, by setting the memory cells to different threshold voltages, as shown in FIG. 3, a non-volatile semiconductor memory device of a multi-value memory cell that expresses a multi-value (hereinafter, multi-value non-volatile semiconductor memory device) (See Non-Patent Document 5, for example). In FIG. 3, R1, R2 and R3 (R1 <R2 <R3) are read voltages for reading the corresponding data from the memory cells programmed with a threshold value higher than the corresponding voltage.

Japanese Patent Laid-Open No. 9-147582. JP 2000-285692 A. JP2003-346485A. Japanese Patent Laid-Open No. 2001-028575. JP 2001-325796 A. JP-A-2006-318584. JP 2004-158111 A.

  In the multi-value nonvolatile semiconductor memory device described above, the level of the source line rises and rises depending on the read data pattern, and the read process cannot be performed normally. The margin may be adversely affected. That is, in the read data pattern, for example, when reading is performed from a memory cell in which most of the erased data “11” is, for example, 1 to 3 minority data “10” is written, the erased data “11” When the precharge for reading is performed on the bit line to which the memory cell holding "" is connected (see FIG. 4), the read voltage R3 for reading the uppermost data "10" (see FIG. 3). ), A large current flows into the source line, and this becomes noise (hereinafter referred to as source line noise). In particular, a memory in which data “10” is written with a low threshold voltage. The cell has a problem that it may be read out erroneously (see, for example, Non-Patent Documents 6 and 7). FIG. 4 is a table showing steps of reading processing of the flash EEPROM according to the conventional example, the horizontal direction is the time passage direction, and the circuit diagrams and the respective symbols are those in FIGS. 6 to 8 according to the first embodiment. These are the same and will be described in detail later.

  An object of the present invention is to provide a nonvolatile semiconductor memory device and a control method therefor that can solve the above problems and prevent “incorrect reading due to source line noise”.

The nonvolatile semiconductor memory device according to the first invention controls a nonvolatile memory cell array that records multiple values by setting a plurality of different threshold values for each memory cell, and writing to the memory cell array, A control circuit that controls to read data from each memory cell using at least the first read voltage R1, the second read voltage R2, and the third read voltage R3 (R1 <R2 <R3); In the provided nonvolatile semiconductor memory device,
For the memory cell determined to be erased data at the time of reading using the first read voltage R1, the control circuit sets the bit line for reading at the time of reading using the third read voltage R3. While precharging is not performed, for memory cells determined to be data other than erased data, bit line precharging for reading is performed at the time of reading using the third reading voltage R3. And

A non-volatile semiconductor memory device according to a second aspect of the present invention is a non-volatile memory cell array that records multiple values by setting a plurality of different threshold values for each memory cell, and a control that controls writing to the memory cell array. In a nonvolatile semiconductor memory device comprising a circuit,
The control circuit charges a bit line of a memory cell to be programmed and discharges a bit line of an unprogrammed memory cell at the time of verifying.

  In the nonvolatile semiconductor memory device, the control circuit sequentially selects memory cells not to be programmed after performing verification by selecting and charging all the memory cells of each bit line before reading the verification. Thus, the charge of the memory cell is discharged.

  Further, in the nonvolatile semiconductor memory device, the control circuit controls writing and reading to the memory cell array via a latch, and the control circuit should be programmed in the latch before the verify reading. Invert data, select all the memory cells on each bit line, discharge the memory cells, sequentially select and charge the memory cells to be verified, and then read the data after verifying In some cases, the data latched in the latch is inverted to read the data.

A nonvolatile semiconductor memory device and a control method thereof according to a third aspect of the invention include a nonvolatile memory cell array that records multiple values by setting a plurality of different threshold values in each memory cell, and writing to the memory cell array And control to read data from each memory cell using at least the first read voltage R1, the second read voltage R2, and the third read voltage R3 (R1 <R2 <R3). In a control method of a nonvolatile semiconductor memory device,
When reading using the first read voltage R1, a bit line for reading is not precharged when reading using the third read voltage R3 for a memory cell determined to be erased data. On the other hand, for memory cells determined to be data other than erased data, a bit line for reading is precharged at the time of reading using the third read voltage R3.

According to a fourth aspect of the present invention, there is provided a nonvolatile semiconductor memory device and a method for controlling the same, which controls writing to a nonvolatile memory cell array that records multiple values by setting a plurality of different threshold values for each memory cell. In a method for controlling a semiconductor memory device,
At the time of verification, the bit line of the memory cell to be programmed is charged, and the bit line of the memory cell that is not programmed is discharged.

  In the non-volatile semiconductor memory device and its control method, before verifying read, by selecting and charging all the memory cells of each bit line, the memory cells not programmed are sequentially selected after verifying. The charge of the memory cell is discharged.

  Further, in the nonvolatile semiconductor memory device and the control method thereof, the writing and reading to the memory cell array are controlled via the latch, and the data to be programmed latched in the latch is inverted before the verify reading. By selecting all the memory cells in the bit line and discharging the memory cells, and sequentially selecting and charging the memory cells to be verified, they are latched in the latch when data is read after verification. Inverted data is inverted and data is read out.

  Therefore, according to the nonvolatile semiconductor memory device and the control method thereof according to the present invention, the third read operation is performed on the memory cell determined as the erased data at the time of reading using the first read voltage R1. The bit line for reading is not precharged at the time of reading using the voltage R3, while the memory cell determined to be data other than the erased data is read at the time of reading using the third reading voltage R3. Precharge the bit line for reading. Thus, by not performing the precharge, it is possible to prevent “a large current from flowing into the source line” described in the section of the prior art and to prevent “incorrect reading due to source line noise”.

  At the time of verification, the bit line of the memory cell to be programmed is charged, and the bit line of the memory cell that is not programmed is discharged. Specifically, before the verify reading, all memory cells of each bit line are selected and charged, and then unprogrammed memory cells are sequentially selected to discharge the memory cells. As a result, only a predetermined program verify target memory cell can be verified, and “incorrect reading due to source line noise” can be prevented.

  Further, before the verify read, the data to be programmed latched in the latch is inverted, all the memory cells of each bit line are selected, the charge of the memory cell is discharged, and the memory cells to be verified are sequentially selected. Then, after verifying by charging, when data is read, the data latched in the latch is inverted and data is read. As a result, only memory cells other than a predetermined number of non-programmed cells can be subjected to verification, and “incorrect reading due to source line noise” can be prevented.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  FIG. 1 is a block diagram showing the overall configuration of a NAND flash EEPROM according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing the configuration of the memory cell array 10 of FIG. 1 and its peripheral circuits. First, the configuration of the NAND flash EEPROM according to this embodiment will be described below.

  In FIG. 1, a NAND flash EEPROM according to this embodiment includes a memory cell array 10, a control circuit 11 for controlling the operation thereof, a row decoder 12, a high voltage generation circuit 13, a data rewrite / read circuit 14, A column decoder 15, a command register 17, an address register 18, an operation logic controller 19, a data input / output buffer 50, and a data input / output terminal 51 are configured.

  As shown in FIG. 2, the memory cell array 10 includes, for example, sixteen stacked gate electrically rewritable nonvolatile memory cells MC0 to MC15 connected in series to form NAND cell units NU (NU0, NU1,...). Composed. Each NAND cell unit NU has a drain side connected to the bit line BL via the selection gate transistor SG1, and a source side connected to the common source line CELSRC via the selection gate transistor SG2. The control gates of the memory cells MC arranged in the row direction are commonly connected to the word line WL, and the gate electrodes of the selection gate transistors SG1 and SG2 are connected to selection gate lines SGD and SGS arranged in parallel with the word line WL. The A range of memory cells selected by one word line WL is one page as a unit of writing and reading. A range of a plurality of NAND cell units NU in one page or an integral multiple of one page is one block as a data erasing unit. The rewrite / read circuit 14 includes a sense amplifier circuit (SA) and a latch circuit (DL) provided for each bit line in order to write and read data in page units, and is hereinafter referred to as a page buffer.

  The memory cell array 10 in FIG. 2 has a simplified configuration, and a page buffer may be shared by a plurality of bit lines. In this case, the number of bit lines that are selectively connected to the page buffer during a data write or read operation is a unit of one page. FIG. 2 shows a range of the cell array in which data is input / output to / from one input / output terminal 52. In order to select a word line WL and a bit line BL of the memory cell array 10, a row decoder 12 and a column decoder 15 are provided, respectively. The control circuit 11 performs sequence control of data writing, erasing and reading. The high voltage generation circuit 13 controlled by the control circuit 11 generates a boosted high voltage or intermediate voltage used for data rewriting, erasing, and reading.

  The input / output buffer 50 is used for data input / output and address signal input. That is, data is transferred between the input / output terminal 51 and the page buffer 14 via the input / output buffer 50 and the data line 52. An address signal input from the input / output terminal 52 is held in the address register 18 and sent to the row decoder 12 and the column decoder 15 to be decoded. An operation control command is also input from the input / output terminal 52. The input command is decoded and held in the command register 17, whereby the control circuit 11 is controlled. External control signals such as a chip enable signal CEB, a command latch enable CLE, an address latch enable signal ALE, a write enable signal WEB, and a read enable signal REB are taken into the operation logic control circuit 19, and an internal control signal is generated according to the operation mode. Is done. The internal control signal is used for control such as data latch and transfer in the input / output buffer 50, and is further sent to the control circuit 11 for operation control.

  The page buffer 14 includes two latch circuits 14a and 14b, and is configured to be able to switch between a multi-value operation function and a cache function. That is, a cache function is provided when 1-bit binary data is stored in one memory cell, and a cache function is provided when 2-bit quaternary data is stored in one memory cell. However, the cache function can be enabled.

  1 and 2, the basic operation of writing and erasing data in the memory cell array 10 is disclosed in, for example, Non-Patent Document 4-5, which is a well-known technique and will not be described in detail.

First embodiment.
6 to 8 are circuit diagrams of the memory cell array 10 and the page buffer 14 showing the steps of the reading method for the flash EEPROM according to the first embodiment of the present invention. In the first embodiment, for a memory cell determined as data “11” in the erased state at the time of reading using the read voltage R1, a bit line is precharged for reading at the time of reading using the read voltage R3. This is characterized by preventing the “large current from flowing into the source line” described in the section of the prior art.

  In FIGS. 6 to 8 (including FIGS. 9 to 11), the meanings of the respective symbols are as follows. In the description with reference to the drawing, only the operation relating to the odd-numbered bit lines will be described as a representative. Also, in FIG. 6 to FIG. 11, circuits that are not related to the present embodiment are omitted.

SL: Source line.
SGD: drain side gate selection voltage.
SGS: Source side gate selection voltage.
VPASSR: non-selection voltage at the time of reading.
VPASSSP: non-selection voltage at the time of writing.
VPGM: Write voltage (program voltage).
R1, R2, R3: Read voltage.
BLE: odd-numbered bit line.
BLO: Even-numbered bit line.
YBLE: enable voltage for odd-numbered bit lines.
YBLO: enable voltage for even-numbered bit lines.
BLSE: odd-numbered bit line selection voltage.
BLSO: Even-numbered bit line selection voltage.
BLCLAMP: Bit line selection clamp voltage.
BLPRE: bit line precharge enable voltage.
REG: Verify selection voltage.
V1: Precharge applied voltage.
V2: Applied voltage for verification.
DTG: verify selection voltage.
BLCD: Transfer switch voltage.
SNS: Transfer signal line voltage.
VL1: Latch voltage (bit line side).
Q1-Q10: Field effect transistors (FET).
Cf: stray capacitance.
14c: Latch.

  Hereinafter, the steps of the reading method for the flash EEPROM according to the first embodiment will be described with reference to FIGS.

  As shown in FIG. 6A, first, in step S1, the FETs Q1, Q5, Q8-Q10 are turned off, while the FETs Q2-Q4, Q6-Q7 are turned on, so that data is read using the read voltage R1. Is read. At this time, the voltage V2 is applied to the bit line via the FETs Q3, Q4, Q6, and Q7, and the voltage on the bit line BLE at that time is read to the signal line via the FETs Q6 and Q2. At this time, the latch voltage VL1 of the latch 14c is at the low level when the read data is "11", and is at the high level when the other data is other data. Next, as shown in FIG. 6B, in step S2, when the data other than the read data “11” is precharged by the voltage V2, the voltage of the bit line BLE becomes about 1.2 V controlled by the BLCLAMP voltage. However, the read data “11” is not precharged, and the voltage of the bit line BLE is in a floating state of approximately the ground potential.

  Then, as shown in FIG. 7A, in step S3, the FET Q1 is turned on and the FET Q6 is turned off. At this time, the latch voltage VL1 of the latch 14c is inverted. When the read data is other than “11”, VL1 = high level, and when the read data is “11”, VL1 = low level. On the other hand, the bit line voltage BLE is a voltage corresponding to the read data (see FIG. 7A). Further, as shown in FIG. 7B, in step S4, the FET Q4 is turned off and the FET Q6 is turned on, and the voltage of the bit line BLE corresponding to the read data is read out to the signal line SNS.

  Next, as shown in FIG. 8A, in step S5, the FET Q4 is turned on, the FET Q6 is turned off, the voltage V2 is applied to the signal line SNS, and the latch voltage VL1 of the latch 14c is set to the signal line SNS. Voltage. Further, as shown in FIG. 8B, in step S6, the FET Q4 is turned off, and the voltage of the signal line SNS is latched in the latch 14c. That is, the voltage corresponding to the read data is latched and read by the latch 14c. Then, the voltage of the latch 14c is inverted.

  As described above, according to the present embodiment, the bit line for reading at the time of reading using the read voltage R3 is applied to the memory cell determined as data “11” at the time of reading using the read voltage R1. Without precharging, the “large current flowing into the source line” described in the section of the prior art can be prevented, and “incorrect reading due to source line noise” can be prevented.

Second embodiment.
FIG. 9 is a circuit diagram of the memory cell array 10 and the page buffer 14 showing the steps of the verify method for the flash EEPROM according to the second embodiment of the present invention. In the following, with reference to FIG. 9, the steps of the verify method for the flash EEPROM of the second embodiment will be described.

  As shown in FIG. 9A, first, the FETs Q2, Q4, Q8-Q10 are turned off, while the FETs Q1, Q3, Q5-Q7 are turned on so that the voltage V1 is passed through the FETs Q5, Q6, Q7. Applied to the bit line BLE. That is, by selecting all the memory cells and precharging all the memory cells, all the memory cells on the bit line BLE are precharged to a predetermined voltage (for example, 1.2V). Next, as shown in FIG. 9B, a small number of memory cells (for example, 1 to 3 memory cells) programmed to the predetermined data value are sequentially selected in a time division manner to turn on the FET Q4. Then, by turning off the FET Q5, electric charges are discharged from each selected small number of memory cells. That is, the bit line BLE is in a floating state for the program target memory cell, but is at the ground potential for the non-target memory cell.

  As described above, according to the present embodiment, the latch voltage VL1 of the latch 14c of the memory cell that is not programmed (not programmed or that has already passed the program verify) is high level at the time of verification. Once the BLPRE voltage is applied to turn on the FET Q5 and charge the bit line BLE, unprogrammed memory cells are discharged to the ground potential via the FETs Q4 and Q3. As a result, a predetermined small number of non-programmed cells can be surely brought into an erased state, and “incorrect reading due to source line noise” can be prevented.

Third embodiment.
FIGS. 10 and 11 are circuit diagrams of the memory cell array 10 and the page buffer 14 showing the steps of the verify method and read method for the flash EEPROM according to the third embodiment of the present invention. Hereinafter, with reference to FIGS. 10 and 11, steps of the verify method and the read method for the flash EEPROM according to the third embodiment will be described.

  As shown in FIG. 10A, first, the FETs Q1, Q5-Q8 are turned off, while the FETs Q2-Q3, Q9-Q10 are turned on, so that the voltage V2 is applied to the signal line via the FETs Q3, Q4, Q2. When applied to the SNS and the latch 14c, the latch voltage VL1 of the latch 14c is inverted. On the other hand, the charges on the bit lines BLE and BLO are discharged through the FETs Q9 and Q10. Next, as shown in FIG. 10B, the FET Q2 is turned off, the FET Q6 is turned on, and the voltage V2 is applied to the bit line BLE via the FETs Q3, Q4, Q6, and Q7. Here, only the memory cells to be programmed are sequentially selected in a time division manner, programmed to a predetermined data value (for example, data “10”), or verified. Further, as shown in FIG. 11, when data is read, mask data processing is performed on the program-inhibited memory cell by inverting the latch voltage VL1 of the latch 14c to restore the latch information and then reading the data. .

  As described above, according to the present embodiment, since the latch voltage VL1 of the latch 14c that is not programmed at the time of verification (not programmed or a memory cell that has already been verified) is at the high level, the verification is started. Sometimes, the latch voltage VL1 is inverted, the programmed memory cell is set to high level, and the non-programmed memory cell is set to low level to selectively charge only the memory cell to be verified to BLE. it can. At the time of data reading, mask data processing can be performed on a memory cell that is prohibited from programming by reversing the latch voltage VL1 to restore the latch information and then reading the data. As a result, the memory cells other than the predetermined small number of non-programmed cells can be surely set in the programmed state, and “incorrect reading due to source line noise” can be prevented.

Modified example.
Although the NAND flash EEPROM has been described in the above embodiments, the present invention is not limited to this, and is widely applied to nonvolatile semiconductor memory devices capable of writing data to a floating gate such as a NOR flash EEPROM. it can.

  In the second embodiment, the control circuit 11 selects all the memory cells of each bit line and charges them before verifying, thereby sequentially selecting unprogrammed memory cells after verifying. Thus, the charge of the memory cell is discharged. In the third embodiment, the control circuit 11 controls writing and reading to the memory cell array via the latch, and the control circuit 11 should be programmed in the latch before the verify reading. Invert data, select all the memory cells on each bit line, discharge the memory cells, sequentially select and charge the memory cells to be verified, and then read the data after verifying In some cases, the data latched in the latch is inverted to read out the data. Therefore, in the second or third embodiment, at least the control circuit 11 may charge the bit line of the memory cell to be programmed and discharge the bit line of the memory cell not to be programmed at the time of verification.

  As described above in detail, according to the nonvolatile semiconductor memory device and the control method thereof according to the present invention, for the memory cell determined to be in the erased state at the time of reading using the first read voltage R1, The bit line for reading is not precharged at the time of reading using the third read voltage R3, while the third read voltage R3 is applied to the memory cell determined to be data other than the erased data. The bit line for reading is precharged at the time of reading using. Thus, by not performing the precharge, it is possible to prevent “a large current from flowing into the source line” described in the section of the prior art and to prevent “incorrect reading due to source line noise”.

  At the time of verification, the bit line of the memory cell to be programmed is charged, and the bit line of the memory cell that is not programmed is discharged. Specifically, before the verify reading, all memory cells of each bit line are selected and charged, and then unprogrammed memory cells are sequentially selected to discharge the memory cells. As a result, only a predetermined program verify target memory cell can be verified, and “incorrect reading due to source line noise” can be prevented.

  Further, before the verify read, the data to be programmed latched in the latch is inverted, all the memory cells of each bit line are selected, the charge of the memory cell is discharged, and the memory cells to be verified are sequentially selected. Then, after verifying by charging, when data is read, the data latched in the latch is inverted and data is read. As a result, only memory cells other than a predetermined number of non-programmed cells can be subjected to verification, and “incorrect reading due to source line noise” can be prevented.

1 is a block diagram showing an overall configuration of a NAND flash EEPROM according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a memory cell array 10 of FIG. 1 and its peripheral circuits. It is a figure which shows the probability distribution of the threshold voltage of a multi-value flash EEPROM. It is a table | surface which shows the process of the read-out process of the flash EEPROM which concerns on a prior art example. It is a table | surface which shows the process of the read-out process of the flash EEPROM which concerns on the 1st Embodiment of this invention. (A) is a circuit diagram of the memory cell array 10 and the page buffer 14 showing a first step of the reading method for the flash EEPROM according to the first embodiment of the present invention, and (b) is a circuit diagram of the reading method. FIG. 6 is a circuit diagram of a memory cell array 10 and a page buffer 14 showing a second step. (A) is a circuit diagram of the memory cell array 10 and the page buffer 14 showing a third step of the reading method for the flash EEPROM according to the first embodiment of the present invention, and (b) is a circuit diagram of the reading method. 4 is a circuit diagram of a memory cell array 10 and a page buffer 14 showing a process of FIG. (A) is a circuit diagram of the memory cell array 10 and the page buffer 14 showing a fifth step of the reading method for the flash EEPROM according to the first embodiment of the present invention, and (b) is a circuit diagram of the reading method. 6 is a circuit diagram of the memory cell array 10 and the page buffer 14 showing the process of FIG. (A) is a circuit diagram of the memory cell array 10 and the page buffer 14 showing the first step of the program and verify method for the flash EEPROM according to the second embodiment of the present invention, and (b) is the program and FIG. 6 is a circuit diagram of a memory cell array 10 and a page buffer 14 showing a second step of the verify method. (A) is a circuit diagram of the memory cell array 10 and the page buffer 14 showing the first step of the verify method and read method for the flash EEPROM according to the third embodiment of the present invention, and (b) 4 is a circuit diagram of a memory cell array 10 and a page buffer 14 showing a second step of a verify method and a read method. FIG. FIG. 6 is a circuit diagram of a memory cell array 10 and a page buffer 14 showing a third step of a verify method and a read method for a flash EEPROM according to a third embodiment of the present invention.

Explanation of symbols

10: Memory cell array,
11 ... control circuit,
12 ... row decoder,
13. High voltage generation circuit,
14, 14A ... Data rewriting and reading circuit (page buffer),
14a, 14b ... latch circuit,
14c ... Latch,
15 ... column decoder,
17 ... Command register,
18 ... Address register,
19 ... Operation logic controller,
50: Data input / output buffer,
51: Data input / output terminal,
52 ... Data line,
Q1-Q10: Field effect transistor (FET),
Cf: stray capacitance.

Claims (8)

A non-volatile memory cell array that records multiple values by setting a plurality of different threshold values for each memory cell, and writing to the memory cell array are controlled, and at least a first read voltage R1 and a second read voltage R1 In a non-volatile semiconductor memory device including a control circuit that controls to read data from each memory cell using a read voltage R2 and a third read voltage R3 (R1 <R2 <R3),
For the memory cell determined to be erased data at the time of reading using the first read voltage R1, the control circuit sets the bit line for reading at the time of reading using the third read voltage R3. While precharging is not performed, for memory cells determined to be data other than erased data, bit line precharging for reading is performed at the time of reading using the third reading voltage R3. A nonvolatile semiconductor memory device. In a nonvolatile semiconductor memory device comprising: a nonvolatile memory cell array that records multiple values by setting a plurality of different threshold values for each memory cell; and a control circuit that controls writing to the memory cell array.
A nonvolatile semiconductor memory device, wherein the control circuit charges a bit line of a memory cell to be programmed and discharges a bit line of an unprogrammed memory cell at the time of verification.   The control circuit selects and charges all the memory cells of each bit line before reading the verify. After verifying, the control circuit sequentially selects the non-programmed memory cells and discharges the charges of the memory cells. The nonvolatile semiconductor memory device according to claim 2.   The control circuit controls writing to and reading from the memory cell array via a latch, and the control circuit inverts data to be programmed latched in the latch before reading of verify, and This memory cell is selected, the memory cell is discharged, the memory cells to be verified are sequentially selected and charged, and after verifying, the data latched in the latch is read when data is read. 3. The nonvolatile semiconductor memory device according to claim 2, wherein the data is read by being inverted. A non-volatile memory cell array that records multiple values by setting a plurality of different threshold values for each memory cell, and writing to the memory cell array are controlled, and at least a first read voltage R1 and a second read voltage R1 In a control method of a nonvolatile semiconductor memory device that controls to read data from each memory cell using a read voltage R2 and a third read voltage R3 (R1 <R2 <R3),
When reading using the first read voltage R1, a bit line for reading is not precharged when reading using the third read voltage R3 for a memory cell determined to be erased data. On the other hand, for a memory cell determined to be data other than data in an erased state, a bit line for reading is precharged at the time of reading using the third reading voltage R3. Storage device control method. In a control method of a nonvolatile semiconductor memory device that controls writing to a nonvolatile memory cell array that records multiple values by setting a plurality of different threshold values for each memory cell,
A control method for a nonvolatile semiconductor memory device, wherein a bit line of a memory cell to be programmed is charged and a bit line of a memory cell not to be programmed is discharged during verification.   By selecting and charging all the memory cells of each bit line before the verify read, the memory cells that are not programmed are sequentially selected after the verify, and the charge of the memory cells is discharged. A method for controlling a nonvolatile semiconductor memory device according to claim 6.   Controls writing to and reading from the memory cell array through the latch, inverts the data to be programmed, latched in the latch, and selects all the memory cells on each bit line before the verify read. By sequentially selecting and charging the memory cells to be verified, the data latched in the latch is inverted when the data is read out. The method for controlling a nonvolatile semiconductor memory device according to claim 6.

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