JPH10233096A - Nonvolatile semiconductor storage and read-out method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a read-out time and to reduce power consumption by successively reading out while changing a word line read-out level from a low side to a high side, holding this read-out data to a latch and selectively performing bit line precharge in next read-out operation based on these hold data. SOLUTION: All bit lines BL of a selection side mat are precharged to prescribed potential prior to read-out. In a step 2, the data read out to a sense latch SL to be held are transferred to a data latch DL through the bit line BL of a non-selection side mat. Then, in the step 3, first, the bit line BL in the selection side mat is precharged using the data held in the sense latch SL. Thus, the bit line connected to the sense latch holding the data '0' isn't precharged, and power consumption is reduced by such amount.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique which is particularly effective when applied to a method of storing and reading multi-valued information in a semiconductor memory device and also in a nonvolatile semiconductor memory device. The present invention relates to a technology that is effective when used in a possible nonvolatile storage device (hereinafter, simply referred to as a flash memory).

[0002]

2. Description of the Related Art A flash memory uses a nonvolatile memory element having a control gate and a floating gate as a memory cell, and the memory cell can be constituted by one transistor. In such a flash memory, in a write operation, as shown in FIG. 16, the drain region of the nonvolatile memory element is set to, for example, about 5 V (volt), and the word line connected to the control gate CG is set to about -11 V. The charge is extracted from the floating gate FG by the tunnel current, and the threshold voltage is set to a low state (logic “0”). In the erase operation, as shown in FIG. 17, the well region, the drain region, and the source region are set to about 0 V, the control gate CG is set to a high voltage such as 16 V, a tunnel current is generated, and negative charges are injected into the floating gate FG. To make the threshold value high (logic "1"). At the time of reading, the control gate is set to an intermediate voltage between the high threshold value and the low threshold value to detect whether or not the current flows. For example, the storage data of the memory cell through which the current flows is “0”, The storage data of the memory cell that does not flow is determined to be "1". Thus, one-bit data is stored in one memory cell.

By the way, in order to increase the storage capacity, 1
A technique relating to a so-called “multi-valued” memory that stores two or more bits of data in a memory cell has been proposed.
The invention relating to this multi-valued memory is disclosed in Japanese Patent Application No. Hei.
No. 031.

In such a multi-valued memory, the threshold value is changed stepwise, for example, to 1 V, 2 V, 3 V by controlling the amount of electric charge injected into the floating gate, and each threshold value is changed. That is, a plurality of bits of information are stored in association with each other. FIG. 18 shows a distribution state of threshold values when one memory cell is divided into four threshold states and stored (hereinafter, referred to as four values). It is difficult to accurately control the threshold value of the memory cell to a predetermined value by writing. As shown in FIG. 3, the threshold voltage of each memory cell has a normal distribution centered on a target threshold voltage. When data is read, a voltage corresponding to a valley portion of the distribution of each threshold is read as a read voltage VRW1,
VRW2 and VRW3 are set and applied to the control gate via a word line. At this time, the drain is set to 1V and the source is set to 0V. To set the drain voltage, a bit line precharge method can be applied.

[0005] Table 1 shows the read voltages VRW1 and VRW.
2 shows the result of reading out memory cells belonging to threshold distributions A, B, C, and D using VRW3 (VRW1 <VRW2 <VRW3). Since the memory cells belonging to the threshold distribution A have the highest threshold, VRW1 and VRW
2 and VRW3, no current flows, and the read result is "1". Even if VRW1 and VRW2 are applied to the memory cells belonging to the threshold distribution B, no current flows and the read result is "1". However, when VRW3 is applied, a current flows and the read result is "0". . Even if VRW1 is applied to the memory cells belonging to the threshold distribution C, no current flows and the read result is "1".
2, when VRW3 is applied, a current flows and the read result is "0". A current flows through the memory cells belonging to the threshold distribution D regardless of which of VRW1, VRW2, and VRW3 is applied, so that the read result is "0" in all cases.
Becomes Although the case of the four-valued memory has been described above, eight-valued and sixteen-valued data are possible in principle.

[0006]

[Table 1]

[0007]

In the four-valued memory, one of four threshold values can be set in one memory cell, so that two bits of information can be stored. By the way, in a conventional binary memory in which one-bit information is stored in one memory cell, one reading is performed to determine two thresholds in order to obtain one-bit information. On the other hand, in the quaternary memory, it is necessary to read three times while changing the potential of the word line to obtain 2-bit information. Therefore, there is a problem that the read time becomes three times as long as that of the binary memory, and the current consumption at the time of the read increases three times even if it is simply considered.

In addition, M having a floating gate
In a nonvolatile memory using an OSFET as a memory cell, if a read operation is repeated, a slight hot electron generated at the time of read is injected into a floating gate and a threshold value increases (hereinafter referred to as read disturb). In addition, the larger the number of times of reading, the greater the fluctuation of the threshold value of the memory cell, and in the worst case, the reading level may be exceeded and the stored data may be corrupted.

As described above, it is necessary to apply the ground potential Vss (0 V) to the source of the memory cell at the time of reading, and the power supply line (ground line) G for that purpose
L is the external terminal of the chip (ground pin) as shown in FIG.
Each memory cell M in the memory array M-ARY from GND
Up to C is installed. Such a power supply line is generally formed of a metal wiring layer of aluminum or the like, but at a portion where the aluminum wiring is used for another signal line such as a bit line, a ground potential is applied to the memory cell MC via a diffusion layer having a high resistance value. May be applied. In such a case, as shown in FIG. 19, the length of the ground line is considerably different between the memory cell near the ground pin GND and the memory cell farthest from the ground pin GND. For example, the wiring of the diffusion layer has a resistance of about several hundred mΩ / μm, the metal wiring has a resistance of about 100Ω, and a resistance of several hundreds to several kΩ is applied to a memory cell far from the ground pin. Become. for that reason,
When a current flows from the memory cell at the time of reading, the source potential rises. However, the source potential greatly differs between a memory cell near the ground pin and a memory cell far from the ground pin. If the read current is 3mA and the ground resistance is 1
If the difference is 00 Ω, the source potential is 0.3 V
Will occur.

On the other hand, as is known from the characteristics of MOSFETs, the drain current changes logarithmically near the threshold value, so that when the source potential rises and the gate-source voltage decreases, the memory cell becomes one digit. Or, the current decreases by two digits. Here, assuming that the characteristics of the memory cells belonging to the distributions B and D in FIG. 18 have the characteristics shown by b and d in FIG. 20, 5 V is applied to each gate.
Is applied, the memory cell D is in a completely saturated region, so that a sufficient amount of current can be secured even if the source potential rises slightly. On the other hand, the memory cell B has a low saturation, It can be seen that the current is greatly reduced by the floating, and there is a possibility that reading is impossible or incorrect data is read.

An object of the present invention is to provide a multi-value storage type nonvolatile semiconductor memory device which has a short read time and low current consumption.

Another object of the present invention is to provide a multi-value storage type nonvolatile semiconductor memory device in which the required number of readings is reduced and storage data is less likely to be garbled.

Still another object of the present invention is to provide a multi-value storage type nonvolatile semiconductor memory device capable of suppressing the rise of the source potential at the time of reading and preventing unreadable or erroneous data reading.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

The following is a brief description of an outline of typical inventions disclosed in the present application.

That is, in a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-value information in one memory cell, the word line read level is changed from a lower level to a higher level. In addition to reading sequentially, a latch means for holding the read data is provided, and the bit line precharge in the next read operation is selectively performed based on the held data.

As is apparent from Table 1, when the word line read level is sequentially changed from the lower level to the higher level, the memory cell from which "0" has been read once is raised in level thereafter. Even if data is read out, "0" is read out, which is the same result as not reading out data. That is, the precharge of the bit line can be omitted.
Since the current consumption can be reduced by omitting the precharge, the current flowing from the memory array to the ground line at the time of reading can be reduced, and the floating amount of the source potential of the memory cell can be reduced. Therefore, it is possible to prevent unreadable or erroneous data reading. In addition, since the number of times of reading can be reduced by omitting the precharge, fluctuation of the threshold value due to read disturb, that is, garbled storage data can be suppressed.

Further, according to the above-mentioned read method, if only the memory cells connected to the selected word line are low-threshold memory cells, all read data are set to "0" before reading to the end. Therefore, by providing the all "0" determination means, the reading operation can be completed halfway, and the data reading time can be reduced in addition to the reduction in current consumption.

Further, it is desirable that the correspondence between the threshold value of the memory cell and the storage data is determined such that the code of the storage data is different by only one bit between adjacent threshold values. Specifically, in the case of a four-valued memory, the threshold distributions A, B, C, and D in FIG. 18 are made to correspond to 2-bit data "11", "10", "00", and "01". By doing so, there is an advantage that when there is read disturb, the load on the error correction circuit for correcting the read disturb is small and the circuit scale can be small. For example, considering the case where the threshold value of the memory cell in the threshold value distribution B of FIG.
"0" is erroneously read as "00".
The error requires only one bit. However, the threshold distributions A, B, C, and D in FIG.
When the threshold values of the memory cell are changed from B to C, “1” is set to “0”, “01”, “00”.
Since "0" is erroneously read as "01", which results in a 2-bit error, trying to correct this would greatly increase the load on the error correction circuit and the circuit scale.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to a flash memory capable of storing four values in one memory cell will be described below with reference to the drawings.

First, the order of reading data from the flash memory of this embodiment will be briefly described with reference to FIG. In this embodiment, the memory array is composed of two mats,
A sense and latch circuit (hereinafter, referred to as a sense latch, which is referred to as SL in the drawing) connected to a bit line BL in each mat and amplifying and latching a read signal is arranged between the two mats. Latch circuits for temporarily holding read data are arranged on opposite sides of the line BL. Hereinafter, this latch circuit will be referred to as a data latch, and will be referred to as DL in the figure.
D is added to distinguish them. Note that WL is a word line, and MC is a memory cell.

In this embodiment, prior to reading, all bit lines BL of the selected mat (here, the case of selecting a memory cell in the upper mat) are set to, for example, 1..
It is precharged to a potential such as 0V. This precharge is performed by setting data in the sense latch SL such that the input / output node on the selected mat side is at the “1” level. The setting of the data in the sense latch SL is performed by grounding the non-selected node to ground via the MOSFET and setting the input / output node on the selected side of the sense latch to high level. The non-selected bit lines are half-precharged to a potential such as 0.5 V, and data is detected by comparing the selected bit line potential with the non-selected bit line potential.

Next, one of the word lines on the selected mat side is first set to the lowest read level VRW1 (= 1.5
V). Then, one row of memory cells connected to the word line are read. Thereby, the memory cell having the highest threshold value (the storage data is “1”
1 ") and the memory cell (storage data" 10 ") having the second highest threshold value and the data read from the memory cell having the third threshold value (storage data" 00 ") to the corresponding sense latch SL are" It becomes "1", and only data read from the memory cell (storage data "01") having the lowest threshold value to the corresponding sense latch SL becomes "0" (step S1).

In step 2, the data read and held by the sense latch SL is transferred to the data latch DLD via the bit line BL of the non-selected mat. Although this data transfer is also described later, conceptually, as shown in FIG. 2, it is provided between bit line BL and sense latch SL and between bit line BL and data latch DL (DLU and DLD), respectively. M for transfer
This is performed by turning on the OSFETs Qt1 and Qt2. At this time, since the data opposite to the above-mentioned held data appears at the input / output node on the non-selected mat side of the sense latch SL, the data is transferred to the data latch DL and held there. Is inverted data. When this data transfer is completed, the potentials of all the bit lines are lowered to the ground potential (0 V) by turning on all the discharge MOSFETs (described later) provided on each bit line BL (hereinafter referred to as bit (Referred to as line reset).

In step 3, first, the sense latch S
The bit line BL in the selected mat is precharged using the data held in L. As a result, the bit line connected to the sense latch holding the data “0” is not precharged, and the power consumption can be reduced accordingly. After the precharge is completed, the same word line as the word line set to the selected level in step 1 is raised to the second read level VRW2, for example, 2.5 V, and the memory for one row connected to the word line is set. The cell is read. Thereby, the memory cell having the highest threshold value (the storage data is “1”
1 ”) and the data read out from the memory cell (storage data“ 10 ”) having the second highest threshold value to the corresponding sense latch SL becomes“ 1 ”, and the memory cell having the third threshold value (storage data“ 10 ”). “00”) and the data read from the memory cell (storage data “01”) having the lowest threshold value to the corresponding sense latch SL are “0”.

In step 4, the data read and held in the sense latch SL is transferred to the data latch DLU via the bit line BL of the selected mat.
This data transfer is also performed by turning on the transfer MOSFETs Qt1 and Qt2 provided between the bit line BL and the sense latch SL and the data latch DL. At this time, since the same data as the held data appears at the input / output node on the selected mat side of the sense latch SL, the data transferred to and held by the data latch DLU is different from that of the step 2 in the sense latch SL.
This is the same data as the held data of L. When this data transfer is completed, the bit lines are reset by turning on all discharge MOSFETs (described later) provided on each bit line.

In step 5, first, the sense latch S
The bit line BL in the selected mat is precharged using the data held in L. After the precharge is completed, the same word line as the word line selected in step 1 is raised to the third read level VRW3, for example, 3.5 V, and the memory cells for one row connected to the word line Is read. Thereby, the memory cell having the highest threshold value (the storage data is “1”
1)), only the data read to the corresponding sense latch SL becomes “1”, and the memory cell having the second highest threshold (storage data “10”) and the memory cell having the third threshold (storage data “00”) and the data read from the memory cell (storage data “01”) having the lowest threshold value to the corresponding sense latch SL are “0”.

In step 6, the exclusive data of the inverted data read and held in the sense latch SL and the data (inverted data of the selected memory cell) held in the non-selected data latch DLD are extracted. The sib-OR logical operation is performed by a wired logical operation using the bit line BL. That is, as shown in FIG. 2B, in this embodiment, the bit line BL and the data latch D are used.
Transfer MOSFET Qt2 provided between LD and LD
MOSFETs Qe1 and Qe2 in series form to bypass
Is provided between the bit line BL and the ground point. Of these MOSFETs, the transfer MOSFET on the side of the sense latch SL is turned off while Qt2 is turned off and Qe1 is turned on.
Qt2 is temporarily turned on to output the held data to the bit line. Then, Qe2 is turned on or off according to the data held in the data latch DLD. Then
At this time, if the data held in the data latch DLD is "0", Qe2 is turned off.
The data output from is maintained as it is. On the other hand, if the data held in the data latch DLD is "1", Qe2 is turned on, and the bit line BL is lowered to the ground potential.

The MOSFETs Qt1, Qt2,
By the operation control of Qe1 and Qe2, the result of the logical operation as shown in the truth table of FIG. 11 remains on the bit line BL.
In the above truth table, the logical operation result when the data held in the sense latch SL is “0” and the data held in the data latch DLD is “1” is not shown in FIG.
Since the read data always becomes "0" (because the read word line level starts from the lower level) in the memory cell where the read data becomes "0" every time, as described above, the sense is not applied to the non-selected side. This is because the case where the data held in the latch SL is “0” and the data held in the data latch DLD is “1” cannot occur.

In step 7, the data latch DLD
Is reset and then the transfer MOSFET Qt2 is turned on, so that the logical operation result on the bit line is transferred to the data latch DLD and held. The data held in the data latch DLD is inverted and supplied to the output circuit, and the data held in the data latch DLU on the selected side is supplied to the output circuit as it is and output to the outside at a predetermined timing. As a result, storage data corresponding to the threshold value of the memory cell from which reading has been performed is externally output.

FIG. 3 shows a specific example of the memory array 10 and peripheral circuits. The memory array 10 of this embodiment has two mats, and FIG. 3 shows a specific example of one (upper) memory mat. As shown in the drawing, each memory mat has n memory cells (MOSFETs having a floating gate) M arranged in a column direction and having a source and a drain connected in common.
A plurality of memory columns MCC including C1 to MCn are arranged in the row direction (word line WL direction) and the column direction (bit line BL direction). In each memory column MCC, the drains and sources of n memory cells MC1 to MCn are connected to a common local drain line LDL and a common local source line LSL, respectively. The line BL and the local source line LSL are connected to a ground point or a negative voltage via a selection switch MOSFET Qs2. The word drive circuit W-DRIVER has driver circuits DR1 to DR4. Each of the driver circuits DR1 to DR4 has power supply terminals t1 and t2, and has corresponding word lines WL11, WL1n,
It is coupled to WL21, WL2n. The erase voltage E, the write protection voltage PP, the read voltages VRW1 to VRW3, the write verify voltages VWW1 to VWW3, the erase verify voltage WEW, the write voltage P, and the ground potential Vss are shown in FIG.
4 and is supplied to the address decoder X-DEC. The address decoder X-DEC selects the supplied voltage, and supplies the power terminals t1 and t2 of each of the driver circuits DR1 to DR4.
To supply. The power supply terminal t1 is selectively supplied with an erase voltage E, a write protection voltage PP, read voltages VRW1 to VRW3, write verify voltages VWW1 to VWW3, and an erase verify voltage WEW. Also, the power supply terminal t2
Are selectively supplied with a write voltage P and a ground potential Vss.

Memory column MCC and selection switch MOSF
ET Qs1 and Qs2 are the same well region W on the semiconductor substrate.
It is formed in the ELL, and at the time of data erasing, a voltage such as an erasing voltage (= 16 V) is applied to a word line to enable batch erasing in word line units. When erasing data, the switch MO of the block including the erase word line is
The SFETs Qs1 and Qs2 are turned on to apply a voltage of 0 V to the selected block and the source and drain of the memory cell.

On the other hand, at the time of data writing, the write voltage P (= −) is applied to the word line to which the selected memory cell is connected.
11V), the bit line BL corresponding to the selected memory cell is set at a potential such as 5 V, and the switch MOSFET Qs1 on the local drain line LDL to which the selected memory cell is connected is turned on. It is turned on, and 5 V is applied to the drain. However, at this time, the selection switch MOS on the local source line LSL
The FET Qs2 is turned off. At the time of data reading, the read voltages VRW1 (= 1.5V) and VRW2 are applied to the word line connected to the selected memory cell.
(= 2.5 V), VRW3 (= 3.5 V), the bit line BL corresponding to the selected memory cell is precharged to a potential of 1 V, and the selected memory cell is Connected local drain line L
The selection switch MOSFET Qs1 on DL is turned on. At this time, the selection switch MOSFET Qs2 on the local source line LSL is turned on, and the ground potential is applied.

At one end of the bit line BL (the center side of the memory array), a sense amplifier, a transfer MOSFET (Qt1), which detects the level of the bit line at the time of reading and applies a potential corresponding to write data at the time of writing, and a precharge. A sense latch circuit SL composed of a MOSFET or the like is connected to each other, and a latch circuit capable of holding write data and read data at the other end of the bit line BL.
SFET (Qt2), additional circuits (Qe1,
Qe2) and the like are connected to each other. Since the memory array of this embodiment is composed of two mats, a memory mat similar to the above is arranged on the opposite side of the sense latch circuit SL, that is, on the lower side of the figure, and each bit in the memory array is arranged. The line BL is connected to the other input / output terminal of the corresponding sense latch circuit SL.

In the above embodiment, the corresponding control MOSFETs (transfer MOSFETs) on all the bit lines are used.
Qt1, Qt2, etc.) have been described as being controlled by a common control signal for each memory mat. Control MOS corresponding to
It is also possible to configure so that the FETs are controlled by a common control signal, thereby reducing the load on the circuit on the side that forms the control signal.

FIG. 4 shows a specific circuit example of the sense latch circuit SL and the data latch circuit DLU. Since the circuit is symmetrical with respect to the sense latch circuit, only one bit line in one memory mat is shown, and for convenience, only one memory column MCC among the memory columns connected to the bit line is shown. However, actually, a plurality of memory columns MCC are connected.

As shown in FIG. 4, the sense latch circuit SL
Is provided with a flip-flop circuit FF1 in which input and output terminals of two CMOS inverters composed of a P-channel MOSFET and an N-channel MOSFET are cross-coupled. Then, one input / output terminal N of the sense latch circuit SL
The bit line BLu in one memory mat is connected to a via a data transfer MOSFET Qt1. Also,
A bit line BLd in the other memory mat is connected to the other input / output terminal Nb of the sense latch circuit SL by a data transfer MOS.
It is connected via FET Qt1 '.

Further, the input / output terminals Na and Nb of the sense latch circuit SL are respectively provided with discharge MOs.
The SFETs Qd1 and Qd1 'are connected, and the other end of the bit line BLu is also connected to a discharging MOSFET Qd2. Precharge MOSFETs Qp1 and Qp2 are connected to each bit line BLu. Of these, Qp1 is connected to a terminal to which a power supply voltage Vcc is supplied via MOSFET Qc1, and the gate of Qc1 is a flip-flop FF.
1 is connected to the input / output node Na and is turned on and off in accordance with the data held therein, and the PCU is set to a potential such as 1 V + Vth (threshold voltage). The corresponding bit line is precharged to 1V. At this time, the non-selected precharge MOSFET Qp2 '(corresponding to Qp2) is precharged to 0.5V by setting its gate control signal PRD (corresponding to PRU) to a potential such as 0.5V + Vth. It has become.

The input / output terminals Na and Nb of the sense latch circuit SL are connected via a column switch MOSFET (Y gate) Qy to the common input / output line CI / O connected to the data switching circuit. Has been enabled. Also, the input / output terminal N of the sense latch circuit SL
MOSFEs for determining all “0” are provided in a and Nb, respectively.
The gate of TQa is connected. The source of the MOSFET Qa for determining all “0” is connected to the ground point, and the drain is connected to the common output line ICO which is precharged in advance, and the data held in at least one of the sense latches SL is “1”. And the corresponding MOSFET Qa is turned on to pull out the potential of the common output line ICO. Therefore, if the potential of the common output line ICO is at a high level, it is determined that the data held in all the sense latches SL is “0”. be able to.

On the other hand, the data latch circuit DLU has a P-channel MOSFET and an N
There is provided a flip-flop circuit FF2 in which the input / output terminals of two CMOS inverters composed of channel MOSFETs are cross-coupled. Then, the data latch circuit D
A bit line BLu in the memory mat is connected to one input / output terminal Nc of the LU via a data transfer MOSFET Qt2. Further, a discharge MOSFET Qd3 is connected to the input / output terminal Nc of the data latch circuit DLU, and between the bit line BLu and the ground is turned on / off by the precharge signal DP_U and the potential of the input / output terminal Nc. MOSFETs Qe1 and Qe2 are connected in series.

Further, the input / output terminal Nc of the data latch circuit DLU can be connected to a data switching circuit via a MOSFET Qg. Although not shown in FIG. 4, a data latch circuit DLD composed of a flip-flop circuit or the like is arranged at the other end of the bit line BLd connected to the input / output terminal Nb of the sense latch circuit SL.

FIG. 21 is a flowchart for reading data. When a read command is input in step 1 (ST1), the flash memory is set to the read mode. In step 2 (ST2), a read address is input. The read address is decoded by an address decoder, and a word line is selected. The read voltage VRW1 is applied to the word line selected in step 3 (ST3), and the data line in the memory mat having the selected word line (selected memory mat) is precharged by the precharge MOSFET Qp1. Is executed, and all data lines are precharged to 1V. All data lines in the other memory mat (non-selected memory mat) are M for precharging.
Precharged to 0.5V by OSFET Qp2.

In step 4 (ST4), data read from the selected word line is applied to sense latch circuit SL.
Is stored in The data stored in the sense latch circuit SL in step 5 (ST5) is the data latch circuit DLD
Is transferred to and stored. In step 6 (ST6), the read voltage VRW2 is applied to the selected word line, and all data lines in the selected memory mat are precharged by the precharge MOSFET Qp1. However, in step 4, the data line coupled to the sense latch circuit SL storing “0” data (threshold lower than the read voltage VRW1) is
Since the FET Qc1 is not turned on, it is not precharged to 1V. That is, the data line precharged to 1 V in step 6 is only the data line coupled to the sense latch circuit SL that stores “1” data (threshold higher than the read voltage VRW1) in the data read in step 3. is there. All data lines in the non-selected memory mats are precharged to 0.5 V by the precharge MOSFET Qp2.

Data read from the word line selected in step 7 (ST7) is stored in sense latch circuit SL. The data stored in the sense latch circuit SL in step 8 (ST8) is transferred to and stored in the data latch circuit DLU. In step 9 (ST9), the read voltage VRW3 is applied to the selected word line, and all data lines in the selected memory mat are precharged by the precharge MOSFET Qp1. However, in Steps 4 and 7, the data line coupled to the sense latch circuit SL storing “0” data (threshold lower than the read voltage VRW2) is pre-charged to 1 V because the MOSFET Qc1 is not turned on. Not charged. That is, step 9
Are the only data lines that are precharged to 1 V and are coupled to the sense latch circuit SL that stores "1" data (threshold higher than the read voltage VRW2) in the data read in step 7. All data lines in the non-selected memory mat are MOS for precharge
Precharged to 0.5V by FET Qp2.
Data read from the word line selected in step 10 (ST10) is stored in the sense latch circuit SL.

In step 11 (ST11), an exclusive OR logic operation is performed on the data stored in the data latch circuit DLD in step 5 and the data stored in the sense latch circuit SL in step 10.
In step 12 (ST12), the operation result of step 10 is stored in the sense latch circuit. Step 13 (ST
In 13), the operation result data stored in the sense latch circuit is transferred to and stored in the data register DLD. At step 14 (ST14), the data registers DLU, D
The data stored in the LD is connected to the external terminal I shown in FIG.
/ O output.

In the read operation, when data is read by dividing the data lines into odd columns and even columns, a precharge operation is performed on the data lines in the odd columns, and then a sense coupled to the data lines in the odd columns. Data is read out to the latch circuit, and then a precharge operation is performed on the even-numbered data lines, and then the data is read out to the sense latch circuit coupled to the even-numbered data lines. Note that, in the figure, step 3 (ST3) and step 4 (ST3)
4) corresponds to the step (Step 1) in FIG. 1, Step 5 (ST5) corresponds to Step 2 (Step 2) in FIG. 1, and Step 6 (ST6) and Step 7 (ST7).
1 corresponds to Step 3 (Step 3) of FIG. 1, Step 8 (ST8) corresponds to Step 4 (Step 4) of FIG. 1, and Step 9 (ST9) and Step 10 (ST1).
0) corresponds to Step 5 (Step 5) in FIG. 1, Steps 11 (ST11) and 12 (ST12) correspond to Step 6 (Step 6) in FIG.
3 (ST13) corresponds to Step 7 (Step 7) in FIG. 1, and Step 14 (ST14) corresponds to Step 8 in FIG.
(Step 8).

FIG. 22 is a diagram showing a potential change of a data line in a selected memory mat in a data read operation. In the figure, for the sake of simplicity, the word line WL has a memory cell a belonging to the threshold distribution A, a memory cell b belonging to the threshold distribution B, a memory cell c belonging to the threshold C, and a threshold D Only the memory cells d belonging to Corresponding data lines BL0 to BL3 are coupled to each of the memory cells a, b, c and d. When the read voltage VRW1 is applied to the word line WL, all the data lines BL0 to BL3 are precharged to 1V. Since the memory cell a is turned on, only the data line BL0 is at the low level. Next, the read voltage V is applied to the word line WL.
When RW2 is applied, the data line BL0 remains at the low level, and the data lines BL1 to BL3 are precharged to 1V. Since the memory cell b is turned on, the data line BL1 goes low. Further, when the read voltage VRW3 is applied to the word line WL, the data line BL0
And BL1 remain at the low level, and the data line BL2
And BL3 are precharged to 1V. Memory cell c
Is turned on, the data line BL2 goes low. As described above, the data line from which “0” is read once is not precharged even if the precharge operation is performed.

FIG. 5 shows the timing for reading data. In FIG. 5, T1 is the first data read period, T2 is the second data read period, and T3 is 3
This is the second data reading period. In each read period, the read operation is performed in substantially the same procedure, and the word line switching period t1, the bit line precharge period t2, and the memory discharge period t
3, an amplification period t4 by the sense latch SL, a data transfer period t5 from the sense latch to the data latch, and a bit line reset period t6. Note that the data transfer direction in the second data read period is opposite to the data transfer direction in the first data read period. In the third read period T3, an operation period t4 ′ is inserted between the amplification period t4 and the data transfer period t5, and the data transfer is performed to the third read data and the data latches DLU and DLD in the sense latch SL. This is slightly different from the first and second read periods in that the held first and second read data are transferred to the output buffer circuit.

Note that in FIG. L. Is the potential of the selected word line; L. Is the bit line potential, PCU is the gate control signal for the precharge MOSFET Qp1, PCD
Is the gate control signal of the precharge MOSFET Qp1 on the opposite mat, n (SU) and n (SD) are the potentials of the input / output nodes Na and Nb of the sense latch SL, and TRU / D is the gate control signal of the transfer MOSFET Qt1. , DTU are gate control signals of the transfer MOSFET Qt2, and n (DU
S) is the potential of the input node Nc of the data latch, SSi,
SDi is a control signal for the selection switches Qs1 and Qs2, and DPU is a gate control signal for the MOSFET Qe1 on the data latch DLU side.

In the WL switching operation, the word line WL
, A read voltage VRW1 (1.5 V) is applied to the precharge MOSFET Qp1 in the selected memory mat.
Is applied with a voltage of 1V + Vth, the data line BL (S) is precharged to 1V.
Assuming that "1" data is stored in the sense latch circuit, a high-level signal RSAU is applied to the gate of MOSFET Qd1, and the potential of input / output node Na of the sense latch circuit is set to low level. In the memory discharge operation, since the potential of the input / output node Na of the sense latch circuit is set to the low level, the potential of the input / output node Nb of the sense latch circuit is set to the high level. M for precharge in non-selected memory mat
When a voltage of 0.5V + Vth is applied to the gate of the OSFET Qp2, the data line BL (R) is precharged to 0.5V. The precharge of the data line in the non-selected memory mat may be executed at the time of the WL switching operation.

Since the threshold value of the memory cell coupled to the selected word line WL is lower than the read voltage VRW1, the data lines are applied by applying the high level signals SDi and SSi to the gates of the switch MOSFETs Qs1 and Qs2. BL (S) has a precharge level of 1
It gradually goes down from V. In the amplification operation, high-level signals TRU and TRD are applied to the gates of the transfer MOSFETs Qt1 and Qt1 'to turn on the transfer MOSFETs Qt1 and Qt1'. At this time, the sense latch circuit and the data line are coupled, and the sense latch circuit amplifies data on the data line. In the transfer operation,
When a high-level signal DTU is applied to the gate of the transfer MOSFET Qt2 provided between the data register DLU and the data line BL (S), the data amplified by the sense latch circuit is transferred and stored in the data register DLU. Is done. In the reset operation, MOSFE
A high level signal RSAU is applied to the gates of TQd1 and Qd1 '.
And RSAD are applied to the data line BL.
(S) and BL (R) are reset to 0V.

In the arithmetic operation, the transfer MOSFET
Transfer MOSFET to turn on Qt1 and Qt1 '
High level signals TRU and TRD are applied to the gates of Qt1 and Qt1 '. Numerical values in parentheses indicate data stored in the data registers DLU and DLD. By adding a high-level signal DPU to the gate of the additional circuit Qe1, the operation shown in FIG.
The operation result is stored in the data register by adding the high level signal DTU to the gate of the FET Qt2.

FIG. 6 shows the structure of a data conversion circuit 20 for converting externally input data to be stored into multi-value data stored in a memory cell, and this data conversion circuit 20.
And the relationship between the sense latch column 11 and the data latch columns 12a and 12b in the memory array 10. The data conversion circuit 20 includes an input buffer unit 21 and a data conversion unit 22, and 8-bit data can be input in parallel in pairs of two bits. FIG. 6 shows details of one set of the input buffer unit and the data conversion unit. Hereinafter, one of the data conversion circuits will be described.

The input buffer unit 21 in one set of data conversion circuits includes two clocked inverters INV1 and INV2.
The data converter 22 includes inverters INV11 and INV12 connected to the above-mentioned set of latch circuits LT1 and LT2, respectively.
Three NAND gate circuits G1, G2, G3 each having the input signals of the outputs of the inverters INV11, INV12 and the outputs of the above-mentioned set of latch circuits LT1, LT2, and the inverter INV2 for inverting the outputs of these gate circuits.
1, INV22, INV23, and transmission gates TG1, T formed of MOSFETs connected to these inverters.
G2 and TG3, convert the input 2-bit data into 3-bit data, and output 3-bit × 4 data as a whole.

Table 2 shows an example of data conversion in the data conversion circuit 20.

[Table 2]

As shown in Table 2, the write data "01" is converted into 3-bit data "010", the write data "00" is converted into 3-bit data "100", and the write data "00" is converted. 10 "is 3-bit data" 0 "
01, and the write data "11" is converted into 3-bit data "000", and after conversion, "1".
Will be written only to the memory cell corresponding to the bit corresponding to ".", And will not be written to the memory cell corresponding to the bit corresponding to "0" after the conversion.

The 8-bit write data first input to the data conversion circuit 20 via the external terminals I / O0 and I / O1 is converted into 3-bit data. The converted data is supplied to data latch columns 12a (corresponding to the DLU) and 12b (corresponding to the DLD) arranged at both ends (upper and lower in the figure) of the memory array 10 and a sense latch arranged at the center of the memory array. The data is transferred to and held by the first latch circuit in column 11 (corresponding to the SL). The write data supplied via the external terminals I / O2 and I / O3 are also converted into 3-bit data, and the data latch columns 12a and 12b arranged at both ends (upper and lower in the figure) of the memory array 10. And the second latch circuit of the sense latch circuit 11 disposed at the center of the memory array, and are held.

Similarly, external terminals I / O4 and I / O
5 is also converted into 3-bit data, transferred to the third latch circuits of the data latch columns 12a and 12b and the sense latch column 11 and held therein. The write data supplied via the external terminals I / O6 and I / O7 are also converted into 3-bit data, transferred to the data latch columns 12a and 12b and the fourth latch circuit of the sense latch column 11, and held. Is done. Next, the input 8-bit write data is converted by the data conversion circuit 20 and the data latch circuit 12
a and 12b and the 5th to 8th bits of the sense latch circuit 11, respectively.

By repeating the above operation, the data latch train 12
When data is stored in the latch circuits a and 12b and all the latch circuits of the sense latch row 11, a control circuit, which will be described later, provided in the memory activates a write sequence and is first held in the sense latch row 11. Data is written, then the data in the sense latch row 12a, and then the data in 12b. The control circuit is an external CP.
The control is performed in accordance with a command input from U or the like.

FIG. 7 shows the timing at the time of data writing. As can be seen from FIG.
First, a write command is input, and then write-destination sector addresses add1 and add2 are input and fetched in synchronization with the fall of the write enable signal / WE. At this time, the discrimination between the command and the address is performed by simultaneously inputting a control signal (command data enable signal).
/ CDE. That is, when / CDE is at a low level, it is determined that a command or data has been input, and when / CDE is at a high level, it is determined that an address has been input.

After the address, the first 8 data to be stored in one sector (memory cell connected to one word line)
The bit write data D1 is input and taken into the input buffer unit 21 in synchronization with the clock SC. Then, after the data conversion in the data conversion circuit 20, the transmission gates TG1 to TG3 are turned on by the gate control signal YG, and the 3-bit × 4 write data is sequentially transferred to the data latch columns 12a and 12b and the sense latch column 11. Will be retained. After that, the write data D2, D3,... D528 input in units of 8 bits are sequentially converted into data, and the sense latch train 11 and the data latch train 12a,.
12b. When the transfer of the write data for one sector is completed, a write start command is input and taken in from the outside, and the command is decoded and the write sequence is executed to write the data for one sector at the same time.

In the memory array 10, a write operation, that is, a write pulse, is performed on the storage element connected to the bit line where the data stored in the sense latch row 11 and the data latch rows 12a and 12b are "1". Is applied, the threshold value of each storage element is shifted to one of the distributions shown in FIG.
The data can be written to the memory cell. FIG. 8 shows a write control procedure. It is assumed that prior to this data writing, erasing is performed to set the threshold values of all memory cells to the highest state (a state corresponding to data "11").

The first step S1 (transfer of write data to latches 1 to 3) in FIG.
From the sense latch train 11 and the data latch trains 12a, 12
b, and the control sequence starting from the second step S2 is started by inputting the write start command.

In this control sequence, first, the word line selected by decoding the already written write address is set to a potential such as -11 V (step S2). At the same time, the transfer MOSFET Qt1 on the bit line is turned on, and the bit line whose data is "1" is set to a potential such as 5V in accordance with the data held in the sense latch array 11 at that time. Write is performed. Next, the bit line is precharged to a potential such as 1 V, and then the selected word line is set to a voltage such as 1.0 V, and verify reading is performed. At this time, the data read into the sense latch row 11 from the memory cell that has been normally written changes to “0”. Therefore, it is determined whether or not all the data held in the sense latch row 11 is “0” (Step S
3). If at least one data of "1" remains, writing is performed again using the data held in the sense latch row 11 at that time (step S4).

As a result of the verify judgment, the sense latch train 1
If all the data of 1 has become "0", step S
Proceeding to 5, the data held in the data latch row 12a is transferred to the sense latch row 11. Then, the selected word line is set to a potential, such as -10.5 V, which is slightly lower than the previous word line (step S6). Next, after writing is performed based on the data held in the sense latch array 11, the selected word line is set to a voltage such as 2.0 V,
A verify read is performed to determine whether or not all the data held in the sense latch row 11 is "0" (step S7). If at least one data of "1" remains, writing is performed again using the data held in the sense latch array 11 at that time (step S8).

As a result of the verify judgment, sense latch row 1
If all the data of 1 has become "0", the process proceeds to step S9, and the data held in the data latch row 12b is transferred to the sense latch row 11 this time. Then, the selected word line is set to -10V which is slightly lower than the previous word line.
(Step S10). Next, after writing is performed based on the data held in the sense latch train 11, the selected word line is set to a voltage such as 3.0 V, and verify-read is performed, and the data held in the sense latch train 11 is read. Are determined to be all "0" (step S11). And even one is "1"
If the data remains, the data is written again using the data held in the sense latch array 11 at that time (step S12).

According to the above-described procedure, writing to memory cells having threshold values far from the erase level and writing to memory cells having threshold values which are close to each other are sequentially performed, and the writing operation is completed. This makes it possible to reduce the number of word line disturbances for memory cells having a threshold value close to the erase level, and to minimize fluctuations in the threshold value due to the word line disturbance. Moreover, in the above embodiment, the write word line voltage is set to -11 V, -10.5
Since the absolute value is gradually reduced as in the case of V and −10 V, the amount of disturbance generated at one time is also gradually reduced, and the fluctuation of the threshold value can be further reduced. However, instead of gradually lowering the write voltage, the write pulse width may be gradually reduced.

FIG. 9 shows how the signal lines in the memory array and the sense latch circuit change when data is written (when data is written in the memory cells in the upper memory mat). In addition, the code | symbol shown in FIG.
It corresponds to the sign of the signal shown in FIG. By the way,
YGi is a gate control signal of the column switch Qy, NOL
Is the potential of the input / output node Nb of the sense latch, BLU is the potential of the selected-side bit line, BLD is the potential of the non-selected-side bit line, and TRU and TRD are the transfer MOSFETs Qt1 'and Qt.
The gate control signal of t1 and PCU are the gate control signal of the precharge MOSFET (Qp1 ') of the selected bit line,
RD is a MOS for half precharge of the non-selected side bit line
A gate control signal for the FET Qp2, RSAU and RSAD are gate control signals for the discharge MOSFETs Qd1 and Qd1 ', and SLP SL is a power supply for the flip-flop FF1 of the sense latch.

FIG. 10 shows an example of a layout configuration and a sectional structure of the memory cell in the above embodiment. In the figure, reference numeral 50 denotes a memory cell MC and a selection switch MO.
Diffusion layers serving as source and drain regions of SFETs Qs1 and Qs2, and 51 and 52 are selection switch MOSFETs Qs1 and Qs2 made of polysilicon or tungsten silicide.
The gate electrode of Qs2, 53 is M which constitutes the memory cell MC.
OSFET control gate electrode (word line), 5
Reference numeral 4 denotes a contact hole for connecting the source regions of the selection switch MOSFETs Qs1 and Qs2 to the bit line BL. 10B is a cross-sectional view taken along line XX in FIG. 10A, FIG. 10C is a cross-sectional view taken along line YY in FIG. As shown in (), the bit line BL is disposed above the control gate electrode 53 so as to be orthogonal thereto. The bit line BL is made of, for example, an aluminum layer. As shown in FIG. 10C, a floating gate electrode 55 made of polysilicon is provided below the control gate electrode 53.

FIGS. 11 to 13 show another embodiment of the memory array. FIG. 11 shows an example of a layout structure and a sectional structure of a memory cell in a memory array called a NAND type. In the NAND-type memory array, as shown in FIG. 11D, a plurality of memory cells MC are connected in series between the selection switch MOSFETs Qs1 and Qs2 connected to the bit line BL and the common source line CSL. Connected to. As in the embodiment of FIG. 10, reference numeral 50 denotes a memory cell MC and a selection switch MOSF.
Diffusion layers serving as source and drain regions of ET Qs1 and Qs2, and 51 and 52 are selection switch MOSFETs Qs1 and Qs2 made of polysilicon or tungsten silicide.
The gate electrode 53 is a MOS constituting the memory cell MC.
A control gate electrode (word line) 54 of the FET is a contact hole for connecting the source region of the selection switch MOSFET Qs1 Qs2 to the bit line BL.

FIG. 11 (B) is a cross-sectional view of FIG.
FIG. 11C is a cross-sectional view taken along the line YY in FIG. 11A, and as shown in FIG. 11B, the bit line BL It is arranged above the gate electrode 53 so as to be orthogonal to this.
The bit line BL is made of, for example, an aluminum layer. As shown in FIG. 11C, a floating gate electrode 55 is provided below the control gate electrode 53 of the memory cell. In the embodiment shown in FIG. 10, when each memory cell is turned on, the bit line discharge current changes in the direction in which the control gate electrode is disposed (FIG.
On the other hand, in the embodiment of FIG. 11, when the memory cell is turned on, the current flows in a direction orthogonal to the control gate electrode (the vertical direction in FIG. 11A).
Also in this embodiment, the floating gate electrode 55 is made of polysilicon.

FIG. 12 shows an example of a layout structure and a sectional structure of a memory cell in a memory array called a NOR type. In a NOR type memory array, as shown in FIG. 12D, a plurality of memory cells are arranged in series, the source / drain terminals of adjacent memory cells are used as common terminals, and each common terminal is used as a common terminal. The bit line BL and the common source line CSL are alternately connected. 12, 50a is a diffusion layer serving as a common drain region of the memory cell MC, 50b is a diffusion layer serving as a common source region of the memory cell MC, 53 is a control gate electrode (word) of the memory cell MC made of polysilicon or tungsten silicide. Lines) and 54 are contact holes for connecting the common drain region 50a of the memory cell MC and the bit line BL. In this example,
The common source region 50b of the memory cell MC also serves as the common source line CSL.

FIG. 12 (B) is a cross-sectional view of FIG.
FIG. 12C is a cross-sectional view taken along the line YY in FIG. 12A, and the bit line BL is connected to the control line as shown in FIG. 12B. It is arranged above the gate electrode 53 so as to be orthogonal to this.
The bit line BL is made of, for example, an aluminum layer. As shown in FIG. 12C, a floating gate electrode 55 is provided below the control gate electrode 53 of the memory cell. Also in this embodiment, the floating gate electrode 55 is made of polysilicon.

FIG. 13 shows an example of a layout structure and a sectional structure of a memory cell in a memory array called a DINOR type. As shown in FIG. 13D, the DINOR type memory array is characterized by a configuration in which the basic configuration is the NOR type of FIG. 12 and a local bit line LBL is added thereto. That is, a plurality of memory cells are arranged in series, the source / drain terminals of adjacent memory cells are used as common terminals, and each common terminal is alternately connected to the local bit line LBL and the common source line CSL. And the local bit line LBL and the bit line B
L is connected to a selection switch MOSFET Qs1.

In FIG. 13A, reference numeral 50a denotes a diffusion layer serving as a common drain region of the memory cell MC; 50b, a diffusion layer serving as a common source region of the memory cell MC; 51, a gate electrode of the selection switch MOSFET Qs1; The control gate electrode (word line) of the memory cell MC made of tungsten silicide, and 54 is a selection switch MO
This is a contact hole for connecting the drain region of the SFET Qs1 to the bit line BL. In this example,
The common source region 50b of the memory cell MC also serves as the common source line CSL.

FIG. 13 (B) is a cross-sectional view of FIG.
FIG. 13C is a cross-sectional view taken along the line YY in FIG. 13A, and the local bit line LBL is, as shown in FIG. The bit line BL is arranged above the control gate electrode 53 so as to be orthogonal thereto, and the bit line BL is arranged above and parallel to the local bit line LBL. In this embodiment, the local bit line LBL is made of, for example, a polysilicon layer, and the bit line BL is made of, for example, an aluminum layer. As shown in FIG. 13C, a floating gate electrode 55 is provided below the control gate electrode 53 of the memory cell.

FIG. 14 shows an example of the entire configuration of a multi-level flash memory including the memory array 10, the data conversion circuit 20, the control circuit, and the memory peripheral circuit on the same semiconductor chip. The flash memory of this embodiment is not particularly limited, but has a command decoder 31 for decoding a command given from an external CPU or the like.
And a control circuit (sequencer) 32 for sequentially forming and outputting a control signal for each circuit in the memory in order to execute a process corresponding to the command based on a decoding result of the command decoder 31. Is given, it is configured to decode it and automatically execute a corresponding process. The control circuit 32 is, for example, a ROM (Read Only Memory) in which a series of microinstructions necessary for executing a command (instruction) is stored, similarly to a control unit of a microprogram type CPU. The micro-program 31 is configured to start by generating a head address of a micro-instruction group corresponding to the command and giving the head address to the control circuit 32.

In FIG. 14, circuit portions denoted by the same reference numerals as in FIG. 4 are circuits having the same functions. That is, 10 is two memory mats MAT-U, MAT-
D, a data conversion circuit for converting write data input from the outside into quaternary data every two bits, 11 a sense latch column for holding the converted write data and read data, 12a , 12b are data latch columns.

Each memory mat M
X-system address decoders 13a and 13b corresponding to AT-U and MAT-D, respectively;
Word drive circuits 14a and 14b are provided for driving one word line WL in each memory mat to a selected level in accordance with the decoding result of b. Although not particularly limited, in the memory array 10 of this embodiment, the word drive circuits are arranged on both sides and the center of each memory mat. Although not shown in FIGS. 3 and 4, a Y-system address decoder circuit and a column switch that is selectively turned on and off by this decoder to transfer data from the data conversion circuit 20 to a corresponding sense latch include:
It is configured integrally with the sense latch row 11. FIG. 9 shows this Y-system decoder circuit, column switch, and sense latch circuit as one functional block Y-DEC & SL.

The multi-level flash memory of this embodiment includes:
In addition to the above circuits, the sense latch train 1
A write / erase determination circuit 33 that determines whether the writing or erasing has been completed based on the data of 1 and notifies the control circuit 32 of the writing or erasing sequence.
And a clock generation circuit 34 which forms a timing clock necessary for internal operation and supplies the clock to each circuit in the memory. The clock generation circuit 34 reflects the internal state of the memory and indicates whether external access is possible to the outside. / Busy signal R /
A status and test system circuit 35 having a function of forming and outputting a signal B and a function of testing an internal circuit; a main amplifier circuit 36 for amplifying a signal read from the memory array 10; a power supply system circuit 37; An input / output buffer circuit 38 for taking in an input address signal, write data signal and command and supplying it to an internal predetermined circuit and outputting a read data signal to the outside, taking in a control signal inputted from the outside and controlling A control signal input buffer & input / output control circuit 39 for supplying a circuit 32 and other internal predetermined circuits and controlling the input / output buffer circuit 38, an address control system circuit 40, and a spare when there is a defective bit in the memory array. A redundant circuit 41 for replacing a memory row is provided.

The flash memory of this embodiment shares an external terminal (pin) I / O for an address signal, a write data signal, and a command input. Therefore, the input / output buffer circuit 38 discriminates these input signals according to the control signal from the control signal input buffer & input / output control circuit 39 and supplies them to a predetermined internal circuit. The power supply circuit 37 includes a reference power supply circuit for generating a reference voltage such as a substrate potential and a write voltage, an erase voltage, a read voltage, a verify voltage, etc. based on a power supply voltage Vcc supplied from the outside. An internal power supply generating circuit including a charge pump for generating a voltage required by
It comprises a power supply switching circuit for selecting a desired voltage from these voltages in accordance with the operation state of the memory and supplying it to the memory array 10, a power supply control circuit for controlling these circuits, and the like.

The address control system circuit 40 fetches an externally input address signal and counts up the address signal. The address counter ACNT automatically updates the Y address at the time of data transfer or automatically shifts the X address at the time of data erasure.
An address generator AGEN for generating an address, a rescue circuit for switching the selected memory row or column when the input address is compared with the defective address and the address matches, and the like are provided.

As a control signal inputted from the external CPU or the like to the flash memory of this embodiment, for example, a reset signal RES, a chip selection signal CE, a write control signal W
E, an output control signal OE, a command enable signal C for indicating a command or data input or an address input
DE, system clock SC, and the like. As an external device for controlling the multi-value flash memory of the above embodiment, a general-purpose microcomputer LSI can be used as long as it has an address generation function and a command generation function.

FIG. 15 shows a configuration example of a system using the flash memory as a storage device. Such a system is suitable for a control system such as a mobile phone, for example, because data is retained in the flash memory even when the power is turned off. In the figure, reference numeral 100 denotes a flash memory, 110 denotes a one-chip microcomputer which mainly executes control of data reading, data writing, data erasing, etc. of the flash memory 100, and 120 denotes an error correction code or data reading when writing data in the flash memory. ECC (Error Correcting Code) circuit that sometimes checks the read data and corrects errors
130 is a flash memory 11 composed of an EEPROM or the like.
A management table memory for storing the number of times of data rewriting of 0 in a table format; 140, a write buffer for temporarily storing write data supplied from a microprocessor (not shown) via a standard bus 150; Memory 100, 130, ECC circuit 1
Reference numeral 170 denotes a local bus for connecting a signal between the local bus 160 and the standard bus 150.

As described above, in the above embodiment, in the nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-value information in one memory cell, the word line read level is set. In order from the lower to the higher side, and a latch means for holding the read data is provided to selectively perform the next bit line precharge based on the held data. Therefore, the memory cell from which "0" has been read once is read as "0" even if the read operation is performed at a higher level, which is the same result as not performing the read operation. The charge can be omitted. Since the current consumption can be reduced by omitting the precharge, the current flowing from the memory array to the ground line at the time of reading can be reduced, and the floating amount of the source potential of the memory cell can be reduced. Erroneous reading of data can be prevented. In addition, since the number of times of reading can be reduced by omitting the precharge, fluctuation of the threshold value due to read disturb, that is, garbled storage data can be suppressed.

In addition, according to the above-mentioned reading method, all the read data becomes "0" before reading to the end of only the memory cells having a low threshold value, so that all "0" judging means is provided. Thus, the read operation can be completed halfway, and the effect of reducing the current consumption and shortening the data read time can be achieved. Furthermore, the correspondence between the threshold value of the memory cell and the storage data is determined so that the code of the storage data is different only by one bit between the adjacent threshold values. There is an effect that the load on the error correction circuit for correcting the error is small and the circuit scale can be small.

Further, in the above embodiment, the memory array is composed of two mats, and between the two mats, the bit line in each mat is connected to the input / output terminal and 1 bit of the read 3-bit data is connected. , And a data latch circuit capable of holding another one bit of the 3-bit data read out by the sense latch is provided outside each of the mats.
Since data transfer is performed between the data latch circuit and the sense latch circuit via the bit line, there is an effect that it is not necessary to provide a register for holding read data on the output circuit side.

Although the invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the above embodiment, the threshold value of the memory cell is set to four levels so that four-level data can be stored in one memory cell. It is also possible to apply the present invention to a nonvolatile memory which is set in stages and stores data of 3 bits or more.

Further, in the embodiment, conversion as shown in Table 2 is performed as an example of a method of converting 2-bit data into quaternary data. However, the conversion method is not limited to that shown in Table 2, and the conversion method is not limited to that shown in Table 2. Any data that can be obtained at different bit positions where "1" stands can be used. Also, the operation for the data reverse conversion is not limited to the method of the embodiment (wired logic method using a bit line), but any operation that can restore 2-bit data such as a dedicated operation circuit or a data conversion circuit can be used. Such a method may be used.

Further, the writing method for each memory cell is not limited to the method of once erasing and raising the threshold value and then lowering the threshold value by the writing pulse as in the embodiment, but the threshold value by the writing pulse. The value may be increased. In the embodiment, the threshold value is changed by writing to the memory cell corresponding to the sense latch circuit holding data "1". However, the memory corresponding to the sense latch circuit holding data "0" is changed. The threshold may be changed by writing to the cell.

Further, in the above-described embodiment, the case where the memory array is constituted by two mats has been described. However, the present invention is not limited to this. It can also be applied when When the memory array is composed of one mat, for example, a method of transferring the data after conversion by the data conversion circuit twice may be applied.

In the above description, the case where the invention made by the present inventor is mainly applied to the collectively erased flash memory which is the application field as the background has been described. However, the present invention is not limited to this. The present invention can be widely used for general non-volatile memory devices using a MOSFET having a floating gate as a memory element, and also for a semiconductor device provided with a memory cell having a plurality of thresholds.

[0093]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the present invention can realize a multi-level nonvolatile semiconductor memory device in which the read time is short, the current consumption is small, the required number of read operations is reduced, and the storage data is not easily garbled. Further, the present invention can realize a multi-level nonvolatile semiconductor memory device capable of suppressing floating of the source potential at the time of reading and preventing unreadable or erroneous data reading.

[Brief description of the drawings]

FIG. 1 is an explanatory view schematically showing a data reading method of a multi-level flash memory according to the present invention.

FIG. 2 is an explanatory diagram showing a method of transferring data held in a sense latch to a data latch via a bit line.

FIG. 3 is a circuit diagram showing a specific example of a memory array.

FIG. 4 is a circuit diagram showing a specific example of a sense latch circuit and a data latch circuit.

FIG. 5 is a timing chart showing a timing at the time of reading data from the multilevel flash memory of the embodiment.

FIG. 6 is a logic circuit diagram showing an embodiment of a data conversion circuit for converting 2-bit write data into quaternary data in the multi-level flash memory of the embodiment.

FIG. 7 is a timing chart showing data input timing at the time of writing in the multi-level flash memory of the embodiment.

FIG. 8 is a flowchart illustrating a writing procedure of the multilevel flash memory according to the embodiment;

FIG. 9 is a timing chart showing signal timings at the time of data writing.

FIG. 10 is a diagram illustrating an example of a layout configuration and a cross-sectional structure of a memory cell according to an embodiment.

FIG. 11 is a diagram showing an example of a layout configuration and a cross-sectional structure of another embodiment of a memory cell.

FIG. 12 is a diagram showing an example of a layout configuration and a cross-sectional structure of another embodiment of a memory cell.

FIG. 13 is a diagram showing an example of a layout configuration and a cross-sectional structure of another embodiment of a memory cell.

FIG. 14 is an overall block diagram schematically showing an embodiment of a multilevel flash memory according to the present invention.

FIG. 15 is a block diagram showing an example of an application system of the multilevel flash memory according to the present invention.

FIG. 16 is a schematic diagram showing a structure of a memory cell used in the flash memory according to the embodiment and a voltage state at the time of data writing.

FIG. 17 is a schematic diagram showing a voltage state at the time of erasing a memory cell used in the flash memory of the example.

FIG. 18 is an explanatory diagram showing a threshold distribution of a memory cell in a four-level flash memory.

FIG. 19 is an explanatory diagram showing an example of routing of a ground line from a ground pin to a memory cell in a flash memory.

FIG. 20 is a characteristic diagram showing a relationship between a gate-source voltage and a drain current of a MOSFET constituting a memory cell in a flash memory.

FIG. 21 is a flowchart illustrating a reading procedure of the multi-level flash memory according to the embodiment.

FIG. 22 is a diagram showing a change in data line potential at the time of writing in the multilevel flash memory of the example.

[Explanation of symbols]

 Reference Signs List 10 memory array 11 sense latch sequence 12a, 12b data latch sequence 13 X-system address decoder 14 word drive circuit 20 data conversion circuit 21 buffer unit 22 data conversion unit SL sense latch circuit DLU, DLD data latch circuit BL bit line WL word line MC Memory cell

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification symbol FI H01L 29/792 (72) Inventor Hiroshi Sato 2326 Imai, Ome-shi, Tokyo Inside Device Development Center, Hitachi, Ltd. (72) Inventor Kubono Shoji 3 3-1-1 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside Hitachi Ultra-LSE Engineering Co., Ltd. (72) Inventor Toshinori Harada 3-1-1 Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi Ultra-SII Engineering Co., Ltd. (72) Inventor Takayuki Kawahara 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Naoki Miyamoto 3681 Hayano, Mobara-shi, Chiba Pref.

Claims (9)

[Claims] 1. A plurality of memory cells each having a plurality of word lines, a plurality of data lines, a control gate, and a floating gate and storing a plurality of bits of data as a threshold value, and each of the plurality of memory cells corresponds to a plurality of memory cells. A read operation for reading a plurality of bits of data stored in a memory cell coupled to one word line and one data line, coupled to the plurality of word lines, and coupled to the selected word line. A word driver circuit that supplies a read voltage to the selected word line a plurality of times; in the read operation, data from a data corresponding to a lowest threshold to a data corresponding to a highest threshold In order to read data in order, the selected word line is first supplied with a first read voltage, and A reading method for a nonvolatile semiconductor memory device in which read voltages higher than a voltage are sequentially supplied. 2. A plurality of sense latch circuits and a precharge circuit are coupled corresponding to the plurality of data lines, and the plurality of data lines are coupled to input / output nodes of a number of sense latch circuits. 2. The method according to claim 1, wherein the reading is performed on the nonvolatile semiconductor memory device. 3. The precharge circuit coupled to the plurality of data lines, during the read operation, precharges a data line coupled to a sense latch circuit in which data higher than a read voltage is stored. 3. The method for reading a nonvolatile semiconductor memory device according to claim 1, wherein: 4. The plurality of memory cells store 2-bit data, and the other plurality of data lines coupled to the other input / output node of the plurality of sense latch circuits, and the other plurality of data lines are 2. The data communication system according to claim 1, wherein two precharge circuits are coupled, said plurality of data lines are coupled to a first data latch circuit, and said other plurality of data lines are coupled to a second data latch circuit. 4. The method for reading a nonvolatile semiconductor memory device according to 1, 2, or 3. 5. In the read operation, when reading data corresponding to the lowest threshold value, the word driver circuit supplies the first read voltage to a selected word line, and the second lowest threshold value. The word driver circuit supplies a second read voltage higher than the first read voltage to the selected word line when reading data corresponding to the word line, and reads the word driver circuit when reading data corresponding to the third lowest threshold value. The circuit supplies a third read voltage higher than the second read voltage to the selected word line,
When reading data corresponding to the lowest threshold value, the precharge circuit supplies a precharge potential to the plurality of data lines, and when reading data corresponding to the second lowest threshold value, The precharge circuit precharges a data line coupled to a sense latch in which data higher than the first read voltage is stored, and reads out data corresponding to a third lowest threshold. 5. The method according to claim 1, wherein a data line coupled to a sense latch circuit storing higher data is precharged. 6. After the first read voltage is supplied to a selected word line and stored in a first read data sense latch circuit read out, the second read voltage is stored in the selected word line. The second read data transferred and stored in the second data latch circuit before or during the supply of the voltage, and read by the second read voltage being supplied to the selected word line, is sense latched. After being stored in the circuit, before or during the supply of the third read voltage to the selected word line, the data is transferred and stored in the first data latch circuit, and the third read voltage is supplied to the selected word line. The third read data read by being supplied to the line is stored in a sense latch circuit, and the second read data and the third read data are stored in the sense latch circuit. 6. A data processing device according to claim 1, wherein a predetermined operation process is executed with the data, and execution result data of the predetermined operation process is stored in the second data latch circuit. The reading method of the nonvolatile semiconductor memory device described in the above. 7. An external terminal, wherein the read operation is executed when a read command is supplied through the external terminal, and the read operation stored in the first data latch circuit and the second data latch circuit is performed. The nonvolatile semiconductor memory device according to claim 1, wherein the first read data and the execution result data are output via the external terminal. 8. A power supply circuit for generating the first, second, and third read voltages, and a word driver circuit, for selecting a read word line from the plurality of word lines in the read operation. A nonvolatile semiconductor memory device comprising a decoder circuit, wherein the decoder selects one of the first, second, and third readout transmissions and supplies it to the word driver circuit. 9. The nonvolatile semiconductor memory according to claim 1, wherein said other plurality of potentials precharged by said second precharge circuit are lower than the potentials of said plurality of data lines precharged by said precharge circuit. apparatus.