JP2007149186A - Nonvolatile semiconductor memory apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent failure of write-in caused by apparent variation of threshold voltage due to capacitive coupling between nonvolatile memory cells. <P>SOLUTION: The apparatus has rewritable nonvolatile memory cells (MC) performing so to speak multi-level storing. Nonvolatile memory cells of write selection to be written and nonvolatile memory cells of non-write selection in accordance with information to be written are included in a rewriting unit of storage information. The threshold voltage is set so as to keep in required distribution from one direction for the write selection nonvolatile memory cells in write processing for the rewriting unit using write verify voltage, for a result of write processing, for example, stored information is read out from the nonvolatile memory cell of write selection and non-write selection of the rewriting unit using upper or lower discriminating voltage. Information read out from the non-write selection nonvolatile memory cell out of read out storage information is excluded from discrimination object of success or not for the write processing. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a so-called non-volatile semiconductor memory device capable of storing information in multiple values, for example, to a technique for determining an upper skirt in additional writing of a flash memory.

  In a flash memory that performs quaternary storage, a threshold voltage distribution corresponding to 2-bit storage information is defined for a nonvolatile memory cell. When writing storage information, first, the nonvolatile memory cells are adjusted to a low threshold voltage by an erasing process, and then the writing (additional writing) process for increasing the threshold voltage in stages is performed on the nonvolatile memory cells. A threshold voltage corresponding to the write data is set according to the procedure. For example, when the storage information in the erased state is “11” and a higher threshold voltage is assigned in the order of the storage information “10”, “00”, “01”, the nonvolatile memory cell to which the data “10” is to be written is Write selection control information is generated at the write operation timing, and threshold voltage control is performed. At this time, the non-volatile memory cell to be erased or to which other data is to be written is inhibited from being written by the write non-selection control information. In the same manner, the threshold voltage control based on the write selection control information is performed on the memory cells selected for writing in response to the write operation timings of “10”, “00”, and “01” sequentially. Write selection and write non-selection control information is latched in a sense latch, and a write current is passed to the memory cell, for example, via a bit line, and the write non-selection control information acts to suppress the generation of the write current. In the above operation, the lower boundary of each threshold voltage distribution is defined by the write verify voltage. The upper boundary of the threshold voltage distribution is defined by the upper skirt determination voltage. In the upper skirt determination, all the nonvolatile memory cells in the write processing unit are selected according to the upper skirt determination level, and all determination is performed. Japanese Patent Application Laid-Open No. H10-228707 describes write verify and all determination in a flash memory.

JP-A-10-106276

  The present inventor has examined an erroneous determination at the time of determining the upper skirt in the flash memory. When the elements are miniaturized due to the improvement in the degree of integration, the interval between the nonvolatile memory cells in the memory array is narrowed, and thereby the parasitic capacitance is relatively increased. In the case of a floating gate type nonvolatile memory cell, the conductive floating gates are insulated from each other by silicon oxide or the like, but the floating gates adjacent to each other in front, rear, left, and right are capacitively coupled by parasitic capacitance. In such capacitive coupling, the floating gate constitutes a capacitive electrode. Therefore, when electrons are injected into the floating gate in the write operation and the threshold voltage is changed, the potential change of the floating gate caused thereby changes the potential of another floating gate that is capacitively coupled thereto. This apparently changes the threshold voltage of the nonvolatile memory cell having the other floating gate. For example, the writing process to the nonvolatile memory cells sharing the word line is performed in the order of “10”, “00”, “01” in accordance with the write data based on the erased state “11”. Is determined in the order of “10” data, “00” data, and “01” data. Therefore, if the coupling capacitance between the memory cells is large, the threshold voltage that has been previously determined will vary according to the charge injection state of the floating gate that is changed by the subsequent write processing. Since the amount of charge injected into the floating gate increases with later writing processing, the threshold voltage fluctuating due to capacitive coupling tends to increase later. In short, the threshold voltage of the memory cell for which the threshold voltage state has been determined first becomes apparently higher later. Then, after the verify operation of the lower skirt for the write processing of “10”, “00”, and “01” is passed, if the upper skirt determination operation is performed in units of word lines, the memory cell whose threshold voltage state has been previously determined It has been found by the present inventor that the threshold voltage apparently increases later and exceeds the upper skirt determination level, which may cause an erroneous determination in the upper skirt determination. There is no problem in the memory operation as long as such fluctuation does not exceed the read word line selection level (read determination level). If a relatively large margin is secured in the potential difference between the upper skirt determination level and the readout determination level between the upper threshold determination level and the threshold voltage distribution above the threshold voltage distribution, the threshold voltage changed by capacitive coupling is Exceeding the read determination level is unlikely to actually occur. Conversely, if such an erroneous determination in the upper skirt determination is detected, the host is notified as a write failure and is subject to error processing, which places a heavy burden on the host system. It has been made clear by the inventors.

  An object of the present invention is to prevent a write failure from being detected due to an apparent variation in threshold voltage due to capacitive coupling between nonvolatile memory cells.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A non-volatile semiconductor memory device (1) according to the present invention has a plurality of rewritable non-volatile memory cells (MC), and each non-volatile memory cell has two or more bits depending on a difference in threshold voltage. Can be stored in a rewritable manner. In this nonvolatile semiconductor memory device, a rewrite unit of stored information includes a nonvolatile memory cell that is selected for writing and a nonvolatile memory cell that is not selected for writing according to information to be written. The non-volatile semiconductor memory device uses the write verify voltage (VWV), for example, for the non-volatile memory cell selected for write in the rewrite unit, so that the threshold voltage falls within a required distribution from one direction. Is stored in a non-volatile memory cell in which rewrite units are selected and unselected using a determination voltage (for example, upper skirt determination voltage (VWE)) that defines the distribution from the other direction with respect to the result of the write process. The information is read, and the information read from the non-programmed non-volatile memory cell among the read storage information is excluded from the determination target of the success or failure of the write process.

  According to the above-described means, when setting a threshold voltage to a nonvolatile memory cell that is selected for writing in a rewrite unit, after passing a write verify operation that defines the bottom of the target threshold voltage distribution, The target of the upper skirt determination for defining the upper skirt is limited to the non-volatile memory cell selected for writing, which is the writing target at that time. In short, some non-programmed non-volatile memory cells included in the rewrite unit have already been written to another write data. As described above, the threshold voltage of the nonvolatile memory cell that has been written may be apparently increased due to capacitive coupling with the nonvolatile memory cell that is currently selected for writing. Even if the non-volatile memory cell whose apparent threshold voltage is increased is included in the read target based on the upper skirt determination level, the non-volatile memory cell which is not selected at this time is excluded from the upper skirt determination. It is possible to suppress erroneous determination of the upper skirt protrusion caused by the nonvolatile memory cell having a higher upper threshold voltage.

  As one specific form of the present invention, the nonvolatile memory cell has a conductive floating gate (FG) insulated for each nonvolatile memory cell as a charge storage region for determining a threshold voltage. The floating gate causes significant capacitive coupling between adjacent non-volatile memory cells.

  As another specific form of the present invention, a plurality of strings including a plurality of nonvolatile memory cells connected in parallel between a source and a drain are provided, and data paths of the plurality of strings are connected to one global bit line (GBL). The plurality of strings sharing the global bit line have nonvolatile memory cells (MC) each having a selection terminal connected to the same word line (WL). Since one word line is commonly connected to select terminals of nonvolatile memory cells in a plurality of rewrite units, significant capacitive coupling occurs between different rewrite units.

  [2] A nonvolatile semiconductor memory device according to the present invention having a different expression from the above has a plurality of rewritable nonvolatile memory cells, and each of the nonvolatile memory cells has a 2 It is possible to store rewritable information of bits or more. In this nonvolatile semiconductor memory device, a rewrite unit of stored information includes a nonvolatile memory cell that is selected for writing according to information to be written and a nonvolatile memory cell that is not selected for writing. The non-volatile memory cell has a write control circuit (16) for setting the threshold voltage of the non-volatile memory cell selected for writing to a required distribution from one direction in a write process for the rewrite unit. . Further, the non-volatile semiconductor memory device reads out from the non-volatile memory cell in which rewrite unit is selected and non-programmed using a determination voltage (VWE) that defines the distribution from the other direction with respect to the result of the write process. Among the information, there is a circuit (32) for excluding information read from the non-programmed non-volatile memory cell from the determination target of whether or not the writing process is successful.

  According to the above-described means, even if the read target based on the upper skirt determination level includes a nonvolatile memory cell whose apparent threshold voltage is increased, the non-volatile memory cell that is not selected this time is determined from the upper skirt determination. Since it is excluded, it is possible to suppress the erroneous determination of the upper skirt protrusion caused by the nonvolatile memory cell whose apparent threshold voltage is increased.

  As one specific form of the present invention, the control circuit uses the write verify voltage (VWV) corresponding to the information to be written to set the threshold voltage for the write selected nonvolatile memory cell from one direction. Set to fit in the distribution. Further, the determination voltage that defines the distribution from the other direction with respect to the result of the writing process is an upper skirt determination voltage (VWE) corresponding to the information to be written.

  As another specific form of the present invention, a word line (WL) connected to a selection terminal of the nonvolatile memory cell (MC), a bit line (GBL) connected to a data terminal of the nonvolatile memory cell, And a sense latch (20) connected to the bit line, and an all determination circuit (35, 36) for determining whether or not all latch data of the sense latch of the write processing unit has a value due to memory discharge. The circuit to be excluded is a selective charge / discharge circuit (32) that performs selective discharge or selective precharge of the bit line in accordance with latch data of the sense latch. An upper skirt determination control circuit (16) for controlling an operation using the selective charge / discharge circuit is further provided.

  As a more specific form of the present invention, the upper skirt determination control circuit latches write selection control information in the sense latch corresponding to the write-selected nonvolatile memory cell after the write process (SX) The sense latch corresponding to the non-programmed non-volatile memory cell latches the program non-selection control information (SX), and the sense latch is applied to the bit line obtained by the memory discharge at the word line level of the read operation. Selective precharge is performed by the selective charge / discharge circuit using latch data to be latched (SY), and the result is latched by the sense latch (S3). Next, the upper skirt determination control circuit performs selective discharge by the selective charge / discharge circuit using latch data latched by the sense latch with respect to the bit line obtained by memory discharge (S6) using the upper skirt determination level. (S7), the result is latched by the sense latch, and the all decision circuit is caused to make a decision based on the latch data of the sense latch.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to prevent a write failure from being detected due to an apparent variation of the threshold voltage due to capacitive coupling between nonvolatile memory cells.

<Overall configuration of flash memory>
FIG. 2 shows a flash memory. The flash memory 1 is formed on a single semiconductor substrate such as single crystal silicon.

  The flash memory 1 is not particularly limited, but has four memory banks BNK0 to BNK3. Each of the memory banks BNK0 to BNK3 has the same configuration and can be operated in parallel. In the figure, the configuration of the memory bank BNK0 is typically illustrated in detail. The memory banks BNK0 to BNK3 include a memory array (ARY) 3, an X decoder (XDEC) 4, a data register (DRG) 5, a data control circuit (DCNT) 6, and a Y address control circuit (YACNT) 7.

  The memory array 3 has a large number of nonvolatile memory cells capable of electrically rewriting stored information. The nonvolatile memory cell is not particularly limited, but has a stacked gate structure in which a control gate is overlaid on a floating gate which is a charge storage region via an insulating film. Although not particularly limited, each nonvolatile memory cell stores 2 bits of data. In short, information is stored in four values. The four values are, for example, four values “11”, “10”, “00”, and “01”. The stored information “11” is obtained by an erasing process that is initialization for the nonvolatile memory cell. The erasing process is not particularly limited, but the circuit ground potential is applied to the source, drain, and well of the nonvolatile memory cell, and a negative high voltage is applied to the control gate to move the electrons in the charge storage region. By doing so, the threshold voltage is lowered. The stored information “10”, “00”, “01” is obtained by program processing (write processing). The write process is not particularly limited, but a current is caused to flow from the drain to the source of the nonvolatile memory cell, hot electrons are generated on the substrate surface at the source end, and this is injected into the floating gate by the electric field generated by the high voltage of the control gate. Thus, the threshold voltage is increased. The target threshold voltage is different depending on the stored information “10”, “00”, “01”. Read processing is performed by precharging a bit line in advance, selecting a nonvolatile memory cell with a predetermined read determination level as a word line selection level, and storing information by changing a current flowing in the bit line or a voltage level appearing on the bit line. Is set to be detectable. The word line selection level differs depending on the storage information “11”, “10”, “00”, “01”. The memory array 3 has a read / write circuit (not shown) connected to the bit line. The read / write circuit latches the storage information read to the bit line in the read process, and controls the bit line potential according to the write data in the write process.

  In the memory array 3, the control gate of the nonvolatile memory cell is connected to the word line. For example, the control gates of nonvolatile memory cells for two pages (page 0, page 1) are connected to one word line. The erasing process is performed in units of two pages, the writing process is performed in units of one page, and the reading process is performed in units of one page.

  The flash memory array 3 and the data register 5 input / output data. For example, the data register 5 is constituted by an SRAM and functions as a buffer for write data to be written to the flash memory array 3 and a buffer for read data read from the flash memory array 3.

  The data control circuit 6 controls input / output of data to / from the data register 5. The Y address control circuit 7 performs address control for the data register 5.

  The external input / output terminals I / O 1 to I / O 16 are also used as address input terminals, data input terminals, data output terminals, and command input terminals, and are connected to the multiplexer (MPX) 10. The page address input to the external input / output terminals I / O 1 to I / O 16 is input from the multiplexer 10 to the page address buffer (PABUF) 11, and the Y address (column address) is input from the multiplexer 10 to the Y address counter (YACUNT) 12. Preset. Write data input to the external input / output terminals I / O 1 to I / O 16 is supplied from the multiplexer 4 to the data input buffer (DIBUF) 13. Write data supplied to the data input buffer 13 is input to the data control circuit 6 via an input data control circuit (IDCNT) 14. Read data output from the data control circuit 6 is supplied to the multiplexer 10 via the data output buffer (DOBUF) 15 and output from the external input / output terminals I / O1 to I / O16.

  A part of the command code and the address signal supplied to the external input / output terminals I / O1 to I / O16 are supplied from the multiplexer 10 to the internal control circuit (OPCNT) 16.

  The page address supplied to the page address buffer 11 is decoded by the X decoder 4 and a word line is selected from the memory array 3 according to the decoding result. The Y address counter 12 preset with the Y address supplied to the page address buffer 11 performs address counting with the preset value as a starting point, and supplies the Y address counted to the Y address control circuit 7. The counted Y address is used as an address signal when write data from the input data control circuit (IDCNT) 14 is written to the data register 5 and when read data to be supplied to the output buffer 15 is selected from the data register 5. The The Y address supplied to the page address buffer 11 is equal to the head address of the counted Y address. This head Y address is referred to as an access head Y address.

  The control signal buffer (CSBUF) 18 includes a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, a read enable signal / RE, and a write protect signal as external access control signals. / WP, power on read enable signal PRE, and reset signal / RES are supplied. The symbol “/” attached to the head of a signal means that the signal is low enable.

  The chip enable signal / CE is a signal for selecting the operation of the flash memory 1, and the flash memory (device) 1 is activated (operable) at a low level, and the flash memory 1 is set to standby (operation stopped) at a high level. The The read enable signal / RE controls the data output timing from the external input / output terminals I / O1 to I / O16, and data is read in synchronization with the clock change of the signal. The write enable signal / WE instructs the flash memory 1 to fetch the command, address, and data at the rising edge. The command latch enable signal CLE is a signal for designating data supplied from the outside to the external input / output terminals I / O1 to I / O16 as a command, and the data of the output terminals I / O1 to I / O16 is CLE = "H". At (high level), it is taken in synchronization with the rising edge of / WE and recognized as a command. The address latch enable signal ALE is a signal for instructing that the data supplied from the outside to the external input / output terminals I / O1 to I / O16 is an address, and the data of the output terminals I / O1 to I / O16 is ALE = When it is “H” (high level), it is fetched in synchronization with the rising edge of / WE and is recognized as an address. When the write protect signal / WP is at a low level, the flash memory 1 is inhibited from being erased and written.

  The internal control circuit 16 performs interface control according to the access control signal and the like, and controls internal operations such as an erase operation, a write operation, and a read operation according to an input command. The internal control circuit 16 includes hard-wired control logic or program control logic such as erase control, read control, write control, and upper skirt determination control. The internal control circuit 16 outputs a ready / busy signal R / B. The ready / busy signal R / B is set to a low level during the operation of the flash memory 1, thereby notifying the outside of the busy state. Vcc is a power supply voltage, and Vss is a ground voltage. The high voltage required for the writing process and the erasing process is not particularly limited, but is generated by an internal booster circuit (not shown) based on the power supply voltage Vcc.

<Global bit line write / read circuit>
FIG. 1 representatively shows a configuration relating to one global bit line as the configuration of the memory array 3. For example, two columns of nonvolatile memory cells MC arranged in parallel with respect to one global bit line GBL are arranged. The first column constitutes part of page 0, and the second column constitutes part of page 1. The common source electrodes of the nonvolatile memory cells MC constituting each column are exclusively selected by string switches Mn1 and Mn2 that are switch-controlled by selection signals STS1 and STS2, and are conducted to the global bit line GBL. The common drain electrodes of the nonvolatile memory cells MC constituting each column are exclusively selected by the string switches Mn3 and Mn4 that are switch-controlled by the selection signals STD1 and STD2, and are conducted to the common drain line CDL. Here, for convenience, the names of the source and drain of the nonvolatile memory cell MC are based on the direction of the write current in the write operation. Therefore, the source and drain are reversed in the read operation. In the figure, a p-channel MOS transistor is marked with an arrow of its base gate to distinguish it from an n-channel MOS transistor.

  The global bit GBL write / read circuit will be described. Reference numeral 20 denotes a sense latch constituted by a CMOS static latch. The high potential side operation power supply node is SLP, and the low potential side operation power supply node is SLN. One input / output node of the sense latch 20 is a reference node REF, and the other input / output node is a sense node SNS. The reference node REF and the sense node SNS can be connected to the input / output paths IORi and IOSi via select MOS transistors 21 and 22 that are switch-controlled by a column selection signal YS, and are switch-controlled by signals RSAR and RSAS. Sense latch set MOS transistors 23 and 24 are connected to precharge power supply node FRPC. The input / output paths IORi and IOSi are connected to the data register 5. The data register 5 has conversion logic for converting between quaternary data and binary data. In the initialization operation of the sense node SNS and the reference node REF, the levels of the signals RSAS and RSAR are different, so that the reference node REF is precharged to approximately half the level of the sense node SNS. The sense node SNS is connected to a circuit ground potential Vss through a sense MOS transistor 25 and a sense enable MOS transistor 26 which is switch-controlled by a signal SENSE. The sense MOS transistor 25 is switch-controlled according to the level of the global bit line, and selectively enables the sense node SNS to be connected to the ground potential Vss. As a result, the sense latch 20 can invert the latch data depending on whether the global bit line GBL is discharged from the precharge level. The sense latch 20 can latch write control data supplied from the input / output paths IORi and IOSi. For convenience, the logical value of the reference node REF is expressed as a data value held by the sense latch 20. For example, when the sense latch 20 holds a high level (logic value 1 data), the reference node REF becomes a high level (logic value 1).

  Reference node REF can be connected to global bit line GBL via isolation MOS transistor 28 that is switch-controlled by signal TR. The isolation MOS transistor 28 is turned on in the write operation, and is turned off in the other operations. The selection MOS transistor 31 and the enable MOS transistor 30 connected in series between the global bit line GBL and the power supply FPC constitute a selection charge / discharge circuit 32. The selection MOS transistor 31 is switch-controlled according to the level of the reference node REF, and the enable MOS transistor 30 is switch-controlled by a control signal PC. The selective charging / discharging circuit 32 selectively discharges the global bit line GBL according to the power supply of the FPC only when the sense latch 20 holds the high level when the PC is instructed to turn on the MOS transistor 30. Precharge. In this sense, the global bit line GBL can be selectively precharged or discharged. Forcible charging / discharging of all global bit lines GBL is performed using MOS transistors 33 that are switch-controlled by a control signal RPCD. When the MOS transistor 33 is turned on, all the global bit lines GBL are discharged or precharged according to the power supply of the FPC. In this sense, the global bit line GBL can be fully precharged or discharged.

  The sense node SNS is coupled to the gate of an all determination MOS transistor 35 used for determination of write or erase verify operation, the source is input to the circuit ground potential Vss, and the drain signal ECD is input to the multi-input AND gate 36. . The output of the AND gate 36 is given to the control circuit 16. The multi-input AND gate 36 is commonly connected to the drains of the all determination MOS transistors 35 of the sense latches shared by a plurality of pages. When the global bit line GBL is discharged by the memory discharge operation for the memory cell having a high threshold voltage exceeding the upper skirt and lower skirt in the determination operation of the upper skirt and the lower skirt, the all determination MOS transistor 35 receives the latch data of the sense latch 20. It is turned on by an inversion operation. When even one all determination MOS transistor 35 is turned on, it is determined that there is an abnormality in the write or erase verify operation.

  In the write operation, isolation MOS transistor 28 is turned on, and reference node REF of sense latch 20 is conducted to global bit line GBL. Low level write control information is latched in the sense latch 20 of the reference node REF connected to the source of the nonvolatile memory cell MC selected for writing. As a result, a write current flows from the common data line CDL to the power supply SLN via the reference node REF. In the write operation, a high voltage is applied to the word line of the nonvolatile memory cell selected for writing, and the write current generates hot electrons in the nonvolatile memory cell selected for writing. At this time, the power supply SLN is set to Vss. High level write non-selection control information is latched in the sense latch 20 of the reference node REF connected to the source of the non-volatile memory cell MC to be unselected. This suppresses the write current from flowing to the non-programmed non-volatile memory cell.

  In the read operation of the stored information in the read operation or the write or erase verify operation, the isolation MOS transistor 28 is turned off, and the reference node REF of the sense latch 20 is disconnected from the global bit line GBL. A basic operation mode of the reading process will be described. First, the global bit line GBL is precharged by the MOS transistor 33, and then the memory discharge operation is started by selecting the word line. If the threshold voltage of the selected nonvolatile memory cell is lower than the word line selection level, the global bit line GBL is discharged. If the threshold voltage of the selected nonvolatile memory cell is higher than the word line selection level, the global bit line GBL is discharged. Maintains the precharge level. During this memory discharge operation, the reference node REF and the sense node SNS are precharged via the power supply FRPC. Due to the level difference between the control signals RSAR and RSAS, the reference node REF is precharged to about half the level of the sense node SNS. Thereafter, the sense enable MOS transistor 26 is turned on. At this time, if the global bit line GBL is discharged by the memory discharge operation, the level of the sense node SNS is not changed, and the sense latch 20 performs an amplifying operation in response to turning on of the operation power to perform a low level data latch operation. Confirm. On the other hand, if the global bit line GBL maintains the precharge level by the memory discharge operation, the level of the sense node SNS is inverted with respect to the reference node REF, and the sense latch 20 amplifies in response to turning on the operation power supply. To confirm the high level data latch operation.

<< Upper hem judging action >>
FIG. 3 shows the distribution of threshold voltages set in the nonvolatile memory cells by the write operation. VW0, VW1, VW2, and VW3 are verify voltages as lower skirt determination voltages corresponding to stored information “11”, “10”, “00”, and “01” at the time of write verify. VEW0, VEW1, and VEW2 are upper skirt determination voltages corresponding to stored information “11”, “10”, and “00” at the time of write verification. The threshold voltage distribution corresponding to the stored information “11”, “10”, “00”, “01” is defined by the upper skirt determination voltage and the lower skirt determination voltage. VRW1, VRW2, and VRW3 are read word line voltages (read determination levels) for enabling determination of stored information “11”, “10”, “00”, and “01” during a read operation. In the page unit write operation, the write process based on the erased state is not particularly limited, but the “01” data write process, the “00” data write process, and the “11” data write process are performed in this order. Although not particularly limited, the data write process is a process in which the write voltage application and the lower skirt determination operation are repeated so that the threshold voltage of the nonvolatile memory cell to be written is equal to or higher than the lower skirt of the target threshold voltage distribution. . Although not particularly limited, it is assumed that the upper skirt determination process is performed when each of the data write processes of “01”, “00”, and “11” is successful.

  FIG. 4 schematically shows a planar arrangement relationship of the nonvolatile memory cells. FG is a floating gate of the nonvolatile memory cell, and WL is a word line. Depending on the matrix arrangement of the nonvolatile memory cells, the floating gates FG of each memory cell are capacitively coupled to each other adjacent to the front, rear, left and right, and serve as a capacitive electrode of the coupling capacitor CC. Therefore, when electrons are injected into the floating gate FG and the threshold voltage is changed in the write operation, the potential change of the floating gate FG caused thereby changes the potential of another floating gate FG capacitively coupled thereto. This apparently changes the threshold voltage of the nonvolatile memory cell having the other floating gate FG. For example, the writing process to the nonvolatile memory cells sharing the word line is performed in the order of “10”, “00”, “01” in accordance with the write data based on the erased state “11”. Is determined in the order of “10” data, “00” data, and “01” data. The previously determined threshold voltage varies according to a change in the state of charge injection with respect to the floating gate of another nonvolatile memory cell to which a writing process is performed in the vicinity. In short, as illustrated in FIG. 5, the threshold voltage distribution of the memory cell whose threshold voltage state has been determined earlier as indicated by the broken line is apparently higher later as indicated by the solid line. This causes a so-called Vth blur. Then, after the lower skirt determination operation using the lower skirt determination voltage VWV for the write processing of “10”, “00”, and “01” is passed, the upper skirt determination operation using the upper skirt determination voltage VWE is performed for each word line. In some cases, the threshold voltage of the memory cell whose threshold voltage state has been previously determined is apparently increased later and exceeds the upper skirt determination level. If the threshold voltage apparent variation due to Vth blur does not exceed the read determination level VRW during the read operation, there is no problem in the memory operation. Conversely, if such an erroneous determination in the upper skirt determination is detected, the host system is notified as a write failure and is subject to error processing, which places a heavy burden on the host system. It is a problem.

  FIG. 6 shows a flowchart of the upper skirt determination process in which the upper skirt determination target is limited to the write selected memory cells. FIG. 7 shows a flowchart of the upper skirt determination process according to the comparative example in which the upper skirt determination target is not limited to the write selection memory cell but remains in the write processing unit. FIG. 8 shows transition of logical values of the global bit line GBL and the sense latch (SLAT) 20 in the processing steps shown in FIGS. FIG. 9 is an explanatory diagram showing three states of threshold voltages that can be taken by the nonvolatile memory cell to be selected by the upper skirt determination voltage assumed in the transition diagram of FIG.

  First, the three states in FIG. 9 will be described. The state A is a state in which the threshold voltage of the nonvolatile memory cell to be selected by the upper skirt determination voltage VWE is equal to or higher than the read determination voltage VRW. The state B is a state in which the threshold voltage of the nonvolatile memory cell to be selected by the upper skirt determination voltage VWE is equal to or higher than the upper skirt determination voltage VWE. This is a state where there is an error in the upper skirt determination. The state C is a state in which the threshold voltage of the nonvolatile memory cell selected by the upper skirt determination voltage VWE is equal to or higher than the lower skirt determination voltage VWV and lower than the upper skirt determination voltage VWE. This is a normal state with no error in the upper skirt determination. For the three states A, B, and C shown in FIG. 9, the transition of the logical values of the global bit line GBL and the sense latch (SLAT) 20 according to the processing flow of FIG. 7 is shown in the CMP-TRNSIT column of FIG. Shown for each of A, B, and C. Similarly, in the column of INVET-TRANSIT in FIG. 8, the transition of the logical values of the global bit line GBL and the sense latch (SLAT) 20 according to the processing flow of FIG. 6 is shown for each of A, B, and C. In FIG. 8, H means high level (logical value 1), and L means low level (logical value 0).

  First, the upper skirt determination processing procedure according to the comparative example of FIG. 7 will be described. All the global bit lines GBL of the page to be written are precharged (S1), and memory discharge is performed by selecting the word line of the page using the read determination voltage VRW (S2). A sense operation by the sense latch (SLAT) 20 is performed according to the state of the global bit line GBL obtained by the memory discharge (S3). As a result, as shown in FIG. 9, the sense latch 20 latches H, L, and L according to the threshold voltage states of A, B, and C. Thereafter, all discharges are performed on the global bit line GBL of the page which is a write processing unit (S4), and further, all precharges are similarly performed on the global bit line GBL (S5). Next, the memory discharge is performed by selecting the word line of the page using the upper skirt determination voltage VWE (S6). As a result, the global bit lines connected to the memory cells in the B and C states whose threshold voltage exceeds the upper tail are maintained as they are without being discharged. As apparent from the logic state at the intersection of CMP-TRNSIT and S6 in FIG. 9, the sense latch 20 latches H when the threshold voltage of the corresponding memory cell exceeds the read voltage VRW. Further, the global bit line GBL maintains the precharge state of the logical value H when the threshold voltage of the corresponding memory cell exceeds the upper skirt determination voltage VWE. Here, the logic state of H represents an abnormality. Thereafter, selective discharge is performed by the latch data of the sense latch 20 on the global bit line GBL subjected to the memory discharge in S6 (S7). The process of S7 serves to mask the state of the logical value H on the global bit line GBL obtained in step S2 (read failure where the threshold voltage exceeds the read determination voltage VRW). The result of this selective discharge is latched in the sense latch 20 by the sense latch operation in step S8, so that only the sense latch 20 corresponding to the volatile memory cell (threshold voltage B state) having the upper tail abnormality has the logical value H. Will be retained. As described above, the logical value of the latch data of the sense latch 20 is the logical value of the reference node REF, and an inversion operation is performed to transfer this to the sense node SNS. The inversion operation is shown only in FIG. 9, and the global bit line GBL precharge, the selective discharge for the global bit line GBL, and the sense operation by the sense amplifier may be sequentially performed. When the all determination MOS transistor 35 is turned on by the inversion operation, the upper skirt determination is abnormal. Since the memory discharge in steps S2 and S6 is performed on all memory cells for one page sharing the word line, the threshold voltage appears to be apparent due to capacitive coupling between adjacent memory cells as described above. If the upper skirt determination voltage VWE is exceeded, naturally an upper skirt determination abnormality is detected.

  The processing procedure of FIG. 6 makes it possible to exclude detection of such upper skirt determination abnormality. The difference from FIG. 7 is that steps SX and SY are added. In step SX, the write control information held in the data register DRG is transferred to the sense latch 20. For example, in the case of determining the upper skirt for writing the write data “00”, the write selection control information or the write non-selection control information corresponding to the write data “00” is latched in the corresponding sense latch 20 for each memory cell unit of the write target page. Let As described above, the write selection control information is the latch data of the logic value L in the sense latch 20. In FIG. 9, the case of the threshold voltage state of C with respect to A, B, and C is a logical value L. In short, it is assumed that the writing target is in a normal state with no upper skirt abnormality. In step SY, using the write control information latched in the sense latch 20 in step SX, selective precharge for the global bit line GBL after the memory discharge operation (S2) is performed. This selective precharge has a function of forcing the global bit line of the sense latch (SLAT) 20 that latches the write non-selection control information to a precharge state. Therefore, the selective precharge processing SY is performed when the threshold voltage of the nonvolatile memory cell connected to the global bit of the sense latch (SLAT) 20 that latches the write non-selection control information is in the B state (S2). Thus, even if the bit line is discharged to the logic value L, it is changed to the logic value H state similar to the A state. This state is latched by the sense amplifier 20 by the sense latch operation in step S3. As a result, the sense latch 20 connected to the memory cell which is not selected for writing and has an upper-side abnormality can hold the logical value H. The data of the logical value H latched in the sense latch 20 by the sense latch operation in step S3 indicates the state of the logical value H on the global bit line indicating an abnormality with respect to the result of the memory discharge operation by the upper skirt determination voltage VWE in S6. , S7 has a function of inverting to a normal logical value L state by the selective discharge of S7. Accordingly, in the sense latch operation of S8, all latch data of the sense latch 20 is set to the logical value L. In this way, in the processing procedure for performing memory discharge (S2, S6) for each write page for the upper skirt determination, even if the threshold voltage of the memory cell that is not the write selection apparently exceeds the upper skirt determination voltage, Can be excluded from the substantial upper skirt determination. In FIG. 8, MSK means that the upper skirt is not determined, and ERROR means that the upper skirt is undesirably defective.

  Here, it is assumed that there is an upper skirt abnormality in the write selection memory cell on the write target page. In this case, the B threshold voltage state column at the intersection of INVNT-TRNSIT and SX in FIG. Since the states of A and C are in the case where writing is not selected, the logical value becomes H. The change of the truth value at this time is as shown in parentheses. Since the selective discharge of S7 cannot discharge the global bit line in the threshold voltage state of B with respect to the result of the memory discharge of S6, S8 In this sense latch operation, it is possible to reliably detect the upper skirt abnormality in the nonvolatile memory cell selected for writing. The processing procedure of FIG. 6 is defined by the control logic of the control circuit 16.

  Thereby, even if the threshold voltage apparently exceeds the upper skirt determination voltage VWE due to capacitive coupling between adjacent memory cells, it is not detected as an upper skirt determination abnormality. Even if the threshold voltage of the nonvolatile memory cell apparently exceeds the upper skirt determination voltage VWE due to capacitive coupling, if such a variation does not exceed the read word line selection level (read determination voltage) VRW, there is nothing in terms of memory operation. No problem. Since a relatively large margin is ensured in the potential difference between the upper skirt determination voltage VWE and the upper read determination voltage VRW, the threshold voltage fluctuated by capacitive coupling exceeds the read determination voltage between adjacent distributions. This is unlikely to happen in practice. Even if the threshold voltage apparently exceeds the upper skirt determination voltage VWE due to capacitive coupling, it is not detected as an upper skirt determination abnormality only in this case. There is no notification to the system. It is possible to suppress the occurrence of an excessive burden on the host system side caused by notifying the host system side of all writing failures.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, a specific method for excluding information read from a non-programmed non-volatile memory cell from the determination target of the success or failure of the write process is not limited to the process procedure of FIG. 6 and can be changed as appropriate. . Further, the present invention is not limited to the flash memory, but can be widely applied to an EEPROM and other storage-type nonvolatile memories. The nonvolatile semiconductor memory device is not limited to a single memory, but can be widely applied to a memory on-chip in an LSI (Large Scale Integrated Circuit) such as a system LSI or a microcomputer.

FIG. 3 is a circuit diagram representatively showing a configuration related to one global bit line as a configuration of a memory array. It is a block diagram which shows schematic structure of flash memory. It is explanatory drawing of the threshold voltage distribution set to a non-volatile memory cell by write-in operation | movement. It is a top view which shows roughly the planar arrangement | positioning relationship of a non-volatile memory cell. It is explanatory drawing which illustrates transition of the threshold voltage when what is called a Vth blur occurs. It is a flowchart of the upper skirt determination process which restricted the upper skirt determination object to the write selection memory cell. 12 is a flowchart of an upper skirt determination process according to a comparative example in which an upper skirt determination target is not limited to a write selection memory cell but remains in a write processing unit. FIG. 8 is a transition diagram of logical values of the global bit line GBL and the sense latch (SLAT) in the processing steps shown in FIGS. 6 and 7; FIG. 9 is an explanatory diagram showing three states that can be taken by the threshold voltage of a nonvolatile memory cell to be selected by an upper skirt determination voltage assumed in the transition diagram of FIG. 8.

Explanation of symbols

1 Flash memory BNK0 to BNK3 Memory bank 3 Memory array (ARY)
4 X decoder (XDEC)
5 Data register (DRG)
6 Data control circuit (DCNT)
7 Y address control circuit (YACNT)
11 Page address buffer (PABUF)
12 Y address counter (YACUNT)
16 Internal control circuit (OPCNT)
MC memory cell WL word line FG floating gate CC coupling capacitance GBL global bit line 20 sense latch REF reference node SNS sense node 35 all judgment MOS transistor 30 enable MOS transistor 31 selection MOS transistor 32 selection charge / discharge circuit VRW read judgment voltage VWE Bottom deciding voltage VWV Bottom skirt judging voltage

Claims (8)

A non-volatile semiconductor memory device having a plurality of rewritable non-volatile memory cells, wherein each non-volatile memory cell can store information of 2 bits or more in a rewritable manner according to a difference in threshold voltage. ,
The rewrite unit of stored information includes a nonvolatile memory cell that is selected for writing according to information to be written and a nonvolatile memory cell that is not selected for writing,
In the write process for the rewrite unit, the threshold voltage is set so as to fall within the required distribution from one direction for the nonvolatile memory cell selected for write, and the distribution is defined from the other direction for the result of the write process. Using the determination voltage, the storage information is read from the non-volatile memory cells that are selected and unselected for rewriting, and the information read from the non-volatile memory cells that are not selected among the read storage information A non-volatile semiconductor memory device excluded from the success / failure determination target.   2. The nonvolatile semiconductor memory device according to claim 1, wherein said nonvolatile memory cell has a conductive floating gate insulated for each nonvolatile memory cell as a charge storage region for determining a threshold voltage.   Multiple strings consisting of multiple non-volatile memory cells connected in parallel between source and drain, with multiple global data lines selectively connected to one global bit line and sharing the global bit line The non-volatile semiconductor memory device according to claim 2, wherein the plurality of strings include non-volatile memory cells whose selection terminals are connected to the same word line. A non-volatile semiconductor memory device having a plurality of rewritable non-volatile memory cells, wherein each non-volatile memory cell can store information of 2 bits or more in a rewritable manner according to a difference in threshold voltage. ,
The rewrite unit of stored information includes a nonvolatile memory cell that is selected for writing according to information to be written and a nonvolatile memory cell that is not selected for writing,
A write control circuit for setting the threshold voltage to a required distribution from one direction for the nonvolatile memory cell for write selection in the write process for the rewrite unit;
Non-volatile memory cell that is not selected for writing out of the information read from the non-volatile memory cell that is selected and unselected for rewriting using a determination voltage that defines the distribution from the other direction with respect to the result of the writing process A non-volatile semiconductor memory device comprising: a circuit that excludes information read out from a determination target of whether or not writing is successful for the writing process.   5. The nonvolatile circuit according to claim 4, wherein the control circuit sets the threshold voltage of the write selection nonvolatile memory cell so as to fall within a predetermined distribution from one direction by using a write verify voltage corresponding to information to be written. Semiconductor memory device.   6. The nonvolatile semiconductor memory device according to claim 5, wherein the determination voltage that defines the distribution from the other direction with respect to the result of the write process is an upper skirt determination voltage corresponding to the information to be written. A word line connected to a selection terminal of the nonvolatile memory cell;
A bit line connected to a data terminal of the nonvolatile memory cell;
A sense latch connected to the bit line;
An all determination circuit for determining whether or not all latch data of the sense latch of the write processing unit is a value due to memory discharge,
The circuit to be excluded is a selective charge / discharge circuit that performs selective discharge or selective precharge of the bit line according to latch data of the sense latch.
The nonvolatile semiconductor memory device according to claim 6, further comprising an upper skirt determination control circuit that controls an operation using the selective charge / discharge circuit.   The upper skirt determination control circuit latches write selection control information in the sense latch corresponding to the write-selected nonvolatile memory cell after the write process, and corresponds to the write-unselected nonvolatile memory cell. Select uncharge control information is latched by the selective charge / discharge circuit using latch data latched by the sense latch with respect to the bit line obtained by memory discharge according to the word line level of the read operation. The result is latched by the sense latch, and then the selective charge / discharge circuit using the latch data latched by the sense latch with respect to the bit line obtained by the memory discharge using the upper skirt determination level. Performs selective discharge and stores the result in the sense latch. Tsu is Ji, non-volatile semiconductor memory device according to claim 7, wherein for the determination based on the latched data of the sense latch to the all-determining circuit.

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